KR20230000596A - Semiconductor memory device and operating method thereof - Google Patents

Abstract

A method of operating a semiconductor memory device includes performing a plurality of program loops for programming selected memory cells among a plurality of memory cells. Each of the plurality of program loops includes a program step and a verify step. The program step includes the phases of: setting a state of a select line connected to a selected memory block including the selected memory cells; setting the state of the select line connected to the selected memory block; and applying a program voltage to a word line selected from among word lines connected to the selected memory block and applying a pass voltage to an unselected word line. In the phase of setting the state of the select line connected to the selected memory block, a voltage is applied to the select line based on the progress state of the program of the selected memory cells. According to the present invention, the method of operating a semiconductor memory device can prevent disturbance while narrowing the width of the distribution of a threshold voltage of memory cells during programming.

Description

Semiconductor memory device and its operating method {SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF}

The present invention relates to an electronic device, and more particularly, to a semiconductor memory device and an operating method thereof.

The semiconductor memory device may have a 2D structure in which strings are horizontally arranged on a semiconductor substrate or a 3D structure in which strings are vertically stacked on a semiconductor substrate. A 3D semiconductor memory device is a semiconductor memory device designed to overcome the integration limit of a 2D memory device, and may include a plurality of memory cells vertically stacked on a semiconductor substrate. Meanwhile, the controller may control the operation of the semiconductor memory device.

Embodiments of the present invention provide a semiconductor memory device capable of preventing disturb while narrowing a threshold voltage distribution width of memory cells during programming, and an operating method thereof.

A method of operating a semiconductor memory device according to an embodiment of the present invention includes a plurality of program loops for programming selected memory cells among a plurality of memory cells. Each of the plurality of program loops includes a program step and a verify step. The programming step may include setting a state of a selection line connected to the selected memory block, including the selected memory cells, setting a state of a bit line connected to the selected memory block, and word lines connected to the selected memory block. Among them, a program voltage is applied to the selected word line and a pass voltage is applied to the unselected word line. In the step of setting states of selection lines connected to the selected memory block, a voltage is applied to the selection lines based on a program progress state of the selected memory cells.

In one embodiment, each of the plurality of memory cells may store N-bit data. The step of setting the state of the selection lines connected to the selected memory block is the step of checking the state of the program that has been programmed in the verification step of the previous program loop, and as a result of the checking, among the first to (2 ^N -1)th program states, The method may include applying a first voltage to the selection line when programming of memory cells to be programmed to the i-program state is not completed. Here, N is a natural number greater than 1, and i may be a natural number greater than 0 and less than (2 ^N -1).

In an embodiment, the setting of the states of the selection lines connected to the selected memory block may include, as a result of the checking, programming of memory cells to be programmed to the i-th programmed state is completed, and the first voltage and the first voltage are applied to the selection line. It may include applying a different second voltage.

In one embodiment, the selection line may be a drain selection line.

In one embodiment, the selection line may be a source selection line.

In one embodiment, the second voltage may be lower than the first voltage.

In one embodiment, the second voltage may be greater than the first voltage.

In one embodiment, the N may be 2 and the i may be 2.

In one embodiment, the N may be 3 and the i may be 6.

In an embodiment, the verifying step includes applying a pre-verification voltage to a word line connected to the selected memory cells and applying a main verify voltage higher than the pre-verification voltage to a word line connected to the selected memory cells. can do.

In an embodiment, the verifying step may further include determining memory cells having threshold voltages higher than the main verifying voltage as program inhibit cells.

In an embodiment, the verifying may include determining memory cells having threshold voltages lower than the pre-verification voltage as first program-allowed cells, and memory cells having threshold voltages higher than the pre-verification voltage and lower than the main verification voltage. The method may further include determining the second program permitted cell.

In an embodiment, setting a state of a bit line connected to the selected memory block may include applying a first program enable voltage to a bit line connected to the first program enable cell and a bit connected to the second program enable cell. The method may further include applying a second program allowable voltage higher than the first program allowable voltage to a line.

In an embodiment, setting the state of the bit line connected to the selected memory cells may further include applying a program inhibit voltage higher than the second program enable voltage to a bit line connected to the program inhibit cell. .

A semiconductor memory device according to another embodiment of the present invention includes a memory block, a peripheral circuit, and a control logic. The memory block includes a plurality of memory cells that store N bits of data per memory cell. The peripheral circuit performs a program operation on selected memory cells among a plurality of memory cells included in the memory block. The control logic controls a program operation of the peripheral circuit. The program operation includes a plurality of program loops, and each of the plurality of program loops includes a program step and a verify step. In the programming step, the control logic sets a state of a selection line connected to the memory block based on a program progress state of the selected memory cells, sets a state of a bit line connected to the selected memory block, and sets a state of a bit line connected to the selected memory block. The peripheral circuit is controlled so that a program voltage is applied to a selected word line among word lines connected to , and a pass voltage is applied to an unselected word line. Here, N is a natural number greater than 1.

In an embodiment, in a process of setting a state of a selection line connected to the memory block based on a program progress state of the selected memory cells, the control logic checks a program state that has been programmed in a verification step of a previous program loop, , As a result of the check, if the programming of memory cells to be programmed to the i-th program state is not completed among the first to (2 ^N -1)-th program states, the peripheral circuit is configured to apply a first voltage to the selection line. You can control it. Here, i may be a natural number greater than 0 and less than (2 ^N -1).

In one embodiment, in the process of setting the state of the selection line connected to the memory block based on the program progress state of the selected memory cells, the control logic determines the first to (2 ^N -1) When programming of memory cells to be programmed to the i-th program state is completed during the program state, the peripheral circuit may be controlled to apply a second voltage different from the first voltage to the selection line.

In an embodiment, the selection line is a drain selection line, and the second voltage may be lower than the first voltage.

In an embodiment, in the verifying step, the control logic may apply a pre-verification voltage to a word line connected to the selected memory cells, and apply a main verification voltage higher than the pre-verification voltage to a word line connected to the selected memory cells. The peripheral circuit can be controlled. The control logic determines memory cells having a threshold voltage higher than the main verify voltage as program inhibit cells, and determines memory cells having a threshold voltage lower than the pre verify voltage as first program permitted cells, and determines memory cells having a threshold voltage lower than the pre verify voltage as first program permitted cells. Memory cells having a threshold voltage lower than the main verification voltage may be determined as the second program allowable cells.

In an embodiment, in the process of setting a state of a bit line connected to the selected memory block, the control logic may apply a first program allow voltage to a bit line connected to the first program allow cell, and may apply the second program allow voltage to the bit line. The peripheral circuit applies a second program enable voltage higher than the first program enable voltage to a bit line connected to the enable cell, and applies a program enable voltage higher than the second program enable voltage to a bit line connected to the program inhibit cell. can control.

The present technology can provide a semiconductor memory device and an operating method capable of preventing disturb while narrowing a threshold voltage distribution width of memory cells during programming.

1 is a block diagram illustrating a memory system including a semiconductor memory device and a controller according to an exemplary embodiment.
FIG. 2 is a block diagram illustrating the semiconductor memory device of FIG. 1 .
FIG. 3 is a diagram illustrating an example of the memory cell array of FIG. 2 .
FIG. 4 is a circuit diagram showing one memory block BLKa among the memory blocks BLK1 to BLKz of FIG. 3 .
FIG. 5 is a circuit diagram showing another embodiment of one memory block BLKb among the memory blocks BLK1 to BLKz of FIG. 3 .
FIG. 6 is a circuit diagram showing an embodiment of one memory block BLKc among a plurality of memory blocks BLK1 to BLKz included in the memory cell array 110 of FIG. 2 .
7 is a diagram for explaining a plurality of program loops included in a program operation, and a program step and a verification step included in each program loop.
8 is a flowchart illustrating an operating method of a semiconductor memory device according to an exemplary embodiment of the present invention.
9 is a flowchart illustrating an embodiment of step S110 of FIG. 8 .
10 is a graph showing a threshold voltage distribution after a program operation of a single-level cell (SLC).
11 is a flowchart illustrating an embodiment of step S210 of FIG. 9 .
12 is a flowchart illustrating an embodiment of step S250 of FIG. 9 .
13 is a diagram for explaining threshold voltages of a program-allowed cell and a program-inhibited cell.
14 is a graph for explaining a verification operation using a pre-verification voltage Vvf_p and a main verification voltage Vvf_m according to an embodiment of the present invention.
15 is a flowchart illustrating another embodiment of step S250 of FIG. 9 .
16 is a flowchart illustrating another embodiment of step S210 of FIG. 9 .
FIG. 17 is a diagram for explaining threshold voltages of first program permitted cells, second program permitted cells, and program inhibited cells.
18 is a graph showing a threshold voltage distribution after a program operation of a multi-level cell (MLC).
19 is a timing diagram for explaining a program operation according to an embodiment of the present invention.
20 is a flowchart illustrating an embodiment of step S200 of FIG. 9 .
21A is a timing diagram illustrating an operation of a semiconductor memory device according to an exemplary embodiment when programming of memory cells to be programmed to an i-th program state is not completed. 21B is a timing diagram illustrating an operation of the semiconductor memory device according to an exemplary embodiment when programming of memory cells to be programmed to an i-th program state is completed.
22 is a graph for explaining an operating method of the semiconductor memory device according to the exemplary embodiment described with reference to FIGS. 21A and 21B from another aspect.
23A is a timing diagram for describing an operation of a semiconductor memory device according to another embodiment when programming of memory cells to be programmed to an i-th program state is not completed. 23B is a timing diagram illustrating an operation of a semiconductor memory device according to another embodiment when programming of memory cells to be programmed to an i-th program state is completed.
24 is a graph for explaining an operating method of the semiconductor memory device according to the exemplary embodiment described with reference to FIGS. 23A and 23B from another aspect.
25 is a flowchart illustrating another embodiment of step S200 of FIG. 9 .
26 is a block diagram illustrating an example of the controller shown in FIG. 1 .
27 is a block diagram illustrating an application example of the memory system of FIG. 26 .
FIG. 28 is a block diagram illustrating a computing system including the memory system described with reference to FIG. 27 .

Specific structural or functional descriptions of the embodiments according to the concept of the present invention disclosed in the present specification or application are only exemplified for the purpose of explaining the embodiment according to the concept of the present invention, and the implementation according to the concept of the present invention Examples may be embodied in many forms and should not be construed as limited to the embodiments described in this specification or application.

1 is a block diagram illustrating a memory system including a semiconductor memory device and a controller according to an exemplary embodiment.

Referring to FIG. 1 , a memory system 1000 includes a semiconductor memory device 100 and a controller 200 . Also, the memory system 1000 communicates with the host 300 . The controller 200 controls overall operations of the semiconductor memory device 100 . Also, the controller 200 controls the operation of the semiconductor memory device 100 based on a command received from the host 300 .

FIG. 2 is a block diagram illustrating the semiconductor memory device of FIG. 1 .

Referring to FIG. 2 , the semiconductor memory device 100 includes a memory cell array 110 , an address decoder 120 , a read and write circuit 130 , a control logic 140 and a voltage generator 150 .

The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to the address decoder 120 through word lines WL. The plurality of memory blocks BLK1 to BLKz are connected to the read and write circuit 130 through bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. As an example embodiment, the plurality of memory cells are nonvolatile memory cells and may include nonvolatile memory cells having a vertical channel structure. The memory cell array 110 may include a two-dimensional memory cell array. According to an embodiment, the memory cell array 110 may be configured as a three-dimensional memory cell array. Meanwhile, each of the plurality of memory cells included in the memory cell array may store at least 1 bit of data. In one embodiment, each of a plurality of memory cells included in the memory cell array 110 may be a single-level cell (SLC) that stores 1-bit data. In another embodiment, each of a plurality of memory cells included in the memory cell array 110 may be a multi-level cell (MLC) that stores 2-bit data. In another embodiment, each of the plurality of memory cells included in the memory cell array 110 may be a triple-level cell (TLC) that stores 3-bit data. In another embodiment, each of the plurality of memory cells included in the memory cell array 110 may be a quad-level cell (QLC) that stores 4-bit data. According to an embodiment, the memory cell array 110 may include a plurality of memory cells each storing 5-bit or more data.

The address decoder 120 , the read/write circuit 130 , and the voltage generator 150 operate as peripheral circuits for driving the memory cell array 110 . The address decoder 120 is connected to the memory cell array 110 through word lines WL. The address decoder 120 is configured to operate in response to control of the control logic 140 . The address decoder 120 receives an address through an input/output buffer (not shown) inside the semiconductor memory device 100 .

The address decoder 120 is configured to decode a block address among received addresses. The address decoder 120 selects at least one memory block according to the decoded block address. In addition, during a read voltage application operation during a read operation, the address decoder 120 applies the read voltage Vread generated by the voltage generator 150 to the selected word line among the selected memory blocks and the other non-selected word lines. A pass voltage Vpass is applied to them. Also, during the program verify operation, the verify voltage generated by the voltage generator 150 is applied to the selected word line among the selected memory blocks, and the pass voltage Vpass is applied to the remaining non-selected word lines.

The address decoder 120 is configured to decode a column address among received addresses. The address decoder 120 transmits the decoded column address to the read and write circuit 130 .

A read operation and a program operation of the semiconductor memory device 100 are performed in units of pages. Addresses received upon request for read operations and program operations include block addresses, row addresses, and column addresses. The address decoder 120 selects one memory block and one word line according to the block address and row address. The column address is decoded by the address decoder 120 and provided to the read and write circuit 130.

The address decoder 120 may include a block decoder, a row decoder, a column decoder, and an address buffer.

The read and write circuit 130 includes a plurality of page buffers PB1 to PBm. The read and write circuit 130 may operate as a "read circuit" during a read operation of the memory cell array 110 and as a "write circuit" during a write operation. The plurality of page buffers PB1 to PBm are connected to the memory cell array 110 through bit lines BL1 to BLm. The plurality of page buffers PB1 to PBm continuously supply sensing current to bit lines connected to memory cells in order to sense the threshold voltages of the memory cells during a read operation and a program verify operation, while monitoring the program state of the corresponding memory cell. A change in the amount of current flowing along is sensed through the sensing node and latched as sensing data. The read/write circuit 130 operates in response to page buffer control signals output from the control logic 140 .

The read/write circuit 130 senses data of a memory cell during a read operation, temporarily stores the read data, and then outputs data DATA to an input/output buffer (not shown) of the semiconductor memory device 100 . As an exemplary embodiment, the read/write circuit 130 may include a column select circuit in addition to page buffers (or page registers).

The control logic 140 is connected to the address decoder 120 , the read and write circuit 130 , and the voltage generator 150 . The control logic 140 receives a command CMD and a control signal CTRL through an input/output buffer (not shown) of the semiconductor memory device 100 . The control logic 140 is configured to control overall operations of the semiconductor memory device 100 in response to the control signal CTRL. Also, the control logic 140 outputs a control signal for adjusting the level of the precharge potential of the sensing node of the plurality of page buffers PB1 to PBm. The control logic 140 may control the read/write circuit 130 to perform a read operation of the memory cell array 110 .

The voltage generator 150 generates a read voltage Vread and a pass voltage Vpass during a read operation in response to a control signal output from the control logic 140 . The voltage generator 150 includes a plurality of pumping capacitors receiving an internal power supply voltage in order to generate a plurality of voltages having various voltage levels, and selects the plurality of pumping capacitors in response to the control of the control logic 140. will be activated to generate a plurality of voltages. As described above, the voltage generator 150 may include a charge pump, and the charge pump may include the plurality of pumping capacitors described above. A specific configuration of the charge pump included in the voltage generator 150 may be designed in various ways as needed.

The address decoder 120 , the read and write circuit 130 , and the voltage generator 150 may function as “peripheral circuits” that perform a read operation, a write operation, and an erase operation on the memory cell array 110 . The peripheral circuit performs a read operation, a write operation, and an erase operation on the memory cell array 110 based on the control of the control logic 140 .

FIG. 3 is a diagram illustrating an example of the memory cell array of FIG. 2 .

Referring to FIG. 3 , the memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. Each memory block may have a 3D structure. Each memory block includes a plurality of memory cells stacked on a substrate. The plurality of memory cells are arranged along the +X direction, the +Y direction, and the +Z direction. The structure of each memory block will be described in more detail with reference to FIGS. 4 and 5 .

FIG. 4 is a circuit diagram showing one memory block BLKa among the memory blocks BLK1 to BLKz of FIG. 3 .

Referring to FIG. 4 , the memory block BLKa includes a plurality of cell strings CS11 to CS1m and CS21 to CS2m. As an embodiment, each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m may be formed in a 'U' shape. Within the memory block BLKa, m cell strings are arranged in a row direction (ie, +X direction). In FIG. 4 , it is illustrated that two cell strings are arranged in a column direction (ie, a +Y direction). However, this is for convenience of explanation, and it will be understood that three or more cell strings may be arranged in a column direction.

Each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m includes at least one source selection transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain. It includes a selection transistor (DST).

Each of the selection transistors SST and DST and the memory cells MC1 to MCn may have a similar structure. As an embodiment, each of the selection transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer. As an embodiment, a pillar for providing a channel layer may be provided to each cell string. As an embodiment, a pillar for providing at least one of a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer may be provided in each cell string.

The source select transistor SST of each cell string is connected between the common source line CSL and the memory cells MC1 to MCp.

As an embodiment, source select transistors of cell strings arranged in the same row are connected to source select lines extending in a row direction, and source select transistors of cell strings arranged in different rows are connected to different source select lines. In FIG. 4 , the source select transistors of the cell strings CS11 to CS1m in the first row are connected to the first source select line SSL1. Source select transistors of the cell strings CS21 to CS2m in the second row are connected to the second source select line SSL2.

As another embodiment, the source select transistors of the cell strings CS11 to CS1m and CS21 to CS2m may be connected in common to one source select line.

The first to nth memory cells MC1 to MCn of each cell string are connected between the source select transistor SST and the drain select transistor DST.

The first to nth memory cells MC1 to MCn may be divided into first to pth memory cells MC1 to MCp and p+1 to nth memory cells MCp+1 to MCn. The first to pth memory cells MC1 to MCp are sequentially arranged in the +Z direction and the reverse direction, and are connected in series between the source select transistor SST and the pipe transistor PT. The p+1th to nth memory cells MCp+1 to MCn are sequentially arranged in the +Z direction and connected in series between the pipe transistor PT and the drain select transistor DST. The first to pth memory cells MC1 to MCp and the p+1 to nth memory cells MCp+1 to MCn are connected through a pipe transistor PT. Gates of the first to n th memory cells MC1 to MCn of each cell string are connected to the first to n th word lines WL1 to WLn, respectively.

The gate of the pipe transistor PT of each cell string is connected to the pipeline PL.

The drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MCp+1 to MCn. Drain select transistors of the cell strings arranged in the row direction are connected to drain select lines extending in the row direction. Drain select transistors of the cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. Drain select transistors of the cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

Cell strings arranged in the column direction are connected to bit lines extending in the column direction. In FIG. 3 , the cell strings CS11 and CS21 of the first column are connected to the first bit line BL1. The cell strings CS1m and CS2m of the mth column are connected to the mth bit line BLm.

Memory cells connected to the same word line in cell strings arranged in a row direction constitute one page. For example, among the cell strings CS11 to CS1m in the first row, memory cells connected to the first word line WL1 constitute one page. Among the cell strings CS21 to CS2m in the second row, memory cells connected to the first word line WL1 constitute another page. When one of the drain select lines DSL1 and DSL2 is selected, cell strings arranged in one row direction are selected. When one of the word lines WL1 to WLn is selected, one page of the selected cell strings is selected.

As another embodiment, even bit lines and odd bit lines may be provided instead of the first to m th bit lines BL1 to BLm. And among the cell strings (CS11 to CS1m or CS21 to CS2m) arranged in the row direction, even-numbered cell strings are connected to the even bit lines, respectively, and the cell strings (CS11 to CS1m or CS21 to CS2m) arranged in the row direction Odd-numbered cell strings may be respectively connected to odd bit lines.

As an example embodiment, at least one of the first to n th memory cells MC1 to MCn may be used as a dummy memory cell. For example, one or more dummy memory cells are provided to reduce an electric field between the source select transistor SST and the memory cells MC1 to MCp. Alternatively, at least one or more dummy memory cells are provided to reduce an electric field between the drain select transistor DST and the memory cells MCp+1 to MCn. As more dummy memory cells are provided, the operation reliability of the memory block BLKa improves, while the size of the memory block BLKa increases. As fewer dummy memory cells are provided, the size of the memory block BLKa decreases while the reliability of an operation of the memory block BLKa may deteriorate.

In order to efficiently control at least one or more dummy memory cells, each of the dummy memory cells may have a required threshold voltage. Program operations may be performed on all or some of the dummy memory cells before or after the erase operation on the memory block BLKa. When an erase operation is performed after a program operation is performed, the dummy memory cells may have a required threshold voltage by controlling voltages applied to dummy word lines connected to the dummy memory cells. .

FIG. 5 is a circuit diagram showing another embodiment of one memory block BLKb among the memory blocks BLK1 to BLKz of FIG. 3 .

Referring to FIG. 5 , the memory block BLKb includes a plurality of cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the plurality of cell strings CS11' to CS1m' and CS21' to CS2m' extends along the +Z direction. Each of the plurality of cell strings CS11' to CS1m' and CS21' to CS2m' includes at least one source select transistor SST stacked on a substrate (not shown) under the memory block BLK1', a first to nth memory cells MC1 to MCn, and at least one drain select transistor DST.

The source select transistor SST of each cell string is connected between the common source line CSL and the memory cells MC1 to MCn. Source select transistors of the cell strings arranged in the same row are connected to the same source select line. The source select transistors of the cell strings CS11' to CS1m' arranged in the first row are connected to the first source select line SSL1. The source select transistors of the cell strings CS21' to CS2m' arranged in the second row are connected to the second source select line SSL2. As another embodiment, the source select transistors of the cell strings CS11' to CS1m' and CS21' to CS2m' may be connected in common to one source select line.

The first to nth memory cells MC1 to MCn of each cell string are connected in series between the source select transistor SST and the drain select transistor DST. Gates of the first to n th memory cells MC1 to MCn are connected to the first to n th word lines WL1 to WLn, respectively.

The drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MC1 to MCn. Drain select transistors of the cell strings arranged in the row direction are connected to drain select lines extending in the row direction. Drain select transistors of the cell strings CS11' to CS1m' in the first row are connected to the first drain select line DSL1. Drain select transistors of the cell strings CS21' to CS2m' in the second row are connected to the second drain select line DSL2.

As a result, the memory block BLKb of FIG. 5 has an equivalent circuit similar to that of the memory block BLKa of FIG. 4 except that the pipe transistor PT is excluded from each cell string.

As another embodiment, even bit lines and odd bit lines may be provided instead of the first to m th bit lines BL1 to BLm. In addition, even-numbered cell strings among the cell strings (CS11' to CS1m' or CS21' to CS2m') arranged in the row direction are connected to the even bit lines, respectively, and the cell strings arranged in the row direction (CS11' to CS1m ' or CS21' to CS2m'), odd-numbered cell strings may be respectively connected to odd bit lines.

As an example embodiment, at least one of the first to n th memory cells MC1 to MCn may be used as a dummy memory cell. For example, one or more dummy memory cells are provided to reduce an electric field between the source select transistor SST and the memory cells MC1 to MCn. Alternatively, at least one or more dummy memory cells are provided to reduce an electric field between the drain select transistor DST and the memory cells MC1 to MCn. As more dummy memory cells are provided, the operation reliability of the memory block BLKb improves, while the size of the memory block BLKb increases. As fewer dummy memory cells are provided, the size of the memory block BLKb decreases while the reliability of an operation with respect to the memory block BLKb may deteriorate.

In order to efficiently control at least one or more dummy memory cells, each of the dummy memory cells may have a required threshold voltage. Program operations may be performed on all or some of the dummy memory cells before or after the erase operation on the memory block BLKb. When an erase operation is performed after a program operation is performed, the dummy memory cells may have a required threshold voltage by controlling voltages applied to dummy word lines connected to the dummy memory cells. .

FIG. 6 is a circuit diagram showing an embodiment of one memory block BLKc among a plurality of memory blocks BLK1 to BLKz included in the memory cell array 110 of FIG. 2 .

Referring to FIG. 6 , the memory block BLKc includes a plurality of cell strings CS1 to CSm. The plurality of cell strings CS1 to CSm may be respectively connected to the plurality of bit lines BL1 to BLm. Each of the plurality of cell strings CS1 to CSm includes at least one source select transistor SST, first to n th memory cells MC1 to MCn, and at least one drain select transistor DST.

Each of the selection transistors SST and DST and the memory cells MC1 to MCn may have a similar structure. As an embodiment, each of the selection transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer. As an embodiment, a pillar for providing a channel layer may be provided to each cell string. As an embodiment, a pillar for providing at least one of a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer may be provided in each cell string.

The source select transistor SST of each cell string is connected between the common source line CSL and the memory cells MC1 to MCn.

The first to nth memory cells MC1 to MCn of each cell string are connected between the source select transistor SST and the drain select transistor DST.

The drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MC1 to MCn.

Memory cells connected to the same word line constitute one page. As the drain select line DSL is selected, the cell strings CS1 to CSm are selected. When one of the word lines WL1 to WLn is selected, one page of the selected cell strings is selected.

As another embodiment, even bit lines and odd bit lines may be provided instead of the first to m th bit lines BL1 to BLm. Among the cell strings CS1 to CSm, even-numbered cell strings may be connected to even bit lines, respectively, and odd-numbered cell strings may be connected to odd bit lines, respectively.

7 is a diagram for explaining a plurality of program loops included in a program operation, and a program step and a verification step included in each program loop.

Referring to FIG. 7 , a program operation may include a plurality of program loops. As shown in FIG. 7 , the program operation may be started by performing a first program loop (1st ^PGM Loop). When the program of the selected memory cells is not completed even though the first program loop (1st ^PGM Loop) is performed, a second program loop ( ^2nd PGM Loop) may be performed. When the program of the selected memory cells is not completed even though the second program loop (2 ^nd PGM Loop) is performed, a third program loop (3 ^rd PGM Loop) may be performed. In this way, program loops may be repeatedly performed until the program operation is completed.

Meanwhile, when the program operation is not completed even though program loops are repeated up to a predetermined maximum number of program loops, it may be determined that the program operation has failed.

8 is a flowchart illustrating an operating method of a semiconductor memory device according to an exemplary embodiment of the present invention. Selected memory cells are programmed by a method of operating a semiconductor memory device according to an embodiment of the present invention. Referring to FIG. 8 , a method of operating a semiconductor memory device according to an embodiment of the present invention includes performing a program loop on memory cells to be programmed to a target threshold voltage state among selected memory cells ( S110 ) and the selected memory cells. and determining whether the programming for the cells has been completed (S130). In step S110, voltages of bit lines connected to program enable cells and program inhibit cells among the selected memory cells are respectively adjusted, and a program voltage is applied to word lines connected to the selected memory cells to raise the threshold voltage of the program allow cells. include action In addition, in step S110, after applying a program voltage to word lines connected to the selected memory cells, a verify voltage is applied to word lines connected to the selected memory cells to determine whether threshold voltages of the respective memory cells are greater than the verify voltage. further include the action. Exemplary embodiments of step S110 will be described in more detail with reference to FIG. 9 .

Meanwhile, in a method of operating a semiconductor memory device according to an embodiment of the present invention, when programming of selected memory cells is completed (S130: Yes), determining that the program operation of the selected memory cells has succeeded (S140). contains more

In addition, in a method of operating a semiconductor memory device according to an embodiment of the present invention, when programming of selected memory cells is not completed (S130: No), whether the number of program loops performed up to now is less than the maximum number of loops is determined. A step of determining (S150) is further included. During the program operation of the selected memory cells, the program loop of step S110 may be performed a plurality of times. However, in order to prevent infinite repetition of program loops for selected memory cells, the maximum number of loops may be set. Whenever a program loop is executed, the number of executed program loops increases by one. If the program for the selected memory cells is not completed (S130: No), if the number of program loops performed is less than the maximum number of loops (S150: Yes), the program loop is performed again in step S110.

Meanwhile, in an operating method of a semiconductor memory device according to an embodiment of the present invention, when the number of program loops performed so far is not less than the maximum number of loops (S150: No), it is determined that the program operation for the selected memory cells has failed. Step S170 is further included. That is, if the program for the selected memory cells is not completed (S130: No), if the number of program loops performed is greater than or equal to the maximum number of loops (S150: No), no more program loops are performed, and the selected memory cells It is determined that the program operation for has failed (S170).

As described above, according to the method of operating a semiconductor memory device according to an embodiment of the present invention, a program loop is repeatedly performed until programming of selected memory cells is completed. However, if the program is not completed even though the number of program loops performed up to now reaches the maximum number of loops, it is determined that the program operation for the selected memory cells has failed.

9 is a flowchart illustrating an embodiment of step S110 of FIG. 8 . 10 is a graph showing a threshold voltage distribution after a program operation of a single-level cell (SLC). 11 is a flowchart illustrating an embodiment of step S210 of FIG. 9 . Hereinafter, a step of setting a bit line state connected to selected memory cells will be described with reference to FIGS. 9 to 11 together.

Referring to FIG. 9 , performing a program loop on memory cells to be programmed to a target threshold voltage state among selected memory cells ( S110 ) includes setting a selection line state connected to a selection transistor included in a selected memory block. (S200), setting a bit line state connected to the selected memory cells (S210), applying a program voltage to a word line connected to the selected memory cells (S230), and performing a verification operation on the selected memory cells (S230). S250).

In this specification, a selection line may mean at least one of the drain selection line DSL and the source selection line SSL described with reference to FIGS. 4 to 6 . That is, in step S200, the state of at least one of the drain select line DSL and the source select line SSL connected to the selected memory block including the memory cells to be programmed may be set. More specifically, in step S200, a specific voltage may be applied to at least one of the drain select line DSL and the source select line SSL connected to the selected memory block.

Among the selected memory cells, a memory cell whose threshold voltage is to be increased in a current program loop is a program-allowed cell, and a memory cell whose threshold voltage is to be maintained is a program-inhibited cell. Both program enable cells and program inhibit cells are applied to the same word line. When a program voltage is applied to the word line, the voltage of the bit line is adjusted to increase the threshold voltage of the program-allowed cell and maintain the threshold voltage of the program-inhibited cell. In step S210, the voltage of the bit line connected to the program enable cell and the voltage of the bit line connected to the program inhibit cell are adjusted. As shown in FIG. 11 , step S210 includes applying a program enable voltage to a bit line connected to a program enable cell (S211) and applying a program inhibit voltage to a bit line connected to a program inhibit cell (S213). includes In an embodiment, the program inhibit voltage may be greater than the program allow voltage. For example, the program allowable voltage may be a ground voltage. Meanwhile, in FIG. 11 , it is illustrated that step S213 is performed after step S211 is performed, but the present invention is not limited thereto. That is, according to embodiments, step S211 may be performed after step S213, or steps S211 and S213 may be performed simultaneously.

Referring to FIG. 10 , a threshold voltage distribution after a program operation of a single-level cell (SLC) may be divided into an erase state (E) and a program state (PVa). During a read operation, it is determined whether the memory cells are in an erase state (E) or a program state (PVa) by the read voltage (Ra). Meanwhile, threshold voltages of memory cells programmed to the program state PVa are greater than the verification voltage Vvfa.

At the beginning of the program operation, all selected memory cells may have threshold voltages in an erase state (E). Among the selected memory cells, memory cells to be maintained in the erase state (E) become program inhibit cells from the beginning of the program operation. Meanwhile, among the selected memory cells, memory cells to be programmed to the program state PVa become program-allowed cells at the beginning of the program operation.

Applying the program enable voltage to the bit line connected to the program enable cell (S211) and applying the program inhibit voltage to the bit line connected to the program inhibit cell (S213), applying the program voltage to the word line connected to the selected memory cells In step S230, the threshold voltages of the program-allowed cells increase, and the threshold voltages of the program-inhibited cells are maintained. Then, a verification operation is performed on the selected memory cells (S250), and it is determined whether the threshold voltages of the memory cells to be programmed to the program state PVa are higher than the verification voltage Vvfa.

As described above, the threshold voltages of all memory cells to be programmed to the program state PVa at the beginning of the program operation are less than the verify voltage Vvfa. Accordingly, all memory cells to be programmed to the program state PVa become program-allowed cells at the beginning of a program operation. As the program loop is repeatedly performed, the threshold voltage of the program allowable cell increases. Accordingly, the threshold voltages of some program allowable cells become higher than the verification voltage Vvfa. In the step of performing a verification operation on the selected memory cells (S250), the state of the program-allowed cells having a threshold voltage greater than the verification voltage Vvfa is changed to program-inhibited cells. Accordingly, the threshold voltages of the corresponding memory cells do not rise any more in the subsequent program loop.

Meanwhile, according to an embodiment of the present invention, the program operation may be performed using an incremental step pulse programming (ISPP) method. The ISPP method is a method of programming memory cells while gradually increasing a program voltage. Each time the number of executions of the program loop is repeated, the program voltage applied to the word lines connected to the memory cells selected in step S230 may gradually increase.

12 is a flowchart illustrating an embodiment of step S250 of FIG. 9 .

Referring to FIG. 12 , performing a verify operation on selected memory cells (S250) includes applying a verify voltage (Vvfa) to a word line connected to the selected memory cells (S251), and programming the selected memory cells to a program state (PVa). Determining memory cells having a threshold voltage higher than the verification voltage Vvfa among the memory cells to be programmed as program inhibited cells (S253) and a threshold voltage lower than the verification voltage Vvfa among the memory cells to be programmed to the program state PVa. and determining memory cells having ? as program allowable cells (S255).

That is, after the program voltage is applied to the word line connected to the selected memory cells (S230), it is determined whether the threshold voltages of the program allowable cells are higher than the verify voltage Vvfa. To this end, the verification voltage Vvfa is applied to the selected word line (S251), and it is determined whether threshold voltages of program-allowed cells among the selected memory cells are greater than the verification voltage Vvfa.

In operation S253 , among memory cells to be programmed to the program state PVa, memory cells having a threshold voltage higher than the verify voltage Vvfa are determined as program inhibit cells. As shown in FIG. 10 , memory cells having a threshold voltage higher than the verification voltage Vvfa are memory cells sufficiently programmed to belong to the program state PVa. Accordingly, a memory cell having a threshold voltage higher than the verification voltage Vvfa is determined as a program inhibit cell, so that the threshold voltage does not rise in a subsequent program loop.

In operation S255 , among memory cells to be programmed to the program state PVa, memory cells having a threshold voltage lower than the verify voltage Vvfa are determined as program inhibit cells. As shown in FIG. 10 , memory cells having threshold voltages lower than the verification voltage Vvfa are memory cells that do not yet belong to the program state PVa and require additional programming. Accordingly, a memory cell having a threshold voltage lower than the verification voltage Vvfa is determined as a program allowable cell, and the threshold voltage is increased in a subsequent program loop.

13 is a diagram for explaining threshold voltages of a program-allowed cell and a program-inhibited cell.

Referring to FIG. 13 , the threshold voltage of the memory cell at position A is lower than the verification voltage Vvfa. Therefore, the memory cell at position A is a program-allowing cell. The program allowable cell may move to the position (B) as the threshold voltage rises in the next program loop. The threshold voltage of the memory cell at position B is higher than the verification voltage Vvfa. Accordingly, the memory cell moved to the position B is determined as a program inhibit cell, and the threshold voltage does not rise in the next program loop.

According to the exemplary embodiments described with reference to FIGS. 10 to 13 , even in the case of a memory cell having a threshold voltage slightly lower than the verification voltage Vvfa, the threshold voltage moves in a width similar to that of other program-allowed cells. This causes threshold voltages of memory cells belonging to the program state PVa to be widely distributed after the program operation. According to another embodiment of the present invention, a threshold voltage movement width of a program allowable cell having a threshold voltage close to the main verification voltage may be reduced by using a pre-verification voltage and a main verification voltage instead of one verification voltage. Through this, a distribution width of threshold voltages of memory cells belonging to the program state PVa after the program operation may be narrowed.

14 is a graph for explaining a verification operation using a pre-verification voltage Vvf_p and a main verification voltage Vvf_m according to an embodiment of the present invention. According to an embodiment of the present invention, the pre-verification voltage Vvf_p and the main verification voltage Vvf_m may be used to determine threshold voltage states of memory cells to be programmed into the program state PVa. The main verification voltage Vvf_m of FIG. 14 may be substantially the same as the verification voltage Vvfa of FIG. 10 . According to an embodiment of the present invention, a threshold voltage distribution of memory cells after a program operation may be narrowed by additionally using the pre-verification voltage Vvf_p in addition to the main verification voltage Vvf_m.

15 is a flowchart illustrating another embodiment of step S250 of FIG. 9 .

Referring to FIG. 15 , performing a verification operation on selected memory cells (S250) includes applying a pre-verification voltage (Vvf_p) to a word line connected to the selected memory cells (S311), and a word connected to the selected memory cells. Applying the main verification voltage Vvf_m to a line (S313), determining memory cells having a threshold voltage higher than the main verification voltage Vvf_m among memory cells to be programmed to the program state PVa as program inhibited cells (S313). S315) determining memory cells having a threshold voltage lower than the pre-verification voltage Vvf_p, among memory cells to be programmed to the programmed state PVa, as first program allowable cells (S317); Among the memory cells to be programmed, memory cells having a threshold voltage lower than the main verification voltage Vvf_m and higher than the pre-verification voltage Vvf_p are determined as second program allowable cells (S319).

That is, after the program voltage is applied to the word line connected to the selected memory cells (S230), whether the threshold voltage of the program allowable cells is lower than the pre-verification voltage (Vvf_p) or whether the threshold voltage of the program allowable cells is the pre-verification voltage ( Vvf_p) and the main verification voltage Vvf_m, or whether the threshold voltages of the program allowable cells are higher than the main verification voltage Vvf_m. To this end, the pre-verification voltage Vvf_p is applied to the selected word line (S311), and it is determined whether threshold voltages of program-allowed cells among the selected memory cells are greater than the pre-verification voltage Vvf_p. In addition, by applying the main verification voltage Vvf_m to the selected word line (S313), it is determined whether threshold voltages of program-allowed cells among the selected memory cells are greater than the main verification voltage Vvf_m.

In operation S315 , among memory cells to be programmed to the program state PVa, memory cells having a threshold voltage higher than the main verification voltage Vvf_m are determined as program inhibited cells. As shown in FIG. 14 , memory cells having threshold voltages higher than the main verification voltage Vvf_m are memory cells sufficiently programmed to belong to the program state PVa. Accordingly, a memory cell having a threshold voltage higher than the main verification voltage Vvf_m is determined as a program inhibit cell so that the threshold voltage does not rise in a subsequent program loop.

In operation S317 , among memory cells to be programmed to the program state PVa, memory cells having a threshold voltage lower than the pre-verification voltage Vvf_p are determined as first program allowable cells. As shown in FIG. 14 , memory cells having threshold voltages lower than the pre-verification voltage Vvf_p are memory cells that do not yet belong to the program state PVa and require additional programming. Therefore, a memory cell having a threshold voltage lower than the pre-verification voltage Vvf_p is determined as a first program allowable cell, and the threshold voltage is increased in a subsequent program loop.

Meanwhile, in step S319, memory cells having a threshold voltage lower than the main verification voltage Vvf_m and higher than the pre-verification voltage Vvf_p, among memory cells to be programmed to the program state PVa, are determined as second program allowable cells. . As shown in FIG. 14 , memory cells having threshold voltages lower than the main verification voltage Vvf_m and higher than the pre-verification voltage Vvf_p are also memory cells that do not yet belong to the programmed state PVa and require additional programming. to be. Accordingly, a memory cell having a threshold voltage lower than the main verification voltage Vvf_m and higher than the pre-verification voltage Vvf_p is determined as a second program allowable cell, and the threshold voltage is increased in a subsequent program loop.

Referring to FIG. 14 together, the first program allowable cell is a memory cell having a threshold voltage lower than the pre-verification voltage Vvf_p, and the second program allowable cell has a voltage between the pre-verify voltage Vvf_p and the main verify voltage Vvf_m. It is a memory cell having a threshold voltage. That is, the second program allowable cell is a memory cell having a threshold voltage closer to the main verification voltage Vvf_m than the first program allowable cell. Therefore, according to the semiconductor memory device and its operating method according to an embodiment of the present invention, the threshold voltage shift width of the second program allowable cell is controlled to be smaller than the threshold voltage shift width of the first program allowable cell in a subsequent program loop. . To this end, a voltage applied to the bit line connected to the first program allowable cell and a voltage applied to the bit line connected to the second program allowable cell are applied differently. Hereinafter, it will be described with reference to FIG. 16 .

16 is a flowchart illustrating another embodiment of step S210 of FIG. 9 . FIG. 17 is a diagram for explaining threshold voltages of first program permitted cells, second program permitted cells, and program inhibited cells. Hereinafter, a step of setting a bit line state connected to selected memory cells will be described with reference to FIGS. 16 and 17 together.

Referring to FIG. 16 , step S210 includes applying a first program allowable voltage to a bit line connected to a first program allow cell (S331), and applying a second program allow voltage to a bit line connected to a second program allow cell. It may include applying (S333) and applying a program inhibiting voltage to a bit line connected to the program inhibiting cell (S335). In an embodiment, the program inhibit voltage may be greater than the second program allow voltage, and the second program allow voltage may be greater than the first program allow voltage. For example, the first program allowable voltage may be a ground voltage.

Since the first program allowable voltage and the second program allowable voltage are different, when the program voltage is applied to the selected word line (S230), threshold voltage shift widths of the first program allowable cell and the second program allowable cell may be different. More specifically, since the second program allowable voltage is greater than the first program allowable voltage, the threshold voltage shift width of the first program allowable cell is greater than the threshold voltage shift width of the second program allowable cell.

Referring to FIG. 17 , the threshold voltage of the memory cell at position C is lower than the pre-verification voltage Vvf_p. Accordingly, the memory cell at position C is a first program allowable cell. Also, the threshold voltage of the memory cell at position E is higher than the pre-verification voltage Vvf_p and lower than the main verification voltage Vvf_m. Accordingly, the memory cell at position E is a second program allowable cell.

As described above, the first program enable voltage applied to the bit line connected to the first program enable cell is lower than the second program enable voltage applied to the bit line connected to the second program enable cell. Accordingly, the threshold voltage shift width of the first program allowable cell is greater than the threshold voltage shift width of the second program allowable cell. As shown in FIG. 17, the first program-allowing cell at position C moves to position D and becomes a program-inhibiting cell, and the second program-allowing cell at position E moves to position F, It becomes a program prohibition cell. Since the threshold voltage shift of the second program allowable cell at position E is smaller than the threshold voltage shift of the first program allowable cell at position C, the threshold voltage shift of the program inhibit cells at positions D and F is The voltage distribution difference becomes small. As a result, the threshold voltage distribution width of the programmed memory cells narrows.

18 is a graph showing a threshold voltage distribution after a program operation of a multi-level cell (MLC).

Referring to FIG. 18, a multi-level cell (MLC) in which 2 bits are stored per one memory cell has an erase state (E), a first program state (PV1), a second program state (PV2) and a second program state (PV2) after a program operation. It belongs to one of the three program states (PV3). According to an embodiment of the present invention, the pre-verification voltage and the main verification voltage are used during verification operations corresponding to the first to third program states PV1 to PV3 .

For example, according to an embodiment of the present invention, during a verification operation corresponding to the first program state PV1, the first pre-verification voltage Vvf_p1 corresponding to the first program state PV1 and the first main verification voltage (Vvf_m1) is used. Also, during a verification operation corresponding to the second program state PV2, the second pre-verification voltage Vvf_p2 and the second main verification voltage Vvf_m2 corresponding to the second program state PV2 are used. Finally, during a verification operation corresponding to the third program state PV3, the third pre-verification voltage Vvf_p3 and the third main verification voltage Vvf_m3 corresponding to the third program state PV3 are used.

Similarly, in a program operation of a triple-level cell (TLC), the verification operation may be performed using the pre-verification voltage and the main verification voltage for each program state.

19 is a timing diagram for explaining a program operation according to an embodiment of the present invention. More specifically, among the program steps and verification steps of each program loop shown in FIG. 7 , a timing diagram corresponding to the program steps is shown in FIG. 19 . Referring to FIG. 19 , voltages of a word line WL, a bit line BL, a drain select line DSL, and a source select line SSL connected to a memory block selected in a programming step are illustrated. Hereinafter, description will be made with reference to FIGS. 9 and 19 together.

Referring to FIG. 19 , at time t1, the voltage VDSL is applied to the drain select line DSL and the voltage VSSL is applied to the source select line SSL (S200). Thereafter, bit line voltages are applied to bit lines connected to the selected memory block at time t2 (S210). More specifically, the first bit line voltage VBL1 is applied to bit lines connected to memory cells determined to be first program allowable cells in the previous verifying step among the bit lines. Meanwhile, the second bit line voltage VBL2 is applied to bit lines connected to memory cells determined to be second program allowable cells in the previous verifying step among the bit lines. The second bit line voltage VBL2 may be greater than the first bit line voltage VBL1. Also, among the bit lines, the third bit line voltage VBL3 is applied to bit lines connected to memory cells determined to be program inhibit cells in the previous verification step. The third bit line voltage VBL3 is higher than the second bit line voltage VBL2 and may be a program inhibit voltage.

Thereafter, the pass voltage Vpass may be applied to word lines connected to the selected memory block at time t3. Thereafter, at time t4 , the program voltage Vpgm may be applied to a selected word line, which is a word line connected to memory cells to be programmed, among word lines. Through this process, threshold voltages of first and second program allowable cells among the selected memory cells may rise. In this case, the range of rise in the threshold voltage of the first program allowable cells may be greater than the range of increase in the threshold voltage of the second program allowable cells.

According to an embodiment of the present invention, the voltage VDSL applied to the drain select line DSL and the voltage SSL applied to the source select line SSL in the program step while the program operation starts and the program loop is repeatedly performed. ) can be kept constant. In order to improve threshold voltage distribution characteristics of memory cells during a program operation, it is necessary to increase the second bit line voltage VBL2, and the voltage VDSL of the drain select line DSL also increases. In this case, disturb may occur due to leakage current of the drain select line (DSL) in the program inhibit string. Accordingly, there is a need for a program method capable of reducing disturb while improving threshold voltage distribution characteristics of memory cells.

According to another embodiment of the present invention, when program verification of memory cells for a specific program state among a plurality of program states is completed, the voltage applied to the selection line may be lowered in a program step of a subsequent program loop. Taking the MLC shown in FIG. 18 as an example, program states whose distribution is important are the first and second program states PV1 and PV2 between the erase state E and the third program state PV3. Also, during the program operation, the region where the largest disturbance occurs is the third program state PV3 to which a relatively high program voltage is applied. When the target cells are programmed in the third program state PV3, the electric field of the word line is increased compared to the low channel potential, and thus the possibility of occurrence of disturb increases. Accordingly, an operation before completion of program verification for the first and second program states PV1 and PV2 and an operation after completion of program verification for the first and second program states PV1 and PV2 Different methods can be applied. For example, in the program operation of the MLC, a relatively high voltage is applied to a selection line before programming of memory cells to be programmed to the second program state PV2 is completed, and the program is programmed to the second program state PV2. After programming of the memory cells to be programmed is completed, a relatively small voltage may be applied to the selection line.

Through this, a relatively high selection line voltage is applied during the program operation of the memory cells to be programmed in the first and second program states PV1 and PV2 to change the distribution of threshold voltages in the first and second program states PV1 and PV2. After programming of the memory cells to be programmed to the first and second program states PV1 and PV2 is completed, program disturb may be reduced by applying a relatively low selection line voltage to alleviate generation of leakage current in the selection transistor. there is.

20 is a flowchart illustrating an embodiment of step S200 of FIG. 9 .

Referring to FIG. 20 , the step of setting the state of the selection line connected to the selection transistor included in the selected memory block (S200) includes the step of checking the program state of the program completed in the verification step of the previous program loop (S201), When the programming of the memory cells to be programmed into the programmed state is not completed (S203: No), a first voltage may be applied to a selection line connected to the selection transistor (S205). Meanwhile, in the step of setting the state of the selection line connected to the selection transistor included in the selected memory block (S200), when the programming of the memory cells to be programmed to the i-th program state is completed (S203: Yes), the selection line connected to the selection transistor It may include applying a second voltage lower than the first voltage (S207).

The i-th program state may be appropriately selected as needed. For example, in the case of an MLC program operation, the i-th program state may be selected as the second program state PV2. In this case, in step S201, program states that have been verified in the verification step of the previous program loop are checked. As a result of checking, if the programming of the memory cells to be programmed to the second program state PV2 is not completed (S203: No), the first voltage is applied to the selection line connected to the selection transistor (S205). Accordingly, in program loops at the beginning of the program operation, the first voltage may be applied to the selection line connected to the selection transistor.

Conversely, if the programming of memory cells to be programmed to the second program state PV2 is completed (S203: Yes), this means that memory cells that have not yet been programmed are memory cells to be programmed to the third program state PV3. Accordingly, a second voltage lower than the first voltage is applied to the selection line connected to the selection transistor in order to alleviate leakage current in the selection transistor (S207).

In the above, the case where the i-th program state is the second program state in the program operation of the MLC has been described as an example, but the present invention is not limited thereto. In another embodiment, in the program operation of the MLC, the i-th program state may be the first program state.

Also, in the TLC program operation, the i-th program state may be the sixth program state. However, the present invention is not limited thereto, and in the TLC program operation, the i-th program state may be any one of the first to fifth program states.

Meanwhile, the selection transistor of steps S205 and S207 may be either a drain selection transistor or a source selection transistor. When the selection transistor of steps S205 and S207 is a drain selection transistor, the selection line may be a drain selection line. When the selection transistor of steps S205 and S207 is a source selection transistor, the selection line may be a source selection line.

21A is a timing diagram illustrating an operation of a semiconductor memory device according to an exemplary embodiment when programming of memory cells to be programmed to an i-th program state is not completed. 21B is a timing diagram illustrating an operation of the semiconductor memory device according to an exemplary embodiment when programming of memory cells to be programmed to an i-th program state is completed.

Referring to FIG. 21A , since the programming of memory cells to be programmed to the i-th program state is not completed (S203: No), a first voltage VDSL1 is applied to the drain select line DSL at time t5 ( S205), the voltage VSSL is applied to the source select line SSL. Thereafter, bit line voltages are applied to bit lines connected to the selected memory block at time t6 (S210). More specifically, the first bit line voltage VBL1 is applied to bit lines connected to memory cells determined to be first program allowable cells in the previous verifying step among the bit lines. Meanwhile, the second bit line voltage VBL2 is applied to bit lines connected to memory cells determined to be second program allowable cells in the previous verifying step among the bit lines. The second bit line voltage VBL2 may be greater than the first bit line voltage VBL1. Also, among the bit lines, the third bit line voltage VBL3 is applied to bit lines connected to memory cells determined to be program inhibit cells in the previous verification step. The third bit line voltage VBL3 is higher than the second bit line voltage VBL2 and may be a program inhibit voltage.

Thereafter, the pass voltage Vpass may be applied to word lines connected to the selected memory block at time t7 . Thereafter, at time t8 , the program voltage Vpgm may be applied to a selected word line, which is a word line connected to memory cells to be programmed, among word lines.

Referring to FIG. 21B, since the programming of memory cells to be programmed to the ith program state is completed (S203: Yes), the second voltage VDSL2 is applied to the drain select line DSL at time t9, and the source A voltage VSSL is applied to the selection line SSL. The second voltage VDSL2 of FIG. 21B is a voltage lower than the first voltage VDSL1 of FIG. 21A. Thereafter, a bit line voltage is applied to bit lines connected to the selected memory block at time t10. Thereafter, the pass voltage Vpass may be applied to word lines connected to the selected memory block at time t11. Thereafter, at time t12 , the program voltage Vpgm may be applied to a selected word line, which is a word line connected to memory cells to be programmed, among word lines.

21A and 21B , when the programming of memory cells to be programmed to the ith program state is not completed (S203: No), the first voltage VDSL1 is applied to the drain select line DSL, and When the programming of memory cells to be programmed to the i-program state is completed (S203: Yes), an embodiment in which a second voltage VDSL2 lower than the first voltage VDSL1 is applied to the drain select line DSL is illustrated. However, the present invention is not limited thereto, and the voltage of the source select line may be adjusted as shown in FIGS. 23A and 23B.

22 is a graph for explaining an operating method of the semiconductor memory device according to the exemplary embodiment described with reference to FIGS. 21A and 21B from another aspect. Referring to FIG. 22 , as the number of program loops is repeated, the magnitude of the DSL voltage applied to the drain select line in the program stage is shown. At the beginning of the program operation, that is, before the programming of the memory cells corresponding to the ith program state PVi is completed, in the first to Kth program loops, the first voltage VDSL1 is applied to the drain select line DSL. can In FIG. 22 , it is shown that the programming of the memory cells corresponding to the i th program state PVi is completed as the K th program loop is performed. Accordingly, in the (K+1)th program loop and subsequent program loops, the second voltage VDSL2 lower than the first voltage VDSL1 may be applied to the drain select line DSL.

23A is a timing diagram for describing an operation of a semiconductor memory device according to another embodiment when programming of memory cells to be programmed to an i-th program state is not completed. 23B is a timing diagram illustrating an operation of a semiconductor memory device according to another embodiment when programming of memory cells to be programmed to an i-th program state is completed.

Referring to FIG. 23A , since the programming of memory cells to be programmed to the i-th program state is not completed (S203: No), the first voltage VSSL1 is applied to the source select line SSL at time t13 ( S205), the voltage VDSL is applied to the drain select line DSL. Thereafter, bit line voltages are applied to bit lines connected to the selected memory block at time t14 (S210). More specifically, the first bit line voltage VBL1 is applied to bit lines connected to memory cells determined to be first program allowable cells in the previous verifying step among the bit lines. Meanwhile, the second bit line voltage VBL2 is applied to bit lines connected to memory cells determined to be second program allowable cells in the previous verifying step among the bit lines. The second bit line voltage VBL2 may be greater than the first bit line voltage VBL1. Also, among the bit lines, the third bit line voltage VBL3 is applied to bit lines connected to memory cells determined to be program inhibit cells in the previous verification step. The third bit line voltage VBL3 is higher than the second bit line voltage VBL2 and may be a program inhibit voltage.

Thereafter, the pass voltage Vpass may be applied to word lines connected to the selected memory block at time t15. Thereafter, at time t16 , the program voltage Vpgm may be applied to a selected word line, which is a word line connected to memory cells to be programmed, among word lines.

Referring to FIG. 23B , since the programming of memory cells to be programmed to the ith program state is completed (S203: Yes), the second voltage VSSL2 is applied to the source select line SSL at time t17 and drain A voltage VDSL is applied to the selection line DSL. The second voltage VSSL2 of FIG. 23B is a voltage lower than the first voltage VSSL1 of FIG. 23A. Thereafter, bit line voltages are applied to bit lines connected to the selected memory block at time t18. Thereafter, the pass voltage Vpass may be applied to word lines connected to the selected memory block at time t19. Thereafter, at time t20 , the program voltage Vpgm may be applied to a selected word line, which is a word line connected to memory cells to be programmed, among word lines.

23A and 23B , when the programming of memory cells to be programmed to the ith program state is not completed (S203: No), the first voltage VSSL1 is applied to the source select line SSL, and the first voltage VSSL1 is applied to the source select line SSL. When the programming of memory cells to be programmed in the i-program state is completed (S203: Yes), an embodiment in which a second voltage VSSL2 lower than the first voltage VSSL1 is applied to the source select line SSL is shown. However, the present invention is not limited thereto, and the voltage of the drain select line may be adjusted as shown in FIGS. 21A and 21B.

24 is a graph for explaining an operating method of the semiconductor memory device according to the exemplary embodiment described with reference to FIGS. 23A and 23B from another aspect. Referring to FIG. 24 , as the number of program loops is repeated, the level of the SSL voltage applied to the source select line in the program stage is shown. At the beginning of the program operation, that is, before the programming of the memory cells corresponding to the ith program state PVi is completed, in the first to Kth program loops, the first voltage VSSL1 is applied to the source selection line SSL. can In FIG. 24 , it is illustrated that the programming of memory cells corresponding to the i th program state PVi is completed as the K th program loop is performed. Accordingly, the second voltage VSSL2 lower than the first voltage VSSL1 may be applied to the source selection line SSL in the (K+1)th program loop and subsequent program loops.

25 is a flowchart illustrating another embodiment of step S200 of FIG. 9 .

Referring to FIG. 25 , setting the state of the selection line connected to the selection transistor included in the selected memory block (S200) includes checking the program state of the program completed in the verification step of the previous program loop (S202), and When the programming of the memory cells to be programmed into the programmed state is not completed (S204: No), a first voltage may be applied to a selection line connected to the selection transistor (S206). Meanwhile, in the step of setting the state of the selection line connected to the selection transistor included in the selected memory block (S200), when the programming of the memory cells to be programmed to the ith program state is completed (S204: Yes), the selection line connected to the selection transistor It may include applying a second voltage lower than the first voltage (S208).

Referring to the embodiment shown in FIG. 20 , when the programming of memory cells to be programmed to the i-th program state is not completed (S203: No), a first voltage is applied to a selection line connected to a selection transistor (S205); When the programming of the memory cells to be programmed to the ith program state is completed (S203: Yes), a second voltage lower than the first voltage is applied to a selection line connected to the selection transistor (S207).

On the other hand, referring to the embodiment illustrated in FIG. 25 , when the programming of memory cells to be programmed to the ith program state is not completed (S204: No), a first voltage is applied to a selection line connected to the selection transistor (S206). ), when the programming of the memory cells to be programmed to the ith program state is completed (S204: Yes), a second voltage greater than the first voltage is applied to a selection line connected to the selection transistor (S208). That is, according to the embodiment shown in FIG. 25 , in program loops at the beginning of a program operation, a relatively small first voltage is applied to a selection line connected to a selection transistor, and memory cells corresponding to an i-th program state After the program is completed, a relatively large second voltage will be applied.

26 is a block diagram illustrating an example of the controller shown in FIG. 1 .

Referring to FIG. 26 , the controller 200 is connected to the semiconductor memory device 100 and the host HOST. The semiconductor memory device 100 may be the semiconductor memory device described with reference to FIG. 2 .

The controller 200 is configured to access the semiconductor memory device 100 in response to a request from a host. For example, the controller 200 is configured to control read, write, erase, and background operations of the semiconductor memory device 100 . The controller 200 is configured to provide an interface between the semiconductor memory device 100 and a host. The controller 200 is configured to drive firmware for controlling the semiconductor memory device 100 .

The controller 200 includes a RAM 210, a processing unit 220, a host interface 230, a memory interface 240, and an error correction block 250. . The RAM 210 is at least one of an operating memory of the processing unit 220, a cache memory between the semiconductor memory device 100 and the host, and a buffer memory between the semiconductor memory device 100 and the host. used

The processing unit 220 controls overall operations of the controller 200 .

The host interface 230 includes a protocol for exchanging data between a host and the controller 200 . As an exemplary embodiment, the controller 200 may include a Universal Serial Bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, and an Advanced Technology Attachment (ATA) protocol. protocol, Serial-ATA protocol, Parallel-ATA protocol, SCSI (small computer system interface) protocol, ESDI (enhanced small disk interface) protocol, and IDE (Integrated Drive Electronics) protocol, various interface protocols such as private protocols, etc. It is configured to communicate with a host through at least one of them.

The memory interface 240 interfaces with the semiconductor memory device 100 . For example, the memory interface includes a NAND interface or a NOR interface.

The error correction block 250 is configured to detect and correct an error in data received from the semiconductor memory device 100 using an error correction code (ECC). The processing unit 220 adjusts the read voltage according to the error detection result of the error correction block 250 and controls the semiconductor memory device 100 to perform re-reading.

The controller 200 and the semiconductor memory device 100 may be integrated into one semiconductor device. As an exemplary embodiment, the controller 200 and the semiconductor memory device 100 may be integrated into a single semiconductor device to form a memory card. For example, the controller 200 and the semiconductor memory device 100 are integrated into a single semiconductor device such as a personal computer memory card international association (PCMCIA), a compact flash card (CF), or a smart media card (SM, SMC). ), memory stick, multimedia card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), universal flash memory (UFS), etc.

The controller 200 and the semiconductor memory device 100 may be integrated into a single semiconductor device to form a solid state drive (SSD). A semiconductor drive (SSD) includes a memory system 1000 configured to store data in a semiconductor memory. When the memory system 1000 including the controller 200 and the semiconductor memory device 100 is used as a semiconductor drive (SSD), the operating speed of a host connected to the memory system 1000 is remarkably improved.

As another example, the memory system 1000 including the controller 200 and the semiconductor memory device 100 may be used in computers, ultra mobile PCs (UMPCs), workstations, net-books, personal digital assistants (PDAs), Portable computers, web tablets, wireless phones, mobile phones, smart phones, e-books, portable multimedia players (PMPs), Portable game consoles, navigation devices, black boxes, digital cameras, 3-dimensional televisions, digital audio recorders, digital audio players , digital picture recorder, digital picture player, digital video recorder, digital video player, device capable of transmitting and receiving information in a wireless environment, home network One of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, an RFID device, or one of various components constituting a computing system, etc. It is provided as one of the various components of the same electronic device.

As an exemplary embodiment, the semiconductor memory device 100 and a memory system including the semiconductor memory device 100 may be mounted in various types of packages. For example, the semiconductor memory device 100 or memory system may include Package on Package (PoP), Ball Grid Arrays (BGAs), Chip Scale Packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In Line Package (PDIP) ), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline Integrated Circuit Package ( SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP), System In Package (SIP), Multi-Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer-Level Processed Stack Package ( WSP) and the like may be packaged and mounted.

27 is a block diagram illustrating an application example of the memory system of FIG. 26 .

Referring to FIG. 27 , a memory system 2000 includes a semiconductor memory device 2100 and a controller 2200 . The semiconductor memory device 2100 includes a plurality of semiconductor memory chips. A number of semiconductor memory chips are divided into a number of groups.

In FIG. 27 , a plurality of groups are illustrated as communicating with the controller 2200 through the first to k th channels CH1 to CHk, respectively. Each semiconductor memory chip may be configured and operated similarly to the semiconductor memory device 100 described with reference to FIG. 2 .

Each group is configured to communicate with the controller 2200 through one common channel. The controller 2200 is configured similarly to the controller 200 described with reference to FIG. 26 and is configured to control a plurality of memory chips of the semiconductor memory device 2100 through a plurality of channels CH1 to CHk.

FIG. 28 is a block diagram illustrating a computing system including the memory system described with reference to FIG. 27 .

The computing system 3000 includes a central processing unit 3100, a RAM 3200 (RAM, Random Access Memory), a user interface 3300, a power supply 3400, a system bus 3500, and a memory system 2000. .

The memory system 2000 is electrically connected to the central processing unit 3100, the RAM 3200, the user interface 3300, and the power supply 3400 through a system bus 3500. Data provided through the user interface 3300 or processed by the CPU 3100 is stored in the memory system 2000 .

In FIG. 28 , the semiconductor memory device 2100 is illustrated as being connected to the system bus 3500 through the controller 2200 . However, the semiconductor memory device 2100 may be configured to be directly connected to the system bus 3500 . At this time, the function of the controller 2200 will be performed by the central processing unit 3100 and RAM 3200.

In FIG. 28 , the memory system 2000 described with reference to FIG. 27 is shown as being provided. However, the memory system 2000 may be replaced with the memory system 1000 including the controller 200 and the semiconductor memory device 100 described with reference to FIG. 26 .

Embodiments of the present invention disclosed in the present specification and drawings are only presented as specific examples to easily explain the technical content of the present invention and help understanding of the present invention, and are not intended to limit the scope of the present invention. It is obvious to those skilled in the art that other modified examples based on the technical spirit of the present invention can be implemented in addition to the embodiments disclosed herein.

100: semiconductor memory device 110: memory cell array
120: address decoder 130: read and write circuit
140: control logic 150: voltage generator
200: Controller 300: Host
1000: memory system

Claims (20)

A method of operating a semiconductor memory device including a plurality of program loops for programming selected memory cells among a plurality of memory cells, each of the plurality of program loops including a program step and a verify step, the programming step comprising:
setting a state of a selection line connected to a selected memory block including the selected memory cells;
setting a state of a bit line connected to the selected memory block;
applying a program voltage to a selected word line among word lines connected to the selected memory block and applying a pass voltage to an unselected word line;
In the step of setting the state of the selection lines connected to the selected memory block, a voltage is applied to the selection line based on a program progress state of the selected memory cells. The method of claim 1 , wherein each of the plurality of memory cells stores N bits of data,
The step of setting the state of selection lines connected to the selected memory block is:
checking a program state of a program completed in a verification step of a previous program loop; and
and applying a first voltage to the selection line when, as a result of the check, the programming of memory cells to be programmed to the i-th program state is not completed among the first to (2 ^N -1)-th programmed states. Characterized in, a method of operating a semiconductor memory device.
(Where N is a natural number greater than 1, and i is a natural number greater than 0 and less than (2 ^N -1)) 3. The method of claim 2, wherein setting states of selection lines connected to the selected memory block comprises:
and applying a second voltage different from the first voltage to the selection line when programming of the memory cells to be programmed to the i-th programmed state is completed as a result of the check. method. 4. The method of claim 3, wherein the selection line is a drain selection line. 4. The method of claim 3, wherein the selection line is a source selection line. 4. The method of claim 3, wherein the second voltage is lower than the first voltage. 4. The method of claim 3, wherein the second voltage is higher than the first voltage. 3. The method of claim 2, wherein N is 2 and i is 2. 3. The method of claim 2, wherein N is 3 and i is 6. 2. The method of claim 1, wherein the verifying step:
applying a pre-verification voltage to word lines connected to the selected memory cells; and
and applying a main verify voltage higher than the pre-verify voltage to word lines connected to the selected memory cells. 11. The method of claim 10, wherein the verifying step:
The method of operating a semiconductor memory device of claim 1 , further comprising determining memory cells having a threshold voltage higher than the main verification voltage as program inhibit cells. 12. The method of claim 11, wherein the verifying step:
determining memory cells having a threshold voltage lower than the pre-verification voltage as first program allowable cells; and
and determining memory cells having a threshold voltage higher than the pre-verification voltage and lower than the main verification voltage as the second program-allowed cells. 13. The method of claim 12, wherein setting a state of a bit line connected to the selected memory block comprises:
applying a first program enable voltage to a bit line connected to the first program enable cell; and
and applying a second program allowable voltage higher than the first program allowable voltage to a bit line connected to the second program allowable cell. 14. The method of claim 13, wherein setting a state of a bit line connected to the selected memory cells comprises:
The method of operating the semiconductor memory device of claim 1 , further comprising applying a program inhibit voltage higher than the second program inhibit voltage to a bit line connected to the program inhibit cell. a memory block including a plurality of memory cells storing N bits of data per memory cell;
a peripheral circuit that performs a program operation on selected memory cells among a plurality of memory cells included in the memory block; and
A semiconductor memory device including control logic for controlling a program operation of the peripheral circuit,
The program operation includes a plurality of program loops, each of the plurality of program loops includes a program step and a verify step, wherein the control logic in the program step:
setting a state of a selection line connected to the memory block based on a program progress state of the selected memory cells;
set a state of a bit line connected to the selected memory block;
The semiconductor memory device of claim 1 , wherein the peripheral circuit is controlled to apply a program voltage to a selected word line among word lines connected to the selected memory block and a pass voltage to an unselected word line.
(where N is a natural number greater than 1) 16. The method of claim 15, wherein in the process of setting a state of a selection line connected to the memory block based on a program progress state of the selected memory cells, the control logic comprises:
In the verification step of the previous program loop, the status of the completed program is checked,
As a result of the check, if the programming of memory cells to be programmed to the ith program state is not completed among the first to (2 ^N -1) th program states, the peripheral circuit is controlled to apply a first voltage to the selection line. Characterized in that, a semiconductor memory device.
(where i is a natural number greater than 0 and less than (2 ^N -1)) 17. The method of claim 16, wherein in a process of setting a state of a selection line connected to the memory block based on a program progress state of the selected memory cells, the control logic comprises:
As a result of the check, when programming of memory cells to be programmed to the i-th program state is completed among the first to (2 ^N -1)-th program states, a second voltage different from the first voltage is applied to the selection line. A semiconductor memory device characterized in that it controls peripheral circuits. 18. The semiconductor memory device according to claim 17, wherein the selection line is a drain selection line, and the second voltage is lower than the first voltage. 16. The method of claim 15, wherein the control logic in the verification step:
controlling the peripheral circuit to apply a pre-verification voltage to a word line connected to the selected memory cells and to apply a main verify voltage higher than the pre-verification voltage to a word line connected to the selected memory cells;
Memory cells having a threshold voltage higher than the main verify voltage are determined as program inhibit cells, memory cells having a threshold voltage lower than the pre-verify voltage are determined as first program-allowed cells, and memory cells having a threshold voltage lower than the pre-verify voltage are determined as first program-allowed cells, and the main verify voltage is higher than the pre-verify voltage. The semiconductor memory device of claim 1 , wherein memory cells having a lower threshold voltage are determined as the second program allowable cells. 20. The method of claim 19, wherein in the process of setting a state of a bit line connected to the selected memory block, the control logic:
a first program allowable voltage is applied to a bit line connected to the first program allowable cell, and a second program allowable voltage greater than the first program allowable voltage is applied to a bit line connected to the second program allowable cell; The semiconductor memory device of claim 1 , wherein the peripheral circuit is controlled to apply a program inhibiting voltage higher than the second program inhibiting voltage to a bit line connected to an inhibit cell.

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