KR20220170450A - Three-dimensional stacked and type synapse array-based neuromorphic system and manufacturing method and operating method of the same - Google Patents

Abstract

The present invention relates to a three-dimensional stacked AND-type synapse array circuit, a manufacturing method therefor, and an operating method of the synapse array circuit. The three-dimensional stacked AND-type synapse array circuit comprises: a metal wiring including a plurality of bit lines, a plurality of outlines, and a plurality of word lines; a three-dimensional synapse array on which a single layer synapse array in which a unit synapse element is arranged in a column and row is stacked, and which comprises one output selection line (OSL); and a layer-by-layer selection circuit which selects an operating layer among the synapse array, wherein the layer-by-layer selection circuit includes a plurality of synapse selection transistors and a plurality of synapse selection lines (SSL). Therefore, the present invention can have a high degree of integration.

Description

Three-dimensional stacked AND-type synaptic array circuit, manufacturing method thereof, and operation method of synaptic array circuit

An embodiment of the present invention relates to a three-dimensional stacked AND-type synaptic array circuit, a method of manufacturing the same, and a method of operating the synapse array circuit, and more particularly, based on a three-dimensional stacked synapse array configured to be suitable for a deep neural network, and It's about the technology.

In a conventional computing system based on the von Neumann architecture, a memory and a central processing unit (CPU) are separated from each other, and commands are transmitted and executed sequentially through the same bus. It is done. In the von Neumann architecture, data is processed sequentially, so it is difficult to take advantage of parallel operation. In order to solve this problem, a neuromorphic system that imitates neurons and synapses of a biological nervous system has recently been in the limelight. Neuromorphic systems can perform data operations in parallel because numerous neurons and synapses are connected in parallel. Therefore, it has the advantage of dramatically lowering power consumption, and can also be used to implement artificial intelligence, which is attracting attention as a core technology of the 4th industrial revolution.

In order to implement a neuromorphic system, it is necessary to understand how neurons and synapses work. Neurons are largely composed of dentrite, axon, and soma. Dendrites serve as input terminals that receive signals transmitted from presynaptic neurons and transmit them to the cell body. The cell body plays the role of generating a spike called 'action potential' when a threshold is exceeded by temporally and spatially summing up signals received from several dendrites. At this time, the axon serves as an output terminal that transmits the generated spike to a postsynaptic neuron.

The operation of these neurons can generally be implemented through a CMOS circuit.

Synapse refers to the junction between the axon of the former neuron and the dendrite of the posterior neuron, and serves to transmit electrical signals through the secretion and adsorption of neurotransmitters. At this time, the size of the transmitted electrical signal is adjusted according to the connection strength of the synapse. Such connection strength is called synaptic weight, and biological synaptic weight can be changed by learning. When implemented in hardware, the synaptic weight usually means conductance. It is known that human memory is stored by the three-dimensional connection structure of synapses and the synaptic weights of each synapse, and it is known that various cognitive operations are performed from this three-dimensional connection structure of neurons and synapses.

Various semiconductor devices are being researched in order to implement a synapse structure through a semiconductor device. SRAM (Static Random-Access Memory), RRAM (Resistive Random-Access Memory), PCM (Phase-Change Memory), STTMRAM (Spin-Transfer Torque Random-Access Memory), FG Memory (Floating-Gate Memory), CTF Memory ( The operating characteristics of synapses can be implemented using memory devices such as Charge-Trap Flash Memory).

However, the devices reported so far have the following disadvantages. First of all, it is difficult to implement multi-level synaptic weight in SRAM, which is a digital memory. And, since it is a volatile memory, it has a disadvantage in that stored weight information is erased when there is no power. In addition, since SRAM cells are usually implemented with eight transistors, they are disadvantageous in terms of integration. In addition, RRAM, PCM, and STT-RAM have disadvantages in terms of reliability, and thus are memory devices that have not yet been commercialized on a large scale. On the other hand, the CTF device is a commercialized technology currently used for NAND flash memory, and is a non-volatile memory with excellent reliability compared to other memory devices.

In general, as the number of layers in which neurons and synapses are connected increases, a neuromorphic system capable of performing complex cognitive calculations can be implemented. An artificial neural network (ANN) with many layers connected to neurons and synapses is called a deep neural network (DNN), and it is essential to develop a synapse array capable of high integration in order to implement it through hardware.

Korean Patent Registration No. 10-1686827 relates to a method for implementing neuromorphic hardware of such an artificial neural network, and describes signal processing technology of artificial neural network-based neuromorphic hardware using sparse connections and reduced parameters in a large-scale feed-forward network. .

Republic of Korea Patent No. 10-1686827

An embodiment of the present invention provides a three-dimensional stacked AND-type synaptic array circuit suitable for a deep neural network using a CTF device, a manufacturing method thereof, and an operation method of the synaptic array circuit.

A three-dimensional stacked AND-type synapse array circuit according to the present invention for achieving the above object is a plurality of bit lines (BL; Bit Line), a plurality of outline lines (OL; Output Line), and a plurality of word lines (WL; Word). Line) including metal wiring; A three-dimensional synapse array including a single output select line (OSL; Output Select Line) in which a monolayer synapse array in which unit synaptic elements are arranged in columns and rows is stacked; and a layer-by-layer selection circuit for selecting an operating layer from among the synapse array, wherein the layer-by-layer selection circuit includes a plurality of synapse select transistors (SST) and a plurality of synapse select lines (SSL). It is characterized by doing.

In one embodiment, the unit synaptic element includes two CTF memory elements, and the two CTF (Charge-Trap Flash) memory elements drain connected to a bit line through a synaptic selection transistor (SST), and an output selection transistor. It includes a source connected to an outline and a gate connected to a word line through an Output Select Transistor (OST), and the two CTF (Charge-Trap Flash) memory devices share the same word line.

In one embodiment, the plurality of synapse selection lines (SSL) includes as many synapse selection lines as the number of stacked synapse array channels in order to apply a bit line input voltage to each layer of the synapse array, and a plurality of stacked output selection transistors. Is characterized in that connected to one output selection line (OSL).

In one embodiment, the synapse select transistor may include a gate connected to the synapse select line SSL, a drain to which the bit line input voltage is input, and a source connected to each layer of the synapse array.

In one embodiment, the three-dimensional synaptic array includes a gate and a gate dielectric in which polycrystalline silicon serving as a channel and silicon oxide for separating synaptic elements of each layer are alternately stacked, and the stacked polycrystalline silicon and silicon oxide are wrapped around the gate. It is characterized by doing.

In one embodiment, the metal wiring is connected at the top of the three-dimensional synapse array, and the source and drain of the CTF memory device of the same block share a local source line (LSL) and a local drain line (LDL), respectively. to be

In one embodiment, the CTF memory device is characterized in that conductance is changed by Fowler-Nordheim (FN) tunneling.

A method for manufacturing a three-dimensional stacked AND-type synaptic array circuit according to an embodiment of the present invention is to alternately deposit silicon oxide and polycrystalline silicon serving as a channel on a substrate including a layer-by-layer selection circuit region and a synaptic array region, and alternately deposit the uppermost layer. depositing silicon nitride; etching the layer-by-layer selection circuit region and forming layer-by-layer selection circuits using a CMOS process; forming a channel formation trench by performing photolithography and dry etching on the synapse array region; forming a gate dielectric layer in the formed channel formation trench, depositing N+ doped polycrystalline silicon, dry etching to form a gate, and doping with ions to form a source and a drain; After forming an insulating film (ILD) using a gap fill process or chemical vapor deposition, separating the synapse array into blocks by performing photolithography and dry etching; selectively wet etching the polycrystalline silicon etch), and then performing a metal deposition process on the entire surface of the synapse array to form metal contacts in the doped regions of the source and drain; Separating the deposited metal layer layer by layer by performing isotropic etching; performing planarization by filling the gap with silicon oxide; and forming a stepped structure for connecting layer-by-layer selection circuits between the layer-by-layer selection circuit region and the synapse array region, and performing a metal wiring process of the layer-by-layer selection circuit.

In one embodiment, the separating may include separating transistors at both ends of the block as a synaptic selection transistor and an output selection transistor.

As a method of operating a three-dimensional stacked AND-type synaptic array circuit according to an embodiment of the present invention, a voltage is applied to a synaptic selection line to select an operating layer of the synaptic array, and a voltage is applied to each bit line, word line, and outline line. By applying, selecting a specific cell of the selected layer, reading the specific synaptic cell, or programming the specific memory cell in the FN tunneling method, and erasing the specific synaptic cell in the FN tunneling method by changing the voltage condition. do.

In one embodiment, during an FN program operation, after precharging unselected bit lines with a voltage of V _CC,BL to put them in a floating state, a voltage V _PGM,PASS that is not to be FN programmed is applied to unselected word lines. It is characterized in that program prevention of non-selected synaptic cells is performed by boosting the voltage of non-selected BLs.

In one embodiment, it is characterized in that the program prevention of unselected synaptic cells is performed by applying a voltage V _PGM,PASS to which FN programming is not performed to the unselected bit line.

In one embodiment, an erase operation is performed by applying a V _ERS,PASS voltage to non-selected bit lines and applying a V _ERS voltage to a selected word line.

According to the present invention, it is possible to have lower power consumption and higher degree of integration than a NOR-type array through the structure of a three-dimensionally stacked AND-type synapse array suitable for a deep neural network.

1 schematically shows the structure of a conventional AND-type synaptic array based on a CTF memory device.
Figure 2 is a diagram schematically showing the structure of a three-dimensional stacked AND type synaptic array circuit according to an embodiment of the present invention.
Figure 3 schematically shows the structure of a three-dimensional stacked synapse array according to an embodiment of the present invention.
4 is a diagram schematically showing the structure of a neuromorphic system based on a three-dimensional stacked AND-type synaptic array according to an embodiment of the present invention.
5 is an enlarged plan view of a layer-by-layer selection circuit and a synapse array connection unit according to an embodiment of the present invention.
6 is a diagram showing a change in area of a system according to an increase in the number of layers according to an embodiment of the present invention.
7a to 7p show a method for manufacturing a three-dimensional stacked AND-type synaptic array according to an embodiment of the present invention.

Since the present invention can have various changes and various embodiments, specific embodiments will be described in detail with reference to the drawings. However, this is not intended to limit the present invention to specific embodiments, and should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention. Like reference numerals have been used for like elements throughout the description of each figure.

Terms such as first, second, A, and B may be used to describe various components, but the components should not be limited by the terms. These terms are only used for the purpose of distinguishing one component from another. For example, a first element may be termed a second element, and similarly, a second element may be termed a first element, without departing from the scope of the present invention. The term and/or includes a combination of a plurality of related items or any one of a plurality of related items.

It should be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, but other elements may exist in the middle. something to do. On the other hand, when an element is referred to as “directly connected” or “directly connected” to another element, it should be understood that no other element exists in the middle.

Terms used in this application are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, the terms "include" or "have" are intended to designate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, but one or more other features It should be understood that the presence or addition of numbers, steps, operations, components, parts, or combinations thereof is not precluded.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related art, and unless explicitly defined in the present application, they should not be interpreted in an ideal or excessively formal meaning. don't

Throughout the specification and claims, when a part includes a certain component, it means that it may further include other components, not excluding other components unless otherwise stated.

In the following embodiment, a synaptic device is implemented based on a CTF (Charge-Trap Flash) device in order to implement a synapse.

1 schematically shows the structure of a two-dimensional AND-type synaptic array based on a conventional CTF memory device.

Referring to Figure 1, the two-dimensional AND-type synaptic array has a plurality of synaptic cells are arranged in columns and rows.

A synapse cell may be composed of a pair of a CTF element responsible for excitation and a CTF element responsible for inhibition. The two CTF elements constituting this pair are separated, and in each block, the drain of the CTF element is connected to LDL and the source to LSL. CTF elements in each block share LDL and LSL.

Transistors arranged in the same column of the two-dimensional AND-type synapse array and having drains and sources connected to the same bit line and the same outline are called synapse array blocks. That is, transistors included in the synapse array block share a bit line and an outline.

A synapse select transistor (SST) and an output select transistor (OST) necessary for performing an array operation are disposed at both ends of the synapse array block. A gate of the synapse select transistor SST is connected to the synapse select line SSL, and a gate of the output select transistor OST is connected to the output select line OSL.

In the case of implementing a neuromorphic system with a CTF memory device, a NOR type array using a crossbar array has been mainly used. However, due to the structural limitations of the crossbar array, a large amount of energy is consumed by adjusting the conductance of the CTF memory device using hot carrier injection (HCI). To solve this problem, an AND-type array as shown in FIG. 1 may be utilized. When changing the conductance of a CTF memory device in an AND type array, FN tunneling is used. When the conductor of the CTF memory device is changed through FN tunneling, energy consumed for conductance control is reduced compared to HCI. As a result, the neuromorphic system based on the AND type array has higher power efficiency than the neuromorphic system based on the NOR type array.

When a deep neural network is implemented through a neuromorphic system, more synaptic cells are required to implement synaptic weights of synapses constituting each layer of the deep neural network. When implemented through a single-layer synapse array, a large area is required to implement a deep neural network due to the low integration of the synapse array. In order to implement a deep neural network while minimizing an increase in the physical area of such a synapse array, a highly integrated synapse array is required.

In response to this demand, embodiments of the present invention can improve the integration of the overall system and have low power consumption through the structure of a three-dimensionally stacked AND-type synaptic array.

Figure 2 is a diagram schematically showing the structure of a three-dimensional stacked AND type synaptic array circuit according to an embodiment of the present invention.

As shown in FIG. 2 , the 3D stacked AND-type synapse array circuit may include a metal wire, a 3D synapse array 100a, and a layer-by-layer selection circuit 200a. Here, the metal wiring includes a plurality of bit lines BL, a plurality of outline lines OL, and a plurality of word lines WL. In addition, the metal wiring further includes an output selection line (OSL) and a synapse selection line (SSL). The plurality of bit lines BL and the plurality of outline lines OL are arranged in parallel, and the word line WL is arranged perpendicular to the bit line BL.

The three-dimensional synapse array 100 is formed by stacking unit synapse elements arranged in columns and rows and a single-layer synapse array including an output selection transistor at one end.

The layer-by-layer selection circuit 200 is formed of a plurality of synapse selection transistors (SST), and the layer that operates among the three-dimensional synapse array is selected by the synapse selection transistor (SST) corresponding to each layer of the three-dimensional synapse array 100. choose

A unit synaptic cell 110 forming the three-dimensional synaptic array 100 is composed of two CTF memory elements, and the stacked synaptic array circuit is based on an AND-type array.

The two CTF memory elements each perform an excitatory function and an inhibitory function.

In other words, one synaptic cell having two CTF memory elements is referred to as a unit synaptic element 110 . That is, a single-layer synapse array is formed by arranging unit synaptic elements, and the three-dimensional synapse array 100 is formed by stacking the single-layer synaptic array in three dimensions.

The unit synaptic element 110 includes a first CTF memory element 111 and a second CTF memory element 112 . Each CTF memory device has a source, a drain, and a gate. The first CTF memory device 111 has a conductance of G ⁺ , the drain of the first CTF memory device 111 is connected to the bit line BL (+) through the synaptic selection transistor SST, and the first CTF memory device 111 The source of the device 111 is connected to the outline OL(+) through the output selection transistor OST. The second CTF memory device 112 has G ^- conductance, the drain of the second CTF memory device 112 is connected to the bit line BL (-) through the synaptic selection transistor SST, and the second CTF memory device 112 A source of the device 112 is connected to an output line (OL) (-) through a selection transistor OST. The gate of the first CTF memory device 111 and the gate of the second CTF memory device 112 are connected to the same word line WL.

In the unit synaptic element 110, the source serves as an axon and the drain serves as a dendrite. The two drains are positive and negative dendrites, respectively. Positive dendrites can excite the synaptic element, and negative dendrites can perform the inhibitory function of the synaptic element.

The synaptic weight of the synaptic element indicates the connection strength of the synaptic element. The weight of the synaptic element is adjusted by injecting electrons or holes into the charge storage layer region to adjust the conductance, and the learning operation may adjust the weight of each synaptic element in a direction to reduce an output error.

More specifically, when the conductances of each unit synaptic element 110 are G ⁺ , G ^- , the synaptic weight of the unit synaptic element 110 is ω = G ⁺ - G ^- can be expressed At this time, the subtraction operation of the two conductances is performed in the output neuron, and through this, it is possible to express the synaptic weight with a negative sign in the artificial neural network.

The gates of the synapse selection transistors of the layer-by-layer selection circuit 200 are connected to the synapse selection line SSL corresponding to each layer of the synapse array, while the outline OL connects the blocks regardless of the layer.

Figure 3 schematically shows the structure of a three-dimensional stacked synapse array according to an embodiment of the present invention.

The three-dimensional synaptic array has a three-dimensional shape in which channels of each unit synaptic element 110 are vertically stacked, and a structure in which polycrystalline silicon serving as a channel and silicon oxide for separating synaptic elements of each layer are alternately stacked. to be.

The gate and gate dielectrics are formed around stacked silicon oxide and polycrystalline silicon. A connection portion between the layer-by-layer selection circuit 200a and the synapse array region 100a is formed in a stepped structure. At the top of the synapse array, a word line (WL), an output selection line (OSL), and an outline (OL) metal wire are connected. Sources and drains of CTF elements present in the block are shared through LSL and LDL, respectively.

4 is a diagram schematically showing the structure of a neuromorphic system based on a three-dimensional stacked AND-type synaptic array according to an embodiment of the present invention.

Referring to FIG. 4 , a neuromorphic system based on a three-dimensionally stacked AND-type synapse array according to an embodiment includes a three-dimensionally stacked AND-type synapse array 100, a bit line control circuit 300, and an output neuron 400. ), an input decoder 500 and a layer decoder 600. That is, here, the three-dimensionally stacked AND-type synaptic array 100 may be composed of a plurality of synaptic elements that are stacked in three dimensions and share the bit line control circuit 300 and the output neuron 400 with each other.

The bit line control circuit 300 is connected to the LDL of the synaptic array through the selection circuit 200 for each layer. The bit line control circuit 300 is shared by the three-dimensionally stacked AND-type synaptic arrays 100 with each other. The bit line control circuit 300 applies voltages for learning and inference operations to drains of each of a plurality of synaptic devices corresponding to a selected layer.

The output neuron 400 is connected to the LSL of the synaptic array through an output selection transistor (OST). The output neuron 400 is connected to each source of a plurality of synaptic elements corresponding to the selected layer, receives and processes an output signal (voltage or current) during learning and reasoning operations.

The output selection transistor (OST) is configured to be separated from the synaptic cell block through the output selection transistor (OST) Cut.

The input decoder 500 is connected to the word line (WL) and the output selection line (OSL) of the synaptic array, and the operating voltage required when performing learning and reasoning operations of the neuromorphic system is connected to the output selection line (OSL) and the word line (OSL). Input to the synapse array through the line (WL).

The layer decoder (layer decoder) 600 selectively operates the selected layer of the synaptic array 100. The layer decoder 600 inputs voltages required for layer-by-layer operation to the synapse selection line (SSL) of the selected layer. BL voltages input from the bit line control circuit 300 are input to the synapse array 100 according to the SSL input to the selected layer.

5 is an enlarged plan view of a layer-by-layer selection circuit and a synapse array connection unit according to an embodiment of the present invention.

Referring to FIG. 5, in the layer-by-layer selection circuit (200 in FIG. 4), in order to selectively apply a BL input voltage to each layer of the synapse array (100 in FIG. Consists of. In FIG. 5, since the synaptic array channel is formed in three layers, the number of synaptic selection transistors (SST) is three. At this time, since the synapse selection transistors SST are disposed in the BL direction, the area of the synapse array 100 is not affected. That is, even if the number of synapse array channel stacks increases, the layer-by-layer operation can be performed by adding synapse selection transistors (SSTs) to the terminals of the BL by the increased number of stacks.

At this time, the drains of the synaptic selection transistor (SST) are connected to the BL of the bit line control circuit 300, the sources of the synaptic selection transistor (SST) are connected to the LDL of each layer of the synaptic array 100, respectively, and the synaptic selection Gates of the transistor SST are connected to SSLs of the layer decoder 600 .

6 is a diagram showing a change in area of a system according to an increase in the number of layers according to an embodiment of the present invention.

Figure 6 (a) is a plan view showing a three-layer stacked synapse array, Figure 6 (b) is a plan view showing a five-layer stacked synapse array. Referring to FIG. 6 (a) and FIG. 6 (b), when the number of layers of the synapse array increases from 3 to 5, 2 synapse selection transistors (SSTs) should also be added from 3 to 5. Due to the added synaptic selection transistor (SST), the area of the selection circuit for each layer is increased. On the contrary, it can be seen that even if the number of layers is increased, the area of the synaptic array region is maintained because the spacing between elements of the synaptic array is constant. In this way, an increase in the area of the synapse array region due to an increase in the number of layers is minimized through the layer-by-layer selection circuit.

Operating voltages required for layer-by-layer operation of the synapse array illustrated in FIG. 5 are shown in Table 1 below.

1st floor selection 2nd floor selection 3rd floor selection SSL 1 V _SSL 0V 0V SSL 2 0V V _SSL 0V SSL 3 0V 0V V _SSL

Referring to Table 1, the layer decoder 600 applies V _SSL to the SSL connected to the synapse array layer desired to operate, and applies 0V to the remaining SSLs.

For example, in order to operate only the synapse array 100 of the first layer, the SSL1 voltage V _SSL is applied to the gate of the synapse selection transistor (SST) connected to the LDL of the first layer of the synapse array 100, and the synapse array 100 ) SSL2 and SSL3 voltages of 0V are applied to the gates of the synaptic selection transistor (SST) connected to the second and third layer LDL.

Meanwhile, the operation of a neuromorphic system implementing an artificial neural network can be largely divided into learning and inference. Learning is a process of adjusting the synaptic weight of each element of the synaptic array in order to obtain the correct output value as a kind of program operation. Inference is a kind of reading operation, which is the process of checking the output value for a given input.

Next, a learning and reasoning operation method of a three-dimensional stacked synaptic array according to an embodiment of the present invention will be described.

First, since the neuromorphic system was constructed based on the AND-type synaptic array for the learning operation, the conductance of the CTF synaptic device can be controlled through FN tunneling.

Table 2 shows the voltage configuration for the learning and reasoning operation of the synaptic device selected in FIG.

FN Program FN Clear Read (a) (b) SSL Selected V _CC,SSL V _PASS,SSL V _PASS,SSL V _PASS,SSL Unselected 0V 0V 0V 0V BL Selected 0V 0V 0V V _READ,BL Unselected _VCC,BL V _{PGM,PASS VERS,PASS} WL Selected V _PGM V _ERS V _READ,WL Unselected V _PGM,PASS 0V 0V OSL 0V 0V 0V V _{PASS, OSL} OL 0V 0V 0V 0V

When the synaptic weight change of the synaptic cell is performed through the FN program, the FN program (a) and the FN program (b) in Table 2 are classified according to the program inhibition method. FN program (a) precharges non-selected (unselected) BLs with V _CC,BL voltage during FN program operation to put LDL in a floating state, and then uses a voltage high enough to prevent FN programming on non-selected WLs. Apply V _PGM,PASS . Through this, program prevention is performed by boosting the voltages of non-selected LDLs. On the other hand, FN program (b), unlike FN program (a), applies a high voltage V _PGM,PASS to non-selected BLs to prevent FN program. Through this, program prevention of non-selected synaptic cells is performed.

When changing the synaptic weight of a synaptic cell through FN cancellation, a voltage is applied with reference to FN cancellation in Table 2. For example, for selected WL V _ERS and non-selected BL V _{ERS, negative voltages such as -14 V and -7 V are applied as PASS} voltages. The unselected WL and selected BL voltages are 0V.

In the conventional NMOS (N-channel metal oxide semiconductor) based planar CTF device with a substrate electrode, when a voltage lower than the substrate voltage is applied to the source or drain, a PN forward bias is formed due to the voltage applied to the substrate and drain. and cannot be used

On the other hand, since the CTF synaptic array device according to an embodiment of the present invention is a floating body device without a substrate electrode in a three-dimensional stacked structure, such a PN forward bias is not formed. Therefore, it is possible to erase individual CTF elements through the FN erase operation voltage proposed in Table 2. To perform erasure inhibition of non-selected synaptic cells, 0 V is applied to non-selected WLs and V _ERS,PASS is applied to non-selected BLs. Through this, it is possible to perform a selective FN erasure operation of a desired synaptic cell.

Methods for changing the synaptic weight of a synaptic cell include potentiation and depression.

Potentiation means to increase the synaptic weight of a synaptic cell, and depression means to decrease the synaptic weight of a synaptic cell. When potentiation and depression of synaptic cells are performed, there is a method using only FN programming or FN extinction, or a method using both.

The method of performing potentiation and depression using only FN program or FN erase operation is as follows.

In the case of using an NMOS-based CTF device, the threshold voltage increases and the conductance decreases during FN programming. Therefore, the following two methods can be used for potentiation of synaptic cells. First, there is a method of applying an FN program pulse to a CTF device having G ^- conductance (G ⁺ fixed, G ^- decreased, w = G ⁺ - G ^- increased). Second, there is a method of applying an FN erase pulse to a CTF device having G ⁺ conductance (G ⁺ increase, G ^- fixed, w = G ⁺ - G ^- increase).

For synaptic cell depression, the following two methods can be used. First, there is a method of applying an FN program pulse to a CTF device having G ⁺ conductance (G ⁺ decrease, G ^- fix, w = G ⁺ - G ^- decrease). Second, there is a method of applying an FN erase pulse to a CTF device having G ^- conductance (G ⁺ fixed, G ^- increased, w = G ⁺ - G ^- decreased).

The method of changing the synaptic weight of a synaptic cell using both FN program and FN erasure is as follows. When the potentiation operation is performed, an FN erase pulse is applied to a CTF device having G ⁺ conductance, and an FN program pulse is applied to a CTF device having G ^- conductance. Through this, G ⁺ conductance increases and G ^- conductance decreases. As a result, the synaptic weight of the synaptic cell increases (G ⁺ increase, G ^- decrease, w = G ⁺ - G ^- increase). When the depression operation is performed, an FN program pulse is applied to a CTF device having G ⁺ conductance, and an FN erase pulse is applied to a CTF device having G ^- conductance. Through this, G ⁺ conductance decreases and G ^- conductance increases. As a result, the synaptic weight of the synaptic cell increases (G ⁺ decrease, G ^- increase, w = G ⁺ - G ^- decrease).

The inference operation through the designed AND-type synapse array is performed by inputting the read voltage of Table 2 into the synapse array 100a and the layer selection circuit 200a. The input signals are applied to the word lines WL in the form of pulses through an input decoder (500 in FIG. 4). The pulses applied to the WLs are transferred to the output neuron in the form of current through OL+ and OL- of the synapse array through a vector-matrix multiplication operation in the synapse array. The vector-matrix multiplication operation result output through OL+ and OL- is as follows.

[Equation 1]

는 k번째 층의 입력뉴런 i와 출력뉴런 j사이의 시냅스 가중치이다. V_READ는 시냅스 어레이의 BL 들을 통하여 인가되는 전압이다. 각 출력 뉴런 j에서 계산되는 출력은 수학식 2와 같다. In this case, i means the i-th WL (or input neuron), and j means the j-th OL (or output neuron), as shown in FIG. 2 . I _i is the number of pulses applied to the ith WL,

is the synaptic weight between the input neuron i and the output neuron j of the kth layer. V _READ is the voltage applied through the BLs of the synaptic array. The output calculated from each output neuron j is shown in Equation 2.

[Equation 2]

A neuromorphic system through a three-dimensional stacked AND-type synapse array can be implemented using such an operating structure. Finally, the process method of the three-dimensional stacked synapse array proposed is as follows.

7 shows a method of manufacturing a three-dimensional stacked AND-type synapse array according to an embodiment of the present invention.

Referring to FIG. 7A , silicon oxide SiO ₂ and poly-Si are alternately deposited on a Si substrate. On top, silicon nitride Si ₃ N ₄ is deposited.

Silicon oxide is used for isolation between stacked devices, and polysilicon is a region in which a channel is to be formed later. Through this, it can be seen that a synapse array in which channels are stacked later is formed.

Referring to FIG. 7B, except for the synapse array region 100a, silicon oxide, polycrystalline silicon, and silicon nitride are dry etched after photolithography in the region 200a where the peripheral circuit including the layer-by-layer selection circuit is to be formed. do.

Referring to FIG. 7C , a selection circuit for each layer including a synaptic selection transistor and a peripheral circuit are formed on the etched region 200a using a basic CMOS process. The synapse selection transistors are formed in a plurality of lines, and the number of synapse selection transistors corresponding to the number of layers of the synapse array is formed in each line. That is, when the number of layers of the synapse array is three, three synapse select transistors (SSTs) are formed in one line.

Referring to FIG. 7D , a silicon oxide film is filled in the region 200a where the selection circuit for each layer and the peripheral circuit are formed (gap fill). Thereafter, planarization is performed through a chemical mechanical planarization (CMP) process.

The cross section taken along line A-A' in (a) of FIG. 7e is shown in (b) of FIG. 7e, and the cross section taken along line BB' in (a) of FIG. 7e is shown in (c) of FIG. 7e. shown in Referring to FIG. 7E , a channel formation trench (CFT) is formed in a region 100a where a synapse array is to be formed through photolithography and dry etching. At this time, only the open portion of the photoresist is dry etched into a desired shape using a dry etching mask. As a result, a channel forming trench (CFT) is formed.

The cross section taken along line A-A' in (a) of FIG. 7F is shown in (b) of FIG. 7F, and the cross section taken along line B-B' in (a) of FIG. 7F is shown in (c) of FIG. shown in Referring to FIG. 7f, a gate dielectric layer (GL) of a CTF device is formed on the entire surface of the three-dimensional layered synaptic array through chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). At this time, a combination of a plurality of various dielectric thin films as well as SiO ₂ /Si ₃ N ₄ /SiO ₂ commonly used in CTF devices may be used as the gate dielectric. For example, Al ₂ O ₃ /SiO ₂ /Si ₃ N ₄ /SiON can be used for the gate dielectric.

The cross section taken along line A-A' in (a) of FIG. 7g is shown in (b) of FIG. 7g, and the cross section taken along line BB' in (a) of FIG. 7g is shown in (c) of FIG. 7g. shown in Referring to FIG. 7G , a gate material (eg, N+ doped polycrystalline silicon) is deposited in the channel formation trench region where the gate dielectric layer GL is formed, and a gate of the CTF device is formed through dry etching after photolithography.

Then, referring to (c) of FIG. 7G, source and drain doping is performed with the channel of the CTF device having the gate formed therebetween through a doping ion implantation process. At this time, in order to dope all of the stacked polycrystalline silicon not covered by the gated poly-Si through the channel formation trench, when the doping is performed through the ion implanter, the Si substrate is rotated through the ion implanter. . At this time, the ion implanter rotates the Si substrate by setting an appropriate tilt so that doping can be uniformly performed on all vertically stacked devices. Through this, all of the stacked polycrystalline silicon not covered by Gated Poly-Si can be doped.

The cross section taken along line A-A' in (a) of FIG. 7H is shown in (b) of FIG. 7H, and the cross section taken along line B-B' in (a) of FIG. 7H is shown in (c) of FIG. 7H shown in Referring to FIG. 7H , silicon oxide is deposited on the entire upper surface of the three-dimensional stacked synapse array using a chemical vapor deposition method or a gap fill process. Thereafter, a planarization operation is performed through a CMP process. The silicon oxide deposited in this process is later used as a hard mask.

The cross section taken along A-A' in (a) of FIG. 7I is shown in (b) of FIG. 7I, and the cross section taken along B-B' in (a) of FIG. 7I is shown in (c) of FIG. 7I. shown in At this time, A-A' is a cut line including the gate of the CTF element and the selection circuit area 200a for each layer, and B-B' is a cut line including the gate of the CTF element, perpendicular to the A-A' cut line. It's a cut line. Referring to FIG. 7i , blocks of the synapse array are separated through photolithography and dry etching. At the same time, an output select transistor (OST) is cut in the shortest transistor of the synapse array block to form an output select transistor (OST) in the block. At this time, dry etching is performed only on open portions of the photoresist, such as a dry etching mask.

The cross section taken along line A-A' in (a) of FIG. 7j is shown in (b) of FIG. 7j, and the cross section taken along line BB' in (a) of FIG. 7j is shown in (c) of FIG. 7j. shown in At this time, A-A' is a cut line including the gate of the CTF element and the selection circuit area 200a for each layer, and B-B' is a cut line including the gate of the CTF element. It is a vertical cut line. Referring to FIG. 7j , selective wet etching is performed on the polycrystalline silicon of the CTF device. When wet etching is performed, the channel and gate of the CTF device are protected through an oxide hard mask. Through wet etching, a structure in which the polycrystalline-silicon exposed on the side of the synapse array block is dug into the silicon oxide is formed. However, the wet etching time must be adjusted so that the doping region, which will be the source/drain of the CTF device, does not disappear.

The cross section taken along line A-A' in (a) of FIG. 7K is shown in (b) of FIG. 7K, and the cross section taken along line B-B' in (a) of FIG. 7K is shown in (c) of FIG. shown in In this case, A-A' is a cut line including the gate of the CTF element and the layer-by-layer selection circuit region 200a, and B-B' is a cut line perpendicular to the A-A' cut line. Referring to FIG. 7K , a metal deposition process is performed on the entire surface of the 3D stacked synapse array (eg, tungsten CVD). Referring to (c) of FIG. 7K , it can be seen that metal contacts are formed in the doped regions of the source and drain of the synaptic cell. In the current process, the metals of all layers are not separated.

The cross section taken along line A-A' in (a) of FIG. 7L is shown in (b) of FIG. 7L, and the cross section taken along line B-B' in (a) of FIG. 7L is shown in (C) of FIG. shown in Referring to FIG. 7L, isotropic etching (wet etching or chemical dry etching) is performed to separate the deposited metal layer by layer. Through this, OL, LDL, and LSL with each layer separated are formed. At this time, A-A' is a cut line including a gate and a selection circuit for each layer, and B-B' is a cut line perpendicular to the A-A' cut line.

A cross section taken along line A-A' in (a) of FIG. 7M is shown in (b) of FIG. 7M, and a cross section taken along line B-B' in (a) of FIG. 7M is shown in (C) of FIG. shown in Referring to FIG. 7M , an oxide film gap fill process is performed. Thereafter, a planarization operation is performed through a CMP process.

The cross section taken along line A-A' in (a) of FIG. 7N is shown in (b) of FIG. 7N, and the cross section taken along line BB' in (a) of FIG. 7N is shown in (C) of FIG. 7N. shown in A-A' is a cut line including the metal lines (LDL, OL) and the selection circuit area 200a for each layer, and B-B' is a cut line including the gate of the CTF element and the selection circuit area 200a for each layer. .

Referring to FIG. 7N , photolithography and dry etching are sequentially performed as many times as the stacked number to form a stepped structure 200b for connecting bit lines BL and selection circuits for each layer.

Referring to FIG. 7O , a synapse array and a metal wire (ML) of a layer-by-layer selection circuit are formed. The metal wiring process may be formed through photolithography or may be formed using a damascene process.

Referring to Figure 7p, it can be confirmed the wiring arrangement of the three-dimensional stacked synapse array. The metal wires (ML) are arranged parallel or perpendicular to each other in the uppermost region of the stacked synapse array.

In this way, according to the embodiments, power consumption can be lowered and the degree of integration of the system can be improved than that of the NOR-type array through the structure of the three-dimensional stacked AND-type synaptic array suitable for deep neural networks.

The above description is merely an example of the technical idea of the present invention, and various modifications and variations can be made to those skilled in the art without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain, and the scope of the technical idea of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed according to the claims below, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

Claims (10)

a metal wiring including a plurality of bit lines, a plurality of outline lines, and a plurality of word lines;
a three-dimensional synapse array in which unit synapse elements arranged in columns and rows and single-layer synapse arrays including output selection transistors are stacked at one end; and
Layer-by-layer selection circuit with a step-like structure that selects an operating layer from among the synapse array by a synapse selection transistor corresponding to each layer
including,
The layer-by-layer selection circuit comprises a plurality of synapse selection transistors and a plurality of synapse selection lines (SSL), the three-dimensional stacked AND-type synaptic array circuit.
According to claim 1,
The unit synaptic element includes two CTF (Charge-Trap Flash) memory elements,
The two CTF (Charge-Trap Flash) memory devices include a drain connected to a bit line through the synapse select transistor, a source connected to an outline through the output select transistor, and a gate connected to a word line,
The two CTF (Charge-Trap Flash) memory elements are three-dimensional stacked AND-type synapse array circuit, characterized in that sharing the same word line.
According to claim 1,
The plurality of synapse selection lines (SSL) include as many synapse selection lines as the number of stacked synapse array channels in order to apply a bit line input voltage to each layer of the synapse array,
A plurality of stacked output selection transistors are three-dimensional stacked AND-type synaptic array circuit, characterized in that connected to one output selection line (OSL).
According to claim 1,
The synapse selection transistor includes a gate connected to the synapse selection line SSL, a drain to which the bit line input voltage is input, and a source connected to each layer of the synapse array.
According to claim 2,
The CTF memory device is a three-dimensional stacked AND-type synapse array circuit, characterized in that the conductance is changed by FN (Fowler-Nordheim) tunneling.
alternately depositing silicon oxide and polycrystalline silicon serving as a channel on a substrate including a layer-by-layer selection circuit region and a synapse array region, and depositing silicon nitride on top;
etching the layer-by-layer selection circuit region and forming layer-by-layer selection circuits using a CMOS process;
forming a channel formation trench by performing photolithography and dry etching on the synapse array region;
forming a gate dielectric layer in the formed channel formation trench, depositing N+ doped polycrystalline silicon, dry etching to form a gate, and doping with ions to form a source and a drain;
After forming an insulating film (ILD) using a chemical vapor deposition method or a gap fill process, photolithography and dry etching are performed to separate the synaptic array into blocks, and the transistors at both ends of the block are synaptic selection transistors and output selection transistors Separating as;
forming metal contacts in doped regions of source and drain by performing a metal deposition process on the entire surface of the synapse array after selectively wet etching the polycrystalline silicon;
Separating the deposited metal layer layer by layer by performing isotropic etching;
performing planarization by filling the gap with silicon oxide; and
Forming a stepped structure for connecting the layer-by-layer selection circuit between the layer-by-layer selection circuit area and the synapse array region, and performing a metal wiring process of the layer-by-layer selection circuit
Method of manufacturing a three-dimensional stacked AND-type synaptic array circuit comprising a.
A method of operating the three-dimensional stacked AND-type synaptic array circuit of claim 1,
A voltage is applied to the synapse selection line to select an operating layer of the synapse array;
By applying a voltage to each bit line, word line, and outline, a specific cell of the selected layer is selected to read the specific synaptic cell or program the specific memory cell in an FN tunneling method;
A method of operating a three-dimensional stacked AND-type synaptic array circuit, characterized in that by changing the voltage condition to erase a specific synaptic cell by FN tunneling method.
According to claim 7,
During FN program operation, after precharging unselected bit lines with V _CC,BL voltage to make LDL floating,
A three-dimensional stacked AND type characterized in that program prevention of unselected synaptic cells is performed by boosting the voltages of unselected LDLs by applying a voltage V _PGM,PASS to unselected word lines, which will not be FN programmed. Method of operation of synaptic array circuit.
According to claim 7,
A method of operating a three-dimensional stacked AND-type synaptic array circuit, characterized in that performing program prevention of unselected synaptic cells by applying a voltage V _PGM,PASS that will not be FN programmed to an unselected bit line.
According to claim 7,
A method of operating a three-dimensional stacked AND-type synaptic array circuit, characterized by performing an erase operation by applying a V _ERS,PASS voltage to non-selected bit lines and applying a V _ERS voltage to a selected word line.

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