KR20200037049A - Storage device - Google Patents

Abstract

The present invention relates to a storage device with improved performance and reduced cost. According to the present invention, the storage device comprises: a first memory device including a plurality of first memory cells; a second memory device including a plurality of second memory cells of the same type as the plurality of first memory cells; and a controller configured to communicate with a first memory device through a first memory interface and communicate with a second memory device through a second memory interface having an operation speed faster than the operation speed of the first memory interface.

Description

Storage device {STORAGE DEVICE}

The present invention relates to an electronic device, and more particularly, to a storage device.

Recently, artificial intelligence (AI) has been used in various fields. As an example, artificial intelligence functions are used for various functions such as voice recognition and image classification in various electronic devices such as personal computers, laptops, tablets, smart phones, and digital cameras. In general, artificial intelligence functions involve many computational operations. In order to implement such a large number of computational operations, a computational circuit having a high operation speed and a large-capacity high-speed memory for processing data are required. In the related art, artificial intelligence functions are supported by using a separate data center equipped with a high-speed memory and a circuit supporting such high-speed operation.

However, the method using the separate data center consumes a separate cost for using the data center, and there is a problem in that a delay occurs due to data transmission and reception through a network.

The present invention is to solve the above-described technical problems, and according to the present invention, a storage device having improved performance and reduced cost is provided.

A storage device according to an embodiment of the present invention includes a first memory device including a plurality of first memory cells, a second memory device including a plurality of second memory cells of the same type as the plurality of first memory cells, and And a controller configured to communicate with the first memory device through a first memory interface, and to communicate with the second memory device through a second memory interface having an operating speed faster than an operating speed of the first memory interface.

A storage device according to an embodiment of the present invention includes a first controller configured to communicate with an external device through a host interface, a plurality of first memory cells, and communicates with the first controller through a first channel of the first memory interface A first memory device configured to communicate, a second memory device including a plurality of second memory cells of the same type as the plurality of first memory cells, and the first controller and a second channel of the first memory interface And a second controller through the second memory device and the second memory interface.

The storage device according to an embodiment of the present invention includes a first memory device including a plurality of first NAND flash memory cells, a second memory device including a plurality of second NAND flash memory cells, and a first memory interface. And a controller configured to communicate with the first memory device and to communicate with the second memory device through a second memory interface having an input / output bandwidth greater than the first memory interface.

According to the present invention, the storage device may perform a special operation according to a request from the host. Accordingly, a storage device having improved performance and reduced cost and a method of operating the same are provided because the burden of using various data centers or data centers required to perform a special operation is reduced.

1 is a block diagram exemplarily showing a computing system according to an embodiment of the present invention.
FIG. 2 is a block diagram exemplarily showing the first controller of FIG. 1.
3 is a block diagram illustrating the second controller of FIG. 1 by way of example.
4 exemplarily shows a first memory interface circuit of a first controller and a second memory interface circuit of a second controller.
5A to 5D are block diagrams exemplarily showing the first memory device and the second memory device of FIG. 1.
FIG. 6 is a circuit diagram exemplarily showing memory blocks included in the first and second memory devices of FIGS. 5A to 5D.
7 is a flowchart illustrating an operation of the storage device of FIG. 1.
8A to 8D are views for explaining the determination operation of S112 in FIG. 5.
9A and 9B are flowcharts showing details of operations of the host and the storage device of FIG. 1.
10 is a flowchart illustrating an operation of the storage device of FIG. 1.
11 is a block diagram showing a storage device according to an embodiment of the present invention.
12 is a block diagram illustrating the controller of FIG. 11 by way of example.
13 is a flowchart illustrating the operation of the storage device of FIG. 11.
Each of FIGS. 14 to 16 is a block diagram showing a storage device according to an embodiment of the present invention.
17A to 17D are views exemplarily showing a configuration of a storage device according to an embodiment of the present invention.
18 is a block diagram illustrating a computing system according to an embodiment of the present invention.
19 is a block diagram exemplarily showing a mobile system to which a storage device according to the present invention is applied.

Hereinafter, embodiments of the present invention will be described clearly and in detail so that a person having ordinary knowledge in the technical field of the present invention can easily implement the present invention.

The term “unit”, “module”, etc. used in the detailed description or functional blocks illustrated in the drawings may be implemented in the form of hardware, software, or a combination thereof configured to perform a specific function. have.

1 is a block diagram exemplarily showing a computing system according to an embodiment of the present invention. Referring to FIG. 1, the computing system 10 may include a host 11 and a storage device 100. In an exemplary embodiment, the computing system 10 may be one of computing devices performing various computing functions, such as a personal computer, tablet PC, digital camera, smart phone, and the like.

The host 11 may perform various operations necessary for the computing system 10 to operate. In an exemplary embodiment, the host 11 may be a central processing unit (CPU) or an application processor (AP) that performs various operations of the computing system 10. The host 11 may communicate with the storage device 100 through a host interface. The host 11 may store data in the storage device 100 or read data stored in the storage device 100.

In an exemplary embodiment, the host 11 provides data (hereinafter referred to as special data (SDT) special data) for performing a machine learning (ML) function to the storage device 100. You can. For example, as described above, the host 11 may be configured to perform various operations of the computing system 10. At this time, during the operation of the host 11, a specific operation (eg, voice recognition, image classification, image recognition, etc.) for specific data may be required. In this case, the host 11 may provide special data (SDT) to the storage device 100.

In an exemplary embodiment, the special data SDT may not be stored in the nonvolatile form in the storage device 100. The special data SDT may include voice data, image data, or a specific type of data according to the type of special operation performed in the second controller 130.

The storage device 100 may selectively perform any one of a normal operation and a machine learning operation under the control of the host 11. In an exemplary embodiment, the general operation is to store user data (UDT) in the first memory device 120 or read user data (UDT) stored in the first memory device 120 under the control of the host 11. Can point to action. Alternatively, the general operation may refer to various operations (eg, read, write, erase, physical erase, device reset, initialization, etc.) performed in a general storage device. That is, the general operation may refer to an operation performed in a general storage device under the control of the host 11. The special operation may refer to an artificial intelligence operation or machine learning operation based on artificial intelligence functions (eg, convolutional neural network, deep neural network, etc.) such as speech recognition, image classification, image identification, and the like.

In other words, when the storage device 100 performs a normal operation under the control of the host 11, the storage device 100 stores the user data UDT received from the host 11 or the stored user data The (UDT) may be transmitted to the host 11, or other general operations (device reset, initialization, power down, power up, etc.) may be performed. When the storage device 100 performs a special operation under the control of the host 11, the storage device 100 receives the special data (SDT) from the host 11, and for the received special data (SDT) The special operation may be performed and result data RDT including the result of the special operation may be transmitted to the host 11.

The storage device 100 may include a first controller 110, a first memory device 120, a second controller 130, and a second memory device 140. The first controller 110 may control various operations of the storage device 100. The first controller 110 may include an input / output router 111. The input / output router 111 determines whether the request received from the host 11 is related to a general operation or a special operation, and receives information (eg, user data (UDT) from the host 11 according to the determination result) ) Or special data (SDT)) to the first memory device 120 or the second controller 130.

For example, when a request related to a general operation is received from the host 11, the input / output router 111 determines that the input data received with the request is user data (UDT), and receives the user data (UDT). May be transmitted to the first memory device 120 through a normal channel (CH_n). When a request related to a special operation is received from the host 11, the input / output router 111 determines that the input data received with the request is special data (SDT), and receives the received special data (SDT) as a dedicated channel ( It can be transmitted to the second controller 130 through a dedicated channel (CH_d). In an exemplary embodiment, the input / output router 111 may transmit the special data SDT to the first memory device 120, and the first memory device 120 may be configured to store the special data SDT.

In an exemplary embodiment, the first memory interface IF1 may include a plurality of channels, one of the plurality of channels may be a normal channel (CH_n), and the other one may be a dedicated channel (CH_d). You can. In an exemplary embodiment, each of the plurality of channels included in the first memory interface IF1 may indicate an independently driven communication path, and each of the plurality of channels may be connected to each other based on the same communication method. Can communicate with others.

In an exemplary embodiment, the input / output router 111 receives a request received from the host 11 based on various information (eg, address information, logical unit information, command information, etc.) from the host 111 in general operation. It may be determined whether or not related to the special operation, or it may be determined whether the input data received from the host 11 is user data (UDT) or special data (SDT).

The first memory device 120 may perform a general operation according to the control of the first controller 110 through the general channel CH_n. For example, the first memory device 120 may receive user data UDT from the first controller 110 through a normal channel CH_n, and store or program the received user data UDT.

The second controller 130 may perform a special operation according to the control of the first controller 110 through a dedicated channel (CH_d). For example, the second controller 130 may be configured to support machine learning functions such as speech recognition, image classification, image identification, and the like. The second controller 130 may receive the special data SDT from the first controller 110 through the dedicated channel CH_d, and perform a special operation on the received special data SDT. The second controller 130 may provide the result data RDT including a result of performing a special operation to the first controller 110 through a dedicated channel CH_d under the control of the first controller 110.

In an exemplary embodiment, the second controller 130 may perform the above-described special operation using the weight WT stored in the second memory device 140 in the second memory interface IF2. For example, the second controller 130 needs weight (WT) information to perform a supported special operation. When the special operation is performed, the second controller 130 may perform the above-described special operation based on the weight WT stored in the second memory device 130.

In an exemplary embodiment, the first and second memory devices 120 and 140 may be memory devices having the same cell type, respectively. For example, the first and second memory devices 120 and 140 may include a NAND flash memory cell, or a charge trap flash (CTF) cell, and may operate at different operating speeds.

In an exemplary embodiment, the first and second memory devices 120 and 140 may be NAND flash memory devices, but the scope of the present invention is not limited thereto. For example, each of the first and second memory devices 120 and 140 may be any one of nonvolatile memory devices such as NAND flash memory, PRAM, MRAM, and RRAM. Alternatively, the operating speed of the second memory device 140 may be faster than the operating speed of the first memory device 120. In an exemplary embodiment, the second memory device 140 may be a high-speed memory such as DRAM.

In an exemplary embodiment, each of the first controller 110, the first memory device 120, the second controller 130, and the second memory device 140 is a separate semiconductor device, a separate semiconductor chip, and a separate It may be implemented as a semiconductor die or a separate semiconductor package. Alternatively, some of the first controller 110, the first memory device 120, the second controller 130, and the second memory device 140 are one semiconductor device, one semiconductor chip, one semiconductor die, or It can be implemented as a single semiconductor package. For example, the second controller 130 and the second memory device 140 may be implemented as one semiconductor package, and the second controller 130 and the second memory device 140 may be implemented in one semiconductor package. They can be connected to each other through high-speed signal lines (for example, through silicon via (TSV)).

In an exemplary embodiment, the normal channel (CH_n) between the first controller 110 and the first memory device 120; And the dedicated channel (CH_d) between the first controller 110 and the second controller 130 may be channels included in the first memory interface IF1. That is, each of the first memory device 120 and the second controller 130 may communicate with the first controller 110 based on the same interface. In an exemplary embodiment, the first memory interface IF1 may be a NAND interface, but the scope of the present invention is not limited thereto.

In an exemplary embodiment, the second controller 130 and the second memory device 140 may communicate with the first memory interface IF1 based on another second memory interface IF2. The second memory interface IF2 may be an interface that supports a faster operation speed than the first memory interface IF1. For example, the amount of data transmitted per hour of the second memory interface IF2 may be greater than the amount of data transmitted per hour of the first memory interface IF1. That is, the second controller 130 can rapidly read the weight WT stored in the second memory device 140.

As described above, the storage device 100 according to an embodiment of the present invention may support a machine learning function. Accordingly, since the computational load performed on the host 11 is reduced or a separate data center is not required, a storage device having improved performance and reduced cost is provided.

2 is a block diagram illustrating the first controller 110 of FIG. 1 by way of example. Referring to FIG. 2, the first controller 110 includes an input / output router 111, a processor 112, an SRAM 113, a ROM 114, a host interface circuit 115, and a first memory interface circuit 116. It can contain.

The input / output router 111 may determine whether the request (or data) provided from the host 11 is related to a general operation or a special operation. The determination operation of the input / output router 111 will be described in more detail with reference to the following drawings.

The processor 112 may perform various operations of the first controller 110. The SRAM 113 may be used as an operation memory or a buffer memory of the first controller 110. The ROM 114 may store various information necessary for the first controller 110 to operate in the form of firmware. In an exemplary embodiment, the input / output router 111 may be implemented in the form of software, hardware, or a combination thereof. When the input / output router 111 is implemented in software form, program code or instructions for performing the operation of the input / output router 111 are stored in the SRAM 113 and may be executed by the processor 112. In an exemplary embodiment, the operation of the input / output router 111 may be performed by a Flash Translation Layer (FTL).

The first controller 110 may communicate with the host 11 through the host interface circuit 115. In an exemplary embodiment, the host interface circuit 115 includes Double Data Rate (DDR), Low-Power DDR (LPDDR), Universal Serial Bus (USB), multimedia card (MMC), peripheral component interconnection (PCI), PCI- E (PCI-express), ATA (Advanced Technology Attachment), SATA (Serial-ATA), PATA (Parallel-ATA), SCSI (small computer small interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics) , MIPI (Mobile Industry Processor Interface), NVM-e (Nonvolatile Memory-express), UFS (Universal Flash Storage), and the like.

The first controller 110 can communicate with the first memory device 120 and the second controller 130 through the first memory interface circuit 116. In an exemplary embodiment, the first memory interface circuit can be based on a NAND interface. The first controller 110 may communicate with the first memory device 120 through the general channel CH_n of the first memory interface circuit 116, and a dedicated channel CH_d of the first memory interface circuit 116 Through it may communicate with the second controller 130. The first memory interface circuit 116 may output data received from the host 11 through one of the normal channel CH_n and the dedicated channel CH_d according to the determination result of the input / output router 111.

In an exemplary embodiment, the first controller 110 may use a program command to transmit user data (UDT) to the first memory device 120 or special data to the second controller 130. . That is, the first controller 110 may transmit the program command and user data UDT to the first memory device 120 through the normal channel CH_n. The first controller 110 may transmit program commands and special data (SDT) to the second controller 130 through a dedicated channel (CH_d).

3 is a block diagram illustrating the second controller of FIG. 1 by way of example. 1 and 3, the second controller 130 may include a controller interface circuit 131, a machine learning core 132, a second memory interface circuit 133, and an ECC engine 134. .

The second controller 130 may communicate with the first controller 110 through the controller interface circuit 131. For example, the controller interface circuit 131 may communicate with the first memory interface circuit 116 of the first controller 110 through a dedicated channel (CH_d). In an exemplary embodiment, the controller interface circuit 131 receives special data SDT from the first memory interface circuit 116 or through the dedicated channel CH_d, or results data to the first memory interface circuit 116. (RDT).

The machine learning core 132 may perform a special operation on the special data SDT received from the controller interface circuit 131. In an exemplary embodiment, the machine learning core 132 may perform a special operation on the special data SDT using the weight WT stored in the second memory device 140.

For example, the second memory interface circuit 133 may read the weight WT from the second memory device 140 under the control of the machine learning core 132. The weight WT may be corrected by the ECC engine 134, and the weight WT ′ corrected for the error may be provided to the machine learning core 132. The machine learning core 132 may perform a special operation on the special data SDT using the error corrected weight WT '.

Hereinafter, in order to easily describe the technical features of the present invention, it is assumed that the special operation performed by the machine learning core 132 is a voice recognition operation. That is, the special data (SDT) provided from the host 11 is voice data, and the machine learning core 132 performs a special operation (ie, voice recognition operation) on the special data (SDT), resulting in Data RDT can be output. In this case, the result data RDT may be text data corresponding to voice data.

The machine learning core 132 may include a feature extraction module 132a, an acoustic model 132b, and a decoding module 132c. The feature extraction module 132a may perform a feature extraction operation on the received special data (SDT) and provide frame-based information to the acoustic model 132b. The acoustic model 132b may perform speech recognition for information on a frame-by-frame basis using an error corrected weight WT '. The decoding module 132c may receive a speech recognition result from the acoustic model 132b, and output result data RDT (that is, text data) corresponding to the received speech recognition result. In an exemplary embodiment, the above-described operations of the machine learning core 132 may be based on artificial intelligence algorithms such as machine learning algorithms, neural network algorithms, and the like. In an exemplary embodiment, the machine learning core 132 may include at least one multiply accumulate (MAC) operator for performing the special operation described above. That is, the machine learning core 132 may be configured to perform the above-described special operation by performing the MAC operation on the weight (WT) and frame-based information described above through at least one multiply accumulate (MAC) operator. .

In the exemplary embodiment, it is assumed that the frame unit is 10 ms, and the weight WT used in the acoustic model 132b has a size of 100 MB. In this case, in order for the machine learning core 132 to perform a special operation (ie, a voice recognition operation) normally, a weight WT of 100 MB should be provided to the acoustic model 132b every 10 ms. That is, the second controller 130 should read the weight WT of 100 MB from the second memory device 140 every 10 ms. To this end, the second memory interface circuit 133 may be implemented as a high speed interface.

For example, FIG. 4 is a diagram exemplarily showing the first memory interface circuit 116 of the first controller 110 and the second memory interface circuit 133 of the second controller 130. As illustrated in FIG. 4, the first memory interface circuit 116 may be implemented as a general NAND interface, but the scope of the present invention is not limited thereto.

For example, the first memory interface circuit 116 may include a chip enable signal CE, an address latch enable signal ALE, a command latch enable signal CLE, a write enable signal WE /, and a read in The enable signal RE / may be provided to the first memory device 120 or the second controller 130, and data signals DQ [1: i] (where i is an integer greater than 1) and data The strobe signal DQS may be exchanged with the first memory device 120 or the second controller 130. In an exemplary embodiment, signals associated with the first memory interface circuit 116 shown in FIG. 4 are signals corresponding to one channel (eg, one of the normal channel CH_n and the dedicated channel CH_d). It is a composition. The first memory device 120 or the second controller 130 may receive user data (UDT) or special data (SDT) from the first controller 110 through the signal configuration illustrated in FIG. 4.

The second memory interface circuit 132 includes a chip enable signal CE, an address latch enable signal ALE, a command latch enable signal CLE, a write enable signal WE /, and a read enable signal RE /) To the second memory device 140, and the data signals DQ [1: k] (where k is an integer greater than i) and the data strobe signal DQS to the second memory device 140. ). At this time, the number of data signals DQ [1: k] of the second memory interface circuit 132 is greater than the number of data signals DQ [1: i] of the first memory interface circuit 116. You can. In other words, the data input / output band of the second memory interface circuit 133 may be larger than the data input / output band of the first memory interface circuit 116. Therefore, the operating speed of the second memory interface circuit 133 may be faster than the operating speed of the first memory interface circuit 116. Accordingly, the second controller 130 can read the weight WT from the second memory device 140 at high speed.

The configuration of the first and second memory interface circuits 116 and 133 described with reference to FIG. 4 is exemplary, and the scope of the present invention is not limited thereto. The first and second memory interface circuits 116 and 133 may be implemented in a different manner from the signal configuration shown in FIG. 4.

5A to 5D are block diagrams exemplarily showing the first memory device and the second memory device of FIG. 1. FIG. 6 is a circuit diagram exemplarily showing memory blocks included in the first and second memory devices of FIGS. 5A to 5D.

First, referring to FIGS. 1, 4, and 5A, the first memory device 120 may include first and second planes PL1 and PL2 and an input / output circuit 121. The first and second planes PL1 and PL2 may each include a plurality of memory blocks. The input / output circuit 121 is connected to the first and second planes PL1 and PL2, and an external device (for example, i is an integer greater than 1) through a plurality of data lines DQ1 to DQi. , It can exchange data with the first controller 110. For example, the input / output circuit 121 may include a plurality of data signal pins respectively connected to the plurality of data lines DQ1 to DQi.

Next, referring to FIGS. 1, 4, and 5B, the second memory device 140 may include a plurality of planes PL1 to PLn and an input / output circuit 141. Each of the plurality of planes PL1 to PLn (where n is an integer greater than 1) may include a plurality of memory blocks. The input / output circuit 141 of the second memory device 140 is connected to a plurality of planes PL1 to PLn, and is external through a plurality of data lines DQ1 to DQk (where k is an integer greater than i). Data may be exchanged with a device (eg, the second controller 130). For example, the input / output circuit 141 may include a plurality of data signal pins respectively connected to the plurality of data lines DQ1 to DQk.

5A and 5B, the number of planes included in the second memory device 140 may be greater than the number of planes included in the first memory device 120. In an exemplary embodiment, the plane may refer to a set of memory blocks sharing the same bit lines. That is, memory blocks included in one plane can share the same bit lines with each other.

In an exemplary embodiment, the number of data signal pins (ie, the number of DQ pins) of the second memory device 140 is greater than the number of data signal pins (ie, the number of DQ pins) of the first memory device 120. It can be many. Alternatively, the number of data lines of the second memory device 140 may be greater than the number of data lines of the first memory device 120. That is, the second memory device 140 may exchange data with an external device at a faster rate than the first memory device 120.

In an exemplary embodiment, since the number of planes of the second memory device 140 is greater than the number of planes of the first memory device 120, DQ signal pins of the first and second memory devices 120 and 140 The arrangement of can be different. For example, as illustrated in FIG. 5C, DQ signal pins (ie, DQ pads) DQ1 to DQi of the first memory device 120 are in the edge area EDGE of the first memory device 120. Can be deployed. On the other hand, DQ signal pins (ie, DQ pads) DQ1 to DQk of the second memory device 140 may be disposed in the center area CENTER of the second memory device 140. As the DQ signal pins DQ1 to DQk of the second memory device 140 are disposed in the center area CENTER of the second memory device 140, the DQ signal pins DQ1 to DQk and a plurality of planes PL1 ~ PLn) is reduced, and accordingly, high-speed operation of the second memory device 140 may be possible.

In an exemplary embodiment, as illustrated in FIG. 5D, the second memory device 140-1 may further include a multiply accumulate module (MAC) module 142. The MAC module 142 is configured to perform a MAC operation on the weight WT stored in the second memory device 140-1 and output the result of the MAC operation through a plurality of data lines DQ1 to DQk. You can. For example, as described with reference to FIG. 3, the machine learning core 132 of the second controller 130 may be configured to perform a MAC operation on the weight WT. At this time, when the second memory device 140-1 outputs the result of the MAC operation on the weight WT, the computational load on the MAC operation to be performed on the second controller 130 can be reduced. That is, the MAC module may be included in the second memory device 140 or the second controller 120 according to the implementation method of the storage device 100.

In an exemplary embodiment, each of the plurality of memory blocks included in the planes of each of the first and second memory devices 120 and 140 includes memory cells of the same cell-type (eg, CTF) with each other. can do. For example, each of the plurality of memory blocks included in the planes of the first and second memory devices 120 and 140 may have a structure similar to the memory block BLK shown in FIG. 6.

 Illustratively, a memory block having a three-dimensional structure is described with reference to FIG. 6, but the scope of the present invention is not limited thereto. The memory block according to the present invention may have a two-dimensional memory block structure. For example, the memory block illustrated in FIG. 6 may be a physical erase unit of each of the first and second memory devices 120 and 140. However, the scope of the present invention is not limited thereto, and the erase unit may be modified in units of pages, word lines, and sub-blocks.

Referring to FIG. 6, the memory block BLK includes a plurality of cell strings CS11, CS12, CS21, and CS22. The plurality of cell strings CS11, CS12, CS21, and CS22 may be arranged along a row direction and a column direction to form rows and columns.

Each of the plurality of cell strings CS11, CS12, CS21, and CS22 includes a plurality of cell transistors. For example, each of the plurality of cell strings CS11, CS12, CS21, and CS22 includes string select transistors SSTa and SSTb, a plurality of memory cells MC1 to MC8, and ground select transistors GSTa and GSTb. And dummy memory cells DMC1 and DMC2. For example, each of the plurality of cell transistors included in the plurality of cell strings CS11, CS12, CS21, and CS22 may be a charge trap flash (CTF) memory cell.

The memory cells MC1 to MC8 are connected in series, and are stacked in a height direction, which is a direction perpendicular to a plane formed by the row direction and the column direction. The string select transistors SSTa and SSTb are connected in series, and the string select transistors SSTa and SSTb connected in series are provided between the plurality of memory cells MC1 to MC8 and the bit line BL. The ground selection transistors GSTa and GSTb are connected in series, and the series connected ground selection transistors GSTa and GSTb are provided between the plurality of memory cells MC1 to MC8 and the common source line CSL.

For example, the first dummy memory cell DMC1 may be provided between the plurality of memory cells MC1 to MC8 and the ground selection transistors GSTa and GSTb. For example, the second dummy memory cell DMC2 may be provided between the plurality of memory cells MC1 to MC8 and the string select transistors SSTa and SSTb.

The ground select transistors GSTa and GSTb of the cell strings CS11, CS12, CS21, and CS22 may be commonly connected to the ground select line GSL. For example, ground select transistors in the same row may be connected to the same ground select line, and ground select transistors in another row may be connected to a different ground select line. For example, the first ground select transistors GSTa of the cell strings CS11 and CS12 of the first row may be connected to the first ground select line, and the cell strings CS21 and CS22 of the second row may be connected. The first ground selection transistors GSTa may be connected to the second ground selection line.

Illustratively, although not shown in the drawings, ground selection transistors provided at the same height from a substrate (not shown) may be connected to the same ground selection line, and ground selection transistors provided at different heights may be connected to different ground selection lines. You can.

Memory cells of the same height from the substrate or ground selection transistors GSTa and GSTb are commonly connected to the same word line, and memory cells of different heights are connected to different word lines. For example, the first to eighth memory cells MC8 of the cell strings CS11, CS12, CS21, and CS22 are commonly connected to the first to eighth word lines WL1 to WL8, respectively.

The string select transistors of the same row among the first string select transistors SSTa of the same height are connected to the same string select line, and the string select transistors of the other row are connected to another string select line. For example, the first string select transistors SSTa of the cell strings CS11 and CS12 in the first row are commonly connected to the string select line SSL1a and the cell strings CS21 and CS22 in the second row. ), The first string select transistors SSTa are commonly connected to the string select line SSL1a.

Similarly, the string select transistors of the same row among the second string select transistors SSTb of the same height are connected to the same string select line, and the string select transistors of the other row are connected to another string select line. For example, the second string select transistors SSTb of the cell strings CS11 and CS12 in the first row are commonly connected to the string select line SSL1b and the cell strings CS21 and CS22 in the second row. ), The second string select transistors SSTb are commonly connected to the string select line SSL2b.

For example, dummy memory cells of the same height are connected to the same dummy word line, and dummy memory cells of different heights are connected to another dummy word line. For example, the first dummy memory cells DMC1 are connected to the first dummy word line DWL1, and the second dummy memory cells DMC2 are connected to the second dummy word line DWL2.

For example, the memory block BLK illustrated in FIG. 6 is exemplary, and the number of cell strings may increase or decrease, and the number of rows and columns of the cell strings may increase or decrease according to the number of cell strings, or Can decrease. In addition, the number of cell transistors (GST, MC, DMC, SST, etc.) of the memory block BLK may be increased or decreased, respectively, and the height of the memory block BLK may be increased or decreased according to the number of cell transistors. can do. Also, the number of lines (GSL, WL, DWL, SSL, etc.) connected to the cell transistors may be increased or decreased according to the number of cell transistors.

7 is a flowchart illustrating an operation of the storage device of FIG. 1. Hereinafter, in order to easily describe the technical idea of the present invention, it is assumed that the storage device 100 receives a write request and data from the host 11. However, the scope of the present invention is not limited thereto.

1 and 7, in step S111, the storage device 100 may receive a write request and input data from the host 11. For example, the host 11 may transmit a write request to the storage device 100 in order to transmit input data (eg, user data or special data) to the storage device 100.

In step S112, the storage device 100 may determine whether the received write request is related to a special operation. For example, the input / output router 111 of the first controller 110 of the storage device 100 receives a write request received based on address information, logical unit information, or attribute of the write request corresponding to the received write request. It can be determined whether it is related to the general operation or the special operation. The operation of step S112 will be described in more detail with reference to FIGS. 8A to 8D.

When the received write request is not related to a special operation (that is, when the received write operation is related to a general operation), in step S113, the storage device 100 first memory device through the normal channel (CH_n) A write operation (or program operation) for 130 may be performed. For example, the first controller 110 transmits the received input data (that is, user data (UDT)) to the first memory device 130 in response to a write request received from the host 11, and 1 The memory device 130 may perform a program operation on the received user data (UDT).

In step S114, the storage device 100 may transmit a result of the write request to the host 11. For example, the first controller 110 receives a result (eg, a program pass / fail) of a program operation to the first memory device 130, and writes information corresponding to the received result to a request for writing. It can be sent to the host 11 as a response. In an exemplary embodiment, when the result of the program operation on the first memory device 130 is a program fail, the storage device 100 may perform the program operation on user data again.

When the judgment result of step S112 indicates that the received write request is related to a special operation, in step S115, the storage device 100 provides input data (ie, special data (SDT)) through a dedicated channel (CH_d). 2 can be transmitted to the controller 130.

In operation S116, the storage device 100 may perform a special operation on the special data SDT using the weight WT stored in the second memory device 140. For example, the second controller 130 reads the weight WT from the second memory device 140 through the second memory interface IF2, and uses the read weight WT, the first memory interface IF1 ) May perform a special operation on the special data SDT provided through the dedicated channel CH_d.

In an exemplary embodiment, as described above, the first controller 110 may use a program command to provide special data (SDT) to the second controller 130. That is, the second controller 130 receives the program command and special data (SDT) through the dedicated channel (CH_d) from the first controller 110, and in response to the received program command, for the special data (SDT) A special operation can be performed.

In step S117, the storage device 100 may transmit a response to the host 11. For example, when the second controller 130 completes the special operation, the first controller 110 of the storage device 100 may transmit a response to the received write request to the host 11.

In step S118, the storage device 100 may receive a read request for a special operation from the host 11. For example, the host 11 responds to a response from the storage device 100 (that is, a response indicating completion of the special operation), and the storage device issues a read request to read the result data RDT for the special operation. It can be transmitted to (100). In an exemplary embodiment, the read request in step S118 includes dedicated address information, dedicated logical unit information, or the like for accessing the second controller 130 to be described with reference to FIGS. 8A to 8D below, or a dedicated read request Can be

In step S119, the storage device 100 may transmit the result of the special operation (that is, the result data RDT) to the host 11 in response to the received read request.

8A to 8D are views for explaining the determination operation of S112 in FIG. 5. For the sake of brevity, elements unnecessary for describing the technical idea of the present invention are omitted. In the exemplary embodiment, the embodiments illustrated in FIGS. 8A to 8D are exemplary, and the scope of the present invention is not limited thereto.

First, referring to FIG. 8A, the host 11 may include a host application 11a and a device driver 11b. The host application 11a may include an operating system (OS) or various user programs running on the host 11.

The device driver 11b may be configured to access the storage device 100 at the request of the host application 11a. For example, the device driver 11b identifies information provided from the application 11a to the host so that the operation requested by the host application 11a can be performed in the storage device 100, and information that can be identified in the storage device 100 It can be configured to convert to or manage. In an exemplary embodiment, dedicated address information, dedicated logical unit information, dedicated requests, etc. described with reference to FIGS. 8B to 8D may be converted or managed by the device driver 11b.

Next, referring to FIGS. 1, 8A, and 8B, the host 11 may recognize the storage area of the storage device 100 as illustrated in FIG. 8B. For example, the storage space of the storage device 100 may include a user area and a dedicated area. The user area may correspond to a space in the storage device 100 that can store user data (UDT), and the dedicated area may correspond to a predetermined separate space or virtual space.

The host 11, and more specifically, the host application 11a of the host 11 may perform access to a user area of the storage device 100. That is, the host application 11a may perform operations such as data writing, reading, and erasing of a user area of the storage device 100.

On the other hand, the device driver 11b of the host 11 may recognize a user area and a dedicated area of the storage device 100. When the host application 11a requests a general operation (eg, reading user data, writing user data, etc.) for the storage device 100, the device driver 11b may display the normal address (Normal) of the user area. Address) may be transmitted to the storage device 100. In this case, the storage device 100 may perform a general operation on the area corresponding to the received general address among the user areas (User).

When the host application 11a requests a special operation, the device driver 11b may transmit a request having a dedicated address of the dedicated area to the storage device 100. In this case, the storage device 100 may perform a special operation in response to a dedicated address included in the received request. That is, the first controller 110 of the storage device 100 may transmit input data (ie, special data (SDT)) corresponding to a request having a dedicated address to the second controller 130.

Next, referring to FIGS. 1, 8A, and 8C, the storage space of the storage device 100 may be divided into logical unit units. In an exemplary embodiment, a logical unit may refer to a designate independent object capable of independently processing requests from the host 11.

The host application 11a may recognize the storage space of the storage device 100 as first to nth logical units. On the other hand, the device driver 11b may recognize the storage space of the storage device 100 as first to nth logical units and dedicated logical units.

Similar to that described with reference to FIG. 8B, when the host application 11a requests a normal operation of the storage device 100, the device driver 11b information about any one of the first to nth logical units A request including a may be transmitted to the storage device 100. In response to a request including information on any one of the first to nth logical units, the storage device 100 may perform a general operation for the corresponding logical unit.

When the host application 11a requests a special operation, the device driver 11b may transmit a request including information about a dedicated logical unit to the storage device 100. The storage device 100 may perform a special operation in response to a request including information about a dedicated logical unit.

Next, referring to FIGS. 1, 8A, and 8D, the device driver 11b may explicitly distinguish a request for a normal operation and a request for a special operation and transmit the request to the storage device 100. For example, in the embodiments described with reference to FIGS. 8B and 8C, the device driver 11b makes a request for a special operation by adding information about a dedicated address or information about a dedicated logical unit to a general write command. Can be issued.

On the other hand, in the embodiment shown in FIG. 8D, the device driver 11b may issue a request for a special operation explicitly distinguished from a request for a normal operation. That is, when a write request (WR RQ) is received from the device driver 11b, the input / output router 111 of the storage device 100 may transmit the received write request (WR RQ) to the first memory device 120. have. When a special operation request (SP RQ) that is explicitly distinguished from a write request (WR RQ) is received from the device driver 11b, the input / output router 111 transmits the received special operation request (SP RQ) to the second controller ( 130).

In an exemplary embodiment, the special operation request (SP RQ) may be one of a request or commands defined by a protocol between the host 11 and the storage device 100, a preliminary command, or a vendor specific command. You can. Alternatively, a special operation request (SP RQ) may be issued by setting a specific value in a reserved field of a specific request or command.

The configurations described with reference to FIGS. 8A to 8D are exemplary for easily explaining the technical spirit of the present invention, and the scope of the present invention is not limited thereto. Various methods for distinguishing general operations and special operations according to a predetermined protocol between the host 11 and the storage device 100 may be used.

In the exemplary embodiment, in the embodiments described with reference to FIGS. 8A to 8D, the device driver 11b of the host 11 has been described as performing management for distinguishing general operations and special operations, but the present invention The scope of is not limited thereto. For example, the host application 11a of the host 11 may be configured to perform the operation of the device driver 11b described above.

9A and 9B are flowcharts showing details of operations of the host and the storage device of FIG. 1. 9A, a general operation of the storage device 100 will be described, and a special operation of the storage device 100 will be described with reference to FIG. 9B. Hereinafter, for convenience of description, elements unnecessary for describing the technical idea of the present invention are omitted.

1, 7, and 9A, in step S111-1, the host 11 writes data together with data (that is, user data (UDT)) to write data to the storage device 100. Can be transmitted to the first controller 110. For example, the host 11 may transmit a write request with data to the first controller 110 based on a communication method according to a predetermined protocol with the storage device 100. At this time, the write request, as described with reference to FIGS. 8A to 8D, may be a general write request, include general address information, or include information of any one of the first to nth logical units. have.

In step S113-1, the first controller 110 may transmit a write command (WR CMD) and data to the first memory device 120 in response to the received write request. For example, when the received write request is related to a normal operation, the first controller 110 responds to the received write request, and then writes a command through the normal channel CH_n of the first memory interface IF1 ( WR CMD) and data to the first memory device 120.

In step S113-2, the first memory device 120 may perform a program operation (ie, a write operation) on the received data in response to the received write command WR CMD. In step S113-3, the first controller 110 may receive information on the result of the program operation (ie, program pass / fail (PGM P / F)) from the first memory device 120. In step S114, the first controller 110 may transmit a response to the write request to the host 11.

Although not shown in the drawing, when the result of the program operation received in step S113-3 indicates a program fail, the first controller 110 sends a command to re-execute the program operation to the first memory device 120. Can transmit.

In an exemplary embodiment, the first controller 110 may transmit a response to the host 11 before directly writing the data received in step S111-1 to the first memory device 120. For example, the first controller 110 may transmit the response to the host 11 after storing the above-described data in a separate buffer memory. Thereafter, the controller 11 may program data stored in a separate buffer memory to the first memory device 120.

In step S120, the host 11 may transmit a read request to the storage device 100 to read data stored in the storage device 100. In step S121, the first controller 110 may transmit a read command (RD CMD) to the first memory device 120 in response to the read request. In step S122, the first controller 110 may receive read data from the first memory device 120. In step S123, the first controller 110 may transmit read data to the host 11. In an exemplary embodiment, the read data may be data corresponding to address information included in the read request received in step S120.

Next, referring to FIGS. 1, 7, and 9B, in step S111-2, the host 11 may transmit a write request and data to the first controller 110 to perform a special operation. At this time, the write request may include information about a dedicated address or information about a dedicated logical unit, as described with reference to FIGS. 8B and 8C. Alternatively, as described with reference to FIG. 8D, the write request may be a request explicitly distinguished from a general write request (ie, a machine learning request (ML RQ) in FIG. 6D).

In step S115, the first controller 110 may transmit the received data (ie, special data (SDT)) to the second controller 130 through a dedicated channel CH_d of the first memory interface IF1. .

In step S116-1, the second controller 130 may read the weight WT from the second memory device 140 through the second memory interface IF2. In step S116-2, the second controller 130 may perform a special operation on the received data (ie, the special data SDT) using the read weight WT. In step S116-3, the second controller 130 may determine whether the special operation is completed. When the special operation is not completed, the second controller 130 may perform the operation of step S116-1. That is, the second controller 130 reads the weight WT from the second memory device 120 and performs a special operation on the received data based on the read weight WT, as described with reference to FIG. 3. Can be repeatedly performed in units of frames.

When the special operation is completed, the second controller 130 may transmit the result of the special operation (ie, the pass / fail of the special operation (ML P / F)) under the control of the first controller 110. In an exemplary embodiment, the first controller 110 may read the result of the special operation from the second controller 130 through status read.

In step S117, the first controller 110 may transmit a response to the write request in step S111-2 to the host 11. In step S118, the host 11 may transmit a read request to read the result of the special operation (ie, the result data RDT) to the first controller 110 in response to the response in step S117. In step S119-1, the first controller 110 may transmit a read command (RD CMD) to the second controller 130. In step S119-2, the second controller 130 may transmit the result data RDT to the first controller 110 in response to the read command RD CMD. In step S119-3, the first controller 110 may transmit the result data RDT to the host 11.

In an exemplary embodiment, the read request in step S118 includes information about a dedicated address or information about a dedicated logical unit, or is explicitly distinguished from a general read request, similar to that described with reference to FIGS. 8A to 8D. It can be a request.

In an exemplary embodiment, before the read request of step S118 is received, the first controller 110 may perform the operations of steps S119-1 and S119-2 in advance.

As described above, the storage device 100 according to an embodiment of the present invention includes general operations (that is, operations such as reading, writing and erasing user data) and special operations (eg, voice recognition, image classification, Image identification, etc.). Therefore, since the burden of computation or data center use of the host to perform special operations (eg, operations based on machine learning, artificial intelligence, etc.) can be alleviated, a storage device having improved performance and reduced cost Is provided.

10 is a flowchart illustrating an operation of the storage device of FIG. 1. 1 and 10, the storage device 100 may perform operations in steps S121 to S126. Since the operations of steps S121 to S126 of FIG. 8 are similar to those of steps S111 to S116 of FIG. 5, a detailed description thereof is omitted.

In step S127, the storage device 100 may transmit a response including the result of the special operation to the host 11. For example, the storage device 100 may transmit a response to the write request in step S121 to the host 11 in a packet unit. In this case, the result of the special operation (ie, result data RDT) may be included in the above-described response. The host 11 may receive a response including the result data RDT, and check the result of the special operation without an additional read operation based on the received response.

11 is a block diagram showing a storage device according to an embodiment of the present invention. Hereinafter, for convenience of description, detailed descriptions of components overlapping with the above-described embodiments are omitted.

Referring to FIG. 11, the storage device 200 may include a first controller 210, a first memory device 220, and a second memory device 240. The first controller 210 can communicate with the host 21. The first controller 210 may communicate with the first memory device 220 storing user data UDT through the first memory interface IF1, and the weight WT through the second memory interface IF2. It may communicate with the second memory device 240 for storing. In an exemplary embodiment, the operating speed of the second memory interface IF2 may be faster than the operating speed of the first memory interface IF1. The first and second memory devices 220 and 240 may include memory cells of the same type, as described above. Each of the first and second memory devices 220 and 240 may include a different number of data signal pins. Since the first and second memory devices 220 and 240 have been described in detail with reference to FIGS. 1 to 6, detailed descriptions thereof are omitted.

In an exemplary embodiment, the first controller 210 may include a second controller 230. The first controller 110 and the second controller 130 described with reference to FIG. 1 are composed of a separate semiconductor device, a separate semiconductor die, a separate semiconductor chip, or a separate semiconductor package. The controller 230 may be included inside the first controller 210. Alternatively, the first controller 210 and the second controller 230 of FIG. 9 may be implemented as one semiconductor device, one semiconductor die, one semiconductor chip, or one semiconductor package.

12 is a block diagram illustrating the controller of FIG. 11 by way of example. 11 and 12, the first controller 210 includes an input / output router 211, a processor 212, an SRAM 213, a ROM 214, a host interface circuit 215, and a first memory interface circuit ( 216), a second memory interface circuit 217, and a machine learning core 230 (the machine learning core 230 may correspond to the second controller 230).

Since the input / output router 211, the processor 212, the SRAM 213, the ROM 214, the host interface circuit 215, and the first memory interface circuit 216 have been described with reference to FIG. 2, a detailed description thereof Is omitted.

Unlike the first controller 110 of FIG. 2, the first controller 210 of FIG. 12 may further include a machine learning core 230 and a second memory interface circuit 217. That is, the first controller 210 of FIG. 12 responds to the request for the special operation received from the host 21, and the weight WT from the second memory device 240 through the second memory interface circuit 217 Read and use the read weight (WT) to perform a special operation.

In an exemplary embodiment, as described above, the first memory interface circuit 216 may be circuitry to support the NAND flash interface, and the second memory interface circuitry 217 may be circuitry to support the high speed interface. You can. In other words, the operating speed of the second memory interface circuit 217 may be faster than the operating speed of the first memory interface circuit 216.

13 is a flowchart illustrating the operation of the storage device of FIG. 11. For brevity, it is assumed that the write request received from the host 21 is a request for a special operation.

11 and 13, in step S211, the host 21 may transmit a write request and data to the first controller 210. For example, in order to perform a special operation, the host 21 first requests a write request including information about a dedicated address or information about a dedicated logical unit, or a machine learning request that is explicitly distinguished from a general write request. It can be transmitted to the controller 210.

In step S212, the first controller 210 responds to the received write request (ie, a write request for a special operation), and the weight WT from the second memory device 340 through the second memory interface IF2. Can read In step S213, the first controller 210 may perform a special operation on the received data (ie, the special data SDT) using the weight WT. In step S214, the first controller 210 determines whether the special operation is completed, and when the special operation is not completed, performs the operation in step S212.

When the special operation is completed, in step S215, the first controller 210 may transmit a response to the host 21. In step S216, the host 21 may transmit a read request to the first controller 210 in response to the received response. In step S217, the first controller 210 may transmit the result data RDT to the host 21 in response to the read request.

Although not shown in the drawing, the first controller 210 may transmit a response including the result data RDT to the host 21 in response to a write request for a special operation. In this case, a read request for reading the result data RDT from the host 21 may be omitted.

14 is a block diagram showing a storage device according to an embodiment of the present invention. Referring to FIG. 14, the storage device 300 includes a first controller 310, a first memory device 320, a second controller 330, a second memory device 340, and a third memory device 350 It may include. The first controller 310 may communicate with the host 31 and may include an input / output router 311. Since the first controller 310, the first memory device 320, the second controller 330, and the second memory device 340 have been described above, detailed description thereof will be omitted.

The storage device 300 of FIG. 14 may further include a third memory device 350. The third memory device 350 may include reference data (RFDT) for a special operation, and may communicate with each other based on the second controller 330 and the third memory interface IF3.

In an exemplary embodiment, the third memory interface IF3 may be an interface based on a communication method different from the second memory interface IF2. The second memory interface IF2 may be a communication method optimized for reading sequential data, and the third memory interface IF3 may be a communication method optimized for reading random data. For example, as described with reference to FIG. 3, when the special operation performed by the machine learning core 132 is a voice recognition operation, the reference data (RFDT) texts the calculation result from the acoustic model 132b. It may be data related to word information for conversion to. In this case, the reference data (RFDT) can be used by the decoding module 132c described with reference to FIG. 3. At this time, the decoding module 132c may require an operation of randomly reading some data of the reference data (RFDT). In other words, since the third memory interface IF3 is configured based on a communication method optimized for reading random data, random reading performance of the reference data RFDT stored in the third memory device 350 may be optimized.

In an exemplary embodiment, the first to third memory devices 320, 340, and 350 may be NAND flash memory devices. That is, the first to third memory devices 320, 340, and 350 are the same type of memory cells (eg, NAND flash memory cell, CTF cell) as the memory devices described with reference to FIGS. 5A to 6. Etc.).

Alternatively, at least one of the first to third memory devices 320, 340, and 350 may be another type of memory device. For example, the first memory device 320 may be a memory device suitable for large-capacity implementation, and the second memory device 340 may be a memory device suitable for a sequential read operation operating at high speed, and the third memory device ( 350) may be a memory device suitable for a random read operation that operates at a high speed.

15 is a block diagram illustrating a storage device according to an embodiment of the present invention. Referring to FIG. 15, the storage device 500 may include a first controller 510, a first memory device 520, a second controller 530, and a second memory device 540. The controller 510 can communicate with the host 51. Since the components of the storage device 500 have been described above, detailed descriptions thereof are omitted.

Unlike the previous embodiments, in the embodiment of FIG. 15, the first controller 510 may be configured to access the second memory device 540. For example, the first controller 510 provides a command for accessing the second memory device 540 to the second controller 530 through a dedicated channel CH_d, and the second controller 530 is received. In response to a command, an access operation to the second memory device 540 may be performed, and the result of the access operation may be provided to the first controller 510 through a dedicated channel CH_d.

In an exemplary embodiment, the first controller 510 may communicate with the second memory device 540 through the second general channel (CH_n2). For example, the controller 510 may perform a general operation for the first memory device 520 through the first general channel CH_n1, and special to the second controller 530 through the dedicated channel CH_d. Data SDT may be provided. At this time, the controller 510 may be configured to perform a general operation on the second memory device 540 in which the weight WT is stored through the second general channel CH_n2. In an exemplary implementation, the controller 510 may be configured to manage the weight WT stored in the second memory device 540 through the second general channel CH_n2.

16 is a block diagram showing a storage device according to an embodiment of the present invention. Referring to FIG. 16, the storage device 600 may include a first controller 610, a first memory device 620, a second controller 630, and a second memory device 640. The controller 610 can communicate with the host 61. Since the components of the storage device 600 have been described above, detailed description thereof is omitted.

Unlike the previous embodiments, the first controller 610 communicates with the first memory device 620 through the first memory interface IF1 and uses a third memory interface IF3 different from the first memory interface IF1. Through the second controller 630 may communicate with. That is, in the previous embodiments, the first controller communicated with the second controller using a specific channel included in the first memory interface IF1 with the first memory device, but in the embodiment of FIG. 15, the second controller ( 630) may further include a separate interface (that is, the third memory interface IF3) for communication.

17A to 17D are views exemplarily showing a configuration of a storage device according to an embodiment of the present invention. For simplicity and convenience of description of the drawings, some configurations of the storage devices 1000a, 1000b, 1000c, and 1000d are illustrated, but the scope of the present invention is not limited thereto.

Referring first to FIG. 17A, the storage device 1000a may include a first controller 1100a, a plurality of nonvolatile memory devices (NVM), a second controller 1200a, and a second memory device 1300a. have.

The first controller 1100a may be connected to a plurality of nonvolatile memory devices NVM through first to third general channels CH_n1 to CH_n3, respectively. The first controller 1100a may be configured to independently control each of the first to third general channels CH_n1 to CH_n3. In an exemplary embodiment, the plurality of nonvolatile memory devices NVM connected to the first to third general channels CH_n1 to CH_n3 are user area (see FIG. 6B) by an external device (eg, host). Can be recognized as That is, the controller 1100a may perform general operations on the plurality of nonvolatile memory devices NVM connected to the first to third general channels CH_n1 to CH_n3.

The first controller 1100a may communicate with the second controller 1200a through the first dedicated channel CH_d1. The second controller 1200a may communicate with the second memory device 1300a including the weight WT through a separate interface.

In an exemplary embodiment, non-volatile memory devices NVM connected to the same general channel may share the same input / output signal lines (eg, DQ lines). That is, the first to third general channels CH_n1 to CH_n3 may be classified in units of input / output lines. The controller 1100a may select or control each of the plurality of nonvolatile memory devices NVM by controlling a chip activation signal for each of the plurality of nonvolatile memory devices NVM.

Next, referring to FIG. 17B, the storage device 1000b includes a first controller 1100b, a plurality of nonvolatile memory devices (NVM), a second controller 1200b, and a second memory device 1300b. can do.

The first controller 1100b may communicate with the plurality of memory devices NVM, respectively, through the first to third general channels CH_n1 to CH_n3 and the first dedicated channel CH_d1. The second controller 1200b may communicate with the first controller 1100b through the first dedicated channel CH_d1, and communicate with the second memory device 1300b including the weight WT through a separate interface. You can.

In an exemplary embodiment, as illustrated in FIG. 17B, a plurality of nonvolatile memory devices NVM may be connected to the first dedicated channel CH_d1. In this case, the controller 1100b may perform a general operation for a plurality of nonvolatile memory devices NVM connected to the first dedicated channel CH_d1 by controlling the chip enable signal. Also, the first controller 1100b may communicate with the second controller 1200b connected to the first dedicated channel CH_d1 by controlling the chip enable signal.

For example, when the first controller 1100b controls any one of a plurality of nonvolatile memory devices NVM connected to the first dedicated channel CH_d1, the first controller 1100b corresponds to the corresponding nonvolatile memory By selecting or activating the chip enable signal of the device and deselecting or deactivating the chip enable signal of the remaining devices (e.g., the remaining non-whisperable memory devices and the second controller 1200b), the corresponding nonvolatile The memory device can be controlled.

In addition, when the first controller 1100b communicates with the second controller 1300b connected to the first dedicated channel CH_d1, the first controller 1100b includes a plurality of nonvolatile memories connected to the first dedicated channel CH_d1. By deselecting or deactivating all of the chip enable signals of the devices NVM and selecting or activating the chip enable signal of the second controller 1200b, the second controller 1200b can be communicated.

Referring to FIG. 17C, the storage device 1000c includes a first controller 1100c, a plurality of nonvolatile memory devices (NVM), a second controller 1210c, a second memory device 1310c, and a third controller 1220c. ), And a third memory device 1320c.

The first controller 1100c may be connected to the plurality of nonvolatile memory devices NVM, respectively, through the first and second general channels CH_n1 and CH_n2. The first controller 1100c may be connected to the second controller 1210c through the first dedicated channel CH_d1, and may be connected to the third controller 1220c through the second dedicated channel CH_d2. The second controller 1210c may be connected to the second memory device 1310c through a separate interface, and the third controller 1220c may be connected to the third memory device 1320c through a separate interface.

In an exemplary embodiment, the second and third controllers 1210c and 1220c may be configured to perform different special operations, respectively. For example, the second controller 1210c performs speech recognition of speech data from an external device (eg, a host) using the weight stored in the second memory device 1310c, and text information as result data A first special operation for outputting may be performed. The third controller 1220c performs a second special operation of performing image classification on image data from an external device using the weight stored in the third memory device 1320c, and outputting information on image classification as result data. Can be done. The controller 1100c may communicate with the second controller 1210c or the third controller 1220c according to the request of the external device, and perform a special operation corresponding to the request of the external device.

Referring to FIG. 17D, the storage device 1000d includes a first controller 1100d, a plurality of nonvolatile memory devices (NVM), a second controller 1210d, a second memory device 1310d, and a third controller 1220d ), And a third memory device 1320d.

The first controller 1100d may communicate with the plurality of nonvolatile memory devices NVM through the first to third general channels CH_n1 to CH_n3. The first controller 1100d may communicate with the second controller 1210d and the third controller 1220d through the first dedicated channel CH_d1. The second controller 1210d may be connected to the second memory device 1310d through a separate interface, and the third controller 1220d may be connected to the third memory device 1320d through a separate interface.

In the embodiment of FIG. 17C, the first controller 1100c communicated with the second and third controllers 1210c and 1220c using the first and second dedicated channels CH_d1 and CH_d2, but the implementation of FIG. 17D In an example, the first controller 1100d may communicate with the second and third controllers 1210d and 1220d through a first dedicated channel (CH_d1) (ie, one channel). In this case, the first controller 1100d may communicate with each of the second and third controllers 1210d and 1220d by controlling the chip enable signal of each of the second and third controllers 1210d and 1220d. .

As described above, the storage device according to the embodiment of the present invention may include a second controller configured to perform a special operation. The first controller may be configured to communicate with nonvolatile memory devices through a first memory interface general channel, and to communicate with a second controller through a dedicated channel of the first memory interface.

18 is a block diagram illustrating a computing system according to an embodiment of the present invention. Referring to FIG. 18, the computing system 2000 may include a host 2100, a first storage device 2210 and a second storage device 2220. The host 2100 may communicate with the first storage device 2210 through the first host channel CH_h1, and may communicate with the second storage device 2220 through the second host channel CH_h1. In an exemplary embodiment, the first and second host channels CH_h1 and CH_h2 may be communication channels based on the same interface.

The first storage device 2210 may include a controller 2211 and memory devices 2212 and 2213. The first storage device 2210 may perform general storage operations (ie, read, write, and erase user data) under the control of the host 2100.

The second storage device 2210 may include a first controller 2221, a second controller 2222, and a memory device 2223. The second storage device 2210 may perform a special operation under the control of the host 2100. In an exemplary embodiment, the second storage device 2210 may be a storage device having a machine learning function described with reference to FIGS. 1 to 17 or based on the operation method described with reference to FIGS. 1 to 17. Can operate as

19 is a block diagram exemplarily showing a mobile system to which a storage device according to the present invention is applied. Referring to FIG. 19, the mobile system 3000 includes an application processor 3100, a network module 3200, a system memory 3300, a storage device 3400, an image device 3500, a display device 3600, and a user. An input / output device 3700 may be included. In an exemplary embodiment, the mobile system 3000 may be a portable computing system, such as a smart phone, tablet PC, laptop, or the like.

The application processor 3100 (AP) may control various operations of the mobile system 3000. The network module 3200 may provide wireless or wired communication with an external device (eg, a base station, server, other mobile device, etc.). The system memory 3300 may be used as an operating memory or buffer memory of the mobile system 3000. In an exemplary embodiment, the system memory 3300 may be a memory (eg, DRAM) supporting high-speed operation.

The storage device 3400 may be used as a mass storage medium for storing various information used in the mobile system 3000. In an exemplary embodiment, the storage device 3400 may be a storage device having a machine learning function described with reference to FIGS. 1 to 18, and an application based on the operation method described with reference to FIGS. 1 to 18. It can communicate with the processor 3100.

The display device 3600 may be a device that displays information processed by the application processor 3100 to a user. The image sensor 3500 may be a device that collects image information about external objects. The user input / output device 3700 may be a device that receives a command from a user or provides information, such as a microphone, speaker, keypad, touch screen, and the like.

The above are specific examples for carrying out the present invention. The present invention will include not only the above-described embodiments, but also simple design changes or easily changeable embodiments. In addition, the present invention will also include techniques that can be easily modified and implemented using embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined not only by the claims to be described later but also by the claims and equivalents of the present invention.

Claims (20)

A first memory device including a plurality of first memory cells;
A second memory device including a plurality of second memory cells of the same type as the plurality of first memory cells; And
A storage device comprising a controller configured to communicate with the first memory device through a first memory interface, and to communicate with the second memory device through a second memory interface having an operating speed faster than an operating speed of the first memory interface. . According to claim 1,
Each of the plurality of first memory cells and the always plurality of second memory cells is a NAND flash memory cell. According to claim 1,
The first memory device may include a first command latch enable signal, a first address latch enable signal, a first write enable signal, a first read enable signal, and a plurality of firsts provided through the first memory interface. Operates in response to data signals,
The second memory device may include a second command latch enable signal, a second address latch enable signal, a second write enable signal, a second read enable signal, and a plurality of second signals provided through the second memory interface. Operates in response to data signals,
The number of second data signals is greater than the number of first data signals. According to claim 1,
The first memory device includes a plurality of first data signal pins connected to the first memory interface,
The second memory device includes a plurality of second data signal pins connected to the second memory interface,
The number of the second data signal pins is greater than the number of the first data signal pins. The method of claim 4,
The plurality of first data signal pins are disposed in an edge region of the first memory device,
The plurality of second data signal pins are disposed in a center area of the second memory device. According to claim 1,
The plurality of first memory cells of the first memory device are divided into a plurality of first planes,
The plurality of second memory cells of the second memory device are divided into a plurality of second planes,
The number of second planes is greater than the number of first planes. According to claim 1,
A storage device having a size of data transmitted and received per unit time through the second interface is greater than a size of data transmitted and received per unit time through the first interface. According to claim 1,
The second memory device;
A storage device including a MAC engine configured to perform a multiply and accumulate (MAC) operation on a weight stored in the plurality of second memory cells and output the result of the MAC operation through the second interface. According to claim 1,
The controller:
A first memory interface circuit configured to communicate with the first memory device through the first interface;
A second memory interface circuit configured to communicate with the second memory device through the second interface;
A first processor configured to control the first memory interface circuit to perform an access operation to the first memory device; And
And a second processor configured to control the second memory interface circuit to perform an access operation to the second memory device. The method of claim 9,
The first processor is further configured to store first user data provided from an external device to the first memory device or to provide second user data stored in the first memory device to the external device,
The second processor is further configured to perform a special operation based on weight information stored in the second memory device on special data provided from an external device, and to provide a result of the special operation to the external device. According to claim 1,
A third memory device including a plurality of third memory cells of the same type as the plurality of first memory cells, and configured to communicate with the controller through the first memory interface,
The first memory device communicates with the controller through a first channel of the first memory interface,
The third memory device is a storage device communicating with the controller through a second channel of the first memory interface. According to claim 1,
A storage device comprising a plurality of third memory cells of the same type as the plurality of first memory cells, and further comprising a third memory device configured to communicate with the controller through a third memory interface. A first controller configured to communicate with the external device through a host interface;
A first memory device including a plurality of first memory cells and configured to communicate with the first controller through a first channel of a first memory interface;
A second memory device including a plurality of second memory cells of the same type as the plurality of first memory cells; And
And a second controller configured to communicate with the first controller through a second channel of the first memory interface, and comprising a second controller via the second memory device and the second memory interface. The method of claim 13,
Each of the plurality of first memory cells and the always plurality of second memory cells is a NAND flash memory cell. The method of claim 13,
The first memory device may include a first command latch enable signal, a first address latch enable signal, a first write enable signal, a first read enable signal, and a plurality of firsts provided through the first memory interface. Operates in response to data signals,
The second memory device may include a second command latch enable signal, a second address latch enable signal, a second write enable signal, a second read enable signal, and a plurality of second signals provided through the second memory interface. Operates in response to data signals,
The number of second data signals is greater than the number of first data signals. The method of claim 13,
The first memory device includes a plurality of first data signal pins connected to the first memory interface,
The second memory device includes a plurality of second data signal pins connected to the second memory interface,
The number of the second data signal pins is greater than the number of the first data signal pins. The method of claim 13,
The plurality of first memory cells of the first memory device are divided into a plurality of first planes, and the plurality of second memory cells of the second memory device are divided into a plurality of first planes,
The number of second planes is greater than the number of first planes. The method of claim 13,
A storage device comprising a plurality of third memory cells of the same type as the plurality of first memory cells, and further comprising a third memory device configured to communicate with the second controller through a third memory interface. A first memory device including a plurality of first NAND flash memory cells;
A second memory device including a plurality of second NAND flash memory cells; And
And a controller configured to communicate with the first memory device through a first memory interface, and to communicate with the second memory device through a second memory interface having a greater input / output bandwidth than the first memory interface. The method of claim 19,
The first memory device may include a first command latch enable signal, a first address latch enable signal, a first write enable signal, a first read enable signal, and a plurality of firsts provided through the first memory interface. Operates in response to data signals,
The second memory device may include a second command latch enable signal, a second address latch enable signal, a second write enable signal, a second read enable signal, and a plurality of second signals provided through the second memory interface. Operates in response to data signals,
The number of second data signals is greater than the number of first data signals.

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