KR20220170041A - Memory device having block select circuit - Google Patents

Abstract

One embodiment relates to a memory device comprising: a first semiconductor layer including a memory cell array connected to a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction; and a second semiconductor layer. The second semiconductor layer includes: a pass transistor circuit overlapping the first semiconductor layer in a vertical direction perpendicular to the first and second directions and connected to the memory cell array through the plurality of word lines; a page buffer circuit connected to the memory cell array through the plurality of bit lines; and a block selection circuit that provides a block selection signal to the pass transistor circuit. The block selection circuit is disposed in a peripheral area of the second semiconductor layer overlapping with at least one of the page buffer circuit and the pass transistor in the second direction. A memory device having a reduced size can be provided.

Description

Memory device having a block selection circuit

The present invention relates to semiconductor technology, and more particularly, to a memory device having a block selection circuit.

Memory devices with a two-dimensional or planar structure have been developed to store more data in the same area by using a fine patterning process. However, as the circuit line width is narrowed due to the demand for high integration, interference between memory cells intensifies, resulting in various limitations such as deterioration in performance. Of course, in addition to such structural limitations, the introduction of expensive equipment for patterning fine line widths is required, which inevitably increases manufacturing costs.

A 3D memory device has been proposed as an alternative to overcome the limitations of the 2D memory device. The 3D memory device has advantages of being able to realize more capacity in the same area and providing high performance and excellent power efficiency by increasing the number of stages by stacking memory cells in a vertical direction.

In a 3D memory device, the degree of integration may be increased by increasing the number of stacked word lines. However, since the number of pass transistors that deliver operating voltages to the word lines increases in proportion to the number of word lines, the area occupied by the pass transistors and the area occupied by the wiring patterns connecting the word lines and the pass transistors increases. As a result, the size of the memory device may be increased.

Embodiments of the present invention may provide a memory device having a reduced size.

A memory device according to an embodiment of the present invention includes a first semiconductor layer including a memory cell array connected to a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction; and a pass transistor circuit overlapping the first semiconductor layer in a vertical direction orthogonal to the first and second directions and connected to the memory cell array through the plurality of word lines, and the memory through the plurality of bit lines. and a second semiconductor layer including a page buffer circuit connected to a cell array and a block selection circuit providing a block selection signal to the pass transistor circuit, wherein the block selection circuit moves the page buffer circuit and the block selection circuit in the second direction. disposed in a peripheral region of the second semiconductor layer overlapping with at least one of the pass transistors.

A memory device according to an embodiment of the present invention includes a first semiconductor layer including a plurality of memory cell arrays connected to a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction; a plurality of pass transistor circuits overlapping the first semiconductor layer in a vertical direction orthogonal to the first and second directions and connected to a corresponding memory cell array through the plurality of word lines; a second semiconductor layer including a plurality of page buffer circuits connected to a corresponding memory cell array through a plurality of block selection circuits, and a plurality of block selection circuits providing a block selection signal to a corresponding pass transistor circuit; Selection circuits are disposed in a peripheral area of the second semiconductor layer overlapping with at least one of the plurality of pass transistors and the plurality of page buffer circuits in the second direction.

According to embodiments of the present invention, the size of a memory device can be reduced.

1 is a block diagram of a memory device according to an exemplary embodiment of the present invention.
2 is a schematic perspective view of a memory device according to an exemplary embodiment of the present invention.
3 is a layout diagram illustrating an example of a second semiconductor layer of a memory device according to the present invention.
FIG. 4 is a layout diagram showing the layout of one of the pass transistor circuits of FIG. 3 and a block selection circuit corresponding thereto.
5 is a layout diagram illustrating another example of a second semiconductor layer of a memory device according to the present invention.
FIG. 6 is a layout diagram illustrating one of the pass transistor circuits of FIG. 5 and the arrangement of first and second block selection regions corresponding thereto.
7 is a layout diagram showing another example of a second semiconductor layer of a memory device according to the present invention.
8 is a layout diagram showing another example of a second semiconductor layer of a memory device according to the present invention.
FIG. 9 is a layout diagram showing the arrangement of first to third pass transistor circuits and first and second block selection circuits of FIG. 8 .
10 is a cross-sectional view of a memory cell array of a memory device according to an exemplary embodiment.
11 is an exemplary layout diagram of a memory device different from the present invention.
12 is an exemplary layout diagram of a memory device according to the present invention, contrasted with FIG. 11 .
13 is a schematic block diagram of a memory system including a memory device according to an embodiment of the present invention.
14 is a schematic block diagram of a computing system including a memory device according to an embodiment of the present invention.

Advantages and features of the present invention, and methods for achieving them, will become clear with reference to the detailed description of the following embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be embodied in a variety of different forms, and only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention pertains. It is provided to completely inform the person who has the scope of the invention, and the present invention is only defined by the scope of the claims.

In addition, since the shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, the present invention is not limited to the matters shown. Like reference numbers designate like elements throughout the specification. In addition, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. In this specification, when 'includes', 'has', 'consists of', etc. are used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, it may include the case of including the plural unless specifically stated otherwise.

In addition, in interpreting the components in the embodiments of the present invention, even if there is no separate explicit description, it should be interpreted as including an error range.

In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the corresponding component is not limited by the term. Also, components in the embodiments of the present invention are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may also be the second component within the technical spirit of the present invention.

When an element is described as being “connected,” “coupled to,” or “connected” to another element, that element is or may be directly connected to that other element, but intervenes between each element. It will be understood that may be "interposed", or each component may be "connected", "coupled" or "connected" through other components. In the case of a description of a positional relationship, for example, 'on top of', 'on top of', 'at the bottom of', 'next to', etc. Or, unless 'directly' is used, one or more other parts may be located between the two parts.

In addition, the features (configurations) in the embodiments of the present invention can be partially or entirely combined, combined or separated from each other, technically various interlocking and driving operations are possible, and each embodiment is implemented independently of each other. It may be possible or it may be possible to implement together in an association relationship.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 1 , a memory device 100 according to an embodiment of the present invention may include a plurality of planes and a PERI circuit 150 . Each plane PLANE may include a memory cell array 110 , a pass transistor circuit 120 , a block select circuit BLKSW 130 and a page buffer circuit PB circuit 140 .

The memory cell array 110 may be connected to the pass transistor circuit 120 through a plurality of word lines WL and connected to the page buffer circuit 140 through a plurality of bit lines BL.

The memory cell array 110 may include a plurality of memory cells disposed in regions where a plurality of bit lines BL and a plurality of word lines WL intersect. The memory cell may be a volatile memory cell that loses stored data when supplied power is cut off, or may be a non-volatile memory cell that retains stored data even when supplied power is cut off. For example, when the memory cell is a volatile memory cell, the memory device 100 includes dynamic random access memory (DRAM), static random access memory (SRAM), mobile DRAM, double data rate synchronous dynamic random access memory (DDR SDRAM), It may be Low Power DDR (LPDDR) SDRAM, Graphic DDR (GDDR) SDRAM, or Rambus Dynamic Random Access Memory (RDRAM). When the memory cell is a non-volatile memory cell, the memory device 100 includes electrically erasable programmable read-only memory (EEPROM), flash memory, phase change random access memory (PRAM), resistance random access memory (RRAM), It may be Nano Floating Gate Memory (NFGM), Polymer Random Access Memory (PoRAM), Magnetic Random Access Memory (MRAM), or Ferroelectric Random Access Memory (FRAM). Also, the memory device 100 may be a hybrid memory device in which the memory cell array 110 includes both volatile memory cells and non-volatile memory cells.

The memory cell may be a single level cell (SLC) that stores one bit of data or a multi-level cell (MLC) that can store two or more bits of data. A multi-level cell can store 2-bit data, 3-bit data, 4-bit data, and the like. In general, a memory cell that stores 2-bit data is called a multi-level cell, a memory cell that stores 3-bit data is called a triple level cell (TLC), and a memory that stores 4-bit data The cell is referred to as a quadruple level cell (QLC). However, in this embodiment, for convenience of explanation, memory cells storing 2 to 4-bit data will be collectively referred to as multi-level cells. The memory cell array 110 may include at least one of single-level cells and multi-level cells.

The memory cell array 110 may include memory cells having a 3D vertical structure. Alternatively, the memory cell array 110 may include memory cells having a two-dimensional horizontal structure.

The memory cell array 110 may include a plurality of memory blocks BLK. The memory block BLK may include a plurality of pages. A memory block BLK may be a basic unit of an erase operation, and a page may be a basic unit of a read operation.

In response to the block selection signal BLKWL from the block selection circuit 130, the pass transistor circuit 120 provides a peripheral circuit ( The operating voltage Vop from 150) may be transmitted.

The pass transistor circuit 120 may include a plurality of pass transistor groups PTR Group corresponding to the plurality of memory blocks BLK. Each pass transistor group PTR Group may be connected to a corresponding memory block BLK through a plurality of word lines WL. In response to the block selection signal BLKWL from the block selection circuit 130, one of a plurality of pass transistor groups PTR Group may be selected, and the selected pass transistor group PTR Group is transmitted from the peripheral circuit 150. An operating voltage Vop of may be transmitted to the word lines WL of the corresponding memory block BLK.

The block selection circuit 130 may generate a block selection signal BLKWL in response to the row address RADD from the peripheral circuit 150, and pass the generated block selection signal BLKWL to the pass transistor circuit 120. can provide The pass transistor circuit 120 and the block selection circuit 130 may constitute a row decoder.

The page buffer circuit 140 may be connected to the memory cell array 110 through bit lines BL. The page buffer circuit 140 can receive the page buffer control signal PBCON from the peripheral circuit 150 and transmit/receive the data signal DATA to and from the peripheral circuit 150 .

The page buffer circuit 140 may control the bit lines BL connected to the memory cell array 110 in response to the page buffer control signal PBCON. For example, the page buffer circuit 140 senses the signal of the bit line BL of the memory cell array 110 in response to the page buffer control signal PBCON, thereby data stored in the memory cells of the memory cell array 110. may be detected, and the data signal DATA may be transmitted to the peripheral circuit 150 according to the detected data. The page buffer circuit 140 may apply a signal to the bit line BL based on the data signal DATA received from the peripheral circuit 150 in response to the page buffer control signal PBCON, and thus apply a signal to the memory cell. Data may be written to the memory cells of the array 110 . The page buffer circuit 140 may write data to or read data from a memory cell connected to a word line WL activated by a row decoder.

The peripheral circuit 150 may receive a command signal CMD, an address signal ADD, and a control signal CTRL from an external device of the memory device 100, for example, a memory controller, and may receive the external device of the memory device 100. It is possible to transmit and receive data (DATA) with the device of. The peripheral circuit 150 is a signal for writing data into the memory cell array 110 or reading data from the memory cell array 110 based on the command signal CMD, the address signal ADD, and the control signal CTRL. For example, row address signals RADD, column address signals CADD, page buffer control signals PBCON, and the like may be output. The peripheral circuit 150 may generate various voltages required by the memory device 100 including the operating voltage Vop. For example, the peripheral circuit 150 may generate various levels of program voltages, pass voltages, read voltages, and erase voltages.

The plurality of memory cell arrays 110 included in the plurality of planes (PLANE) may be controlled independently of each other. The word lines of the plurality of memory cell arrays 110 of the plurality of planes PLANE can be independently activated by the row decoder included in each plane PLANE, and the page included in each plane PLANE Through the buffer circuit 140 , operations of the plurality of memory cell arrays 110 of the plurality of planes (PLANE) may be controlled independently of each other, for example, a write operation and a read operation. The plurality of memory cell arrays 110 of the plurality of planes may be independently controlled to perform specific operations in parallel or different operations.

Although the embodiments described herein show a case where the memory device 100 has a 4-plane structure including 4 planes, it is not limited thereto. The memory device 100 may have a single plane structure including one plane or a multi plane structure including two or more planes.

Hereinafter, in the accompanying drawings, a direction that protrudes vertically from the upper surface of the substrate is defined as a vertical direction (VD), and two directions that are parallel to the upper surface of the substrate and intersect each other are respectively a first direction (FD) and a second direction ( SD) will be defined as For example, the first direction FD may be the extension direction of the word lines WL and the arrangement direction of the bit lines BL, and the second direction SD may be the extension direction of the bit lines BL. and the arrangement direction of the word lines WL. The first direction FD and the second direction SD may substantially perpendicularly cross each other. A direction indicated by an arrow in the drawings and an opposite direction thereof indicate the same direction.

2 is a schematic perspective view of a memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 2 , the memory device 100 may include a first semiconductor layer S1 and a second semiconductor layer S2. The first semiconductor layer S1 and the second semiconductor layer S2 may overlap each other in the vertical direction VD. The second semiconductor layer S2 may be disposed below the first semiconductor layer S1 in the vertical direction VD.

The memory device 100 may include a plurality of planes. A plurality of memory cell arrays 110 each included in a plurality of planes may be disposed on the first semiconductor layer S1 . Although not shown, a plurality of pass transistor circuits ( 120 in FIG. 1 ), a plurality of block selection circuits ( 130 in FIG. 1 ), and a plurality of page buffer circuits ( 140 in FIG. 1 ) are formed in the second semiconductor layer S2 . , and the peripheral circuit 150 may be disposed.

The second semiconductor layer S2 may include a plurality of regions R1 to R4. Illustratively, the second semiconductor layer S2 may include the first to fourth regions R1 to R4. The first to fourth regions R1 to R4 may be arranged in a 2x2 matrix form along the first direction FD and the second direction SD. The first region R1 and the second region R2 are adjacent to each other in the first direction FD, and the third region R3 and the fourth region R4 are adjacent to each other in the first direction FD. The first region R1 and the third region R3 may be adjacent to each other in the second direction SD, and the second region R2 and the fourth region R4 may be adjacent to each other in the second direction SD. there is.

The plurality of memory cell arrays 110 may be respectively disposed on the first to fourth regions R1 to R4 . Each memory cell array 110 may overlap one of the first to fourth regions R1 to R4 in the vertical direction VD. The plurality of memory cell arrays 110 may be arranged in a 2X2 matrix form along the first direction (FD) and the second direction (SD).

A plurality of word lines WL and a plurality of bit lines BL may be arrayed in each of the memory cell arrays 110 . The memory cell array 110 may be connected to a plurality of word lines WL and a plurality of bit lines BL.

The first semiconductor layer S1 and the second semiconductor layer S2 may be formed on a single wafer. Although not shown, the second semiconductor layer S2 may include a substrate, and pass transistors are formed on the substrate by forming semiconductor devices such as transistors and wiring patterns connected to the semiconductor devices. Circuits corresponding to the circuits, block selection circuits, page buffer circuits, and peripheral circuits may be formed. After circuits are formed on the second semiconductor layer S2 , memory cell arrays 110 may be built up on the second semiconductor layer S2 , and word lines of the memory cell arrays 110 may be built up. Wiring patterns may be formed to electrically connect the circuits WL and the bit lines BL and the circuits formed in the second semiconductor layer S2 . In this case, the memory device 100 may be defined as having a Peri Under Cell (PUC) structure.

Meanwhile, the first semiconductor layer S1 and the second semiconductor layer S2 may be fabricated on different wafers or may be unified through a wafer bonding process. In this case, the memory device 100 may be defined as having a Peri Over Cell (POC) structure.

3 is a layout diagram illustrating an example of a second semiconductor layer of a memory device according to the present invention.

Referring to FIG. 3 , a pass transistor circuit 120, a block selection circuit 130, and a page buffer circuit 140 are disposed in each of the first to fourth regions R1 to R4 of the second semiconductor layer S2. can

The pass transistor circuit 120 corresponds to the upper memory cell array and may be connected to the corresponding memory cell array through a plurality of word lines. The page buffer circuit 140 corresponds to the upper memory cell array and may be connected to the upper memory cell array through a plurality of bit lines. Illustratively, the pass transistor circuit 120 of the first region R1 may be connected to the memory cell array above the first region R1 through a plurality of word lines, and the page buffer circuit of the first region R1. 140 may be connected to the memory cell array above the first region R1 through a plurality of bit lines.

In order to reduce the delay time occurring in the process of transferring the operating voltage from the pass transistor circuit 120 to the word lines, the pass transistor circuit 120 extends in the second direction SD, which is the direction in which the word lines are aligned. , and the length of the second direction SD may be substantially equal to or similar to the length of the corresponding memory cell array in the second direction SD.

The pass transistor circuit 120 may not overlap a corresponding memory cell array in the vertical direction VD. As another example, the pass transistor circuit 120 may partially or entirely overlap a corresponding memory cell array in the vertical direction (VD).

The pass transistor circuit 120 of the first region R1 and the pass transistor circuit 120 of the second region R2 are disposed adjacent to each other in the first direction FD in the central region of the second semiconductor layer S2. It can be. Similarly, the pass transistor circuit 120 of the third region R3 and the pass transistor circuit 120 of the fourth region R4 are connected to each other in the first direction FD in the central region of the second semiconductor layer S2. may be placed adjacent to each other. That is, the pass transistor circuits 120 connected to adjacent memory cell arrays in the first direction FD may be disposed to be adjacent to each other in the first direction FD.

In order to reduce the delay time of signals applied to the bit lines by the page buffer circuit 140 or signals provided to the page buffer circuit 140 through the bit lines, the page buffer circuit 140 is arranged in the direction in which the bit lines are arranged. may be configured to have a shape extending in the first direction (FD) of which the length of the first direction (FD) is substantially the same as or similar to the length of the first direction (FD) of the corresponding memory cell array. It can be configured as a list. All or part of the page buffer circuit 140 may overlap a corresponding memory cell array in the vertical direction (VD).

In each of the first to fourth regions R1 to R4 , the block selection circuit 130 may be connected to the pass transistor circuit 120 through block selection lines to provide a block selection signal to the pass transistor circuit 120 .

The block selection circuits 130 may be disposed in a peripheral area of the second semiconductor layer S2 overlapping with at least one of the pass transistor circuits 120 and the page buffer circuits 140 in the second direction SD. there is. In this embodiment, the block selection circuits 130 are disposed in the peripheral area of the second semiconductor layer S2 overlapping with at least one of the pass transistor circuits 120 in the second direction SD.

Specifically, in each of the first to fourth regions R1 to R4 , the block selection circuit 130 may be disposed adjacent to the pass transistor circuit 120 in the second direction SD. The pass transistor circuit 120 of the first region R1 and the pass transistor circuit 120 of the third region R3 may be spaced apart from each other with a gap in the second direction SD, and the first region R1 The block selection circuit 130 of ) and the block selection circuit 130 of the third region R3 are the pass transistor circuit 120 of the first region R1 and the pass transistor circuit 120 of the third region R3 It may be arranged to be adjacent to each other in the second direction (SD) between them. Similarly, the pass transistor circuit 120 of the second region R2 and the pass transistor circuit 120 of the fourth region R4 may be spaced apart from each other in the second direction SD, and The block selection circuit 130 of the region R2 and the block selection circuit 130 of the fourth region R4 include the pass transistor circuit 120 of the second region R2 and the pass transistor circuit of the fourth region R4. 120 may be disposed adjacent to each other in the second direction SD.

Since the block selection circuits 130 are disposed in the peripheral area of the second semiconductor layer S2 overlapping at least one of the pass transistor circuits 120 in the second direction SD, the block selection circuits 130 The size of the second semiconductor layer S2 and the memory device in the first direction FD will not change. That is, the size of the first direction (FD) of the memory device does not increase due to the block selection circuits 130 .

Although not shown, a well region may be formed on a portion of the substrate of the second semiconductor layer S2 including the boundary between the first region R1 and the second region R2, and the first region ( Pass transistor circuits 120 may be respectively formed in the R1 side well region and the second region R2 side well region. The pass transistor circuit 120 of the first region R1 and the pass transistor circuit 120 of the second region R2 may share a well region. Similarly, a well region may be formed on another part of the substrate of the second semiconductor layer S2 including the boundary between the third region R3 and the fourth region R4, and the well region on the side of the third region R3 may be formed. Pass transistor circuits 120 may be respectively formed in the region and the well region on the fourth region R4 side. The pass transistor circuit 120 of the third region R3 and the pass transistor circuit 120 of the fourth region R4 may share a well region. Pass transistor circuits 120 connected to adjacent memory cell arrays in the first direction FD may share one well area.

The block selection circuits 130 are disposed in a peripheral area of the second semiconductor layer S2 overlapping with at least one of the pass transistor circuits 120 in the second direction SD, and the pass transistor circuits 120 are the first Since they are arranged to be adjacent to each other in one direction (FD), the pass transistor circuits 120 may be configured to share the well area by merging the well areas of the pass transistor circuits 120 .

Although not shown, the peripheral circuit (150 in FIG. 1 ) is the remaining area of the second semiconductor layer S2 where the pass transistor circuits 120, block selection circuits 130, and page buffer circuits 140 are not disposed. can be placed in

The second semiconductor layer S2 may include a pad area PAD. Illustratively, the pad area PAD may be configured to have a shape extending in the first direction FD from the edge of the second semiconductor layer S2 . Although not shown, a plurality of pads may be disposed in the pad area PAD. The plurality of pads may be connected to the circuits of the first to fourth regions R1 to R4 through the wiring patterns of the second semiconductor layer S2. The memory device may be electrically connected to an external device, for example, a memory controller, through pads disposed in the pad area PAD. The pads may include pads for receiving command signals, address signals, and control signals from the memory controller, and pads for exchanging data with the memory controller.

FIG. 4 is a layout diagram showing the layout of one of the pass transistor circuits of FIG. 3 and a block selection circuit corresponding thereto.

Referring to FIG. 4 , the pass transistor circuit 120 may include a plurality of pass transistor stages (PTR Group). As described with reference to FIG. 1, a plurality of pass transistor groups (PTR Group) correspond to a plurality of memory blocks (BLK in FIG. 1) included in a memory cell array (110 in FIG. 1), respectively. It may be connected to a corresponding memory block through a plurality of word lines.

Although not shown, a plurality of memory blocks of the memory cell array may be arranged along the second direction SD. In order to reduce the delay time occurring in the process of transferring the operating voltage from the pass transistor groups (PTR Group) to the memory blocks, the plurality of pass transistor groups (PTR Group) are arranged in the same direction as the arrangement direction of the memory blocks. They can be arranged along two directions (SD).

Each pass transistor group PTR Group may include a plurality of pass transistors PTR. The pass transistor PTR includes, for example, a gate line G extending in the first direction FD and a source region S and a drain region D provided in active regions of the substrate on both sides of the gate line G. can do.

As described with reference to FIG. 3 , the block selection circuit 130 may be disposed adjacent to the pass transistor circuit 120 in the second direction SD. The block selection circuit 130 may be connected to the gate lines G of the pass transistors PTR of the pass transistor circuit 120 through block selection lines (not shown). The gate lines (G) of the pass transistors (PTR) included in the single pass transistor group (PTR Group) may be connected in common to one block selection line, in response to a block selection signal provided through the block selection line. It can be turned on all at once or turned off all at once.

5 is a layout diagram illustrating another example of a second semiconductor layer of a memory device according to the present invention.

Referring to FIG. 5 , a pass transistor circuit 120, a block selection circuit 130, and a page buffer circuit 140 are disposed in each of the first to fourth regions R1 to R4 of the second semiconductor layer S2. can

In each of the first to fourth regions R1 to R4, the block selection circuit 130 is divided into a first block selection region BLKSW1 and 131 and a second block selection region BLKSW2 and 132, and the second direction SD ) may be disposed on both sides of the pass transistor circuit 120, respectively. The first block selection regions 131 and the second block selection regions 132 of the block selection circuits 130 overlap with at least one of the pass transistor circuits 120 in the second direction SD. It may be disposed in a peripheral area of the semiconductor layer S2. Since the first and second block selection regions 131 and 132 are disposed in the peripheral region of the second semiconductor layer S2 overlapping at least one of the pass transistor circuits 120 in the second direction SD, the first and second block selection regions 131 and 132 are disposed in the second direction SD. Due to the two-block selection regions 131 and 132, the size of the second semiconductor layer S2 and the first direction FD of the memory device will not change. That is, the size of the first direction (FD) of the memory device does not increase due to the first and second block selection regions 131 and 132 .

In each of the first to fourth regions R1 to R4, the first block selection region 131 is connected to the pass transistor circuit 120 through first block selection lines (not shown) so that the pass transistor circuit 120 selects a block. A signal may be provided, and the second block selection region 132 may be connected to the pass transistor circuit 120 through second block selection lines (not shown) to provide a block selection signal to the pass transistor circuit 120. .

Although not shown, a well region may be formed on a portion of the substrate of the second semiconductor layer S2 including the boundary between the first region R1 and the second region R2, and the well region on the side of the first region R1 may be formed. Pass transistor circuits 120 may be respectively formed in the region and the well region on the second region R2 side. The pass transistor circuit 120 of the first region R1 and the pass transistor circuit 120 of the second region R2 may share a well region. Similarly, a well region may be formed on another part of the substrate of the second semiconductor layer S2 including the boundary between the third region R3 and the fourth region R4, and the well region on the side of the third region R3 may be formed. Pass transistor circuits 120 may be respectively formed in the region and the well region on the fourth region R4 side. The pass transistor circuit 120 of the third region R3 and the pass transistor circuit 120 of the fourth region R4 may share a well region. That is, pass transistor circuits 120 connected to neighboring memory cell arrays in the first direction FD may share a well area.

A peripheral area of the second semiconductor layer S2 in which the first block selection regions 131 and the second block selection regions 132 overlap with at least one of the pass transistor circuits 120 in the second direction SD. Since the pass transistor circuits 120 are disposed adjacent to each other in the first direction FD, the well regions of the pass transistor circuits 120 are integrated so that the pass transistor circuits 120 share the well region with each other. can be configured to do so. According to this embodiment, the size of the memory device can be reduced by configuring the pass transistor circuits 120 to share the well area.

FIG. 6 is a layout diagram illustrating one of the pass transistor circuits of FIG. 5 and the arrangement of first and second block selection regions corresponding thereto.

Referring to FIG. 6 , the pass transistor circuit 120 may include a plurality of first pass transistor stages (PTR Group 1) and a plurality of second pass transistor stages (PTR Group 2). Each of the plurality of first pass transistor groups PTR Group 1 and the plurality of second pass transistor groups PTR Group 2 may include a plurality of pass transistors PTR.

Each of the plurality of first pass transistor stages (PTR Group 1) is connected to the first block selection region 131 through the first block selection line to receive a block selection signal from the first block selection region 131. . Each of the plurality of second pass transistor stages (PTR Group 2) is connected to the second block selection region 132 through the second block selection line to receive a block selection signal from the second block selection region 132. .

The plurality of first pass transistor groups PTR Group 1 may be disposed closer to the first block selection region 131 than the plurality of second pass transistor groups PTR Group 2 . The plurality of second pass transistor groups PTR Group 2 may be disposed closer to the second block selection region 132 than the plurality of first pass transistor groups PTR Group 1 . According to this arrangement structure, the first block selection lines connecting between the first block selection region 131 and the first pass transistor stages (PTR Group 1) are connected to the first block selection region 131 and the first pass transistors. The second block selection lines connecting between the second block selection region 132 and the second pass transistor stages (PTR Group 2) may be configured with a short length connecting between the stages (PTR Group 1). Since the block selection region 132 and the second pass transistor stages (PTR Group 2) can be configured with a short length, it is possible to arrange a large number of block selection lines in one wiring layer, thereby improving the utilization efficiency of the wiring layer. can be raised

7 is a layout diagram showing another example of a second semiconductor layer of a memory device according to the present invention.

Referring to FIG. 7 , a pass transistor circuit 120, a block selection circuit 130, and a page buffer circuit 140 are disposed in each of the first to fourth regions R1 to R4 of the second semiconductor layer S2. can The block selection circuits 130 may be disposed in a peripheral area of the second semiconductor layer S2 overlapping with at least one of the page buffer circuits 140 in the second direction SD. In each of the first to fourth regions R1 to R4 , the block selection circuit 130 may be disposed adjacent to the page buffer circuit 140 in the second direction SD.

Since the block selection circuits 130 are disposed in the peripheral area of the second semiconductor layer S2 overlapping at least one of the page buffer circuits 140 in the second direction SD, the block selection circuits 130 The size of the second semiconductor layer S2 and the memory device in the first direction FD will not change. That is, the size of the first direction (FD) of the memory device does not increase due to the block selection circuits 130 . .

Although not shown, a well region may be formed on a portion of the substrate of the second semiconductor layer S2 including the boundary between the first region R1 and the second region R2, and the well region on the side of the first region R1 may be formed. Pass transistor circuits 120 may be respectively formed in the region and the well region on the second region R2 side. The pass transistor circuit 120 of the first region R1 and the pass transistor circuit 120 of the second region R2 may share a well region. Similarly, a well region may be formed on another part of the substrate of the second semiconductor layer S2 including the boundary between the third region R3 and the fourth region R4, and the well region on the side of the third region R3 may be formed. Pass transistor circuits 120 may be respectively formed in the region and the well region on the fourth region R4 side. The pass transistor circuit 120 of the third region R3 and the pass transistor circuit 120 of the fourth region R4 may share a well region. That is, pass transistor circuits 120 connected to neighboring memory cell arrays in the first direction FD may share a well area.

The block selection circuits 130 are disposed in the peripheral area of the second semiconductor layer S2 overlapping with at least one of the page buffer circuits 140 in the second direction SD, and the pass transistor circuits 120 are Since the pass transistor circuits 120 are adjacent to each other in one direction FD, the pass transistor circuits 120 may be configured to share the well region by integrating the well regions of the pass transistor circuits 120 . According to this embodiment, the size of the memory device can be reduced by configuring the pass transistor circuits 120 to share the well area.

A part or all of the block selection circuit 130 in each of the first to fourth regions R1 to R4 may overlap the upper memory cell array ( 110 in FIG. 2 ) in the vertical direction VD. Illustratively, all of the block selection circuit 130 of the first region R1 may overlap the memory cell array on the first region R1 in the vertical direction VD. According to this embodiment, since the block selection circuit 130 overlaps the memory cell array in the vertical direction (VD), the area consumed for disposing the block selection circuit 130 can be reduced.

8 is a layout diagram showing another example of a second semiconductor layer of a memory device according to the present invention.

Referring to FIG. 8 , a plurality of pass transistor circuits 120-1 to 120-6, a plurality of block selection circuits 130-1 to 130-4, and a plurality of page buffers are provided in the second semiconductor layer S2. Circuits 140-1 to 140-4 may be disposed. For convenience of description below, pass transistor circuits 120-1 to 120-6 are defined as first to sixth pass transistor circuits, and block selection circuits 13-1 to 130-4 are defined as first to sixth pass transistor circuits. It will be defined as a fourth block selection circuit, and the page buffer circuits 140-1 to 140-4 will be defined as first to fourth page buffer circuits.

The first pass transistor circuit 120-1, the first block selection circuit 130-1, and the first page buffer circuit 140-1 are disposed in the first region R1 of the second semiconductor layer S2. The second pass transistor circuit 120-2, the second block selection circuit 130-2, and the second page buffer circuit 140-2 may be formed in the second region R2 of the second semiconductor layer S2. , and the third pass transistor circuit 120 - 3 may be disposed in the center of the second semiconductor layer S2 including the boundary between the first region R1 and the second region R2 .

The first pass transistor circuit 120-1 may be disposed adjacent to the third pass transistor circuit 120-3 in the first direction (FD), and the second pass transistor circuit 120-2 may be disposed in the first direction (FD). (FD) may be arranged adjacent to the third pass transistor circuit 120-3.

The first block selection circuit 130-1 is connected to the first pass transistor circuit 120-1 and the third pass transistor circuit 120-3 through block selection lines, and the first pass transistor circuit 120-1 ) and a block selection signal to the third pass transistor circuit 120-3. The second block selection circuit 130-2 is connected to the second pass transistor circuit 120-2 and the third pass transistor circuit 120-3 through block selection lines, and the second pass transistor circuit 120-2 ) and a block selection signal to the third pass transistor circuit 120-3.

The first pass transistor circuit 120-1 and the third pass transistor circuit 120-3 may be connected to the memory cell array above the first region R1, and the second pass transistor circuit 120-2 and the The 3-pass transistor circuit 120-3 may be connected to the memory cell array above the second region R2. The third pass transistor circuit 120 - 3 may be commonly connected to the memory cell array over the first region R1 and the memory cell array over the second region R2 .

The first pass transistor circuit 120-1 may transmit an operating voltage to the memory cell array on the first region R1 in response to a block selection signal from the first block selection circuit 130-1. The second pass transistor circuit 120-2 may transfer an operating voltage to the memory cell array in the upper portion of the second region R2 in response to a block selection signal from the second block selection circuit 130-2. The third pass transistor circuit 120-3 transmits an operating voltage to the memory cell array over the first region R1 in response to a block selection signal from the first block selection circuit 130-1, or the second pass transistor circuit 120-3. In response to a block selection signal from the block selection circuit 130 - 2 , an operating voltage may be transferred to the memory cell array on the second region R2 .

The fourth pass transistor circuit 120-4, the third block selection circuit 130-3, and the third page buffer circuit 140-3 are disposed in the third region R3 of the second semiconductor layer S2. The fifth pass transistor circuit 120-5, the fourth block selection circuit 130-4, and the fourth page buffer circuit 140-4 may be formed in the fourth region R4 of the second semiconductor layer S2. , and the sixth pass transistor circuit 120 - 6 may be disposed in the center of the second semiconductor layer S2 including the boundary between the third region R3 and the fourth region R4 .

The fourth pass transistor circuit 120-4 may be disposed adjacent to the sixth pass transistor circuit 120-6 in the first direction (FD), and the fifth pass transistor circuit 120-5 may be adjacent to the first direction. (FD) may be arranged adjacent to the sixth pass transistor circuit 120-6.

The third block selection circuit 130-3 is connected to the fourth pass transistor circuit 120-4 and the sixth pass transistor circuit 120-6 through block selection lines, and the fourth pass transistor circuit 120-4 ) and a block selection signal to the sixth pass transistor circuit 120-6. The fourth block selection circuit 130-4 is connected to the fifth pass transistor circuit 120-5 and the sixth pass transistor circuit 120-6 through block selection lines, and the fifth pass transistor circuit 120-5 ) and a block selection signal to the sixth pass transistor circuit 120-6.

The fourth pass transistor circuit 120-4 and the sixth pass transistor circuit 120-6 may be connected to the memory cell array above the third region R3, and the fifth pass transistor circuit 120-5 and the The 6-pass transistor circuit 120 - 6 may be connected to the memory cell array above the fourth region R4 . The sixth pass transistor circuit 120 - 6 may be commonly connected to the memory cell array over the third region R3 and the memory cell array over the fourth region R4 .

The fourth pass transistor circuit 120-4 may transfer an operating voltage to the memory cell array on the third region R3 in response to a block selection signal from the third block selection circuit 130-3. The fifth pass transistor circuit 120-5 may transfer an operating voltage to the memory cell array on the fourth region R4 in response to a block selection signal from the fourth block selection circuit 130-4. The sixth pass transistor circuit 120-6 transmits an operating voltage to the memory cell array on the third region R3 in response to a block selection signal from the third block selection circuit 130-3, or the fourth pass transistor circuit 120-6. In response to a block selection signal from the block selection circuit 130-4, an operating voltage may be transferred to the memory cell array above the fourth region R4.

The first to fourth block selection circuits 130-1 to 130-4 overlap at least one of the first to sixth pass transistor circuits 120-1 to 120-6 in the second direction SD. It may be disposed in a peripheral area of the semiconductor layer S2. The first to fourth block selection circuits 130-1 to 130-4 overlap with at least one of the first to sixth pass transistor circuits 120-1 to 120-6 in the second direction SD. Since it is disposed in the peripheral area of the second semiconductor layer S2, the first to fourth block selection circuits 130-1 to 130-4 reduce the size of the second semiconductor layer S2 and the memory device in the first direction (FD). It won't change. That is, the size of the first direction (FD) of the memory device does not increase due to the first to fourth block selection circuits 130-1 to 130-4.

Although not shown, a well region may be formed on a portion of the substrate of the second semiconductor layer S2 including the boundary between the first region R1 and the second region R2, and the first to third regions may be formed in the well region. Pass transistor circuits 120-1 to 120-3 may be configured. The first to third pass transistor circuits 120-1 to 120-3 may share a well region. Similarly, a well region may be formed on another part of the substrate of the second semiconductor layer S2 including the boundary between the third region R3 and the fourth region R4, and the fourth to sixth well regions may be formed in the well region. Pass transistor circuits 120-4 to 120-6 may be configured. The fourth to sixth pass transistor circuits 120-4 to 120-6 may share a well region.

The first to fourth block selection circuits 130-1 to 130-4 overlap with at least one of the first to sixth pass transistor circuits 120-1 to 120-6 in the second direction SD. The first to third pass transistor circuits 120-1 to 120-3 are disposed adjacent to each other in the first direction FD, and the fourth to sixth pass transistor circuits 120-1 to 120-3 are disposed in the peripheral area of the second semiconductor layer S2. Since the pass transistor circuits 120-4 to 120-6 are arranged to be adjacent to each other in the first direction (FD), the well regions of the first to third pass transistor circuits 120-1 to 120-3 are integrated to form a second pass transistor circuit. The first to third pass transistor circuits 120-1 to 120-3 may be configured to share a well region with each other, and the well regions of the fourth to sixth pass transistor circuits 120-4 to 120-6 may be integrated. Thus, the fourth to sixth pass transistor circuits 120-4 to 120-6 may share a well region with each other. According to this embodiment, the first to third pass transistor circuits 120-1 to 120-3 are configured to share a well region, and the fourth to sixth pass transistor circuits 120-4 to 120-6 are By configuring the well area to be shared, the size of the memory device can be reduced.

FIG. 9 is a layout diagram showing the arrangement of first to third pass transistor circuits and first and second block selection circuits of FIG. 8 .

Referring to FIG. 9 , the first block selection circuit 130-1 is disposed to overlap portions of the first pass transistor circuit 120-1 and the third pass transistor 120-3 in the second direction (SD). It can be. The second block selection circuit 130-2 may be disposed to overlap other portions of the second pass transistor circuit 120-2 and the third pass transistor 120-3 in the second direction SD.

As described with reference to FIG. 8, the first pass transistor circuit 120-1 is connected to the first block selection circuit 130-1 through block selection lines, and from the first block selection circuit 130-1 A block selection signal may be provided. The second pass transistor circuit 120-2 may be connected to the second block selection circuit 130-2 through block selection lines and receive a block selection signal from the second block selection circuit 130-2. The third pass transistor circuit 120-3 is connected to the first block selection circuit 130-1 through block selection lines and can receive a block selection signal from the first block selection circuit 130-1. It may be connected to the second block selection circuit 130-2 through selection lines and receive a block selection signal from the second block selection circuit 130-2.

The first block selection circuit 130-1 is arranged to overlap parts of the first pass transistor circuit 120-1 and the third pass transistor 120-3 in the second direction (SD), and the second block selection circuit The circuit 130-2 is arranged to overlap other parts of the second pass transistor circuit 120-2 and the third pass transistor 120-3 in the second direction (SD), so that the first block selection circuit 130 Delay time occurring in the process of the block selection signal from -1) being transferred to the first pass transistor circuit 120-1 and the third pass transistor 120-3, and the second block selection circuit 130-2 A delay time occurring in a process in which the block selection signal from is transferred to the second pass transistor circuit 120-2 and the third pass transistor 120-3 may be reduced.

The pass transistors PTR of the first pass transistor circuit 120 - 1 may be connected to the memory cell array above the first region R1 , and the pass transistors PTR of the second pass transistor circuit 120 - 2 may be connected. ) may be connected to the memory cell array above the second region R2. The pass transistors PTR of the third pass transistor circuit 120 - 3 may be connected in common to the memory cell array over the first region R1 and the memory cell array over the second region R2 . That is, the memory cell array above the first region R1 and the memory cell array above the second region R2 may share the pass transistors PTR of the third pass transistor circuit 120 - 3 .

According to the present embodiment, a pass transistor for transmitting an operating voltage to the memory cell array over the first region R1 and a pass transistor for transmitting an operating voltage to the memory cell array over the second region R2 are integrated to form the first The size of the memory device can be reduced by configuring the memory cell array above the region R1 and the memory cell array above the second region R2 to share pass transistors.

10 is a cross-sectional view of a memory cell array of a memory device according to an exemplary embodiment.

Referring to FIG. 10 , the memory cell array 110 includes a plurality of electrode layers 20, a plurality of interlayer insulating layers 22, and a plurality of electrode layers 20 alternately stacked on a source plate 10. and a plurality of cell plugs CP penetrating the plurality of interlayer insulating layers 22 .

The cell plug CP may include a filling layer FI, a channel layer CL surrounding the filling layer FI, and a memory layer ML surrounding the channel layer CL. The filling layer FI, the channel layer CL, and the memory layer ML may extend in the vertical direction VD to pass through the plurality of electrode layers 22 and the plurality of interlayer insulating layers 24 .

The filling layer FI may include an insulating material. For example, the filling layer FI may include oxide. The channel layer CL may include a semiconductor material. For example, the channel film CL may include polysilicon. The memory layer ML may include a tunnel insulating layer surrounding the channel layer CL, a data storage layer surrounding the tunnel insulating layer, and a blocking layer surrounding the data storage layer. The tunnel insulating layer may include a material capable of charge tunneling. For example, the tunnel insulating layer may include oxide. In one embodiment, the data storage layer may include a material capable of trapping charges. For example, the data storage layer may include nitride. In another embodiment, the data storage layer may include various materials according to data storage methods. For example, the data storage layer may include silicon, a phase change material, or nanodots. The blocking layer may include a material capable of blocking the movement of charges. For example, the blocking layer may include oxide.

The electrode layers 20 may include at least one source select line, at least one drain select line, and a plurality of word lines. A source selection transistor may be formed at a portion where the source selection line surrounds the cell plug CP. A memory cell may be configured in a portion surrounding the cell plug CP. A drain select transistor may be formed in a portion where the drain select line surrounds the cell plug CP. At least one source selection transistor, a plurality of memory cells, and at least one drain selection transistor may be disposed along one cell plug CP in a vertical direction VD to form one cell string. The channel film CL may be connected to the bit line BL through the bit line contact BLC.

The electrode layers 20 may be staggered with each other in the first direction FD to form a staircase structure. Although not shown, wiring patterns connected to the electrode layers 20 may be disposed on the stair structure. The electrode layers 20 may be connected to a corresponding pass transistor circuit ( 120 in FIG. 3 ) through wiring patterns.

Although, in this embodiment, the case where the memory cell array 110 is a 3D stacked memory is illustratively shown, the scope of the present invention is not limited thereto. The memory cell array 110 may be a two-dimensional memory in which memory cells are planarly arranged on a two-dimensional plane. Although, in this embodiment, the memory cell is a flash memory cell as an example, the type of memory cell is not limited thereto.

FIG. 11 is an exemplary layout diagram of a memory device different from the present invention, and FIG. 12 is an exemplary layout diagram of a memory device according to the present invention in contrast to FIG. 11 .

Referring to FIG. 11 , block selection circuits 130 are provided between the pass transistor circuit 120 in the first region R1 and the pass transistor circuits 120 in the second region R2 and in the third region R3. It is disposed between the pass transistor circuit 120 of ) and the pass transistor circuits 120 of the fourth region R4, and the pass transistor circuits 120 and the page buffer circuits 140 extend in the second direction SD. It is not placed in an area overlapping with

According to this arrangement structure, the size of the first direction (FD) of the second semiconductor layer (S2) is the first direction (FD) of the pass transistor circuits 120 in the first region (R1) and the second region (R2). ) size, the size of the page buffer circuits 140 in the first direction (FD) of the first and second regions R1 and R2, and block selection of the first and second regions R1 and R2 It will have a size proportional to the sum of the first direction (FD) sizes of the circuits 130 . That is, the size of the first direction (FD) of the memory device will increase due to the block selection circuits 130 .

As the degree of integration of the memory device increases, the number of word lines increases, and the number of pass transistors that transfer operating voltages to the word lines increases in proportion to the number of word lines, so that the first direction of the pass transistor circuits 120 ( FD) increases and the size of the first direction FD of the memory device tends to increase. Also, as the capacity of a single memory block increases and the number of memory blocks decreases, the size of the memory device in the second direction (SD) tends to decrease.

Since the memory device is used after being packaged, it is mounted and used in a mobile product, for example, and therefore, it must be packaged in a size smaller than that required by the demand. Therefore, it is difficult to arbitrarily change the size of the memory device.

As one method for preventing the size increase in the first direction (FD) of the memory device due to integration, a method of reducing the size of the first direction (FD) of the memory cell array (110 in FIG. 2 ) and reducing the pitch of bit lines is a method. There may be. The pitch of bit lines represents the sum of the width of one bit line and the spacing between adjacent bit lines. If the pitch of bit lines is reduced, the margin of the bit line formation process decreases, increasing the probability of occurrence of defects, and the adjacent bit lines Interference noise may increase due to an increase in parasitic capacitance between the BLs.

Referring to FIG. 12, according to the present invention, block selection circuits 130 are disposed in the peripheral area of the second semiconductor layer S2 overlapping with at least one of the pass transistor circuits 120 in the second direction SD. It can be. Alternatively, as described with reference to FIG. 7 , the block selection circuits 130 are located in the peripheral area of the second semiconductor layer S2 overlapping with at least one of the page buffer circuits 140 in the second direction SD. can be placed.

According to this arrangement structure, the size of the second semiconductor layer S2 and the first direction FD of the memory device will not increase due to the block selection circuits 130 . Therefore, compared to FIG. 11 , the size of the memory device in the first direction FD can be reduced. In the case of the comparative example of FIG. 11, the size of the first direction (FD) of the second semiconductor layer S2 has the size of L1, and in the case of the embodiment of the present invention shown in FIG. 12, the first direction of the second semiconductor layer S2 (FD) The size may have a size of L2 smaller than L1. That is, according to an embodiment of the present invention, the size of the first direction (FD) of the memory device may be reduced by the size of L1-L2.

Referring back to FIG. 11 , the pass transistor circuits 120 are spaced apart from each other with an interval in the first direction FD, and a block is formed in the center of the second semiconductor layer S2 between the pass transistor circuits 120. Since the selection circuits 130 are disposed, the block selection circuits 130 as well as the wiring patterns connecting the memory cell arrays and the pass transistor circuits 120 are formed in the wiring layer at the center of the second semiconductor layer S2. Wiring patterns connected to are also disposed, causing a bottleneck phenomenon of the wiring patterns, which will cause difficulty in disposing the wiring patterns. Also, since the pass transistor circuits 120 are spaced apart from each other with the block selection circuits 130 interposed therebetween, it will be impossible to integrate the well regions of the pass transistor circuits 120 .

Referring back to FIG. 12, according to an embodiment of the present invention, the pass transistor circuits 120 are disposed adjacent to each other in the center of the second semiconductor layer S2, and between the pass transistor circuits 120, a block selection circuit ( 130) is not located, only wiring patterns connecting the memory cell arrays and the pass transistor circuits 120 are disposed in the wiring layer at the center of the second semiconductor layer S2, and wirings connected to the block selection circuits 130 are disposed. Patterns may not be placed. The wiring patterns connected to the pass transistor circuits 120 and the wiring patterns connected to the block selection circuit 130 can be distributedly arranged, and the bottleneck phenomenon of the wiring patterns can be prevented to facilitate the arrangement of the wiring patterns. there is. In addition, since the pass transistor circuits 120 are disposed to be adjacent to each other in the first direction FD, the pass transistor circuits 120 are configured to share the well area by integrating the well area of the pass transistor circuits 120. By doing so, the size of the memory device can be reduced.

13 is a schematic block diagram of a memory system including a memory device according to an embodiment of the present invention.

Referring to FIG. 13 , a memory system 500 may store data accessed by a host 600 such as a mobile phone, MP3 player, laptop computer, desktop computer, game console, TV, in-vehicle infotainment system, and the like. there is.

The memory system 500 may be manufactured as one of various types of storage devices according to an interface protocol connected to the host 600 . For example, the memory system 500 includes a solid state drive (SSD), MMC, eMMC, RS-MMC, multimedia card in the form of micro-MMC, SD, mini-SD, and micro-SD. secure digital card, USB (universal storage bus) storage device, UFS (universal flash storage) device, PCMCIA (personal computer memory card international association) card type storage device, PCI (peripheral component interconnection) card type Any of various types of storage devices such as a storage device, a storage device in the form of a PCI-E (PCI-express) card, a compact flash (CF) card, a smart media card, a memory stick, etc. can be configured.

The memory system 500 may be manufactured in any one of various types of packages. For example, the memory system 500 includes package on package (POP), system in package (SIP), system on chip (SOC), multi-chip package (MCP), chip on board (COB), wafer- level fabricated package), wafer-level stack package (WSP), and the like.

The memory system 500 may include a nonvolatile memory device 510 and a controller 520 .

The nonvolatile memory device 510 may operate as a storage medium of the memory system 500 . The nonvolatile memory device 510 includes a NAND flash memory device, a NOR flash memory device, a ferroelectric random access memory (FRAM) using a ferroelectric capacitor, and a tunneling magneto-resistive memory device according to memory cells. , magnetic random access memory (MRAM) using a TMR film, phase change random access memory (PRAM) using chalcogenide alloys, and resistive RAM using a transition metal oxide (resistive random access memory, ReRAM), etc. may be configured with any one of various types of nonvolatile memory devices.

13 illustrates that the memory system 500 includes one nonvolatile memory device 510, but this is for convenience of explanation, and the memory system 500 may include a plurality of nonvolatile memory devices. , the present invention can be equally applied to the memory system 500 including a plurality of nonvolatile memory devices. The nonvolatile memory device 510 may include a memory device according to an embodiment of the present invention.

The controller 520 may control overall operations of the memory system 500 by driving firmware or software loaded into the memory 523 . The controller 520 may decode and run instructions or algorithms in code form such as firmware or software. The controller 520 may be implemented in hardware or a combination of hardware and software.

The controller 520 may include a host interface 521 , a processor 522 , a memory 523 and a memory interface 524 . Although not shown in FIG. 13 , the controller 520 encodes write data provided from the host with Error Correction Code (ECC) to generate parity, and uses the parity to read data read from the nonvolatile memory device 510. and an ECC engine that performs ECC decoding.

The host interface 521 may interface between the host 600 and the memory system 500 in response to a protocol of the host 600 . For example, the host interface 521 may include universal serial bus (USB), universal flash storage (UFS), multimedia card (MMC), parallel advanced technology attachment (PATA), serial advanced technology attachment (SATA), and small computer (SCSI). System interface), serial attached SCSI (SAS), peripheral component interconnection (PCI), and PCI express (PCI-E) protocols may be used to communicate with the host 600 .

The processor 522 may include a micro control unit (MCU) and a central processing unit (CPU). The processor 522 may process a request transmitted from the host 600 . In order to process the request transmitted from the host 600, the processor 522 runs an instruction or algorithm in the form of code loaded into the memory 523, that is, firmware, and the host interface 521, the memory ( 523) and internal functional blocks such as the memory interface 524 and the nonvolatile memory device 510 may be controlled.

The processor 522 generates control signals to control the operation of the nonvolatile memory device 510 based on requests transmitted from the host 600, and transfers the generated control signals to the nonvolatile memory memory device 524 through the memory interface 524. device 510.

The memory 523 may be comprised of random access memory such as dynamic random access memory (DRAM) or static random access memory (SRAM). The memory 523 may store firmware driven by the processor 522 . In addition, the memory 523 may store data necessary for driving the firmware, for example, meta data. That is, the memory 523 may operate as a working memory of the processor 522 .

The memory 523 is a data buffer for temporarily storing write data to be transmitted from the host 600 to the nonvolatile memory device 510 or read data to be transmitted from the nonvolatile memory device 510 to the host 600. ) may be configured to include. That is, the memory 523 may operate as a buffer memory. The memory 523 may receive and store map data from the nonvolatile memory device 510 when the memory system boots.

The memory interface 524 may control the nonvolatile memory device 510 according to the control of the processor 522 . Memory interface 524 may also be referred to as a memory controller. The memory interface 524 may provide control signals to the nonvolatile memory device 510 . The control signals may include commands, addresses, and operation control signals for controlling the nonvolatile memory device 510 . The memory interface 524 may provide data stored in the data buffer to the nonvolatile memory device 510 or store data transmitted from the nonvolatile memory device 510 in the data buffer.

In addition, the controller 520 may further include a map cache (not shown) for caching map data referenced by the processor 522 among map data stored in the memory 423 .

14 is a schematic block diagram of a computing system including a memory device according to an embodiment of the present invention.

Referring to FIG. 14, a computing system 700 according to the present invention includes a memory system 710 electrically connected to a system bus 760, a microprocessor 720, a RAM 730, a user interface 740, and a baseband. When the computing system 700 according to the present invention is a mobile device, a battery (not shown) for supplying an operating voltage of the computing system 700 may include a modem 750 such as a baseband chipset. additional will be provided. Although not shown in the drawing, it is typical in the field that an application chipset, a camera image processor (CIS), a mobile DRAM, and the like may be further provided to the computing system 700 according to the present invention. It is self-evident to those who have acquired human knowledge. The memory system 710 may constitute, for example, a Solid State Drive/Disk (SSD) using a non-volatile memory to store data. Alternatively, the memory system 710 may be provided as a fusion flash memory (eg, OneNAND flash memory).

The embodiments of the present invention described above are not implemented only through devices and methods, but may also be implemented through a program that realizes functions corresponding to the configuration of the embodiments of the present invention or a recording medium on which the program is recorded. Implementation will be easily implemented by an expert in the technical field to which the present invention belongs based on the description of the above-described embodiment.

Although the detailed description of the present invention described above has been described with reference to embodiments of the present invention, those skilled in the art or those having ordinary knowledge in the art will find the spirit and spirit of the present invention described in the claims to be described later. It will be understood that the present invention can be variously modified and changed without departing from the technical scope.

110: memory cell array
120, 120-1 to 120-6: pass transistor circuit
130, 130-1 to 130-4: block selection circuit
140, 140-1 to 140-4: page buffer circuit
150: peripheral circuit

Claims (20)

A first semiconductor layer including a memory cell array connected to a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction; and
A pass transistor circuit overlapping the first semiconductor layer in a vertical direction orthogonal to the first and second directions and connected to a memory cell array through the plurality of word lines; and the memory cell through the plurality of bit lines. A second semiconductor layer including a page buffer circuit connected to the array and a block selection circuit providing a block selection signal to the pass transistor circuit;
wherein the block selection circuit is disposed in a peripheral area of the second semiconductor layer overlapping with at least one of the page buffer circuit and the pass transistor in the second direction. According to claim 1,
The memory device according to claim 1 , wherein the block selection circuit is disposed adjacent to the pass transistor circuit in the second direction. According to claim 1,
The block selection circuit is divided into a first block selection region and a second block selection region and disposed on both sides of the pass transistor circuit in the second direction. 4 . The method of claim 3 , wherein the pass transistor circuit comprises a plurality of first pass transistor stages receiving block selection signals from the first block selection region and a plurality of second pass transistor stages receiving block selection signals from the second block selection region. Including pass transistor stages,
The plurality of first pass transistor stages are disposed closer to the first block selection region than the plurality of second pass transistor stages;
The plurality of second pass transistor stages are arranged closer to the second block selection region than the plurality of first pass transistor stages. According to claim 1,
The memory device of claim 1 , wherein the block selection circuit is disposed adjacent to the page buffer circuit in the second direction. According to claim 5,
The memory device according to claim 1 , wherein at least a portion of the block selection circuit overlaps the memory cell array in the vertical direction. a first semiconductor layer including a plurality of memory cell arrays connected to a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction;
a plurality of pass transistor circuits overlapping the first semiconductor layer in a vertical direction orthogonal to the first and second directions and connected to a corresponding memory cell array through the plurality of word lines; a second semiconductor layer including a plurality of page buffer circuits connected to the corresponding memory cell array through a plurality of page buffer circuits and a plurality of block selection circuits providing a block selection signal to a corresponding pass transistor circuit;
The plurality of block selection circuits are disposed in a peripheral area of the second semiconductor layer overlapping with at least one of the plurality of pass transistors and the plurality of page buffer circuits in the second direction. According to claim 7,
the plurality of memory cell arrays include a first memory cell array and a second memory cell array adjacent to each other in the first direction;
The plurality of pass transistor circuits include a first pass transistor circuit connected to the first memory cell array and a second pass transistor circuit connected to the second memory cell array;
The memory device according to claim 1 , wherein the first pass transistor circuit and the second pass transistor circuit are disposed adjacent to each other in the first direction at the center of the second semiconductor layer. According to claim 8,
The second semiconductor layer includes a first region and a second region adjacent to each other in the first direction;
the first memory cell array overlaps the first area in the vertical direction, and the second memory cell array overlaps the second area in the vertical direction;
wherein the first pass transistor circuit is disposed at an edge of the first region adjacent to the second region, and the second pass transistor circuit is disposed at an edge of the second region adjacent to the first region. Device. According to claim 8,
The first pass transistor circuit and the second pass transistor circuit share a well area. According to claim 7,
the plurality of memory cell arrays include a first memory cell array and a second memory cell array adjacent to each other in the first direction;
The plurality of pass transistor circuits include a first pass transistor circuit connected to the first memory cell array, a second pass transistor circuit connected to the second memory cell array, and the first memory cell array and the second memory cell array. A third pass transistor circuit connected in common;
The memory device according to claim 1 , wherein the first to third pass transistor circuits are arranged adjacent to each other in the first direction at the center of the second semiconductor layer. According to claim 11,
The second semiconductor layer includes a first region and a second region adjacent to each other in the first direction;
the first memory cell array overlaps the first area in the vertical direction, and the second memory cell array overlaps the second area in the vertical direction;
The third pass transistor circuit is disposed in a region including a boundary between the first region and the second region;
The first pass transistor circuit is disposed adjacent to the third pass transistor in the first direction in the first region;
The memory device of claim 1 , wherein the second pass transistor circuit is disposed adjacent to the third pass transistor in the first direction in the second region. According to claim 11,
The first to third pass transistor circuits share a well region. According to claim 7,
The memory device according to claim 1 , wherein each of the plurality of block selection circuits is disposed adjacent to a corresponding pass transistor circuit in the second direction. According to claim 7,
Each of the plurality of block selection circuits is divided into a first block selection region and a second block selection region and disposed on both sides of the corresponding pass transistor circuit in the second direction. According to claim 15,
Each of the pass transistor circuits includes a plurality of first pass transistor stages receiving block selection signals from the first block selection region and a plurality of second pass transistor stages receiving block selection signals from the second block selection region. contains,
The plurality of first pass transistor stages are disposed closer to the first block selection region than the plurality of second pass transistor stages,
The plurality of second pass transistor stages are arranged closer to the second block selection region than the plurality of first pass transistor stages. According to claim 7,
wherein each of the plurality of block selection circuits is disposed adjacent to one of the plurality of page buffer circuits in the second direction. According to claim 7,
The memory device according to claim 1 , wherein at least a portion of each of the plurality of block selection circuits overlaps one of the plurality of memory cell arrays in the vertical direction. According to claim 7,
The memory device according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are formed on a single wafer. According to claim 7,
The first semiconductor layer and the second semiconductor layer are formed on different wafers and bonded to each other.

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