KR20210091457A - Semiconductor memory device having page buffer - Google Patents

Abstract

A semiconductor memory device is disclosed. The disclosed semiconductor memory device includes: a latch provided on a circuit chip; and a bit line selection transistor provided on each of a first memory chip and a second memory chip stacked on the circuit chip and exchanging data with the latch. According to the present invention, it is possible to reduce a difference in program and read speeds between stacked memory chips.

Description

A semiconductor memory device having a page buffer {SEMICONDUCTOR MEMORY DEVICE HAVING PAGE BUFFER}

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a page buffer.

As the demand for mobile phones, removable memory devices, and digital cameras increases, the demand for nonvolatile memory devices that are mainly used as memory devices for these products is increasing. Among nonvolatile memory devices, a NAND flash memory device is widely used as a data storage device. A NAND flash memory device includes a plurality of page buffers connected to bit lines and performs operations necessary to read and output data stored in memory cells using the page buffers.

Recently, as a part of increasing the capacity and performance of a semiconductor memory device, a structure in which a plurality of memory chips are stacked on a circuit chip provided with page buffers has been proposed.

Embodiments of the present invention may provide a semiconductor memory device capable of reducing a difference in operating speed between stacked memory chips.

Embodiments of the present invention may provide a semiconductor memory device capable of improving operating speed.

A semiconductor memory device according to an embodiment of the present invention includes: a latch provided on a circuit chip; and a bit line selection transistor provided on each of the first and second memory chips stacked on the circuit chip and transmitting and receiving data to and from the latch.

A semiconductor memory device according to an embodiment of the present invention includes: a bit line selection transistor provided in each of first and second memory chips stacked on a circuit chip; a through chip interconnect traversing the first and second memory chips and commonly connected to a bit line select transistor of the first memory chip and a bit line select transistor of the second memory chip; and a through chip interconnect provided in the circuit chip; and a latch connected to the bit line select transistor of the first memory chip and the bit line select transistor of the second memory chip through an interconnect.

A semiconductor memory device according to an embodiment of the present invention includes: low voltage devices of a page buffer circuit provided on a circuit chip; and high voltage devices of the page buffer circuit provided in each of the first and second memory chips stacked on the circuit chip.

According to embodiments of the present invention, a difference in program and read speeds between stacked memory chips can be reduced.

According to embodiments of the present invention, it is possible to improve the program, read, and erase speeds of the semiconductor memory device without increasing the size and manufacturing cost.

1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention.
FIG. 2 is an equivalent circuit diagram of one of the memory blocks shown in FIG. 1 .
3A and 3B are circuit diagrams illustrating a page buffer and a CSL eraser according to embodiments of the present invention.
4 to 10 are schematic views of semiconductor memory devices according to embodiments of the present invention.
11 is a cross-sectional view of a semiconductor memory device according to an exemplary embodiment.
12A to 13B are diagrams illustrating a semiconductor memory device according to the present invention.
14 is a block diagram schematically illustrating a memory system including a semiconductor memory device according to an exemplary embodiment of the present invention.
15 is a block diagram schematically illustrating a computing system including a semiconductor memory device according to an embodiment of the present invention.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims.

In addition, since the shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in a singular, it may include a case in which a plural is included unless otherwise explicitly stated. In interpreting the components in the embodiments of the present invention, even if there is no separate explicit description, it should be interpreted as including an error range.

In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, order, or number of the elements are not limited by the terms. In addition, components in the embodiments of the present invention are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

When it is described that a component is “connected”, “coupled” or “connected” to another component, the component may be directly connected or connected to the other component, but other components may be interposed between each component. It will be understood that each component may be “interposed” or “connected”, “coupled” or “connected” through another component. In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between the two parts unless 'directly' is used.

In addition, the features (configurations) in the embodiments of the present invention can be partially or wholly combined or combined or separated from each other, and technically various interlocking and driving are possible, and each embodiment is implemented independently with respect to each other It may be possible or may be implemented together in a related relationship.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 1 , a semiconductor memory device 100 according to an embodiment of the present invention includes a memory cell array 110 , a row decoder X-DEC 120 , a page buffer circuit 130 , and a peripheral circuit (PERI Circuit). , 140) and a CSL erase unit (CSL Erase Unit, 150).

The memory cell array 110 may include a first memory cell array 110A and a second memory cell array 110B. The first memory cell array 110A and the second memory cell array 110B may be provided on different memory chips. In the present embodiment, the memory cell array 110 is configured in two memory chips, but may be configured in three or more memory chips.

Each of the first and second memory cell arrays 110A and 110B may include a plurality of memory blocks BLK. Although not shown, the memory block BLK may include a plurality of cell strings. The cell string may include at least one drain select transistor, a plurality of memory cells, and at least one source select transistor connected in series. The memory cell may be a volatile memory cell or a non-volatile memory cell. Hereinafter, the semiconductor memory device 100 will be described as a vertical NAND flash device, but it should be understood that the technical spirit of the present invention is not limited thereto.

Each of the memory blocks BLK of the first and second memory cell arrays 110A and 110B may be connected to the row decoder 120 through a plurality of row lines RL. The first and second memory cell arrays 110A and 110B may be connected to the page buffer circuit 130 through bit lines BL.

The row decoder 120 may select any one of the memory blocks BLK included in the first and second memory cell arrays 110A and 110B in response to the row address X_A provided from the peripheral circuit 140 . there is. The row decoder 120 applies the operating voltage X_V provided from the peripheral circuit 140 to a row line connected to a selected memory block among the memory blocks BLK included in the first and second memory cell arrays 110A and 110B. It can be transmitted to the RLs. To transfer the operating voltage, the row decoder 120 may include a plurality of pass transistor units respectively corresponding to the memory blocks BLK. The pass transistor unit may include a plurality of pass transistors respectively connected to the row lines RL of the corresponding memory block BLK. The number of pass transistor units may be equal to the sum of the number of memory blocks BLK included in the first memory cell array 110A and the number of memory blocks BLK included in the second memory cell array 110B. there is.

The erase operation of the semiconductor memory device 100 may be performed in units of memory blocks BLK. When the erase voltage Verase is applied to the channels of the memory cells during the erase operation, the row decoder 120 responds to the row address X_A provided from the peripheral circuit 140 at least one of the memory blocks BLK. can be selected.

The page buffer circuit 130 may include a plurality of page buffers PB respectively connected to the bit lines BL. The page buffer circuit 130 may receive the page buffer control signal PB_C from the peripheral circuit 140 and transmit/receive the data signal DATA to and from the peripheral circuit 140 . The page buffer circuit 130 may control the bit lines BL arranged in the memory cell array 110 in response to the page buffer control signal PB_C. For example, the page buffer circuit 130 detects a signal of the bit line BL of the memory cell array 110 in response to the page buffer control signal PB_C to thereby detect data stored in the memory cells of the memory cell array 110 . may be detected, and the data signal DATA may be transmitted to the peripheral circuit 140 according to the detected data. The page buffer circuit 130 may apply a signal to the bit line BL based on the data signal DATA received from the peripheral circuit 140 in response to the page buffer control signal PB_C, and thus the memory cell Data may be written into memory cells of the array 110 . The page buffer circuit 130 may write data to or read data from a memory cell connected to the activated word line.

The peripheral circuit 140 may receive the command signal CMD, the address signal ADD, and the control signal CTRL from the outside of the semiconductor memory device 100 , and may be an external device of the semiconductor memory device 100 , for example, Data may be transmitted/received to and from the memory controller. The peripheral circuit 140 is a signal for writing data into or reading data from the memory cell array 110 based on the command signal CMD, the address signal ADD, and the control signal CTRL. For example, the row address X_A, the page buffer control signal PB_C, and the like may be output. The peripheral circuit 140 may generate various voltages required by the semiconductor memory device 100 by using an external voltage supplied to the semiconductor memory device 100 .

The peripheral circuit 140 may include a plurality of pumping capacitors, and may generate a plurality of voltages by selectively activating the plurality of pumping capacitors. The plurality of voltages may include an operating voltage X_V and an erase voltage Verase. The peripheral circuit 140 may provide an erase voltage Verase to the page buffer circuit 130 and the CSL erase unit 150 during an erase operation.

The CSL eraser 150 may be connected to the first and second memory cell arrays 110A and 110B through a common source line CSL. The CSL eraser 150 may connect an erase voltage Verase provided from the peripheral circuit 140 to the common source line CSL during an erase operation, and accordingly, the first and second memory cell arrays 110A and 110B. An erase voltage Vrease may be transferred to channels of the memory cells of .

Hereinafter, in the accompanying drawings, a stacking direction of memory chips is defined as a first direction FD, an arrangement direction of bit lines is defined as a second direction SD, and an extension direction of the bit lines is defined as a third direction ( TD) will be defined. The second direction SD and the third direction TD may substantially perpendicularly cross each other. The first direction FD may correspond to a direction perpendicular to the second direction SD and the third direction TD. In the following specification, 'vertical' or 'vertical direction' will be used to have substantially the same meaning as the first direction FD. A direction indicated by an arrow in the drawing and a direction opposite thereto indicate the same direction.

FIG. 2 is an equivalent circuit diagram of the memory blocks BLK illustrated in FIG. 1 .

Referring to FIG. 2 , the memory block BLK may include a plurality of cell strings CSTR connected between a plurality of bit lines BL and a common source line CSL.

The bit lines BL extend in the third direction TD and may be arranged along the second direction SD. A plurality of cell strings CSTR may be connected in parallel to each of the bit lines BL. The cell strings CSTR may be commonly connected to the common source line CSL. A plurality of cell strings CSTR may be connected between the plurality of bit lines BL and one common source line CSL.

Each of the cell strings CSTR includes a drain select transistor DST connected to the bit line BL, a source select transistor SST connected to a common source line CSL, a drain select transistor DST, and a source select transistor SST. It may include a plurality of memory cells M connected therebetween. The drain select transistor DST, the memory cells M, and the source select transistor SST may be connected in series along the first direction FD.

The drain select lines DSL, the plurality of word lines WL, and the source select line SSL may be disposed between the bit lines BL and the common source line CSL in the first direction FD. there is. The drain select lines DSL may be respectively connected to gates of the corresponding drain select transistors DST. The word lines WL may be respectively connected to gates of the corresponding memory cells M. As shown in FIG. The source select line SSL may be connected to gates of the source select transistors SST. Memory cells M commonly connected to one word line WL may constitute one page. The semiconductor memory device 100 may perform a program operation and a read operation in units of pages. Cell strings CSTR commonly connected to one bit line BL may constitute one cell string group CSG.

3A and 3B are circuit diagrams illustrating a page buffer PB and a CSL eraser 150 according to embodiments of the present invention.

Referring to FIG. 3A , the page buffer PB may be connected to the cell string group CSG through the bit line BL. The page buffer PB may include a latch LC, a bit line select transistor BL_HVN, and a first erase voltage pass transistor BL_GIDL.

The CSL erasing unit 150 may be connected to the cell string group CSG through the common source line CSL. The CSL eraser 150 may include a second erase voltage pass transistor SOC_GIDL. The page buffer PB may be provided for each bit line BL. The CSL eraser 150 may be provided for each of the first memory cell array ( 110A of FIG. 1 ) or the second memory cell array ( 110B of FIG. 1 ).

The bit line selection transistor BL_HVN is connected between the bit line BL and the sensing line SO, and may operate in response to the bit line selection signal BLSEL. When the bit line select signal BLSEL is activated, the bit line select transistor BL_HVN may connect the bit line BL and the sensing line SO. When the bit line select signal BLSEL is deactivated, the bit line select transistor BL_HVN may separate the bit line BL from the sensing line SO.

The latch LC may apply a voltage to the sensing line SO based on the stored data. The voltage applied to the sensing line SO may be transferred to the bit line BL through the bit line select transistor BL_HVN. The latch LC may perform latching based on the voltage of the sensing line SO. Latching may be performed based on a voltage transferred from the bit line BL to the sensing line SO through the bit line selection transistor BL_HVN.

The first erase voltage pass transistor BL_GIDL is connected between the erase voltage Verase and the bit line BL, and operates in response to the erase enable signal EREN. When the erase enable signal EREN is activated, the first erase voltage pass transistor BL_GIDL may connect the erase voltage Verase to the bit line BL, and accordingly, channels of the memory cells through the bit line BL. An erase voltage Verase may be applied to the . When the erase enable signal EREN is deactivated, the first erase voltage pass transistor BL_GIDL may separate the erase voltage Verase from the bit line BL.

The second erase voltage pass transistor SOC_GIDL is connected between the erase voltage Verase and the common source line CSL and operates in response to the erase enable signal EREN. When the erase enable signal EREN is activated, the second erase voltage pass transistor SOC_GIDL may connect the erase voltage Verase and the common source line CSL, and accordingly, the memory cells are separated through the common source line CSL. An erase voltage Vrease may be applied to the channels. When the erase enable signal EREN is deactivated, the second erase voltage pass transistor SOC_GIDL may separate the erase voltage Verase from the common source line CSL.

During an erase operation, the bit line select signal BLSEL may be deactivated and the erase enable signal EREN may be activated. When the erase enable signal EREN is activated, the first and second erase voltage pass transistors BL_GIDL and SOC_GIDL are turned on to apply the first and second erase voltage pass transistors BL_GIDL and SOC_GIDL to the bit line select transistor BL_HVN and the first and second erase voltage pass transistors BL_GIDL and SOC_GIDL. A high level erase voltage Verase may be applied. To withstand the high level of the erase voltage Verase, the bit line select transistor BL_HVN and the first and second erase voltage pass transistors BL_GIDL and SOC_GIDL may be configured as high voltage transistors. When the bit line select signal BLSEL is inactivated during an erase operation, the bit line select transistor BL_HVN is turned off, so that the erase voltage Verase is not transferred to the latch LC. The latch LC may include low voltage transistors. The first erase voltage pass transistor BL_GIDL and the second erase voltage pass transistor SOC_GIDL may be included in the erase circuit. The erase circuit may be connected to at least one of the bit line BL and the common source line CSL to transmit an erase voltage to at least one of the bit line BL and the common source line CSL during an erase operation.

Referring to FIG. 3B , the page buffer PB may not include the first erase voltage pass transistor (BL_GIDL of FIG. 3A ). The page buffer PB may include a bit line select transistor BL_HVN and a latch LC.

The CSL eraser 150 may include a third erase voltage pass transistor SOC_COUPLING. One terminal of the third erase voltage pass transistor SOC_COUPLING may be connected to the erase voltage Verase, and the other terminal of the third erase voltage pass transistor SOC_COUPLING is common to the common source line CSL and the wiring W. can be connected

The wiring W may overlap the bit line BL. An insulating layer (not shown) may be disposed between the wiring W and the bit line BL. At the overlapping portion between the wiring W and the bit line BL, a first electrode formed of the wiring W, a second electrode formed of the bit line BL, and an insulating layer formed between the wiring W and the bit line BL are formed. A coupling capacitor C including a dielectric layer made of may be configured.

When the erase enable signal EREN is activated during an erase operation, the third erase voltage pass transistor SOC_COUPLING is turned on to connect the erase voltage Verase to the common source line CSL and the wiring W. Accordingly, the erase voltage Verase may be transferred to the channels of the memory cells through the common source line CSL. Further, the potential of the bit line BL may be boosted by following the erase voltage Verase applied to the wiring W due to the coupling capacitor C, and the boosted voltage may be transmitted to the channels of the memory cells. can When the erase enable signal EREN is deactivated, the third erase voltage pass transistor SOC_COUPLING may be turned off, so that the erase voltage Verase may be separated from the common source line CSL and the wiring W. The third erase voltage pass transistor SOC_COUPLING may be included in the erase circuit. The erase circuit may be connected to at least one of the bit line BL and the common source line CSL to transmit an erase voltage to at least one of the bit line BL and the common source line CSL during an erase operation.

4 is a diagram illustrating a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 4 , in the semiconductor memory device according to an embodiment of the present invention, a circuit chip PC and first and second memory chips MC1 stacked on the circuit chip PC in a first direction FD are shown. ,MC2) may be included. Although two memory chips are stacked in the following embodiments, the number of stacked memory chips may be three or more.

The first memory chip MC1 may include a first memory cell array 110A, and the second memory chip MC2 may include a second memory cell array 110B. The first memory cell array 110A and the second memory cell array 110B may constitute the memory cell array 110 illustrated in FIG. 1 .

Each of the first memory cell array 110A and the second memory cell array 110B includes a source plate SOURCE, a plurality of memory blocks BLK and a plurality of bit lines BL provided on the source plate SOURCE. may include. The memory block BLK may include a plurality of cell strings. The cell string may be connected between the bit line BL and the source plate SOURCE. In each of the first and second memory chips MC1 and MC2 , the bit line BL may be commonly connected to the plurality of memory blocks BLK.

A bit line selection transistor BL_HVN may be provided in each of the first and second memory chips MC1 and MC2 . The bit line selection transistor BL_HVN provided in the first memory chip MC1 may be connected to one of the bit lines BL of the first memory chip MC1 . The bit line selection transistor BL_HVN provided in the second memory chip MC2 may be connected to one of the bit lines BL of the second memory chip MC2 . For simplification of the drawing, only one bit line selection transistor BL_HVN is shown in each of the first and second memory chips MC1 and MC2 in FIG. 4 , but a plurality of each of the first and second memory chips MC1 and MC2 is shown in FIG. 4 . It should be understood that a plurality of bit line selection transistors BL_HVN respectively connected to the bit lines BL are provided.

A latch circuit 130A and a peripheral circuit 140 may be provided in the circuit chip PC. The latch circuit 130A may be defined as a group of latches LC included in the page buffers PB constituting the page buffer circuit 130 of FIG. 1 .

The drain D1 of the bit line selection transistor BL_HVN of the first memory chip MC1 and the drain D1 of the bit line selection transistor BL_HVN of the second memory chip MC2 are connected to one sensing line SO. It may be connected in common, and may be connected to the latch LC provided in the circuit chip PC through one sensing line SO. The bit line select transistor BL_HVN of the first memory chip MC1 and the bit line select transistor BL_HVN of the second memory chip MC2 are commonly connected to one latch LC, and the latch LC and the data can be exchanged

The bit line selection signal BLSEL may be provided to the first memory chip MC1 and the second memory chip MC2 from the peripheral circuit 140 . The bit line select transistor BL_HVN of the first memory chip MC1 and the bit line select transistor BL_HVN of the second memory chip MC2 may operate in response to the bit line select signal BLSEL. When the bit line select signal BLSEL is activated, the bit line select transistor BL_HVN of the first memory chip MC1 and the bit line select transistor BL_HVN of the second memory chip MC2 are turned on at the same time to turn on the first memory chip The bit line BL of the MC1 and the bit line BL of the second memory chip MC2 may be connected to the sensing line SO.

When the bit line select signal BLSEL is deactivated, the bit line select transistor BL_HVN of the first memory chip MC1 and the bit line select transistor BL_HVN of the second memory chip MC2 are turned off at the same time, so that the first memory The bit line BL of the chip MC1 and the bit line BL of the second memory chip MC2 may be separated from the sensing line SO.

5 is a diagram illustrating a semiconductor memory device according to an embodiment of the present invention. For simplicity, the description of the same configuration as in FIG. 4 will be omitted and only differences will be described.

Referring to FIG. 5 , a first erase voltage pass transistor BL_GIDL may be provided in each of the first and second memory chips MC1 and MC2 . The first erase voltage pass transistor BL_GIDL provided in the first memory chip MC1 is connected to one of the bit lines BL of the first memory chip MC1 and is applied to the bit line BL during an erase operation. Verase) can be passed. The first erase voltage pass transistor BL_GIDL provided in the second memory chip MC2 is connected to one of the bit lines BL of the second memory chip MC2 and is applied to the bit line BL during an erase operation. Verase) can be passed. For the sake of simplicity, in FIG. 5 , only one first erase voltage pass transistor BL_GIDL is shown in each of the first and second memory chips MC1 and MC2 , but each of the first and second memory chips MC1 and MC2 is illustrated in FIG. 5 . It should be understood that a plurality of first erase voltage pass transistors BL_GIDL respectively connected to the plurality of bit lines BL are provided.

In each of the first and second memory chips MC1 and MC2 , the bit line selection transistor BL_HVN and the first erase voltage pass transistor BL_GIDL may share a source S1 , and may be formed with the bit line selection transistor BL_HVN and the bit line selection transistor BL_HVN. The bit line BL may be connected to the source S1 shared by the first erase voltage pass transistor BL_GIDL.

The drain D2 of the first erase voltage pass transistor BL_GIDL of the first memory chip MC1 and the drain D2 of the first erase voltage pass transistor BL_GIDL of the second memory chip MC2 are connected to one line ( It may be commonly connected to L1 , and may be connected to the peripheral circuit 140 through the line L1 to receive the erase voltage Verase from the peripheral circuit 140 . The drain D2 of the first erase voltage pass transistor BL_GIDL of the first memory chip MC1 and the drain D2 of the first erase voltage pass transistor BL_GIDL of the second memory chip MC2 are connected in common. , may share the line L1.

The first erase enable signal EREN1 from the peripheral circuit 140 may be provided to the first memory chip MC1 , and the second erase enable signal EREN2 from the peripheral circuit 140 may be transmitted to the second memory chip MC1 . MC2) can be provided. The first erase voltage pass transistors BL_GIDL of the first memory chip MC1 may operate in response to the first erase enable signal EREN1 , and may operate in response to the first erase voltage pass transistor of the second memory chip MC2 . The BL_GIDL may operate in response to the second erase enable signal EREN2 . During the erase operation, the erase voltage Verase is applied to the bit lines BL of the memory chip including the selected memory block and the erase voltage Verase is applied to the bit lines BL of the memory chip not including the selected memory block. In order not to apply an on/off control, the first erase voltage pass transistors BL_GIDL of the first memory chip MC1 and the first erase voltage pass transistors BL_GIDL of the second memory chip MC2 may be turned on/off.

For example, when the memory block included in the first memory chip MC1 is selected and the memory block included in the second memory chip MC2 is not selected during the erase operation, the first erase enable signal EREN1 is is activated, and the second erase enable signal EREN2 may be deactivated. Accordingly, the first erase voltage pass transistor BL_GIDL of the first memory chip MC1 is turned on and the first erase voltage pass transistor BL_GIDL of the second memory chip MC2 is turned off, so that the first memory chip ( The erase voltage Verase may be applied to the bit lines BL of the MC1 , and the erase voltage Verase may not be applied to the bit lines BL of the second memory chip MC2 . In addition, an erase voltage Verase may be applied to the source plate SOURCE of the first memory chip MC1 .

During the erase operation, an erase operation voltage of 0V is applied to the word lines of the selected memory block BLK among the memory blocks BLK of the first memory chip MC1 , and the erase operation voltage of 0V is applied to the drain select line and the source select line. A voltage is applied to turn off the drain select transistor and the source select transistor. When the erase voltage Verase is applied to the bit line BL and the source plate SOURCE while the drain select transistor and the source select transistor are turned off and the potentials of the bit line BL and the source plate SOURCE rise, As a leakage current flows between the drain and the bulk, a gate induced drain leakage (GIDL) flows in the channel direction, and hot holes generated in the drain select transistor and the source select transistor flow in the channel direction to increase the potential of the channel. will rise Accordingly, the potential difference between the potential (0V) of the word lines of the selected memory block BLK and the potential between the channels becomes greater than a size necessary for erasing the memory cell, and thus the memory cells of the memory block BLK are erased.

During the erase operation, the word lines, the drain select line, and the source select line of the unselected memory block BLK among the memory blocks BLK of the first memory chip MC1 are floated. When the erase voltage Verase is applied to the bit line BL and the source plate SOURCE to increase the potentials of the bit line BL and the source plate SOURCE, the potential of the channel increases to the bit line BL and the source plate SOURCE. SOURCE), and the potentials of the floating word lines, the drain select line, and the source select line rise along the channel potential due to the coupling phenomenon. Accordingly, the potential difference between the word lines and the channel of the unselected memory block BLK is maintained to be less than a size necessary for erasing the memory cell, so that the memory cells of the unselected memory block BLK are not erased.

Since the erase voltage Verase is not applied to the bit lines BL of the second memory chip MC2 , the memory blocks BLK of the second memory chip MC2 are not erased.

6 is a diagram illustrating a semiconductor memory device according to an embodiment of the present invention. For simplicity, the description of the same configuration as in FIG. 5 will be omitted and only differences will be described.

Referring to FIG. 6 , a second erase voltage pass transistor SOC_GIDL may be provided in each of the first and second memory chips MC1 and MC2 . The second erase voltage pass transistor SOC_GIDL provided in the first memory chip MC1 is connected to the source plate SOURCE of the first memory chip MC1 , and during an erase operation, the source plate SOURCE of the first memory chip MC1 . ) to an erase voltage (Verase). The second erase voltage pass transistor SOC_GIDL provided in the second memory chip MC2 is connected to the source plate SOURCE of the second memory chip MC2 to perform an erase operation on the source plate SOURCE of the second memory chip MC2 . ) to an erase voltage (Verase).

In each of the first and second memory chips MC1 and MC2 , the first erase voltage pass transistor BL_GIDL and the second erase voltage pass transistor SOC_GIDL may share a drain D2 , and the first erase voltage pass transistor An erase voltage Verase may be connected to the drain D2 shared by BL_GIDL and the second erase voltage pass transistor SOC_GIDL.

The drain D2 of the second erase voltage pass transistor SOC_GIDL of the first memory chip MC1 and the drain D2 of the second erase voltage pass transistor SOC_GIDL of the second memory chip MC2 are connected to one line ( It may be commonly connected to L1 , and may be connected to the peripheral circuit 140 through the line L1 to receive the erase voltage Verase from the peripheral circuit 140 . The drain D2 of the second erase voltage pass transistor SOC_GIDL of the first memory chip MC1 and the drain D2 of the second erase voltage pass transistor SOC_GIDL of the second memory chip MC2 are connected in common. Line L1 may be shared.

The first erase enable signal EREN1 from the peripheral circuit 140 may be provided to the first memory chip MC1 , and the second erase enable signal EREN2 from the peripheral circuit 140 may be transmitted to the second memory chip MC1 . MC2) can be provided. The first erase voltage pass transistor BL_GIDL and the second erase voltage pass transistor SOC_GIDL of the first memory chip MC1 may operate in response to the first erase enable signal EREN1 , and may operate in response to the first erase enable signal EREN1 . The first erase voltage pass transistor BL_GIDL and the second erase voltage pass transistor SOC_GIDL of MC2 may operate in response to the second erase enable signal EREN2 .

During the erase operation, the erase voltage Verase is applied to the bit lines BL and the source plate SOURCE of the memory chip including the selected memory block, and the bit lines BL of the memory chip not including the selected memory block; and In order not to apply the erase voltage Verase to the source plate SOURCE, the first and second erase voltage pass transistors BL_GIDL and SOC_GIDL of the first memory chip MC1 and the first and second erase voltage pass transistors BL_GIDL and SOC_GIDL of the second memory chip MC2 The second erase voltage pass transistors BL_GIDL and SOC_GIDL may be controlled on/off.

For example, when the memory block included in the first memory chip MC1 is selected during the erase operation and the memory block included in the second memory chip MC2 is not selected, the first erase enable signal EREN1 may be activated, and the second erase enable signal EREN2 may be deactivated. Accordingly, the erase voltage Verase may be applied to the bit lines BL and the source plate SOURCE of the first memory chip MC1 , and the bit lines BL of the second memory chip MC2 and The erase voltage Verase may not be applied to the source plate SOURCE.

7 is a diagram illustrating a semiconductor memory device according to an embodiment of the present invention. For simplicity, the description of the same configuration as in FIG. 4 will be omitted and only differences will be described.

Referring to FIG. 7 , the first bit line selection signal BLSEL1 is provided to the first memory chip MC1 from the peripheral circuit 140 , and the second bit line selection signal BLSEL2 is supplied from the peripheral circuit 140 . 2 may be provided in the memory chip MC2 .

The bit line select transistors BL_HVN of the first memory chip MC1 may operate in response to the first bit line select signal BLSEL1 , and the bit line select transistors BL_HVN of the second memory chip MC2 may be operated. may operate in response to the second bit line selection signal BLSEL2.

The first bit line selection signal BLSEL1 and the second bit line selection signal BLSEL2 may be selectively activated. For example, when a page of the first memory chip MC1 is programmed or read, the first bit line selection signal BLSEL1 may be activated and the second bit line selection signal BLSEL2 may be deactivated. Accordingly, the bit line select transistor BL_HVN of the first memory chip MC1 is turned on and the bit line select transistor BL_HVN of the second memory chip MC2 is turned off, and thus the bit of the first memory chip MC1 is turned off. The line BL may be connected to the sensing line SO, and the bit line BL of the second memory chip MC2 may be separated from the sensing line SO.

8 is a diagram illustrating a semiconductor memory device according to an embodiment of the present invention. For simplicity, the description of the same configuration as in FIG. 7 will be omitted and only differences will be described.

Referring to FIG. 8 , a first erase voltage pass transistor BL_GIDL may be provided in each of the first and second memory chips MC1 and MC2 . The first erase voltage pass transistor BL_GIDL provided in the first memory chip MC1 is connected to one of the bit lines BL of the first memory chip MC1 and is applied to the bit line BL during an erase operation. Verase) can be passed. The first erase voltage pass transistor BL_GIDL provided in the second memory chip MC2 is connected to one of the bit lines BL of the second memory chip MC2 to provide an erase voltage to the bit line BL during an erase operation. (Verase) can be passed. For simplicity of the drawing, in FIG. 8 , only one first erase voltage pass transistor BL_GIDL is shown in each of the first and second memory chips MC1 and MC2 , but each of the first and second memory chips MC1 and MC2 is illustrated in FIG. It should be understood that a plurality of first erase voltage pass transistors BL_GIDL respectively connected to the plurality of bit lines BL are provided.

The drain D2 of the first erase voltage pass transistor BL_GIDL of the first memory chip MC1 and the drain D2 of the first erase voltage pass transistor BL_GIDL of the second memory chip MC2 are connected to one line ( It may be commonly connected to L1 , and may be connected to the peripheral circuit 140 through the line L1 to receive the erase voltage Verase from the peripheral circuit 140 . The drain D2 of the first erase voltage pass transistor BL_GIDL of the first memory chip MC1 and the drain D2 of the first erase voltage pass transistor BL_GIDL of the second memory chip MC2 are connected in common. Line L1 can be shared.

The first erase enable signal EREN1 from the peripheral circuit 140 may be provided to the first memory chip MC1 , and the second erase enable signal EREN2 from the peripheral circuit 140 may be transmitted to the second memory chip MC1 . MC2) can be provided. The first erase voltage pass transistors BL_GIDL of the first memory chip MC1 may operate in response to the first erase enable signal EREN1 , and may operate in response to the first erase voltage pass transistor of the second memory chip MC2 . The BL_GIDL may operate in response to the second erase enable signal EREN2 . During the erase operation, the erase voltage Verase is applied to the bit lines BL of the memory chip including the selected memory block and the erase voltage Verase is applied to the bit lines BL of the memory chip not including the selected memory block. In order not to apply an on/off control, the first erase voltage pass transistor BL_GIDL of the first memory chip MC1 and the first erase voltage pass transistor BL_GIDL of the second memory chip MC2 may be controlled on/off.

For example, when the memory block included in the first memory chip MC1 is selected and the memory block included in the second memory chip MC2 is not selected during the erase operation, the first erase enable signal EREN1 is is activated, and the second erase enable signal EREN2 may be deactivated. Accordingly, the first erase voltage pass transistor BL_GIDL of the first memory chip MC1 is turned on and the first erase voltage pass transistor BL_GIDL of the second memory chip MC2 is turned off, so that the first memory chip ( The erase voltage Verase may be applied to the bit lines BL of the MC1 , and the erase voltage Verase may not be applied to the bit lines BL of the second memory chip MC2 .

9 is a diagram illustrating a semiconductor memory device according to an embodiment of the present invention. For simplicity, the description of the same configuration as in FIG. 8 will be omitted and only differences will be described.

Referring to FIG. 9 , a second erase voltage pass transistor SOC_GIDL may be provided in each of the first and second memory chips MC1 and MC2 . The second erase voltage pass transistor SOC_GIDL provided in the first memory chip MC1 is connected to the source plate SOURCE of the first memory chip MC1 , and during an erase operation, the source plate SOURCE of the first memory chip MC1 . ) to an erase voltage (Verase). The second erase voltage pass transistor SOC_GIDL provided in the second memory chip MC2 is connected to the source plate SOURCE of the second memory chip MC2 to perform an erase operation on the source plate SOURCE of the second memory chip MC2 . ) to an erase voltage (Verase).

In each of the first and second memory chips MC1 and MC2 , the first erase voltage pass transistor BL_GIDL and the second erase voltage pass transistor SOC_GIDL may share a drain D2 , and the first erase voltage pass transistor An erase voltage Verase may be connected to the drain D2 shared by BL_GIDL and the second erase voltage pass transistor SOC_GIDL.

The drain D2 of the second erase voltage pass transistor SOC_GIDL of the first memory chip MC1 and the drain D2 of the second erase voltage pass transistor SOC_GIDL of the second memory chip MC2 are connected to one line ( It may be commonly connected to L1 , and may be connected to the peripheral circuit 140 through the line L1 to receive the erase voltage Verase from the peripheral circuit 140 . The drain D2 of the second erase voltage pass transistor SOC_GIDL of the first memory chip MC1 and the drain D2 of the second erase voltage pass transistor SOC_GIDL of the second memory chip MC2 are connected in common. Line L1 may be shared.

The first erase enable signal EREN1 from the peripheral circuit 140 may be provided to the first memory chip MC1 , and the second erase enable signal EREN2 from the peripheral circuit 140 may be transmitted to the second memory chip MC1 . MC2) can be provided. The first erase voltage pass transistor BL_GIDL and the second erase voltage pass transistor SOC_GIDL of the first memory chip MC1 may operate in response to the first erase enable signal EREN1 , and may operate in response to the first erase enable signal EREN1 . The first erase voltage pass transistor BL_GIDL and the second erase voltage pass transistor SOC_GIDL of MC2 may operate in response to the second erase enable signal EREN2 .

During the erase operation, the erase voltage Verase is applied to the bit lines BL and the source plate SOURCE of the memory chip including the selected memory block, and the bit lines BL of the memory chip not including the selected memory block; and The first and second erase voltage pass transistors BL_GIDL and SOC_GIDL of the first memory chip MC1 and the first and second erase voltages of the second memory chip MC2 are not applied to the source plate SOURCE. The second erase voltage pass transistors BL_GIDL and SOC_GIDL may be controlled on/off.

For example, when the memory block included in the first memory chip MC1 is selected during the erase operation and the memory block included in the second memory chip MC2 is not selected, the first erase enable signal EREN1 may be activated, and the second erase enable signal EREN2 may be deactivated. Accordingly, the erase voltage Verase may be applied to the bit lines BL and the source plate SOURCE of the first memory chip MC1 , and the bit lines BL of the second memory chip MC2 and The erase voltage Verase may not be applied to the source plate SOURCE.

10 is a diagram illustrating a semiconductor memory device according to an embodiment of the present invention. For simplicity, the description of the same configuration as in FIG. 7 will be omitted and only differences will be described.

Referring to FIG. 10 , each of the first and second memory chips MC1 and MC2 may include a wiring W overlapping the bit lines BL. The wiring W may overlap the bit lines BL with an insulating layer (not shown) interposed therebetween. At the overlapping portion between the wiring W and the bit line BL, a first electrode formed of the wiring W, a second electrode formed of the bit line BL, and an insulating layer formed between the wiring W and the bit line BL are formed. A coupling capacitor C including a dielectric layer made of may be configured. Each of the first and second memory chips MC1 and MC2 may include a plurality of coupling capacitors C. Referring to FIG.

A third erase voltage pass transistor SOC_COUPLING may be provided in each of the first and second memory chips MC1 and MC2 . The third erase voltage pass transistor SOC_COUPLING of the first memory chip MC1 is connected to the source plate SOURCE and the wiring W of the first memory chip MC1 so as to An erase voltage Verase may be transferred to the source plate SOURCE and the wiring W. The third erase voltage pass transistor SOC_COUPLING of the second memory chip MC2 is connected to the source plate SOURCE and the wiring W of the second memory chip MC2 to remove the second memory chip MC2 during the erase operation. An erase voltage Verase may be transferred to the source plate SOURCE and the wiring W.

The first erase enable signal EREN1 from the peripheral circuit 140 may be provided to the first memory chip MC1 , and the second erase enable signal EREN2 from the peripheral circuit 140 may be transmitted to the second memory chip MC1 . MC2) can be provided. The third erase voltage pass transistor SOC_COUPLING of the first memory chip MC1 may operate in response to the first erase enable signal EREN1 , and may operate in response to the third erase voltage pass transistor SOC_COUPLING of the second memory chip MC2 . SOC_COUPLING may operate in response to the second erase enable signal EREN2 . During the erase operation, an erase voltage Verase is applied to the source plate SOURCE and the wiring W of the memory chip including the selected memory block, and the source plate SOURCE and the wiring W of the memory chip not including the selected memory block are erased. ), the third erase voltage pass transistor SOC_COUPLING of the first memory chip MC1 and the third erase voltage pass transistor SOC_COUPLING of the second memory chip MC2 are turned on / Off can be controlled.

For example, when the memory block included in the first memory chip MC1 is selected during the erase operation and the memory block included in the second memory chip MC2 is not selected, the first erase enable signal EREN1 may be activated, and the second erase enable signal EREN2 may be deactivated. Accordingly, an erase voltage Verase may be applied to the source plate SOURCE and the wiring W of the first memory chip MC1 , and the source plate SOURCE and the wiring W of the second memory chip MC2 may be applied. ) may not be applied to the erase voltage Verase.

Although, in the embodiment described with reference to FIG. 10 , the bit line select transistor BL_HVN of the first memory chip MC1 and the bit line select transistor BL_HVN of the second memory chip MC2 select different bit lines. A case of operating in response to a signal is shown, but is not limited thereto. As described with reference to FIGS. 4 to 6 , the bit line select transistor BL_HVN of the first memory chip MC1 and the bit line select transistor BL_HVN of the second memory chip MC2 select one bit line. It may operate in response to a signal.

11 is a cross-sectional view schematically illustrating a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 11 , each of the first and second memory chips MC1 and MC2 includes a source plate SOURCE, a plurality of vertical channels CH protruding from the source plate SOURCE in a first direction FD, It may include a plurality of electrode layers 30 and a plurality of interlayer insulating layers 32 alternately stacked along the vertical channels CH, and a transistor HVN provided on the semiconductor layer 20 . The transistor HVN may constitute one of the bit line select transistor BL_HVN and the first, second, and third source voltage pass transistors BL_GIDL, SOC_GIDL, and SOC_COUPLING described above with reference to FIGS. 4 to 10 . can

The source plate SOURCE and the semiconductor layer 20 may be disposed on the base layer 10 . The base layer 10 may be made of an insulating material. The semiconductor layer 20 and the source plate SOURCE may be formed through the same process and may be made of the same material. Although the semiconductor layer 20 is separated from the source plate SOURCE in this embodiment, the semiconductor layer 20 may be integrally formed with the source plate SOURCE.

The electrode layers 30 and the interlayer insulating layers 32 may be alternately stacked on the source plate SOURCE. The electrode layers 30 may include a conductive material. For example, the electrode layers 30 may include a doped semiconductor (eg, doped silicon, etc.), a metal (eg, tungsten, copper, aluminum, etc.), a conductive metal nitride (eg, titanium nitride, tantalum nitride, etc.) or a transition It may include at least one selected from a metal (eg, titanium, tantalum, etc.). The interlayer insulating layers 32 may include silicon oxide. At least one layer from the bottom of the electrode layers 30 may constitute a source selection line. At least one layer from the top of the electrode layers 30 may constitute a drain selection line. The electrode layers 30 between the source select line and the drain select line may constitute word lines.

The vertical channels CH may be connected to the source plate SOURCE through the alternately stacked electrode layers 30 and the interlayer insulating layers 32 . Each of the vertical channels CH may include a channel layer 40 and a gate insulating layer 42 . The channel layer 40 may include polysilicon or single crystal silicon, and may include P-type impurities such as boron (B) in some regions. The gate insulating layer 42 may have a straw or cylinder shell shape surrounding the outer wall of the channel layer 40 . The gate insulating layer 42 may include a tunnel insulating layer, a charge storage layer, and a blocking layer sequentially stacked from the outer wall of the channel layer 40 . In some embodiments, the gate insulating layer 42 may have an oxide-nitride-oxide (ONO) stack structure in which an oxide film, a nitride film, and an oxide film are sequentially stacked. A source select transistor may be configured in portions where the source select line surrounds the vertical channels CH. Memory cells may be formed in portions where the word lines surround the vertical channels CH. A drain select transistor may be configured in portions where the drain select line surrounds the vertical channels CH.

A plurality of bit lines BL may be disposed on the vertical channels CH and the alternatingly stacked electrode layers 30 and interlayer insulating layers 32 . Bit line contacts BLC may be provided under the bit lines BL to connect the bit lines BL and the vertical channels CH.

A first through chip interconnect TCV1 crossing the first memory chip MC1 in the first direction FD may be provided. An upper end of the first through-chip interconnect TCV1 may be exposed as an upper surface of the first memory chip MC1 , and a lower end of the first through-chip interconnect TCV1 may be exposed as a lower surface of the first memory chip MC1 . there is.

A second through chip interconnect TCV2 crossing the second memory chip MC2 in the first direction FD may be provided. An upper end of the second through-chip interconnect TCV2 may be exposed as an upper surface of the second memory chip MC2 , and a lower end of the second through-chip interconnect TCV2 may be exposed as a lower surface of the second memory chip MC2 . there is. Upper and lower ends of the first and second through-chip interconnects TCV1 and TCV2 may be formed of a pad PAD1.

The pad PAD1 under the first through chip interconnect TCV1 may be bonded to the pad PAD2 of the circuit chip PC. The pad PAD1 under the second through chip interconnect TCV2 may be bonded to the pad PAD1 at the upper end of the first through chip interconnect TCV1 . The first through chip interconnect TCV1 and the second through chip interconnect TCV2 arranged in a line along the first direction FD may be connected to each other to form the through chip interconnect TCV. The through chip interconnect TCV may provide a routing path crossing the first and second memory chips MC1 and MC2 in the first direction FD. A plurality of through chip interconnects TCV may be provided in the first and second memory chips MC1 and MC2 .

The transistor HVN of the first memory chip MC1 and the transistor HVN of the second memory chip MC2 may be commonly connected to one through-chip interconnect TCV, and one through-chip interconnect TCV may be connected in common. It may be connected to the circuit chip PC through the When the transistor HVN is a bit line select transistor, the through chip interconnect TCV is formed between the bit line select transistor of the first memory chip MC1 and the bit line select transistor of the second memory chips MC1 and MC2 and the circuit chip ( A sensing line that connects the latch of the PC) can be configured.

12A to 13B are diagrams illustrating a semiconductor memory device according to the present invention. Hereinafter, effects of embodiments of the present invention will be described with reference to FIGS. 12A to 13B .

Referring to FIG. 12A , the bit line selection transistor BL_HVN may be provided in the circuit chip PC. The second memory chip MC2 is located farther from the circuit chip PC than the first memory chip MC1 . Accordingly, the length D2 of the path from the bit line select transistor BL_HVN to the bit line BL of the second memory chip MC2 is from the bit line select transistor BL_HVN to the bit line of the first memory chip MC1 . It will be longer than the length D1 of the path to (BL).

During the operation of the semiconductor memory device such as programming or reading, the bit line BL needs to be set to a predetermined voltage so that the operation can occur. Reference numeral PRECH, which is not described, denotes a charging/discharging circuit for charging the bit line BL. Since the bit line BL acts like an RC circuit, it will take time to charge or discharge to a predetermined voltage. When the bit line selection transistor BL_HVN is turned on, charging or discharging of the bit line BL is started. Due to the difference in length between D1 and D2, the bit line BL of the second memory chip MC2 is charged and discharged more slowly than the bit line BL of the first memory chip MC1, and accordingly, the second memory chip MC2 ) may be programmed or read at a slower speed than the memory cells of the first memory chip MC1 .

In embodiments of the present invention, the bit line select transistor BL_HVN is disposed in the first and second memory chips MC1 and MC2 . This arrangement includes the length of the path from the bit line select transistor BL_HVN to the bit line BL of the second memory chip MC2 and the bit line BL of the first memory chip MC1 from the bit line select transistor BL_HVN. ) makes it possible to reduce or eliminate the difference in the length of the path to ), and to increase the charge and discharge rates between the bit line BL of the first memory chip MC1 and the bit line BL of the second memory chip MC2. By reducing or eliminating the difference, the difference between the program speed and the read speed between the memory cell of the first memory chip MC1 and the memory cell of the second memory chip MC2 may be reduced.

Referring back to FIG. 12A , the bit line BL of the first memory chip MC1 and the bit line BL of the second memory chip MC2 may be commonly connected to one line L2, and the line ( L2) may be connected to the bit line selection transistor BL_HVN provided in the circuit chip PC. Line L2 may correspond to the through chip interconnect TCV described with reference to FIG. 11 .

During a program operation or a read operation with respect to a page of the first memory chip MC1 , the bit line selection transistor BL_HVN is turned on so that the bit line BL of the first memory chip MC1 and the second memory chip MC2 are connected. The bit line BL may be connected to the charge/discharge circuit PRECH. During a program or read operation, the bit line BL needs to be set to a predetermined voltage so that the operation can occur. Since the bit line BL acts like an RC circuit, it takes time to charge or discharge the bit line BL to a predetermined voltage. During a program or read operation on the first memory chip MC1 , the bit line BL of the first memory chip MC1 as well as the bit line BL of the second memory chip MC2 are charged and discharged through the charge/discharge circuit PRECH. connected to so that the bit line BL of the second memory chip MC2 is charged or discharged together with the bit line BL of the first memory chip MC1 so that the bit line BL of the first memory chip MC1 is A charging or discharging rate may be slowed, and accordingly, programming and reading rates may be reduced.

Referring to FIG. 12B , the bit line selection transistor BL_HVN corresponding to the bit line BL of the first memory chip MC1 and the bit line BL of the second memory chip MC2 respectively in the circuit chip PC. can be configured. The number of bit line selection transistors BL_HVN of the circuit chip PC is the number of bit lines BL of the first memory chip MC1 and the number of bit lines BL of the second memory chip MC2 . can be equal to the sum of

During a program or read operation for the first memory chip MC1 , the bit line selection transistor BL_HVN connected to the bit line BL of the second memory chip MC2 is turned off by turning off the bit of the second memory chip MC2 . The line BL may be separated from the charge/discharge circuit PRECH. Accordingly, since the bit line BL of the second memory chip MC2 is not charged or discharged, the charging or discharging speed of the bit line BL of the first memory chip MC1 is improved to improve program and read speeds. can

However, for connecting the bit line select transistors BL_HVN of the circuit chip PC to the bit lines BL of the first memory chip MC1 and the bit lines BL of the second memory chip MC2 The number of lines L2 is required as many as the sum of the number of bit lines BL of the first memory chip MC1 and the number of bit lines BL of the second memory chip MC2, This will be approximately double compared to the case of FIG. 12A. The line L2 is a configuration corresponding to the through-chip interconnect TCV described with reference to FIG. 11 , and as the number of the through-chip interconnects TCV increases, the manufacturing cost becomes high and the size of the semiconductor memory device increases.

According to the embodiments of the present invention, by configuring the bit line selection transistor BL_HVN in the memory chips MC1 and MC2, the bit line is charged and discharged during program and read operations without increasing the number of lines L2. can be reduced to improve the program and read speed.

Referring to FIG. 13A , the bit line BL of the first memory chip MC1 and the bit line BL of the second memory chip MC2 may be commonly connected to one line L2, and the line L2 ) may be connected to the first source voltage pass transistor BL_GIDL provided in the circuit chip PC. Line L2 may correspond to the through chip interconnect TCV described with reference to FIG. 11 .

The source plate SOURCE of the first memory chip MC1 and the source plate SOURCE of the second memory chip MC2 may be commonly connected to one line L3, and through the line L3, the circuit chip ( It may be connected to the second source voltage pass transistor SOC_GIDL provided in the PC). Line L3 may correspond to the through chip interconnect TCV described with reference to FIG. 11 .

During an erase operation on the memory block of the first memory chip MC1 , the first and second source voltage pass transistors BL_GIDL and SOC_GIDL are turned on so that the bit line BL and the source plate of the first memory chip MC1 are turned on. SOURCE) and the bit line BL and the source plate SOURCE of the second memory chip MC2 may be connected to the erase voltage Verase.

Since the bit line BL and the source plate SOURCE act like an RC circuit, it takes time to charge or discharge to the erase voltage Verase. During an erase operation on the memory block of the first memory chip MC1 , the bit line BL and the source plate SOURCE of the first memory chip MC1 as well as the bit line BL of the second memory chip MC2 and the source plate SOURCE is also connected to the erase voltage Verase to charge the bit line BL and the source plate SOURCE of the second memory chip MC2 together, so the bit line BL of the first memory chip MC1 ) and the charging rate of the source plate SOURCE may be slowed, and thus the erase rate may be lowered.

Referring to FIG. 13B , first source voltage pass transistors respectively corresponding to the bit line BL of the first memory chip MC1 and the bit line BL of the second memory chip MC2 are provided in the circuit chip PC. (BL_GIDL) and second source voltage pass transistors SOC_GIDL corresponding to the source plate SOURCE of the first memory chip MC1 and the source plate SOURCE of the second memory chip MC2, respectively can do.

The number of the first source voltage pass transistors BL_GIDL of the circuit chip PC is the number of bit lines BL of the first memory chip MC1 and the bit lines BL of the second memory chip MC2 can be equal to the sum of the number of

During an erase operation on the block BLK included in the first memory chip MC1 , the first and second source voltage pass transistors BL_GIDL and SOC_GIDL corresponding to the first memory chip MC1 are turned on and the second memory The first and second source voltage pass transistors BL_GIDL and SOC_GIDL corresponding to the chip MC1 are turned off so that the bit line BL and the source plate SOURCE of the second memory chip MC1 are erased by the erase voltage Verase. can be separated from Accordingly, since the bit line BL and the source plate SOURCE of the second memory chip MC2 are not charged, the charging speed of the bit line BL and the source plate SOURCE of the first memory chip MC1 is improved. It is possible to improve the erasing speed.

However, to connect the first source voltage pass transistor BL_GIDL of the circuit chip PC to the bit lines BL of the first memory chip MC1 and the bit lines BL of the second memory chip MC2 The number of lines L2 for this purpose is the number corresponding to the sum of the number of bit lines BL of the first memory chip MC1 and the number of bit lines BL of the second memory chip MC2. , this will be about twice as compared to the case of Fig. 12a. The line L2 is a configuration corresponding to the through-chip interconnect TCV described with reference to FIG. 11 , and as the number of the through-chip interconnects TCV increases, the manufacturing cost becomes high and the size of the semiconductor memory device increases.

According to embodiments of the present invention, by configuring the first source voltage pass transistor BL_GIDL in the memory chips MC1 and MC2, the bit line BL is charged during the erase operation without increasing the number of lines L2. Erasing speed can be improved by reducing the time.

14 is a block diagram schematically illustrating a memory system including a semiconductor memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 14 , a memory system 600 according to an embodiment of the present invention may include a nonvolatile memory device 610 and a memory controller 620 .

The nonvolatile memory device 610 may be configured as the aforementioned semiconductor memory device and may be operated in the aforementioned method. The memory controller 620 may be configured to control the nonvolatile memory device 610 . The combination of the nonvolatile memory device 610 and the memory controller 620 may provide a memory card or a solid state disk (SSD). The SRAM 621 is used as the working memory of the processing unit 622 . The host interface 623 includes a data exchange protocol of a host connected to the memory system 600 .

The error correction block 624 detects and corrects errors included in data read from the nonvolatile memory device 610 .

The memory interface 625 interfaces with the non-volatile memory device 610 of the present invention. The processing unit 622 performs various control operations for data exchange of the memory controller 620 .

Although not shown in the drawings, it is common knowledge in the art that the memory system 600 according to the present invention may further include a ROM (not shown) for storing code data for interfacing with a host. It is self-evident to those who have acquired The nonvolatile memory device 620 may be provided in a multi-chip package including a plurality of flash memory chips.

The memory system 600 of the present invention as described above may be provided as a high-reliability storage medium having a low probability of error occurrence. In particular, the nonvolatile memory device of the present invention may be provided in a memory system such as a solid state disk (SSD), which has been actively researched recently. In this case, the memory controller 620 may be configured to communicate with the outside (eg, a host) through one of various interface protocols such as USB, MMC, PCI-E, SATA, PATA, SCSI, ESDI, and IDE. will be.

15 is a block diagram schematically illustrating a computing system including a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 15 , a computing system 700 according to the present invention includes a memory system 710 electrically connected to a system bus 760 , a microprocessor 720 , a RAM 730 , a user interface 740 , and a baseband. It may include a modem 750 such as a baseband chipset. When the computing system 700 according to the present invention is a mobile device, a battery (not shown) for supplying the operating voltage of the computing system 700 is provided. additional will be provided. Although not shown in the drawings, it is common in the art that an application chipset, a camera image processor (CIS), a mobile DRAM, and the like may be further provided in the computing system 700 according to the present invention. It is self-evident to those who have acquired human knowledge. The memory system 710 may configure, for example, a solid state drive/disk (SSD) using nonvolatile memory to store data. Alternatively, the memory system 710 may be provided as a fusion flash memory (eg, one-NAND flash memory).

The embodiment of the present invention described above is not implemented only through the apparatus and method, and may be implemented through a program for realizing a function corresponding to the configuration of the embodiment of the present invention or a recording medium in which the program is recorded. The implementation will be easily implemented by those skilled in the art to which the present invention pertains from the description of the above-described embodiments.

Although the detailed description of the present invention described above has been described with reference to the embodiments of the present invention, those skilled in the art or those having ordinary skill in the art will have the spirit and spirit of the present invention described in the claims to be described later It will be understood that various modifications and variations of the present invention can be made without departing from the technical scope.

Claims (20)

a latch provided on the circuit chip; and
and a bit line selection transistor provided on each of the first and second memory chips stacked on the circuit chip and configured to exchange data with the latch. 2. The semiconductor memory device of claim 1, wherein the bit line select transistor of the first memory chip and the bit line select transistor of the second memory chip share one of through chip interconnects across the first and second memory chips. . The semiconductor memory device of claim 1 , wherein the bit line select transistor of the first memory chip and the bit line select transistor of the second memory chip are simultaneously turned on/off. The semiconductor memory device of claim 1 , wherein the bit line select transistor of the first memory chip and the bit line select transistor of the second memory chip are individually controlled on/off. The method of claim 1 , wherein each of the first and second memory chips comprises a memory cell array connected between a bit line connected to the bit line selection transistor and a source plate and including a plurality of memory blocks in which data is stored;
and a first erase voltage pass transistor connected to the bit line, each of the first and second memory chips, to apply an erase voltage to the bit line during an erase operation. The first memory according to claim 5, wherein, during an erase operation, an erase voltage is applied to a bit line of a memory chip including a selected memory block and an erase voltage is not applied to a bit line of a memory chip that does not include the selected memory block. A semiconductor memory device in which a first erase voltage pass transistor of a chip and a first erase voltage pass transistor of the second memory chip are individually controlled on/off. The semiconductor memory device of claim 1 , wherein each of the first and second memory chips further comprises a second erase voltage pass transistor connected to the source plate to apply an erase voltage to the source plate during an erase operation. The first memory of claim 7 , wherein an erase voltage is applied to the source plate of the memory chip including the selected memory block and the erase voltage is not applied to the source plate of the memory chip not including the selected memory block during the erase operation. A semiconductor memory device in which a second erase voltage pass transistor of a chip and a second erase voltage pass transistor of the second memory chip are individually on/off controlled. The apparatus of claim 1 , wherein each of the first and second memory chips comprises: a coupling capacitor including the bit line, a wiring overlapping the bit line, and an insulating layer disposed between the bit line and the wiring; and
a third erase voltage pass transistor connected to the source plate and the line to transfer an erase voltage to the source plate and the line during an erase operation; A semiconductor memory device further comprising a. 10. The method of claim 9, wherein the erase voltage is applied to the source plate and the wiring of the memory chip including the selected memory block during the erase operation, and the erase voltage is not applied to the source plate of the memory chip not including the selected memory block. A semiconductor memory device in which the third erase voltage pass transistor of the first memory chip and the third erase voltage pass transistor of the second memory chip are individually on/off controlled. a bit line selection transistor provided in each of the first and second memory chips stacked on the circuit chip;
a through chip interconnect traversing the first and second memory chips and commonly coupled to a bit line select transistor of the first memory chip and a bit line select transistor of the second memory chip; and
and a latch provided on the circuit chip and coupled to the bit line select transistor of the first memory chip and the bit line select transistor of the second memory chip through the through chip interconnect. The semiconductor memory device of claim 11 , wherein the bit line select transistor of the first memory chip and the bit line select transistor of the second memory chip are individually controlled on/off. The method of claim 11 , wherein each of the first and second memory chips comprises a memory cell array connected between a bit line connected to the bit line selection transistor and a source plate and including a plurality of memory blocks in which data is stored;
and a first erase voltage pass transistor connected to the bit line, each of the first and second memory chips, to apply an erase voltage to the bit line during an erase operation. The first memory of claim 13 , wherein, during an erase operation, an erase voltage is applied to a bit line of a memory chip including a selected memory block and an erase voltage is not applied to a bit line of a memory chip that does not include the selected memory block. A semiconductor memory device in which a first erase voltage pass transistor of a chip and a first erase voltage pass transistor of the second memory chip are individually controlled on/off. The semiconductor memory device of claim 13 , wherein each of the first and second memory chips further comprises a second erase voltage pass transistor connected to the source plate to apply an erase voltage to the source plate during an erase operation. The first memory of claim 15 , wherein, during an erase operation, an erase voltage is applied to a source plate of a memory chip including a selected memory block and an erase voltage is not applied to a source plate of a memory block that does not include the selected memory block. A semiconductor memory device in which a second erase voltage pass transistor of a chip and a second erase voltage pass transistor of the second memory chip are individually on/off controlled. The apparatus of claim 11 , wherein each of the first and second memory chips comprises: a coupling capacitor including the bit line, a wiring overlapping the bit line, and an insulating layer disposed between the bit line and the wiring; and
and a third erase voltage pass transistor connected to the source plate and the line to transfer an erase voltage to the source plate and the line during an erase operation. 18. The method of claim 17, wherein the erase voltage is applied to the source plate and wiring of the memory chip including the selected memory block during the erase operation, and the erase voltage is not applied to the source plate and the wiring of the memory chip not including the selected memory block; and a third erase voltage pass transistor of the first memory chip and a third erase voltage pass transistor of the second memory chip are individually on/off controlled. Low voltage elements of the page buffer circuit provided on the circuit chip; And
and high voltage devices of the page buffer circuit provided in each of the first and second memory chips stacked on the circuit chip. 20. The method of claim 19, wherein each of the first and second memory chips comprises a memory cell array connected between a bit line connected to the bit line selection transistor and a source plate and including a plurality of memory blocks in which data is stored;
each of the first and second memory chips includes an erase circuit connected to at least one of the bit line and the source plate to transfer an erase voltage to at least one of the bit line and the source plate during an erase operation; memory device.

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