KR20220169642A - Controller and operation method thereof - Google Patents

Abstract

A method of operating a controller which controls a memory device including multi-level cells programmed through first and second program steps comprises: a step of buffering data chunks to be programmed in a write buffer; a step of selectively backing up the data chunks to a backup memory; a step of determining a program order for each of the data chunks buffered in the write buffer, wherein a non-backup data chunk among the data chunks is programmed in a second program step; and a step of controlling the memory device to program the data chunks by having the memory device perform a first program step on a first physical page and perform a first program step on a second physical page following the first physical page and then performing a second program step on the first physical page. Accordingly, the present invention can provide a controller and a method of operating the controller which can reduce the manufacturing cost of the memory system while maintaining the performance and reliability of the memory system.

Description

Controller and operation method of controller {CONTROLLER AND OPERATION METHOD THEREOF}

The present invention relates to a controller and a method of operating the controller.

Recently, a paradigm for a computer environment is shifting to ubiquitous computing that allows a computer system to be used anytime and anywhere. As a result, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers is rapidly increasing. Such a portable electronic device generally uses a memory system using a memory device, that is, a data storage device. Data storage devices are used as main storage devices or auxiliary storage devices in portable electronic devices.

A data storage device using a non-volatile memory device, unlike a hard disk, has excellent stability and durability because it does not have a mechanical driving unit, and also has advantages such as very fast information access speed and low power consumption. As an example of a memory system having such an advantage, the data storage device includes a universal serial bus (USB) memory device, a memory card having various interfaces, a solid state drive (SSD), and the like.

SUMMARY OF THE INVENTION An object of the present invention is to provide a controller and an operating method of the controller capable of reducing manufacturing costs of a memory system while maintaining performance and reliability of the memory system.

According to an embodiment of the present invention, a method of operating a controller for controlling a memory device including multi-level cells programmed through first and second program steps includes buffering data chunks to be programmed in a write buffer; selectively backing up the data chunks to a backup memory; determining a program order of each of the data chunks buffered in the write buffer so that a non-backup data chunk among the data chunks is programmed in a second program step; and the memory device executes a first program step on a first physical page, performs a first program step on a second physical page subsequent to the first physical page, and then executes a second program step on the first physical page. and controlling the memory device to program the data chunks by performing.

The determining of the program order of each of the data chunks may include determining a program order such that a normal data chunk among the data chunks is programmed in a first or second program step, and the normal data chunk is written Among the data chunks buffered in the buffer, a corresponding backup data chunk may be a data chunk backed up in the backup memory.

The determining of the program order of each of the data chunks buffered in the write buffer may include determining the program order so that a normal data chunk among the data chunks is programmed when the memory device performs the first program step. step; determining the program order so that the non-backup data chunk is programmed when the non-backup data chunk is buffered in the write buffer when it is the turn of the memory device to perform the second program step; and determining the program order so that the normal data chunk is programmed when only the normal data chunk is buffered in the write buffer when the memory device is to perform the second program step.

In addition, the operating method may include providing a non-backup data chunk to the memory device; and removing the non-backup data chunk from the write buffer when a program operation of a physical page associated with the non-backup data chunk is successfully completed.

The operating method may further include providing the non-backup data chunk buffered in the write buffer to the memory device again, if the program operation of the physical page associated with the non-backup data chunk fails.

The operating method may further include providing a normal data chunk to the memory device; and removing the normal data chunk from the write buffer after providing the normal data chunk to the memory device, wherein the normal data chunk is the corresponding backup data among data chunks buffered in the write buffer. A chunk may be a data chunk backed up in the backup memory.

The operation method may further include removing a backup data chunk corresponding to the normal data chunk from the backup memory when a program operation of a physical page associated with the normal data chunk is successfully completed.

The operating method may further include providing the backup data chunk backed up in the backup memory to the memory device when a program operation of the physical page associated with the normal data chunk fails.

The step of selectively backing up the data chunks to the backup memory may include discarding the data chunks or backing them up to the backup memory so that a bottleneck does not occur in a data path where the data chunks received from the host are backed up to the backup memory. Including, the write buffer may be a memory that operates at a higher speed than the backup memory.

In addition, the step of selectively backing up the data chunks in the backup memory may include buffering the data chunks in the temporary buffer if there is free space in the temporary buffer through which the data chunks received from the host pass through, and buffering the data chunks in the temporary buffer. backing up the data chunk to a backup memory; and discarding the data chunk without buffering it in the temporary buffer when there is no free space in the temporary buffer.

According to an embodiment of the present invention, a controller controlling a memory device including multi-level cells programmed through first and second program steps includes a write buffer buffering data chunks to be programmed; a backup memory that selectively backs up the data chunks; and a processor configured to determine a program order of each of the data chunks buffered in the write buffer, such that a non-backup data chunk among the data chunks is programmed in a second program step, wherein the processor determines the program order. The device executes a first program step on a first physical page, performs a first program step on a second physical page subsequent to the first physical page, and then performs a second program step on the first physical page. Controls the memory device to program data chunks.

Also, the processor determines a program sequence such that a normal data chunk among the data chunks is programmed in a first or second program step, and the normal data chunk is a corresponding backup data chunk among data chunks buffered in the write buffer. A controller is a data chunk backed up to the backup memory.

In addition, the processor programs a normal data chunk among the data chunks when the memory device performs the first program step, and the non-backup data chunk is buffered in the write buffer when the second program step is performed. In this case, the non-backup data chunk is programmed, and when only the normal data chunk is buffered in the write buffer at the turn of performing the second program step, the program sequence may be determined to program the normal data chunk.

Also, the processor may provide a non-backup data chunk to the memory device, and may remove the non-backup data chunk from the write buffer when a program operation of a physical page associated with the non-backup data chunk is successfully completed.

Also, if a program operation of a physical page associated with the non-backup data chunk fails, the processor may provide the non-backup data chunk buffered in the write buffer to the memory device again.

In addition, the processor provides a normal data chunk to a memory device, removes the normal data chunk from the write buffer, and the normal data chunk is a corresponding backup data chunk among data chunks buffered in the write buffer. It can be a chunk of data backed up in memory.

Also, the processor may remove a backup data chunk corresponding to the normal data chunk from the backup memory when a program operation of a physical page associated with the normal data chunk is successfully completed.

Also, when a program operation of a physical page associated with the normal data chunk fails, the processor may provide the backup data chunk backed up in the backup memory to the memory device.

In addition, the backup memory selectively backs up data chunks received from the host to the backup memory so that a bottleneck does not occur in a data path backed up to the backup memory, and the write buffer operates at a higher speed than the backup memory. It can be a working memory.

In addition, the controller further includes a temporary buffer through which the data chunk received from the host passes, and the temporary buffer buffers the data chunk when there is free space therein and transfers the buffered data chunk to the backup memory. provided, and if there is no free space inside, the data chunk may be discarded without buffering.

The present invention may provide a controller and an operating method of the controller capable of reducing manufacturing costs of a memory system while maintaining performance and reliability of the memory system.

1 is a diagram schematically illustrating an example of a data processing system 100 including a memory system 110 according to an embodiment of the present invention.
2 is a diagram illustrating a memory system 110 according to an exemplary embodiment in detail.
FIG. 3 is a diagram for explaining a data path of data received from the host 102. Referring to FIG.
4 is a diagram illustrating a 3D memory cell array of the memory device 150 .
5 is a diagram for explaining a multi-step program operation of the memory device 150. Referring to FIG.
6 is a diagram illustrating a program sequence of the memory device 150 performing a multi-step program operation.
7 illustrates a transaction between the controller 130 and the memory device 150 for performing a write operation according to an embodiment of the present invention.
8 is a diagram illustrating the detailed operation of step S706.
9A and 9B are diagrams illustrating the operation of the controller 130 according to an embodiment of the present invention with specific examples.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

However, the present invention is not limited to the embodiments disclosed below and may be configured in various different forms, but only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art within the scope of the present invention. It is provided to fully inform you.

1 is a diagram schematically illustrating an example of a data processing system including a memory system according to an embodiment of the present invention.

Referring to FIG. 1 , a data processing system 100 includes a host 102 and a memory system 110 .

The host 102 may include electronic devices, for example, portable electronic devices such as mobile phones, MP3 players, and laptop computers, or electronic devices such as desktop computers, game consoles, TVs, and projectors.

The host 102 may include at least one operating system (OS). The operating system generally manages and controls the functions and operations of the host 102 and provides interaction between a user using the data processing system 100 or memory system 110 and the host 102 . The operating system supports functions and operations corresponding to the purpose and purpose of use of the user, and can be divided into a general operating system and a mobile operating system according to the mobility of the host 102 . The general operating system system in the operating system can be divided into a personal operating system and a corporate operating system according to a user's use environment.

The memory system 110 may operate to store data of the host 102 in response to a request of the host 102 . For example, the memory system 110 may include a solid state drive (SSD), MMC, embedded MMC (eMMC), reduced size MMC (RS-MMC), and a multi-media card (MMC) in the form of micro-MMC. Media Card), Secure Digital (SD) card in the form of SD, mini-SD, and micro-SD, USB (Universal Serial Bus) storage device, UFS (Universal Flash Storage) device, CF (Compact Flash) card, smart It may be implemented as one of various types of storage devices such as a smart media card, a memory stick, and the like.

The memory system 110 may be implemented by various types of storage devices. For example, the storage device includes a volatile memory device such as dynamic random access memory (DRAM) and static RAM (SRAM), read only memory (ROM), mask ROM (MROM), programmable ROM (PROM), and erasable memory (EPROM). ROM), electrically erasable ROM (EEPROM), ferromagnetic ROM (FRAM), phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, and the like.

The memory system 110 may include a memory device 150 and a controller 130 . The memory device 150 may store data for the host 102 , and the controller 130 may control data storage into the memory device 150 .

The controller 130 and the memory device 150 may be integrated into a single semiconductor device. For example, the controller 130 and the memory device 150 may be integrated into a single semiconductor device to form an SSD. When the memory system 110 is used as an SSD, the operating speed of the host 102 connected to the memory system 110 may be improved. In addition, the controller 130 and the memory device 150 may be integrated into a single semiconductor device to form a memory card. For example, the controller 130 and the memory device 150 may include a PC card (Personal Computer Memory Card International Association (PCMCIA)), a compact flash card (CF), a smart media card (SM, SMC), a memory stick, a multimedia card ( Memory cards such as MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), and Universal Flash Storage (UFS) can be configured.

As another example, the memory system 110 may include a computer, an ultra mobile PC (UMPC), a workstation, a net-book, a personal digital assistant (PDA), a portable computer, a web tablet, Tablet computer, wireless phone, mobile phone, smart phone, e-book, portable multimedia player (PMP), portable game console, navigation ) device, black box, digital camera, DMB (Digital Multimedia Broadcasting) player, 3-dimensional television, smart television, digital audio recorder , digital audio player, digital picture recorder, digital picture player, digital video recorder, digital video player, constitutes a data center storage, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, It may constitute a radio frequency identification (RFID) device, or one of various components constituting a computing system.

The memory device 150 may be a non-volatile memory device, and may maintain stored data even when power is not supplied. The memory device 150 may store data provided from the host 102 through a program operation, and may provide the data stored in the memory device 150 to the host 102 through a read operation. The memory device 150 includes a plurality of memory blocks, each of which includes a plurality of pages, and each of the pages may include a plurality of memory cells connected to word lines. In one embodiment, memory device 150 may be a flash memory. The flash memory may have a 3D stack structure.

The controller 130 may control the memory device 150 in response to a request from the host 102 . For example, the controller 130 may provide data read from the memory device 150 to the host 102 and store the data provided from the host 102 in the memory device 150 . For this operation, the controller 130 may control read, program, and erase operations of the memory device 150 .

The controller 130 may include a write buffer 146 . The controller 130 may buffer data to be programmed into the memory device 150 , for example, data received along with a write request from the host 102 in the write buffer 146 . The controller 130 may control the memory device 150 to program the data while providing data buffered in the write buffer 146 to the memory device 150 .

In case the program operation of the memory device 150 fails, the controller 130 stores the data until the program operation is successfully completed even after providing the data to the memory device 150. can be kept inside.

Write buffer 146 may be implemented with high-speed memory such as SRAM to quickly process write requests. High-speed memory has a faster access speed than general memory such as DRAM, but may have a low degree of integration and high manufacturing cost. If the controller 130 has to maintain all data to be programmed into the memory device 150 in the write buffer 146 until the program operation is successfully completed, the write buffer 146 with a large capacity may be required. When the high-capacity write buffer 146 is included in the memory system 110 , a circuit area of the memory system 110 may increase and manufacturing cost may increase.

The controller 130 may include a backup memory 148 for maintaining data to be programmed until the program operation is successfully completed. The controller 130 may buffer data from the host 102 in the write buffer 146 and back up the same data in the backup memory 148 . When the same data as the buffered data is backed up in the backup memory 148, the controller 130 provides the data buffered in the write buffer 146 to the memory device 150 and then transfers the data to the write buffer 146. can be removed from

The backup memory 148 may be implemented with a general memory such as DRAM, and the general memory may have a higher degree of integration and a lower manufacturing cost than the high-speed memory. When the controller 130 uses the backup memory 148, data to be programmed in the memory device 150 can be maintained in the controller 130, so even if the program operation of the memory device 150 fails, the reliability of the memory system 110 This can be maintained, and the circuit area and manufacturing cost of the memory system 110 can be reduced.

Meanwhile, when new data is backed up in the backup memory 148 faster than the speed at which data backed up in the backup memory 148 is deleted, a bottleneck may occur in the backup memory 148 . If the controller 130 has to back up all the data buffered in the write buffer 146 to the backup memory 148, when a bottleneck occurs in the backup memory 148, the data may not be buffered even in the write buffer 146. there is. If a bottleneck occurs in the backup memory 148 , write performance of the memory system 110 may deteriorate even though the write buffer 146 can provide a sufficient data transfer rate.

According to an embodiment of the present invention, the controller 130 may discard some of the data buffered in the write buffer 146 without backing it up so that a bottleneck does not occur in the backup memory 148 . Referring to FIG. 1 , the write buffer 146 may buffer a plurality of data chunks. Some of the plurality of data chunks buffered in the write buffer 146 may be backed up in the backup memory 148, and other data chunks may not be backed up in the backup memory 148.

A data chunk backed up in the backup memory 148 may be referred to as a backup data chunk, and the backup data chunk is shown as a shaded rectangle in FIG. 1 . A data chunk having a corresponding backup data chunk among the data chunks buffered in the write buffer 146 may be referred to as a normal data chunk, and is shown as a square with a dot pattern in FIG. 1 . That a data chunk buffered in the write buffer 146 has a backup data chunk may indicate that a data chunk having the same value as the data chunk is stored in the backup memory 148 . Among the data chunks buffered in the write buffer 146, a data chunk that does not have a backup data chunk may be referred to as a non-backup data chunk, and is shown as a rectangle marked with a hatched pattern in FIG. 1 . In FIG. 1 , a normal data chunk and a backup data chunk connected by a broken line may represent data chunks having the same value.

Even if the controller 130 removes the normal data chunk from the write buffer 146 immediately after providing the normal data chunk to the memory device 150, the same data as the normal data chunk can be maintained in the backup memory 148. On the other hand, the controller 130 may maintain the non-backup data chunk in the write buffer 146 until the non-backup data chunk is successfully programmed to maintain the non-backup data chunk in the controller 130. .

According to an embodiment of the present invention, the controller 130 attempts to reduce the time during which non-backup data chunks accumulate in the write buffer 146 in order to minimize the capacity required for the write buffer 146 . In the following, the non-backup data chunks are written to the write buffer by quickly removing the non-backup data chunks from the write buffer 146 while the controller 130 retains the data chunks in the controller 130 until the data chunks are successfully programmed. The method of avoiding congestion at 146 is described in detail with reference to FIGS. 2 to 9B.

2 is a diagram illustrating a memory system 110 according to an exemplary embodiment in detail.

The memory system 110 may include a controller 130 and a memory device 150 . The controller 130 and memory device 150 shown in FIG. 2 correspond to those described with reference to FIG. 1 .

The controller 130 includes a host interface 132, a processor 134, an error correction code (ECC) 138, a power management unit 140, a memory interface 142, and a memory 144 operably connected to each other through an internal bus. ) may be included.

The host interface 132 processes commands and data of the host 102, and includes USB (Universal Serial Bus), MMC (Multi-Media Card), PCI-E (Peripheral Component Interconnect-Express), SAS (Serial Bus) -attached SCSI), SATA (Serial Advanced Technology Attachment), PATA (Parallel Advanced Technology Attachment), SCSI (Small Computer System Interface), ESDI (Enhanced Small Disk Interface), IDE (Integrated Drive Electronics), MIPI (Mobile Industry Processor Interface) ) may be configured to communicate with the host 102 through at least one of a variety of interface protocols, such as the like.

The host interface 132 may run firmware called a host interface layer (HIL) to exchange data with the host 102 .

The ECC 138 may detect and correct errors included in data read from the memory device 150 . That is, the ECC 138 may perform an error correction decoding process on data read from the memory device 150 through the ECC code used in the ECC encoding process. Depending on the result of the error correction decoding process, ECC 138 may output a signal, such as an error correction success/failure signal, for example. If the number of error bits exceeds the threshold of correctable error bits, the ECC 138 cannot correct the error bits and may output an error correction failure signal.

ECC 138 is a low density parity check (LDPC) code, Bose, Chaudhuri, Hocquenghem (BCH) code, turbo code, Reed-Solomon code, convolution code ), RSC (recursive systematic code), TCM (trellis-coded modulation), BCM (block coded modulation) such as coded modulation (coded modulation) can be used to perform error correction. However, the ECC 138 is not limited to a specific structure. The ECC 138 may include any circuit, module, system, or device for error correction.

The memory interface 142 is a memory/storage for interfacing between the controller 130 and the memory device 150 so that the controller 130 controls the memory device 150 in response to a request from the host 102. It can serve as an interface. When the memory device 150 is a flash memory, particularly a NAND flash memory, the memory interface 142 generates control signals for the memory device 150 and provides them to the memory device 150 under the control of the processor 134. data can be processed. The memory interface 142 may operate as an interface for processing commands and data between the controller 130 and the memory device 150, for example, a NAND flash interface.

The memory interface 142 may drive firmware called a Flash Interface Layer (FIL).

The processor 134 may control the overall operation of the memory system 110 . The processor 134 may drive firmware to control overall operations of the memory system 110 . The firmware may be referred to as a Flash Translation Layer (FTL). Also, the processor 134 may be implemented as a microprocessor or a central processing unit (CPU).

The processor 134 may drive a flash conversion layer to perform a foreground operation corresponding to a request received from the host 102 . For example, the processor 134 may control a write operation of the memory device 150 in response to a write request from a host, and may control a read operation of the memory device 150 in response to a read request.

Also, the controller 130 may perform a background operation of the memory device 150 through the processor 134 implemented as a microprocessor or a central processing unit (CPU). For example, the background operation for the memory device 150 includes a garbage collection (GC) operation, a wear leveling (WL) operation, a map flush operation, and a bad block management. actions, etc.

The memory 144 may serve as an operation memory for the memory system 110 and the controller 130 and may store data for driving the memory system 110 and the controller 130 . The controller 130 may control the memory device 150 to perform read, program, and erase operations in response to a request from the host 102 . The controller 130 may provide data read from the memory device 150 to the host 102 and may store the data provided from the host 102 in the memory device 150 . The memory 144 may store data necessary for the controller 130 and the memory device 150 to perform these operations.

Memory 144 may be implemented as volatile memory. For example, the memory 144 may be implemented as static random access memory (SRAM) or dynamic random access memory (DRAM). Memory 144 may be located inside or outside controller 130 . 1 illustrates memory 144 disposed within controller 130 . In one embodiment, the memory 144 may be implemented as an external volatile memory device, and the memory 144 may have a controller 130 and a memory interface for inputting/outputting data.

The memory 144 may include the write buffer 146 and the backup memory 148 described with reference to FIG. 1 . 3 for a data path in which the controller 130 buffers the data chunks received from the host 102 in the write buffer 146 and selectively backs up the data chunks in the backup memory 148. explained in detail.

FIG. 3 is a diagram for explaining a data path of data received from the host 102. Referring to FIG.

FIG. 3 shows some of the configurations of the controller 130 described with reference to FIGS. 1 and 2 . Specifically, FIG. 3 shows host interface 132 , write buffer 146 and backup memory 148 .

3 shows a main datapath 302 and a backup datapath 304 . The main data path 302 may refer to a path until a data chunk received from the host 102 is buffered in the write buffer 146 . The backup data path 304 may refer to a path until data chunks from the host 102 are backed up in the backup memory 148 .

The controller 130 may further include a temporary buffer 140 . Data chunks from the host 102 may be received through the host interface 132 and backed up in the backup memory 148 via the temporary buffer 140 . Temporary buffer 140 may be included in memory 144 .

The controller 130 may prevent a bottleneck from occurring in the backup data path 304 by selectively backing up or discarding data chunks from the host 102 in order to maintain write operation performance of the memory system 110 .

In the example of FIG. 3 , the host interface 132 receives first to fourth data chunks D1 to D4 from the host 102, and transfers the data chunks to the main data path 302 and the backup data path 304. can be provided with The write buffer 146 may buffer all of the first to fourth data chunks D1 to D4 received through the main data path 302 . The temporary buffer 140 may selectively buffer the data chunks received through the backup data path 304 according to whether there is free space for buffering the data chunks therein. For example, the temporary buffer 140 may buffer the first to third data chunks D1 to D3, and discard the fourth data chunk D4 without buffering it when there is no more free space. The temporary buffer 140 may back up the buffered first to third data chunks D1 to D3 in the backup memory 148 .

In the example of FIG. 3 , among the data chunks buffered in the write buffer 146, the first to third data chunks D1 to D3 correspond to normal data chunks, and the fourth data chunk D4 corresponds to a non-backup data chunk. may correspond to The first to third data chunks D1 to D3 backed up in the backup memory 148 may correspond to backup data chunks.

The processor 134 may control a program operation of the memory device 150 while providing the first to fourth data chunks D1 to D4 to the memory device 150 . The processor 134 may remove the first to third data chunks D1 to D3, which are normal data chunks, from the write buffer 146 after being provided to the memory device 150. If the program operation for the normal data chunk fails, the processor 134 provides the backup data chunk corresponding to the normal data chunk from the backup memory 148 to the memory device 150 through the memory interface 142 again. can

On the other hand, the processor 134 may maintain the fourth data chunk D4 , which is a non-backup data chunk, without removing it from the write buffer 146 even after being provided to the memory device 150 . If the program operation for the non-backup data chunk fails, the processor 134 may provide the non-backup data chunk from the write buffer 146 to the memory device 150 through the memory interface 142 . When the program operation of the memory device 150 is successfully completed, the processor 134 may remove the backup data chunk from the backup memory 148 and the non-backup data chunk from the write buffer 146 .

According to an embodiment of the present invention, the controller 130 adjusts the order in which data chunks are programmed into the memory device 150 so that the program operation for the non-backup data chunk can be completed quickly and the non-backup data chunk is We want to quickly remove it from the light buffer 146. According to an embodiment of the present invention, the non-backup data chunks are accumulated in the write buffer 146 while the non-backup data chunks are maintained in the write buffer 146 until the program operation of the memory device 150 is successfully completed. this can be prevented.

A sequence of programming data in the memory device 150 will be described in detail with reference to FIGS. 4 to 6 .

4 is a diagram illustrating a 3D memory cell array of the memory device 150 .

Referring to FIG. 4 , the memory device 150 may include a plurality of memory blocks MB1 to MBk. A memory block may include a plurality of strings ST11 to ST1m and ST21 to ST2m. As an embodiment, each of the plurality of strings ST11 to ST1m and ST21 to ST2m may be formed in a 'U' shape. Within the first memory block MB1, m strings may be arranged in a row direction (X direction). In FIG. 6 , it is illustrated that two strings are arranged in a column direction (Y direction), but this is for convenience of description and three or more strings may be arranged in a column direction (Y direction).

Each of the plurality of strings ST11 to ST1m and ST21 to ST2m includes at least one source select transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain select transistor. (DST).

The source and drain select transistors SST and DST and the memory cells MC1 to MCn may have structures similar to each other. For example, each of the source and drain select transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunnel insulating layer, a charge trap layer, and a blocking insulating layer. For example, a pillar for providing a channel film may be provided in each string. For example, a pillar for providing at least one of a channel layer, a tunnel insulating layer, a charge trap layer, and a blocking insulating layer may be provided in each string.

The source select transistor SST of each string may be connected between the source line SL and the memory cells MC1 to MCp.

As an embodiment, source select transistors of strings arranged in the same row may be connected to source select lines extending in a row direction, and source select transistors of strings arranged in different rows may be connected to different source select lines. In FIG. 4 , the source select transistors of the strings ST11 to ST1m in the first row may be connected to the first source select line SSL1 . The source select transistors of the strings ST21 to ST2m in the second row may be connected to the second source select line SSL2.

As another embodiment, the source select transistors of the strings ST11 to ST1m and ST21 to ST2m may be connected in common to one source select line.

The first to nth memory cells MC1 to MCn of each string may be connected between the source select transistor SST and the drain select transistor DST.

The first to nth memory cells MC1 to MCn may be divided into first to pth memory cells MC1 to MCp and p+1 to nth memory cells MCp+1 to MCn. The first to pth memory cells MC1 to MCp may be sequentially arranged in a vertical direction (Z direction) and may be serially connected to each other between the source select transistor SST and the pipe transistor PT. The p+1th to nth memory cells MCp+1 to MCn may be sequentially arranged in a vertical direction (Z direction) and may be serially connected to each other between the pipe transistor PT and the drain select transistor DST. there is. The first to pth memory cells MC1 to MCp and the p+1 to nth memory cells MCp+1 to MCn may be connected to each other through the pipe transistor PT. Gates of the first to nth memory cells MC1 to MCn of each string may be connected to the first to nth word lines WL1 to WLn, respectively.

As an example embodiment, at least one of the first to n th memory cells MC1 to MCn may be used as a dummy memory cell. When a dummy memory cell is provided, a voltage or current of a corresponding string can be stably controlled. Gates of the pipe transistors PT of each string may be connected to the pipeline PL.

The drain select transistor DST of each string may be connected between the bit line and the memory cells MCp+1 to MCn. The strings arranged in the row direction may be connected to the drain select line extending in the row direction. Drain select transistors of the strings ST11 to ST1m in the first row may be connected to the first drain select line DSL1. The drain select transistors of the strings ST21 to ST2m in the second row may be connected to the second drain select line DSL2.

Strings arranged in the column direction may be connected to bit lines extending in the column direction. In FIG. 4 , the strings ST11 and ST21 of the first column may be connected to the first bit line BL1. The strings ST1m and ST2m of the mth column may be connected to the mth bit line BLm.

Among strings arranged in a row direction, memory cells connected to the same word line may constitute one physical page. For example, among the strings ST11 to ST1m in the first row, memory cells connected to the first word line WL1 may constitute one physical page. Among the strings ST21 to ST2m in the second row, memory cells connected to the first word line WL1 may constitute another physical page. When one of the drain select lines DSL1 and DSL2 is selected, strings arranged in one row direction are selected. When one of the word lines WL1 to WLn is selected, one physical page among the selected strings is selected.

The memory device 150 includes a single level cell (SLC) memory block storing 1-bit data in one memory cell, a multi-level cell (MLC) memory block storing plural-bit data in one memory cell, and the like. of memory blocks. SLC memory blocks may include a plurality of pages implemented with memory cells that store one bit of data in one memory cell. SLC memory blocks may have high durability and fast data operation performance. On the other hand, MLC memory blocks may include a plurality of pages implemented with memory cells that store multiple bits of data, such as two or more bits, in one memory cell. For example, the MLC memory blocks include a Dual Level Cell (DLC) memory block capable of storing 2 bits of data in one memory cell, and a Triple Level Cell (TLC) memory block capable of storing 3 bits of data in one memory cell. It may be a quadruple level cell (QLC) memory block capable of storing 4-bit data in a memory block or one memory cell. The MLC memory blocks may have a larger data storage space than the SLC memory blocks. That is, the MLC memory blocks can be highly integrated.

The memory device 150 may perform multi-step program operations to program plural-bit data into memory cells. For example, in order to program the DLC, the memory device 150 may perform a first program step of first programming data corresponding to a least significant bit (LSB) among 2 bits of the DLC. The memory device 150 may program all 2-bit data of the DLC by performing a second program step for programming data corresponding to a most significant bit (MSB) after performing the first program step. Each program step may include a plurality of program loops. Hereinafter, a program operation comprising a plurality of program steps is referred to as a multi-step program operation.

5 is a diagram for explaining a multi-step program operation of the memory device 150. Referring to FIG.

5 illustrates distribution charts showing threshold voltage states of TLCs, as an example of memory cells. In each distribution chart, the horizontal axis represents the threshold voltage of a memory cell, and the vertical axis represents the number of memory cells having the corresponding threshold voltage.

A first distribution chart 502 shows threshold voltage states of erased memory cells. In the first distribution diagram 502, all memory cells may have an erase state. In the example of FIG. 5 , memory cells in an erase state may have a logical value of '1'.

The second distribution chart 504 represents threshold voltage states of memory cells after the memory device 150 performs the first program step. The memory device 150 may first program first bit data among bits of memory cells, eg, least significant bit (LSB) data into the memory cells. An operation of programming the first bit data is referred to as a first program step. To perform the first program step, the memory device 150 may obtain first bit data from the controller 130 . When the memory device 150 performs the first program step on the memory cells using the first bit data, some of the memory cells in the erase state may move to the program state. In the example of FIG. 5 , memory cells may have logic '1' or logic '0' values.

A third distribution chart 506 represents threshold voltage states of memory cells after the memory device 150 performs the second program step. After the first bit data is programmed, the memory device 150 adds second bit data among the bits of the memory cells, for example, most significant bit (MSB) data and central significant bit (CSB) data to the memory cells. can be programmed An operation of further programming the second bit data is referred to as a second program step. The memory device 150 may perform a second program step on memory cells using the first and second bit data. Depending on implementation, in order to perform the second program step, the memory device 150 may obtain first and second bit data from the controller 130, or obtain only the second bit data from the controller 130 and obtain the memory device 150. First bit data may be obtained from the cells. When the memory device 150 performs the second program step on the memory cells, all of MSB data, CSB data, and LSB data may be programmed. In the example of FIG. 5 , memory cells may have values of '111', '101', '001', '011', '010', '110', '100', and '000'.

5 illustrates the multi-step program operation by taking a TLC memory block as an example, the multi-step program operation can be applied to various types of MLC memory blocks. For example, when the memory device 150 performs a multi-step program operation on a DLC memory block, two threshold voltage states may be formed using LSB data among 2-bit data in a first program step. Also, the memory device 150 may finally form four threshold voltage states using the LSB data and the MSB data in the second program step.

Meanwhile, when a program operation is performed on a certain physical page, a program disturbance in which a threshold voltage distribution of an adjacent physical page is also changed due to word line coupling may occur. A program sequence of the memory device 150 may be determined to minimize an effect of program disturbance when programming a plurality of physical pages.

6 is a diagram illustrating a program sequence of the memory device 150 performing a multi-step program operation.

When the memory device 150 is an MLC memory device, each physical page may include a plurality of subpages. For example, when the memory device 150 is a DLC memory device, each physical page may include a first bit page and a second bit page.

A first table 600 shown in FIG. 6 indicates a program order for each subpage included in one memory block. First to eighth drain select lines DSL1 to DSL8 are displayed in the first row of the first table 600 , and first to third word lines WL1 to WL3 are displayed in the first column. As described with reference to FIG. 4 , a plurality of physical pages in one memory block may be selected by drain select lines DSL and word lines WL. Hereinafter, a physical page selected by the X-th word line and the Y-th drain select line may be referred to as page XY. For example, a physical page specified by the first word line WL1 and the fourth drain select line DSL4 may be referred to as page 14 (Page14).

A first bit and a second bit of each of the first to third word lines WL1 to WL3 are displayed in the second column of the first table 600 . Each entry of the first table 600 may correspond to each subpage, and numbers such as '1', '2', ... '40' displayed in the first table 600 may correspond to each subpage. indicates the program sequence of

When the memory device 150 continuously performs the second program step on the N-th word line after performing the first program step on the N-th word line, the memory cell connected to the N+1-th word line in an erase state can be greatly affected by program disturbances. To minimize the effect of program disturbance, the first program step is performed on the N-th word line, and the second program step is performed on the N-th word line after the first program step is performed on the N+1-th word line. can do.

For example, referring to program sequences '1' to '8' of the first table 600, the memory device 150 displays the first bits of pages 11 to 18 associated with the first word line WL1 of the memory block. Pages can be programmed sequentially. Referring to program sequences '9' and '10', when the programming of the first bit pages of pages 11 to 18 is completed, the memory device 150 first executes the programming of the first bit page corresponding to page 21, The program of the second bit page corresponding to page 11 can be performed. Referring to program sequences '11' to '24', similarly to the case of pages 11 and 21, the first bit page associated with the second word line WL2 also appears in pages 12 to 18 and 22 to 28. It may be programmed prior to the second bit page associated with one word line WL1. Similarly, referring to program sequences '25' to '40', the memory device 150 sets the first bit page associated with the third word line WL3 prior to the second bit page associated with the second word line WL2. can be programmed

When both the first and second program steps of a certain physical page are successfully completed, the program operation of the physical page can be completed. Even if the first program step is successfully completed, if the second program step fails, the memory device 150 determines that the program operation of the physical page has failed and reprograms the first and second bit pages into different physical pages. can To ensure reliability of the memory system 110, the controller 130 may maintain the first and second bit pages until the second program step is completed.

In the example of FIG. 6 , the first program step of page 21 may be performed in the 9th order, and the second program step may be performed in the 26th order. The program operation of page 21 can be completed only when the second program step performed in the 26th order is completed. If the data chunk programmed in the 9th order can be maintained in the controller 130 until the second program step performed in the 26th order is completed. If the data chunk is a non-backup data chunk, the data chunk may be maintained in the write buffer 146 until the second program step in the 26th sequence is completed.

If the non-backup data chunk is programmed in the 10th order, the non-backup data chunk can be programmed through the second program step in page 12, and when the second program step in the 10th order is completed, the write buffer 146 can be removed

According to an embodiment of the present invention, the controller 130 adjusts the order in which data chunks are programmed into the memory device 150, but allows the non-backup data chunks to be programmed in the second program step, so that the non-backup data chunks are written to the write buffer ( 146) can be quickly removed. An operation of the controller 130 according to an embodiment of the present invention will be described in detail with reference to FIGS. 7 to 9B.

7 illustrates a transaction between the controller 130 and the memory device 150 for performing a write operation according to an embodiment of the present invention.

In step S702 , the write buffer 146 may buffer the data chunks received through the host interface 132 .

In step S704 , the backup memory 148 may selectively back up the data chunks received through the host interface 132 .

Steps S702 and S704 may be performed in parallel through the main data path 302 and backup data path 304 described with reference to FIG. 3 , respectively.

In step S706, the processor 134 may determine the order in which the data chunks buffered in the write buffer 146 are programmed into the memory device 150. Specifically, the processor 134 may adjust the program order so that the non-backup data chunk is programmed into the second bit page.

In step S708 , the memory interface 142 may provide the data chunk to be programmed in the first bit page of the first physical page to the memory device 150 . Hereinafter, a data chunk to be programmed into the first bit page may be referred to as a first bit data chunk. According to an embodiment of the present invention, the first bit data chunk may always be a normal data chunk.

After the first bit data chunk of the first physical page is provided to the memory device 150 , the processor 134 may remove the first bit data chunk from the write buffer 146 in operation S710 .

In step S712, the memory device 150 may perform the first program step of the first physical page by using the first bit data chunk received from the controller 130.

In operation S714 , the memory interface 142 may provide the first bit data chunk of the second physical page subsequent to the first physical page to the memory device 150 .

After the first bit data chunk of the second physical page is provided to the memory device 150 , the processor 134 may remove the first bit data chunk from the write buffer 146 in operation S716 .

In step S718, the memory device 150 may perform the first program step of the second physical page by using the first bit data chunk received from the controller 130.

In step S720 , the memory interface 142 may provide the second bit data chunk, which is a data chunk to be programmed into the second bit page of the first physical page, to the memory device 150 . According to an embodiment of the present invention, the second bit data chunk may be a non-backup data chunk or a normal data chunk. 7 illustrates a case where the second bit data chunk is a non-backup data chunk. After the second bit data chunk is provided to the memory device 150 , the processor 134 may retain the second bit data chunk in the write buffer 146 without removing it from the write buffer 146 .

In step S722, the memory device 150 may perform the second program step of the first physical page by using the second bit data chunk received from the controller 130.

When the first program step of step S712 and the second program step of step S722 are successfully completed, the memory device 150 may provide a program completion signal for the first physical page to the controller 130 in step S724.

In step S726, the processor 134 may remove the backup data chunk and the non-backup data chunk associated with the first physical page in response to the program completion signal. Specifically, the processor 134 may remove the backup data chunk corresponding to the first bit data chunk of the first physical page from the backup memory 148 . Also, the processor 134 may remove the second bit data chunk of the first physical page, which is the non-backup data chunk, from the write buffer 146 .

Hereinafter, an example of how the processor 134 determines the program order so that the non-backup data chunk can be programmed through the second program step will be described in detail with reference to FIG. 8 .

8 is a diagram illustrating the detailed operation of step S706.

In S802, the processor 134 may determine whether it is the turn to perform the first program step according to the program order of the memory device 150. An example of the program sequence of the memory device 150 has been described with reference to FIG. 6 .

When it is the turn of the memory device 150 to perform the first program step (“YES” in step S802), the processor 134 selects a normal data chunk among the data chunks buffered in the write buffer 146 in step S804. A program sequence may be determined to be programmed in the first program step. For example, the processor 134 may determine a program order such that the oldest data chunk among the normal data chunks buffered in the write buffer 146 is programmed in the first program step. Even when the oldest data chunk among the data chunks buffered in the write buffer 146 is a non-backup data chunk, the processor 134 may suspend programming of the non-backup data chunk.

When it is the turn of the memory device 150 to perform the second program step ("NO" in step S802), the processor 134 determines whether the non-backup data chunk is buffered in the write buffer 146 in step S806. can do.

If the non-backup data chunk is buffered in the write buffer 146 ("YES" in step S806), the processor 134 determines the program order so that the non-backup data chunk is programmed in the second program step in step S808. can For example, the controller 130 may determine the program order so that the oldest data chunk among the non-backup data chunks buffered in the write buffer 146 is programmed in the second program step.

When only the normal data chunks are buffered in the write buffer 146 ("NO" in step S806), the processor 134 program in step S804 such that any one of the normal data chunks is programmed in the second program step. order can be determined.

According to an embodiment of the present invention, non-backup data chunks may be programmed into the memory device 150 in a later order than normal data chunks received later. For example, the normal data chunk received later than the non-backup data chunk may be first programmed into the first bit page of the second physical page, and the non-backup data chunk may be programmed into the second bit page of the first physical page. .

However, data programmed in the first bit page of the second physical page can be removed from the controller 130 after the program operation of the second bit page of the second physical page is completed, whereas the non-backup data chunk If the second bit page of one physical page is successfully programmed, it can be removed from the write buffer 146 immediately. Accordingly, non-backup data chunks buffered in the write buffer 146 can be quickly removed.

Hereinafter, the operation of the controller 130 according to an embodiment of the present invention will be described with reference to specific examples of FIGS. 9A and 9B.

9A illustrates data chunks buffered in the write buffer 146.

In the example of FIG. 9A , a plurality of data chunks may be buffered in the write buffer 146 in the order of first to twenty-fourth data chunks D1 to D24. Among the plurality of data chunks, a normal data chunk is shown as a rectangle marked with a dot pattern, and a non-backup data chunk is shown as a square marked with a hatched pattern. The 4th, 7th, 11th, 15th, 18th and 23rd data chunks (D4, D7, D11, D15, D18, D23) among the 1st to 24th data chunks (D1 to D24) are non-backup data chunks. , and the operation of the controller 130 will be described taking a case where the remaining data chunks are normal data chunks as an example.

FIG. 9B is a diagram for explaining an order in which data chunks buffered in the write buffer 146 in the example of FIG. 9A are programmed.

The second table 900 shows a program sequence for each subpage included in one memory block and data chunks programmed for each subpage. The first row of the second table 900 represents the first to eighth drain select lines DSL1 to DSL8, and the first and second columns represent first to third word lines WL1 to WL3 respectively. Indicates a bit page and a second bit page. The second table 900 shows the program order (PO) for each subpage and the data chunk (D) programmed in each subpage according to an embodiment of the present invention. The program order of each subpage of the second table 900 is the same as that described with reference to the first table 600 of FIG. 6 .

Referring to FIG. 9B, the first to third data chunks D1 to D3, which are normal data chunks, are programmed into subpages corresponding to program sequences '1' to '3' in the order in which they are buffered in the write buffer 146. It can be.

According to an embodiment of the present invention, the program sequence of the fourth data chunk D4, which is a non-backup data chunk, can be programmed in the second program step. 9B, the fourth data chunk D4 cannot be programmed in subpages corresponding to program sequences '4' to '9', but can be programmed in subpages corresponding to program sequence '10'. In subpages corresponding to program sequences '4' to '9', normal data chunks received later than the fourth data chunk D4 may be programmed first.

In FIG. 9B, the order in which each data chunk is programmed and the subpages in which each data chunk is programmed are shown for the fifth to 24th data chunks D5 to D24 as well as the first to fourth data chunks D1 to D4. do. In FIG. 9B, a dot pattern is displayed on a subpage where a normal data chunk is to be programmed, and a hatched pattern is displayed on a subpage where a non-backup data chunk is to be programmed. A subpage in which a pattern is not shown may be in an erase state.

Referring to FIG. 9B , unlike the normal data chunks that can be programmed to both the first bit page and the second bit page, all of the non-backup data chunks can be programmed to the second bit page.

Referring to FIG. 9B , when the program order is adjusted so that the non-backup data chunks can be programmed into the second bit page, the data chunks are programmed into the memory device 150 in the order in which they are buffered in the write buffer 146. Non-backup data chunks can be quickly removed from the write buffer 146.

As a first example, according to an embodiment of the present invention, the fourth data chunk D4 may be programmed in the second bit page of page 11. The fourth data chunk D4 may be buffered in the write buffer 146 in the fourth order and programmed in the memory device 150 in the tenth order. When programming up to the second bit page of page 11 is successfully completed, the fourth data chunk D4 may be removed from the write buffer 146 . In contrast, if the fourth data chunk D4 is programmed in the fourth order as received in the write buffer 146, the fourth data chunk D4 can be programmed in the first bit page of page 14. The fourth data chunk D4 can be removed from the write buffer 146 only when the second bit page of page 14 is successfully programmed, and the second bit page of page 14 can be programmed in the 16th order.

As a second example, according to an embodiment of the present invention, the 23rd data chunk D23 may be programmed in the 24th order of the 2nd bit page of page 18. The 23rd data chunk D23 may be removed from the write buffer 146 when the 24th sequential program is successfully completed. In contrast, if the 23rd data chunk D23 is programmed in the 23rd order, the 23rd data chunk D23 can be programmed in the first bit page of page 28. The second bit page of page 28 can be programmed in the 40th order, and the 23rd data chunk D23 can be removed from the write buffer 146 only when the 40th order of programming is successfully completed.

When the program order is adjusted so that not only the 4th and 23rd data chunks D4 and D23 but also the remaining non-backup data chunks can be programmed in the second bit page, the non-backup data chunks are written to the write buffer 146 The time maintained in may be reduced or equal to that of programming in the memory device 150 in the buffered order.

According to an embodiment of the present invention, the controller 130 buffers data chunks to be programmed into the memory device 150 through the main data path 302 in the write buffer 146, and the backup data path 304 is the bottleneck. Data chunks may be selectively backed up in the backup memory 148 to prevent this from occurring. The controller 130 may determine a program order of each of the data chunks. Specifically, the controller 130 may determine the program order so that the non-backup data chunk is programmed in the second program step. When the non-backup data chunk is programmed into the second bit page, since the program operation of the physical page including the second bit page can be completed, the controller 130 transfers the non-backup data chunk from the write buffer 146. can be quickly removed. If the non-backup data chunks are promptly removed from the write buffer 146, accumulation of the non-backup data chunks in the write buffer 146 can be prevented.

Meanwhile, in FIGS. 5 to 9B, the embodiment of the present invention has been described taking a case in which the memory device 150 is a DLC memory device and performs a 2-step program operation as an example, but the present invention is not limited to the examples of FIGS. 5 to 9B. don't

As a first example, the present invention can also be applied to a case where the memory device 150 is a TLC memory device, LSB data is programmed in the first program step, and CSB data and MSB data are programmed in the second program step. When determining the program order of the data chunks, the controller 130 may determine the program order so that the non-backup data chunk is programmed into a CSB page or an MSB page.

As a second example, the present invention may also be applied to a case in which a physical page is programmed by the memory device 150 performing three or more program steps. When determining the program order of the data chunks, the controller 130 may determine the program order so that the non-backup data chunk is programmed at the last program step.

According to an embodiment of the present invention, similar to the case where all data chunks of the write buffer 146 are backed up in the backup memory 148, the data chunks may be maintained in the controller 130 until the program operation is completed. In addition, according to an embodiment of the present invention, since the bottleneck of the backup memory 148 is prevented, the write operation speed of the memory system 110 is increased compared to the case of backing up all the data chunks of the write buffer 146 in the backup memory 148. can be improved In addition, since accumulation of non-backup data chunks in the write buffer 146 is prevented according to an embodiment of the present invention, the required capacity of the write buffer 146 implemented as a high-speed memory is stored in the backup memory 148 as a write buffer. It may hardly increase compared to the case of backing up all the data chunks of (146). Accordingly, the performance of the memory system 110 is improved and reliability is maintained, while increasing manufacturing cost or circuit area of the memory system 110 can be prevented.

Although the controller and the operating method of the controller according to the embodiment of the present invention have been described as specific embodiments, this is only an example, and the present invention is not limited thereto, and is to have the widest scope according to the basic ideas disclosed herein. should be interpreted A person skilled in the art may implement an embodiment that is not indicated by combining or substituting the disclosed embodiments, but this also does not deviate from the scope of the present invention. In addition, those skilled in the art can easily change or modify the disclosed embodiments based on this specification, and it is clear that such changes or modifications also fall within the scope of the present invention.

Claims (21)

A method of operating a controller for controlling a memory device including multi-level cells programmed through first and second program steps,
buffering data chunks to be programmed in a write buffer;
selectively backing up the data chunks to a backup memory;
determining a program order of each of the data chunks buffered in the write buffer so that a non-backup data chunk among the data chunks is programmed in a second program step; and
The memory device performs a first program step on a first physical page, performs a first program step on a second physical page subsequent to the first physical page, and then performs a second program step on the first physical page. controlling the memory device to program the data chunks by
Operation method including.
According to claim 1,
Determining the program order of each of the data chunks
determining a program sequence so that a normal data chunk among the data chunks is programmed in a first or second program step;
In the normal data chunk, among data chunks buffered in the write buffer, a corresponding backup data chunk is a data chunk backed up in the backup memory.
how it works.
According to claim 2,
Determining the program order of each of the data chunks buffered in the write buffer
determining the program sequence such that a normal data chunk among the data chunks is programmed when it is the turn of the memory device to perform a first program step;
determining the program order so that the non-backup data chunk is programmed when the non-backup data chunk is buffered in the write buffer when it is the turn of the memory device to perform the second program step; and
Determining the program order so that the normal data chunk is programmed when only the normal data chunk is buffered in the write buffer when it is the turn of the memory device to perform the second program step.
how it works.
According to claim 1,
The above operation method is
providing a non-backup data chunk to the memory device; and
removing the non-backup data chunk from the write buffer when a program operation of a physical page associated with the non-backup data chunk is successfully completed;
Operation method further comprising.
According to claim 4,
The above operation method is
If a program operation of a physical page associated with the non-backup data chunk fails, providing the non-backup data chunk buffered in the write buffer to the memory device again.
Operation method further comprising.
According to claim 1,
The above operation method is
providing a normal data chunk to the memory device; and
removing the normal data chunk from the write buffer after providing the normal data chunk to the memory device;
Including more,
Among the data chunks buffered in the write buffer, the normal data chunk corresponds to a data chunk backed up in the backup memory.
how it works.
According to claim 6,
The above operation method is
removing a backup data chunk corresponding to the normal data chunk from the backup memory when a program operation of a physical page associated with the normal data chunk is successfully completed;
Operation method further comprising.
According to claim 7,
The above operation method is
If a program operation of a physical page associated with the normal data chunk fails, providing the backup data chunk backed up in the backup memory to the memory device.
Operation method further comprising.
According to claim 1,
The step of selectively backing up the data chunks to the backup memory
Discarding the data chunk received from the host or backing it up to the backup memory so that a bottleneck does not occur in a data path where the data chunk is backed up to the backup memory;
The write buffer is a memory that operates at a higher speed than the backup memory.
how it works.
According to claim 9,
The step of selectively backing up the data chunks to the backup memory
buffering the data chunk in the temporary buffer and backing up the data chunk buffered in the temporary buffer to a backup memory when there is free space in the temporary buffer through which the data chunk received from the host passes; and
Discarding the data chunk without buffering it in the temporary buffer when there is no free space in the temporary buffer.
how it works.
A controller for controlling a memory device including multi-level cells programmed through first and second program steps,
a write buffer buffering data chunks to be programmed;
a backup memory that selectively backs up the data chunks;
A processor determining a program order of each of the data chunks buffered in the write buffer, wherein a non-backup data chunk among the data chunks is programmed in a second program step;
The processor
The memory device performs a first program step on a first physical page, performs a first program step on a second physical page subsequent to the first physical page, and then performs a second program step on the first physical page. Controlling the memory device to program the data chunks by
controller.
According to claim 11,
The processor
determining a program order so that a normal data chunk among the data chunks is programmed in a first or second program step;
In the normal data chunk, among data chunks buffered in the write buffer, a corresponding backup data chunk is a data chunk backed up in the backup memory.
controller.
According to claim 12,
The processor
When the memory device programs a normal data chunk among the data chunks in the turn to perform the first program step and the non-backup data chunk is buffered in the write buffer in the turn to perform the second program step, the non-backup data chunk Determining the program order to program the normal data chunk when only the normal data chunk is buffered in the write buffer at the turn of programming the chunk and performing the second program step
controller.
According to claim 11,
The processor
Providing a non-backup data chunk to the memory device, and removing the non-backup data chunk from the write buffer when a program operation of a physical page associated with the non-backup data chunk is successfully completed
controller.
According to claim 14,
The processor
If the program operation of the physical page associated with the non-backup data chunk fails, providing the non-backup data chunk buffered in the write buffer to the memory device again.
controller.
According to claim 11,
The processor
providing a normal data chunk to a memory device and removing the normal data chunk from the write buffer;
In the normal data chunk, a corresponding backup data chunk among data chunks buffered in the write buffer is a data chunk backed up in the backup memory.
controller.
According to claim 16,
The processor
removing a backup data chunk corresponding to the normal data chunk from the backup memory when the program operation of the physical page associated with the normal data chunk is successfully completed;
controller.
According to claim 17,
The processor
Providing the backup data chunk backed up in the backup memory to the memory device when a program operation of the physical page associated with the normal data chunk fails.
controller.
According to claim 11,
The backup memory is
selectively backing up the data chunks received from the host to the backup memory so that a bottleneck does not occur in a data path where the data chunks are backed up to the backup memory;
The write buffer is a memory that operates at a higher speed than the backup memory.
controller.
According to claim 19,
The controller
Further comprising a temporary buffer through which the data chunk received from the host passes;
The temporary buffer is
If there is free space inside, the data chunk is buffered and then the buffered data chunk is provided to the backup memory, and when there is no free space inside, the data chunk is discarded without buffering.
controller.
A controller for controlling a memory device including multi-level cells programmed through first and second program steps,
a write buffer buffering data chunks to be programmed;
a backup memory that selectively backs up the data chunks;
A processor determining a program order of each of the data chunks buffered in the write buffer, wherein a non-backup data chunk among the data chunks is programmed in a second program step;
The processor
The memory device executes a first program step on a first physical page, performs a first program step on a second physical page subsequent to the first physical page, and then performs a second program step on the first physical page. By controlling the memory device to program the data chunks, and if the program operation of the physical page associated with the non-backup data chunk fails, providing the non-backup data chunk buffered in the write buffer to the memory device again
controller.

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