KR20220167688A - Semiconductor memory device and manufacturing method of semiconductor memory device - Google Patents

Abstract

A semiconductor memory device and a manufacturing method thereof are provided. The semiconductor memory device includes: a conductive gate contact that penetrates a contact region of a stepped stack including a plurality of interlayer insulating films and a plurality of conductive patterns alternately stacked. The purpose of the present invention is to improve the structural stability and the stability of a manufacturing process.

Description

Semiconductor memory device and manufacturing method thereof

The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly, to a three-dimensional semiconductor memory device and a manufacturing method thereof.

A semiconductor memory device includes memory cells capable of storing data. A 3D semiconductor memory device may include a 3D memory cell array.

In order to improve the degree of integration of the 3D memory cell array, the number of stacked memory cells may be increased. As the number of stacked memory cells increases, a manufacturing process of the 3D semiconductor memory device becomes more complicated and structural stability may deteriorate.

Embodiments of the present invention may provide a semiconductor memory device capable of improving structural stability and stability of a manufacturing process and a manufacturing method thereof.

A semiconductor memory device according to an embodiment of the present invention includes a first conductive gate contact; a first contact insulation pattern surrounding the first conductive gate contact; a first conductive pattern surrounding the first contact insulating pattern; a second conductive pattern disposed on the first conductive pattern and surrounding the first conductive gate contact; and a cell plug penetrating the first conductive pattern and the second conductive pattern. The second conductive pattern may include a first edge portion overlapping the first contact insulating pattern and contacting the first conductive gate contact; and a first base portion that extends from the first edge portion toward the cell plug and is thicker than the first edge portion.

A semiconductor memory device according to an embodiment of the present invention includes a horizontally doped semiconductor pattern; A staircase including a plurality of interlayer insulating films and a plurality of conductive patterns alternately stacked on the horizontally doped semiconductor pattern, and including a cell region overlapping the horizontally doped semiconductor pattern and a contact region extending from the cell region. mold laminate; a cell channel film connected to the horizontally doped semiconductor pattern and penetrating the cell region of the stepped stack; a plurality of conductive gate contacts penetrating the contact region of the stepped stack and extending to a level at which the horizontally doped semiconductor pattern is disposed; and a protective layer penetrating sidewalls of each of the conductive gate contacts.

A semiconductor memory device according to an embodiment of the present invention includes a stepped stack including a plurality of interlayer insulating films and a plurality of conductive patterns that are alternately stacked, and including a cell region and a contact region extending from the cell region; a horizontally doped semiconductor pattern disposed under the cell region of the stepped stack; a lower insulating layer disposed below the contact region of the stepped stack at a level where the horizontally doped semiconductor pattern is disposed; a plurality of lower contacts penetrating the lower insulating layer; a cell channel film connected to the horizontally doped semiconductor pattern and penetrating the cell region of the stepped stack; and a plurality of conductive gate contacts connected to the plurality of lower contacts and penetrating the contact region of the stepped stack.

A method of manufacturing a semiconductor memory device according to an embodiment of the present invention includes a lower interlayer insulating film, an intermediate interlayer insulating film, an upper interlayer insulating film, a lower base portion between the lower interlayer insulating film and the middle interlayer insulating film, and the middle interlayer insulating film from the lower base portion. A lower sacrificial film that protrudes more to the side and includes a lower edge portion that is thinner than the lower base, and an upper base portion between the middle interlayer insulating film and the upper interlayer insulating film, and a lower sacrificial film that protrudes laterally from the upper base part than the upper interlayer insulating film and the upper interlayer insulating film. forming a pre-stepped laminate comprising an upper edge portion that is thinner than an upper base portion; forming a filling insulating film covering the preliminary stepped laminate; forming a contact hole penetrating the filling insulating layer, the upper edge portion, the middle interlayer insulating layer, the lower base portion, and the lower interlayer insulating layer; replacing the upper edge portion with a sacrificial pad through the contact hole; replacing a part of the lower base portion with a contact insulation pattern through the contact hole; and forming a support structure surrounded by the contact insulating pattern and the sacrificial pad inside the contact hole.

A method of manufacturing a semiconductor memory device according to an embodiment of the present invention includes forming a lower stack in which a preliminary horizontal film and a passivation film are stacked; Separating the lower laminate into a preliminary horizontal pattern and a preliminary contact structure; forming a preliminary stepped stack including a lower interlayer insulating layer, a lower sacrificial layer, a middle interlayer insulating layer, an upper sacrificial layer, and an upper interlayer insulating layer sequentially stacked on the preliminary horizontal pattern and the preliminary contact structure; forming a support structure penetrating the preliminary stepped laminate and extending into the preliminary contact structure; replacing each of the lower sacrificial layer and the upper sacrificial layer with a conductive pattern; and replacing the preliminary horizontal film and the support structure of the preliminary contact structure with a conductive gate contact.

A method of manufacturing a semiconductor memory device according to an embodiment of the present invention includes forming a lower stack in which a preliminary horizontal film and a passivation film are stacked; Separating the lower laminate into a preliminary horizontal pattern and a preliminary contact structure; forming a lower contact penetrating the preliminary contact structure; forming a preliminary stepped laminate including a plurality of interlayer insulating films and a plurality of sacrificial films alternately stacked on a lower structure including the preliminary horizontal pattern, the preliminary contact structure, and the lower contact; By etching the preliminary stepped laminate, a slit passing through the cell region of the preliminary stepped laminate overlapped with the preliminary horizontal film and a contact passing through the contact region of the preliminary stepped laminate overlapped with the lower contact forming a hole; forming a support structure disposed inside the contact hole and extending between the interlayer insulating films; replacing each of the sacrificial layers with a conductive pattern; and replacing a part of the support structure inside the contact hole with a conductive gate contact connected to the lower contact.

According to the present technology, a contact insulating pattern may be self-aligned at a target position by using a difference in thickness of a sacrificial material including at least one of a sacrificial film and a sacrificial pad. Thus, the present technology can increase the stability of the manufacturing process.

The present technology can reduce the area occupied by the conductive gate contact and the support structure by replacing the support structure with the conductive gate contact. In addition, the present technology can improve structural stability and manufacturing process stability through a pre-formed support structure in an area where the conductive gate contact is to be disposed, even without disposing a separate support structure around the conductive gate contact.

According to the present technology, even if some support structures arranged around the conductive gate contact are omitted, the stability of the manufacturing process can be improved, and thus the area of the conductive gate contact can be increased by the area of the omitted support structure.

1 is a diagram showing a schematic configuration of a semiconductor memory device according to an exemplary embodiment of the present invention.
2 is a plan view illustrating a part of a semiconductor memory device according to an exemplary embodiment of the present invention.
3A, 3B, and 3C are cross-sectional views of the semiconductor memory device shown in FIG. 2 .
FIG. 4 is an enlarged cross-sectional view of the AR1 region shown in FIG. 3B.
5 is a cross-sectional view illustrating a semiconductor memory device according to an exemplary embodiment of the present invention.
FIG. 6 is an enlarged cross-sectional view of the area AR2 shown in FIG. 5 .
7A and 7B are cross-sectional views illustrating a process of separating a lower laminate into a plurality of patterns according to an embodiment of the present invention.
8a, 8b, 9a, 9b, 10a and 10b are cross-sectional views illustrating a method of forming a preliminary stepped laminate according to an embodiment of the present invention.
11A, 11B, 12A, 12B, 13A and 13B are cross-sectional views illustrating a method of forming a contact hole and a dummy hole according to an embodiment of the present invention.
14A, 14B, 15A, 15B, 16A, 16B, 17A, and 17B are cross-sectional views illustrating a method of forming a sacrificial pad and a contact insulating pattern according to an embodiment of the present invention.
18 is a cross-sectional view showing a method of forming a channel hole according to an embodiment of the present invention.
19a, 19b, 20a, 20b, 21, 22a, and 22b are cross-sectional views illustrating a method of forming a preliminary memory pattern, a channel structure, a first support structure, and a second support structure according to an embodiment of the present invention. admit.
23A, 23B, 24A, 24B, 25A, and 25B are cross-sectional views illustrating a method of forming a blocking insulating film and a conductive pattern according to an embodiment of the present invention.
26, 27, 28a, 28b, 29a, 29b, 30a, 30b, 31a, 31b, 32a, and 32b show a common source pattern and a conductive gate contact according to an embodiment of the present invention. and cross-sectional views illustrating a method of forming a dummy contact.
33A to 33J are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.
34A to 34O are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.
35 is a block diagram showing the configuration of a memory system according to an embodiment of the present invention.
36 is a block diagram showing the configuration of a computing system according to an embodiment of the present invention.

Specific structural or functional descriptions of embodiments according to the concept of the present invention disclosed in this specification or application are illustrated to explain the embodiment according to the concept of the present invention. Embodiments according to the concept of the present invention are not construed as being limited to the embodiments described in this specification or application, and may be implemented in various forms.

In embodiments of the present invention, terms such as first and second may be used to describe various components, but the components are not limited by the terms. The terms are used for the purpose of distinguishing one component from another.

1 is a diagram showing a schematic configuration of a semiconductor memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 1 , the semiconductor memory device may include a memory cell array 20 and a peripheral circuit 30 that controls the memory cell array 20 . The memory cell array 20 may be disposed on the peripheral circuit 30 . Accordingly, the area of the substrate occupied by the memory cell array 20 and the peripheral circuit 30 can be reduced.

The memory cell array 20 may include a plurality of memory blocks. Each memory block is connected to the peripheral circuit 30 via a bit line (BL1 or BL2), a word line (WL), a source select line (SSL), a drain select line (DSL1 or DSL2) and a common source pattern (CSL). can be connected.

Each memory block may include a plurality of bit lines. The plurality of bit lines may include a first bit line BL1 and a second bit line BL2. The number of bit lines is not limited as shown in the drawing.

A plurality of memory cell strings may be connected in parallel to each bit line BL1 or BL2. Each memory block includes a first memory cell string CS1, a second memory cell string CS2, a third memory cell string CS3, and a fourth memory cell string CS4 connected in parallel to the common source pattern CSL. ) may be included. As an embodiment, the first memory cell string CS1 and the third memory cell string CS3 may be connected in parallel to the first bit line BL1, and the second memory cell string CS2 and the fourth memory The cell string CS4 may be connected in parallel to the second bit line BL2. The number of memory cell strings connected to each bit line BL1 or BL2 and the number of memory cell strings connected to the common source pattern CSL are not limited as shown in the drawing.

The first memory cell string CS1 , the second memory cell string CS2 , the third memory cell string CS3 , and the fourth memory cell string CS4 may be connected to a plurality of word lines WL. The first memory cell string CS1 , the second memory cell string CS2 , the third memory cell string CS3 , and the fourth memory cell string CS4 may be commonly connected to respective word lines WL. .

The first memory cell string CS1 , the second memory cell string CS2 , the third memory cell string CS3 , and the fourth memory cell string CS4 commonly connected to each word line WL are separated from each other. may be separately connected to two or more source select lines, or may be separately connected to two or more drain select lines separated from each other. As an embodiment, the first memory cell string CS1 , the second memory cell string CS2 , the third memory cell string CS3 , and the fourth memory cell string CS4 are common to the source select line SSL. can be connected. In this case, the first and second memory cell strings CS1 and CS2 connected to the first and second bit lines BL1 and BL2 are commonly connected to the first drain select line DSL1. The third memory cell string CS3 and the fourth memory cell string CS4 respectively connected to the first and second bit lines BL1 and BL2 are common to the second drain select line DSL2. can be connected. The present invention is not limited thereto, and connection structures of memory cell strings, drain select lines, and source select lines may vary.

Each memory cell string CS1 , CS2 , CS3 , or CS4 may include a source select transistor SST, a drain select transistor DST, and a plurality of memory cells MC connected in series with each other. Each of the memory cell strings CS1 , CS2 , CS3 , or CS4 may be connected to the common source pattern CSL via the source select transistor SST. Each memory cell string CS1 , CS2 , CS3 , or CS4 may be connected to a bit line BL1 or BL2 corresponding to each memory cell string via a drain select transistor DST. The plurality of memory cells MC may be connected in series between the source select transistor SST and the drain select transistor DST by a cell channel layer.

A gate of the source select transistor SST may be connected to the source select line SSL. A gate of the drain select transistor DST may be connected to the drain select line DSL1 or DSL2. A gate of the memory cell MC may be connected to a corresponding word line WL.

The peripheral circuit 30 may include a source driver (SD), a page buffer (PB) and a row decoder (RD).

The source driver SD may be connected to the memory cell array 20 through the common source pattern CSL. The source driver SD may transmit a voltage necessary for the operation of the memory cell array 20 to the common source pattern CSL.

The row decoder RD may be connected to the memory cell array 20 through a plurality of word lines WL, a source select line SSL, and first and second drain select lines DSL1 and DSL2. The row decoder RD is configured to transmit operating voltages to a plurality of word lines WL, a source select line SSL, and first and second drain select lines DSL1 and DSL2 in response to a row address signal. It can be.

The page buffer PB may be connected to the memory cell array 20 through first and second bit lines BL1 and BL2 . The page buffer PB may selectively precharge the first and second bit lines BL1 and BL2 according to external data input thereto so as to store data in the memory cell MC. The page buffer PB may sense current or voltage of the first and second bit lines BL1 and BL2 to read data from the memory cell MC.

The source driver SD, the page buffer PB, and the row decoder RD may include a plurality of word lines WL, a source select line SSL, and first and second drain select lines DSL1 through interconnections. DSL2) and the first and second bit lines BL1 and BL2.

2 is a plan view illustrating a part of a semiconductor memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 2 , the semiconductor memory device may include a plurality of stepped stacked bodies ST separated from each other by a plurality of slits SI. Each stepped stacked body ST may include a cell region CAR, a contact region CTR, and an extension region ER.

The cell region CAR of the stepped stack structure ST may be penetrated by a plurality of cell plugs CPL. The plurality of cell plugs CPL may be arranged in a zigzag pattern in the XY plane of the XYZ coordinate system. The arrangement of the plurality of cell plugs CPL is not limited thereto. Each cell plug CPL may extend in the Z-axis direction of the XYZ coordinate system. The cross-sectional shape of the cell plug CPL may be various, such as a circular shape, an elliptical shape, a polygonal shape, and a square shape.

The contact region CTR of the stepped stack structure ST may extend from the cell region CAR. The contact region CTR of the stepped stack structure ST may be penetrated by the plurality of conductive gate contacts 181A. Each conductive gate contact 181A may extend in the Z-axis direction. The cross-sectional shape of the conductive gate contact 181A may be various, such as circular, elliptical, polygonal, and square. The conductive gate contact 181A may be formed with a larger area than the cell plug CPL in the XY plane.

The extension region ER of the stepped laminate ST may extend from the contact region CTR. The extension region ER of the stepped stack ST may be penetrated by the plurality of dummy contacts 181B. The cross-sectional shape of the dummy contact 181B may be various, such as a circular shape, an elliptical shape, a polygonal shape, and a square shape. Each dummy contact 181B may have an area larger than that of the cell plug CPL in the XY plane. As an example, the dummy contact 181B may have substantially the same area as the conductive gate contact 181A in the XY plane.

At least one drain separation slit DSI may be disposed between adjacent slits SI. The first drain select line DSL1 and the second drain select line DSL2 shown in FIG. 1 may be separated from each other by a drain separation slit DSI. The drain separation slit DSI may be buried inside the stepped stack structure ST. In the Z-axis direction, the drain separation slit DSI may be shorter than the slit SI.

3A, 3B, and 3C are cross-sectional views of the semiconductor memory device shown in FIG. 2 . FIG. 3A is a cross-section of the cell region CAR of the stepped stack structure ST taken along the line AA' shown in FIG. 2 . FIG. 3B shows a cross section of the contact region CTR of the stepped laminate ST taken along the line BB′ shown in FIG. 2 . FIG. 3C shows a cross section of the extension region ER of the stepped laminate ST taken along the line C-C′ shown in FIG. 2 .

3A to 3C , the stepped stack structure ST may be disposed on the first lower insulating layer 101 penetrated by the plurality of lower contacts 103A and the plurality of lower dummy contacts 103B. can The plurality of lower contacts 103A and the plurality of lower dummy contacts 103B may be formed of various conductive materials.

The semiconductor memory device may include a horizontal source layer 10 and a second lower insulating layer 104 between the first lower insulating layer 101 and the stepped stack structure ST.

The horizontal source layer 10 may include a first semiconductor pattern 105A, a horizontally doped semiconductor pattern 173H, and a second semiconductor pattern 111A sequentially stacked on the first lower insulating layer 101 . Each of the first semiconductor pattern 105A, the horizontally doped semiconductor pattern 173H, and the second semiconductor pattern 111A may include at least one of an n-type impurity and a p-type impurity. As an example, each of the first semiconductor pattern 105A, the horizontally doped semiconductor pattern 173H, and the second semiconductor pattern 111A may include an n-type impurity. The horizontal source layer 10 may overlap the cell region CAR of the stepped stack structure ST.

The second lower insulating layer 104 may be disposed on substantially the same level as the horizontal source layer 10 . The second lower insulating layer 104 may be disposed between the first lower insulating layer 101 and each of the contact region CTR and extension region ER of the stepped stack structure ST.

The cell plug CPL may extend into the horizontal source layer 10 . As an example, the cell plug CPL may pass through the second semiconductor pattern 111A and the horizontally doped semiconductor pattern 173H and extend into the first semiconductor pattern 105A. The cell plug CPL may include a channel structure CH and a memory pattern 151A surrounding the channel structure CH.

The horizontally doped semiconductor pattern 173H may pass through the memory pattern 151A to contact the channel structure CH. The memory pattern 151A may be separated into a first memory pattern 151P1 and a second memory pattern 151P2 by the horizontal doped semiconductor pattern 173H. The first memory pattern 151P1 may be disposed between the channel structure CH and the stepped stack structure ST. The second memory pattern 151P2 may be disposed between the channel structure CH and the first semiconductor pattern 105A.

Although not specified in the drawings, the memory pattern 151A may include a tunnel insulating layer, a data storage layer, and a first blocking insulating layer. The tunnel insulating layer may extend along the surface of the channel structure CH and may include an insulating material capable of charge tunneling. The data storage layer may extend along the surface of the channel structure CH with the tunnel insulating layer interposed therebetween. The data storage layer may include a material layer capable of storing data changed using Fowler Nordheim tunneling. As an example, the data storage layer may include a nitride layer capable of trapping charges. The present invention is not limited thereto, and the data storage layer may include a phase change material, nanodots, and the like. The first blocking insulating layer may extend along the surface of the channel structure CH with the tunnel insulating layer and the data storage layer interposed therebetween. The first blocking insulating layer may include an insulating material capable of blocking the movement of charges.

The channel structure CH may include a cell channel layer 153A, a core insulating pattern 155A, and a capping pattern 157. The cell channel film 153A is used as a channel of a memory cell string. The cell channel layer 153A may be connected to the horizontal doped semiconductor pattern 173H of the horizontal source layer 10 .

The cell channel layer 153A may be disposed on the memory pattern 151A. The cell channel layer 153A may be formed of a semiconductor material. For example, the cell channel layer 153A may include silicon. The core insulating pattern 155A and the capping pattern 157 may fill a central region of the channel structure CH. The core insulating pattern 155A may include oxide. The capping pattern 157 may include a sidewall disposed on the core insulating pattern 155A and surrounded by an upper end of the cell channel layer 153A. The capping pattern 157 may include a doped semiconductor layer including at least one of n-type impurities and p-type impurities.

The stepped stack structure ST may include a plurality of interlayer insulating films IL and a plurality of conductive patterns CP alternately stacked in the Z-axis direction.

The plurality of conductive patterns CP may be used as the source select line SSL, the plurality of word lines WL, and the drain select line DSL1 or DSL2 shown in FIG. 1 . As an embodiment, the lowest layer among the plurality of conductive patterns CP may be used as the source select line SSL shown in FIG. 1 , and the uppermost layer among the plurality of conductive patterns CP may be used as the drain shown in FIG. 1 . It may be used as the select line DSL1 or DSL2, and a plurality of intermediate layers between the lowest layer and the uppermost layer among the plurality of conductive patterns CP may be used as the plurality of word lines WL shown in FIG. 1.

The plurality of conductive patterns CP may extend from the cell region CAR of the stepped stack structure ST toward the contact region CTR and the extension region ER. The plurality of conductive patterns CP may form a stepped structure in the contact region CTR and the extension region ER. To this end, the plurality of conductive patterns CP may be extended laterally in the contact region CTR and the extension region ER closer to the second lower insulating layer 104 . As an example, the plurality of conductive patterns CP may extend in the X-axis direction in the contact region CTR and the extension region ER closer to the second lower insulating layer 104 .

Each conductive pattern CP may include an edge portion CE and a base portion CB extending from the edge portion CE. The plurality of edge portions CE of the plurality of conductive patterns CP may form a stepped structure in the contact region CTR and the extension region ER. The plurality of base portions CB of the plurality of conductive patterns CP may extend from the plurality of edge portions CE to the cell region CER to surround the cell plug CPL.

The stepped stacked body ST may be covered with the filling insulating layer 131 . The filling insulating layer 131 may include a first filling insulating layer 131A and a second filling insulating layer 131B on the first filling insulating layer 131A. The first filling insulating layer 131A may overlap the contact region CTR and the extension region ER of the stepped stack ST to cover the plurality of edge portions CE of the plurality of conductive patterns CP. there is. The second filling insulating layer 131B may extend to cover the cell region CAR, the contact region CTR, and the extension region ER of the stepped stack ST. The filling insulating layer 131 may be penetrated by the cell plug CPL and the slit SI.

The filling insulating layer 131 and the plurality of edge portions CE may be penetrated by the plurality of conductive gate contacts 181A and the plurality of dummy contacts 181B. The plurality of conductive gate contacts 181A may pass through the plurality of edge portions CE in the contact region CTR, respectively, and the plurality of dummy contacts 181B may pass through the plurality of edge portions CE in the extension region ER. CE), respectively. Each of the conductive gate contact 181A and the dummy contact 181B may be surrounded by at least one of a plurality of conductive patterns CP and at least one of a plurality of interlayer insulating films IL. At least one of the plurality of conductive gate contacts 181A and the plurality of dummy contacts 181B may pass through at least one base portion CB of the plurality of conductive patterns CP.

The plurality of conductive gate contacts 181A and the plurality of dummy contacts 181B are spaced apart from the plurality of base portions CB of the plurality of conductive patterns CP by the plurality of contact insulation patterns 141 . and may be insulated from the plurality of conductive patterns CP. The plurality of contact insulating patterns 141 may include a first contact insulating pattern 141A and a second contact insulating pattern 141B. The first contact insulating pattern 141A may be disposed between the conductive gate contact 181A and the base portion CB of the conductive pattern CP. The first contact insulating pattern 141A may cover a sidewall of the corresponding conductive gate contact 181A. The second contact insulating pattern 141B may be disposed between the dummy contact 181B and the base portion CB of the conductive pattern CP. The second contact insulating pattern 141B may cover the corresponding dummy contact 181B.

The plurality of conductive gate contacts 181A and the plurality of dummy contacts 181B may extend to the level where the horizontal source layer 10 is disposed. For example, the plurality of conductive gate contacts 181A and the plurality of dummy contacts 181B may extend through the second lower insulating layer 104 . At least one groove filled with a protective layer may be defined on sidewalls of the conductive gate contact 181A and the dummy contact 181B. As an example, the semiconductor memory device includes a first passivation layer 107 and a second passivation layer 109 spaced apart from each other in the Z-axis direction at a level where the horizontal source layer 10 and the second lower insulating layer 104 are disposed. can do. The first passivation layer 107 and the second passivation layer 109 may penetrate the sidewall of the conductive gate contact 181A or the sidewall of the dummy contact 181B. Each of the first passivation layer 107 and the second passivation layer 109 may cover a sidewall of the corresponding conductive gate contact 181A or dummy contact 181B.

The slit SI may be filled with the sidewall insulating layer 171 and the conductive vertical contact 173VC. The sidewall insulating layer 171 may extend along sidewalls of the plurality of conductive patterns CP and the plurality of interlayer insulating layers IL. The slit SI and the sidewall insulating layer 171 may extend to pass through the second semiconductor pattern 111A. The conductive vertical contact 173VC is disposed on the sidewall insulating layer 171 and may be disposed in a central region of the slit SI. The conductive vertical contact 173VC may be insulated from the plurality of conductive patterns CP as well as spaced apart from the plurality of conductive patterns CP by the side wall insulating layer 171 . The conductive vertical contact 173VC may extend in the Z-axis direction parallel to the cell channel layer 153A from the horizontally doped semiconductor pattern 173H. As an example, the conductive vertical contact 173VC may be integrated with the horizontally doped semiconductor pattern 173H and may be formed of the same material as the horizontally doped semiconductor pattern 173H. Embodiments of the present invention are not limited thereto. As another example, the conductive vertical contact 173VC may include a conductive material different from that of the horizontally doped semiconductor pattern 173H, for example, metal. The conductive vertical contact 173VC and the horizontally doped semiconductor pattern 173H may be used as the common source pattern CSL shown in FIG. 1 .

The semiconductor memory device may include a second blocking insulating layer 161 extending along the surface of each conductive pattern CP. The second blocking insulating layer 161 may include an insulating material having a higher dielectric constant than the first blocking insulating layer of the memory pattern 151A. As an example, the first blocking insulating layer may include silicon oxide, and the second blocking insulating layer 161 may include a metal oxide such as aluminum oxide.

The second blocking insulating film 161 includes a first opening OP1 facing the sidewall insulating film 171, a second opening OP2 facing each conductive gate contact 181A, and a third opening OP2 facing each dummy contact 181B. An opening OP3 may be included. The conductive pattern CP may contact the sidewall insulating layer 171 through the first opening OP1 . The conductive pattern CP may contact the corresponding conductive gate contact 181A through the second opening OP2 . The conductive pattern CP may contact the corresponding dummy contact 181B through the third opening OP3.

Each conductive gate contact 181A may be in contact with an edge portion CE corresponding to each conductive gate contact 181A and may be surrounded by an edge portion CE corresponding to each conductive gate contact 181A. . Each dummy contact 181B may contact an edge portion CE corresponding to each dummy contact 181B and may be surrounded by an edge portion CE corresponding to each dummy contact 181B. The base portion CB of the conductive pattern CP may be thicker than the edge portion CE. According to this, the width of each of the second and third openings OP2 and OP3 in the Z-axis direction may be smaller than that of the first opening OP1 in the Z-axis direction.

The filling insulating layer 131 may be covered with an upper insulating layer UI. The upper insulating film UI may include a first upper insulating film 191 on the filling insulating film 131 and a second upper insulating film 195 on the first upper insulating film 191 .

The capping pattern 157 of the cell plug CPL may be connected to the bit line BL via the bit line contact 193A. The bit line BL may be disposed at a level where the second upper insulating layer 195 is disposed. That is, the bit line BL may be disposed on the first upper insulating layer 191 . The bit line contact 193A may pass through the first upper insulating layer 191 and may interconnect the capping pattern 157 and the bit line BL.

The plurality of conductive gate contacts 181A may be connected to the plurality of upper interconnections UL via the plurality of upper contacts 193B. The first upper insulating layer 191 may fill between the plurality of upper contacts 193B. The second upper insulating layer 195 may fill between the plurality of upper interconnections UL. The plurality of upper interconnections UL, the plurality of upper contacts 193B, the plurality of conductive gate contacts 181A, and the plurality of lower contacts 103A represent the plurality of conductive patterns CP in FIG. 1 . may be used as interconnections to connect to the decoder (RD).

The plurality of dummy lower contacts 103B and the plurality of dummy contacts 181B may remain as floating patterns that are not electrically connected to the peripheral circuit 30 shown in FIG. 1 . To this end, upper surfaces of the plurality of dummy contacts 181B may be covered with an upper insulating layer UI.

According to an embodiment of the present invention, since the contact region CTR and the extension region ER are formed in a structure similar to each other, a manufacturing process for providing the contact region CTR is used to provide the extension region ER. manufacturing process can be performed. Thus, according to an embodiment of the present invention, a manufacturing process of a semiconductor memory device can be simplified.

FIG. 4 is an enlarged cross-sectional view of the AR1 region shown in FIG. 3B.

Referring to FIG. 4 , the plurality of conductive gate contacts 181A include a first conductive gate contact A1 surrounded by a relatively large number of conductive patterns CP and surrounded by a relatively small number of conductive patterns CP. A second conductive gate contact A2 may be included. The first conductive gate contact A1 and the second conductive gate contact A2 may be spaced apart from each other.

The plurality of conductive patterns CP may include a first conductive pattern CP1 disposed relatively lower and a second conductive pattern CP2 disposed relatively upper. That is, the second conductive pattern CP2 may be disposed on the first conductive pattern CP1. One of the plurality of interlayer insulating layers IL may be disposed between the first conductive pattern CP1 and the second conductive pattern CP2.

The first conductive pattern CP1 and the second conductive pattern CP2 may extend parallel to each other to surround the first conductive gate contact A1. A first contact insulation pattern 141A may be disposed between the first conductive gate contact A1 and the first conductive pattern CP1. The first conductive pattern CP1 may be insulated from the first conductive gate contact A1 by the first contact insulation pattern 141A. The first conductive pattern CP1 may extend to surround the second conductive gate contact A2.

The second blocking insulating layer 161 may cover sidewalls of the first insulating pattern 141A. The second blocking insulating layer 161 may extend along surfaces of each of the first conductive pattern CP1 and the second conductive pattern CP2 facing the first filling insulating layer 131A, and the first blocking insulating layer 161 facing the interlayer insulating layer IL. It may extend along surfaces of each of the conductive pattern CP1 and the second conductive pattern CP2. The second opening OP2 of the second blocking insulating layer 161 may be aligned with a level where the first conductive pattern CP1 is disposed and a level where the second conductive pattern CP2 is disposed. The edge portion CE of each of the first conductive pattern CP1 and the second conductive pattern CP2 may contact the corresponding conductive gate contact 181A through the second opening OP2.

For example, the second conductive pattern CP2 includes a first edge portion E1 in contact with the first conductive gate contact A1 and a first base portion B1 extending from the first edge portion E1. can do. The first conductive pattern CP1 may include a second edge portion E2 contacting the second conductive gate contact A2 and a second base portion B2 extending from the second edge portion E2. As described with reference to FIGS. 3A to 3C , the thickness D2 of each of the first edge portion E1 and the second edge portion E2 is the first base portion B1 and the second base portion B2, respectively. It may be less than the thickness (D1) of.

The first edge portion E1 of the second conductive pattern CP2 may overlap the first contact insulation pattern 141A. The first edge portion E1 may surround the first conductive gate contact A1. The first filling insulating layer 131A may be interposed between the first edge portion E1 of the second conductive pattern CP2 and the second conductive gate contact A2.

Among the plurality of first contact insulating patterns 141A, the first contact insulating pattern 141A overlapping the first edge portion E1 may be surrounded by the second base portion B2 of the first conductive pattern CP1. there is. The second conductive gate contact A2 may be spaced apart from the first contact insulating pattern 141A overlapping the first edge portion E1. The second conductive gate contact A2 may have a sidewall contacting the second edge portion E2 of the first conductive pattern CP1. The second edge portion E2 may extend from the second base portion B2 and cover the second conductive gate contact A2.

5 is a cross-sectional view illustrating a semiconductor memory device according to an exemplary embodiment of the present invention. More specifically, FIG. 5 is a cross-sectional view showing a modified embodiment of a stepped stack. 5 shows a contact region CTR' of a stepped laminate ST' according to an exemplary embodiment. The contact region CTR′ shown in FIG. 5 may extend from the cell region CAR shown in FIG. 3A. Although not shown in the figure, the extension region of the stepped laminate ST' extending from the contact region CTR' shown in FIG. 5 may be formed in a structure similar to that of the contact region CTR' shown in FIG. there is. FIG. 6 is an enlarged cross-sectional view of the area AR2 shown in FIG. 5 . Hereinafter, for simplicity of description, descriptions overlapping those of FIGS. 3A to 3C and FIG. 4 will be omitted.

Referring to FIGS. 5 and 6 , a second lower insulating layer 104 may be disposed on the first lower insulating layer 101 penetrated by the plurality of lower contacts 103A. The second lower insulating layer 104 may be penetrated by a plurality of conductive gate contacts 181A' respectively connected to the plurality of lower contacts 103A. The plurality of conductive gate contacts 181A' may pass through the stepped stack ST'. A first passivation layer 107 and a second passivation layer 109 may be buried in each conductive gate contact 181A'.

The plurality of conductive patterns CP' of the stepped stack ST' may be alternately disposed with the plurality of interlayer insulating films IL' in the Z-axis direction. Each conductive pattern CP' may include an edge portion CE' and a base portion CB extending from the edge portion CE'. The plurality of edge portions CE' of the plurality of conductive patterns CP' may form a stepped structure in the contact region CTR'. As shown in FIG. 3A , the base portion CB may contact the sidewall insulating layer 171 through the first opening OP1 of the second blocking insulating layer 161, and the edge portion CE' may be in contact with the sidewall insulating layer 171 as shown in FIGS. 5 and 5. As shown in FIG. 6 , the second opening OP2 ′ of the second blocking insulating layer 161 may contact the corresponding conductive gate contact 181A′. A thickness D2' of the edge portion CE' may be greater than a thickness D1 of the base portion CB. Also, the width of the second opening OP2′ shown in FIGS. 5 and 6 in the Z-axis direction may be greater than the width of the first opening OP1 shown in FIG. 3A in the Z-axis direction.

The plurality of edge portions CE' of the plurality of conductive patterns CP' may be spaced apart from sidewalls of the plurality of interlayer insulating films IL. The first filling insulating layer 131A of the filling insulating layer 131 may extend between the interlayer insulating layer IL and the edge portion CE′ adjacent to each other at the same level.

Each conductive gate contact 181A' may extend in the Z-axis direction to pass through the stepped stack ST', the first filling insulating layer 131A, and the second filling insulating layer 131B. The edge portion CE' of the conductive pattern CP' may cover the corresponding conductive gate contact 181A'.

The contact insulation pattern 141 may overlap the edge portion CE' of the conductive pattern CP', and another conductive pattern CP' disposed under the edge portion CE' of the conductive pattern CP'. It may be surrounded by the base portion CB of. The conductive gate contact 181A' may be insulated from the base portion CB by the contact insulation pattern 141 .

Hereinafter, a method of manufacturing a semiconductor memory device according to embodiments of the present invention will be described.

7A and 7B are cross-sectional views illustrating a process of separating a lower laminate into a plurality of patterns according to an embodiment of the present invention.

Referring to FIGS. 7A and 7B , the lower laminate may include a first protective film 107, a preliminary horizontal film 201 on the first protective film 107, and a second protective film 109 on the preliminary horizontal film 201. can

Before forming the lower laminate, forming a first lower insulating layer 101 penetrated by the plurality of lower contacts 103A and the plurality of lower dummy contacts 103B; A step of stacking a first semiconductor film on the top may be performed. Although not shown, the first lower insulating layer 101 may be formed on the peripheral circuit structure including the source driver SD, page buffer PB and row decoder RD shown in FIG. 1 . The first semiconductor layer is a layer for the plurality of first semiconductor patterns 105A, 105B, and 105C, and may include at least one of an n-type impurity and a p-type impurity. As an example, the first semiconductor layer may include n-type impurities.

The first passivation layer 107, the preliminary horizontal layer 201, and the second passivation layer 109 of the lower laminate may be sequentially stacked on the first semiconductor layer. The preliminary horizontal layer 201 may be selected from materials having etching selectivity with respect to the first passivation layer 107 and the second passivation layer 109 . The first passivation layer 107 and the second passivation layer 109 may include the same material as each other. As an example, the first passivation layer 107 and the second passivation layer 109 may include silicon oxide, and the preliminary horizontal layer 201 may include undoped silicon.

After forming the lower laminate, a second semiconductor layer may be formed on the second passivation layer 109 . The second semiconductor layer is a layer for the plurality of second semiconductor patterns 111A, 111B, and 111C, and may be an undoped semiconductor layer or a doped semiconductor layer including at least one of an n-type impurity and a p-type impurity. As an example, the second semiconductor layer may include n-type impurities.

Subsequently, the second semiconductor layer, the lower laminate, and the first semiconductor layer may be etched through an etching process using a photolithography process. As a result, the second semiconductor layer may be separated into a plurality of second semiconductor patterns 111A, 111B, and 111C. In addition, the lower laminate may be separated into a preliminary horizontal pattern 200A, a plurality of preliminary contact structures 200B, and a plurality of preliminary dummy structures 200C. Also, the first semiconductor layer may be separated into a plurality of first semiconductor patterns 105A, 105B, and 105C. The plurality of first semiconductor patterns 105A, 105B, and 105C may each be overlapped by a preliminary horizontal pattern 200A, a plurality of preliminary contact structures 200B, and a plurality of preliminary dummy structures 200C. The preliminary horizontal pattern 200A may overlap the first lower insulating layer 101 . The plurality of preliminary contact structures 200B may overlap each of the plurality of lower contacts 103A. The plurality of preliminary dummy structures 200C may overlap each of the plurality of lower dummy contacts 103B. The plurality of second semiconductor patterns 111A, 111B, and 111C may overlap the preliminary horizontal pattern 200A, the plurality of preliminary contact structures 200B, and the plurality of preliminary dummy structures 200C, respectively.

8a, 8b, 9a, 9b, 10a and 10b are cross-sectional views illustrating a method of forming a preliminary stepped laminate according to an embodiment of the present invention.

Referring to FIGS. 8A and 8B , a space between the plurality of first semiconductor patterns 105A, 105B, and 105C may be filled with a second lower insulating layer 104 . The second lower insulating layer 104 is interposed between the preliminary horizontal pattern 200A, the plurality of preliminary contact structures 200B, and the plurality of preliminary dummy structures 200C, and the plurality of second semiconductor patterns 111A, 111B, and 111C. ) can be filled in.

Thereafter, a plurality of first material films 221 and a plurality of second material films 223 are formed on the second lower insulating film 104 and the plurality of second semiconductor patterns 111A, 111B, and 111C. It can be laminated alternately in the axial direction.

Then, a plurality of first preliminary layers passing through the plurality of first material layers 221 and the plurality of second material layers 223 and extending into the plurality of first semiconductor patterns 105A, 105B, and 105C. Holes H1A, H1B, and H1C may be formed. The plurality of first preliminary holes H1A, H1B, and H1C may include a first preliminary channel hole H1A, a plurality of first preliminary contact holes H1B, and a plurality of first preliminary dummy holes H1C. can The first preliminary channel hole H1A may pass through the second semiconductor pattern 111A and the preliminary horizontal pattern 200A, and extend into the first semiconductor pattern 105A. Each of the first preliminary contact holes H1B may pass through the corresponding second semiconductor pattern 111B and the corresponding preliminary contact structure 200B, and extend into the corresponding first semiconductor pattern 105B. It can be. The first preliminary dummy hole H1C may pass through the corresponding second semiconductor pattern 111C and the corresponding preliminary dummy structure 200C, and may extend into the corresponding first semiconductor pattern 105C. there is. Each of the width W2 of the first preliminary contact hole H1B and the width W3 of the first preliminary dummy hole H1C may be wider than the width W1 of the first preliminary channel hole H1A. The width W2 of the first preliminary contact hole H1B and the width W3 of the first preliminary dummy hole H1C may be the same as or different from each other.

In etching processes for forming the plurality of first preliminary holes H1A, H1B, and H1C, the plurality of first semiconductor patterns 105A, 105B, and 105C may be used as an etch stop layer.

Subsequently, the first preliminary holes H1A, H1B, and H1C may be filled with a plurality of sacrificial pillars 225A, 225B, and 225C, respectively. The plurality of sacrificial pillars 225A, 225B, and 225C may include a first sacrificial pillar 225A, a plurality of second sacrificial pillars 225B, and a plurality of third sacrificial pillars 225C. The first sacrificial pillar 225A may fill the first preliminary channel hole H1A. Each of the second sacrificial pillars 225B may fill a corresponding first preliminary contact hole H1B. Each of the third sacrificial pillars 225C may fill a corresponding first preliminary dummy hole H1C.

Referring to FIGS. 9A and 9B , a plurality of first material layers 221 and a plurality of second material layers 223 are stacked on a plurality of sacrificial pillars 225A, 225B, and 225C. The third material layers 227 and the plurality of fourth material layers 229 may be alternately stacked in the Z-axis direction.

In the stack of the plurality of third material layers 227 and the plurality of fourth material layers 229, the third material layer 227 of the lowermost layer includes the plurality of first material layers 221 and the plurality of second material layers 229 . In the stack of material layers 223 , it may be in contact with the first material layer 221 of the uppermost layer. The plurality of third material layers 227 may be made of the same material as the plurality of second material layers 223 , and the plurality of fourth material layers 229 may be formed of the plurality of first material layers 221 . ) and may be composed of the same material.

The plurality of first material films 221 and the plurality of fourth material films 229 may be formed of an insulating material for interlayer insulating films. The plurality of second material layers 223 and the plurality of third material layers 227 are formed of a material having etching selectivity with respect to the plurality of first material layers 221 and the plurality of fourth material layers 229 . may consist of As an example, the plurality of second material films 223 and the plurality of third material films 227 may include silicon nitride. The plurality of sacrificial pillars 225A, 225B, and 225C include a plurality of first material layers 221 , a plurality of second material layers 223 , a plurality of third material layers 227 , and a plurality of fourth material layers 221 . It may be made of a material having etch selectivity with respect to the material layers 229 . As an example, the plurality of sacrificial pillars 225A, 225B, and 225C may include a metal such as tungsten.

10A and 10B , a plurality of first material layers 221, a plurality of second material layers 223, and a plurality of third material layers ( 227) and the plurality of fourth material layers 229 may be etched. The preliminary stepped laminate 220 may include a plurality of interlayer insulating films IL and a plurality of sacrificial films SC alternately disposed in the Z-axis direction. The plurality of interlayer insulating layers IL may include a plurality of remaining first material layers 221 and a plurality of remaining fourth material layers 229 . The plurality of sacrificial layers SC may include a plurality of remaining second material layers 223 and a plurality of remaining third material layers 227 . Each of the plurality of interlayer insulating layers IL and the plurality of sacrificial layers SC may have a plate shape extending in an XY plane.

The preliminary stepped laminate 220 may include a cell region CAR, a contact region CTR extending from the cell region CAR, and an extension region ER extending from the contact region CTR. The preliminary stepped laminate 220 may form a stepped structure in the contact region CTR and the extension region ER. To this end, the plurality of sacrificial layers SC may be patterned to have longer lengths in the contact region CTR and the extension region ER closer to the second lower insulating layer 104 . As an example, the plurality of sacrificial layers SC may have a longer length in the X-axis direction as they get closer to the second lower insulating layer 104 in the contact region CTR and the extension region ER.

Each sacrificial layer SC may include a base portion SB and an edge portion SE extending from the base portion SB. The base portion SB may be disposed between interlayer insulating films IL adjacent to each other in the Z-axis direction, and an upper surface of the edge portion SE may be open.

The plurality of base portions SB of the plurality of sacrificial layers SC may overlap the preliminary horizontal pattern 200A in the cell area CAR.

The plurality of edge portions SE of the plurality of sacrificial layers SC may form a stepped structure in the contact region CTR and the extension region ER. For example, the plurality of interlayer insulating layers IL may include a lower interlayer insulating layer LIL, a middle interlayer insulating layer MIL, and an upper interlayer insulating layer UIL sequentially disposed in the Z-axis direction. The plurality of sacrificial layers SC include a lower sacrificial layer LSC between the lower interlayer insulating layer LIL and the middle interlayer insulating layer MIL, and an upper sacrificial layer between the middle interlayer insulating layer MIL and the upper interlayer insulating layer UIL. (USC). At this time, the lower sacrificial film LSC is formed on the lower base part LB between the lower interlayer insulating film LIL and the middle interlayer insulating film MIL, and from the lower base part LB to the side compared to the middle interlayer insulating film MIL. A protruding lower edge portion LE may be included. The upper sacrificial layer USC includes an upper base portion UB between the middle interlayer insulating layer MIL and the upper interlayer insulating layer UIL, and an upper portion protruding from the upper base portion UB to the side compared to the upper interlayer insulating layer UIL. An edge portion SE may be included.

The first sacrificial pillar 225A may be buried in the cell region CAR of the preliminary stepped stacked body 220 . Some of the plurality of edge parts SE may overlap some of the plurality of second sacrificial pillars 225B and the plurality of third sacrificial pillars 225C, and some of the plurality of edge parts SE may overlap Some of the plurality of second sacrificial pillars 225B and the plurality of third sacrificial pillars 225C may protrude more than other parts in the Z-axis direction.

Subsequently, a portion of each of the plurality of edge portions SE may be etched so that the plurality of edge portions SE have a thickness D22 smaller than the thickness D11 of the plurality of base portions SB. Accordingly, each of the upper edge UE and the lower edge LE may have a thickness smaller than that of the upper base UB and the lower base LB, respectively.

11A, 11B, 12A, 12B, 13A and 13B are cross-sectional views illustrating a method of forming a contact hole and a dummy hole according to an embodiment of the present invention.

Referring to FIGS. 11A and 11B , a filling insulating layer 131 may be formed on the preliminary stepped laminate 220 . The filling insulating layer 131 includes a first filling insulating layer 131A covering the contact region CTR and the extension region ER of the preliminary stepped laminate 220 and a second filling insulating layer 131B on the first filling insulating layer 131A. ) may be included. A surface of the first filling insulating layer 131A may be substantially flat. The second filling insulating layer 131B may extend to cover the cell region CAR of the preliminary stepped stack 220 .

Referring to FIGS. 12A and 12B , the filling insulating film 131 and the preliminary stepped laminate 220 overlapping the plurality of second sacrificial pillars 225B and the plurality of third sacrificial pillars 225C may be etched. can Thus, a plurality of second preliminary contact holes H2B and a plurality of second preliminary dummy holes H2C exposing the plurality of second sacrificial pillars 225B and the plurality of third sacrificial pillars 225C may be formed. there is.

Each of the second preliminary contact holes H2B may pass through the filling insulating layer 131 overlapping the corresponding second sacrificial pillar 225B and the contact region CTR of the preliminary stepped laminate 220 . Each of the second preliminary dummy holes H2C may pass through the filling insulating layer 131 overlapping the corresponding third sacrificial pillar 225C and the extension region ER of the preliminary stepped laminate 220 . The width of the second preliminary contact hole H2B may be the same as or different from that of the second preliminary dummy hole H2C. A width of each of the second preliminary contact hole H2B and the second preliminary dummy hole H2C may be greater than that of the first preliminary channel hole H1A.

Referring to FIGS. 13A and 13B , the plurality of second sacrificial pillars shown in FIGS. 12A and 12B are provided through the plurality of second preliminary contact holes H2B and the plurality of second preliminary dummy holes H2C. 225B) and the plurality of third sacrificial pillars 225C may be removed. As a result, the plurality of first preliminary contact holes H1B and the plurality of first preliminary dummy holes H1C may be opened. The plurality of first preliminary contact holes H1B may be respectively connected to the plurality of second preliminary contact holes H2B, thereby defining the plurality of contact holes HB. The plurality of first preliminary dummy holes H1C may be connected to the plurality of second preliminary dummy holes H2C, thereby defining a plurality of dummy holes HC.

The plurality of edge portions SE of the plurality of sacrificial layers SC may be penetrated by a plurality of contact holes HB and a plurality of dummy holes HC, respectively. Each contact hole HB may pass through the contact region CTR of the preliminary stepped stack 220, the second semiconductor pattern 111B corresponding thereto, and the preliminary contact structure 200B corresponding thereto. It may extend into the corresponding first semiconductor pattern 105B. Each dummy hole HC may pass through the connection region ER of the preliminary stepped laminate 220, the second semiconductor pattern 111C corresponding thereto, and the preliminary dummy structure 200C corresponding thereto. It may extend into the corresponding first semiconductor pattern 105C. The width of the contact hole HB may be different from or the same as the width WC of the dummy hole HC.

Hereinafter, an upper sacrificial layer USC, an intermediate interlayer insulating layer MIL, a lower sacrificial layer LSC, and a lower interlayer insulating layer LIL defined with reference to FIG. 10A based on the reference hole R among the plurality of contact holes HB. ) will be described in more detail with respect to the structure of the contact hole passing through. The reference hole R may be spaced apart from the upper interlayer insulating layer UIL. The reference hole R may pass through the upper edge UE of the upper sacrificial layer USC and the lower base portion LB of the lower sacrificial layer LSC.

14A, 14B, 15A, 15B, 16A, 16B, 17A, and 17B are cross-sectional views illustrating a method of forming a sacrificial pad and a contact insulating pattern according to an embodiment of the present invention.

Referring to FIGS. 14A and 14B , the plurality of edge portions SE of the plurality of sacrificial layers SC shown in FIGS. 13A and 13B may be removed through the contact hole HB and the dummy hole HC. there is. Thus, a plurality of first recessed regions 231 may be defined in the region where the plurality of edge portions SE are removed. While removing the plurality of edge portions SE, the plurality of base portions SB may be etched through the contact hole HB and the dummy hole HC. As a result, a plurality of second recess regions 233 may be defined in the region where the plurality of base portions SB are removed. Due to the difference in thickness between the edge SE and the base SB, the first recessed area 231 may be narrower than the second recessed area 233 in the Z-axis direction.

15A and 15B, a sacrificial pad layer 241 is formed along the surfaces of the first recess region 231, the second recess region 233, the contact hole HB and the dummy hole HC. can do. The sacrificial pad layer 241 may extend along the surface of the filling insulating layer 131 .

The sacrificial pad layer 241 may be formed of the same material as the plurality of sacrificial layers SC. The sacrificial pad layer 241 may fill the plurality of first recess regions 231 having a relatively narrow width. The sacrificial pad layer 241 may extend along surfaces of the plurality of second recess regions 233 . The relatively wide second recess region 233 may not be completely filled with the sacrificial pad layer 241 and a central region thereof may be opened.

Referring to FIGS. 16A and 16B , the sacrificial pad layer 241 may be etched so that the sacrificial pad layer 241 shown in FIGS. 15A and 15B is separated into a plurality of sacrificial pads 241P. Each of the sacrificial pads 241P may remain inside the corresponding first recess region 231 . The plurality of second recess regions 233 may be opened by the etching process of the sacrificial pad layer 241 .

Referring to FIGS. 17A and 17B , the plurality of second recess regions 233 may be filled with a plurality of contact insulating patterns 141 through the contact hole HB and the dummy hole HC, respectively. The plurality of contact insulating patterns 141 may include a material having etch selectivity with respect to the plurality of sacrificial layers SC and the plurality of sacrificial pads 241P.

As described above, the edge portion SE of the sacrificial film SC shown in FIGS. 13A and 13B is replaced with the sacrificial pad 241P as shown in FIGS. 17A and 17B, and in FIGS. 13A and 13B A portion of the base portion SB of the illustrated sacrificial layer SC may be replaced with the contact insulating pattern 141 . At this time, the contact insulation pattern 141 may be automatically aligned at the target position by using the thickness difference between the base portion SB and the edge portion SE of the sacrificial film SC shown in FIGS. 13A and 13B. . More specifically, the contact insulation pattern 141 may be automatically aligned to overlap the sacrificial pad 241P. In addition, the contact insulating pattern 141 may be automatically aligned between the interlayer insulating layers IL. Also, the contact insulating pattern 141 may be automatically aligned on the sidewall of the base portion SB of the sacrificial layer SC toward each of the contact hole HB and the dummy hole HC.

18 is a cross-sectional view showing a method of forming a channel hole according to an embodiment of the present invention.

Referring to FIG. 18 , the filling insulating layer 131 overlapping the first sacrificial pillar 225A shown in FIG. 17A and the cell region CAR of the preliminary stepped laminate 220 may be etched. Accordingly, the second preliminary channel hole H2A exposing the first sacrificial pillar 225A shown in FIG. 17A may be formed.

Subsequently, the first sacrificial pillar 225A shown in FIG. 17A may be removed through the second preliminary channel hole H2A. As a result, the first preliminary channel hole H1A may be opened. The second preliminary channel hole H2A may be connected to the first preliminary channel hole H1A, thereby defining the channel hole HA. The channel hole HA not only penetrates the plurality of base portions SB and the plurality of interlayer insulating layers IL of the plurality of sacrificial layers SC, but also penetrates the second semiconductor pattern 111A corresponding thereto. can In addition, the channel hole HA may pass through the preliminary horizontal pattern 200A and may extend into the corresponding first semiconductor pattern 105A. The width WA of the channel hole HA may be smaller than the width WB of the contact hole HB and the width WC of the dummy hole HC shown in FIG. 17B.

19a, 19b, 20a, 20b, 21, 22a, and 22b are cross-sectional views illustrating a method of forming a preliminary memory pattern, a channel structure, a first support structure, and a second support structure according to an embodiment of the present invention. admit.

Referring to FIGS. 19A and 19B , a memory layer 151 may be formed along surfaces of each of the channel hole HA, the plurality of contact holes HB, and the plurality of dummy holes HC. The memory layer 151 may be formed by sequentially stacking the first blocking insulating layer, the data storage layer, and the tunnel insulating layer. Sidewalls of the contact insulating pattern 141 and sidewalls of the sacrificial pad 241P may be covered with the memory layer 151 .

Subsequently, a channel layer 153 may be formed along the surface of the memory layer 151 . A central region of each of the channel hole HA, the plurality of contact holes HB, and the plurality of dummy holes HC may not be completely filled with the channel layer 153 and may be partially opened.

Thereafter, forming an insulating material on the surface of the channel film 153 and planarizing the insulating material to expose the channel film 153 may be performed. Thus, the insulator is formed by the preliminary core insulating pattern 155PA inside the channel hole HA, the plurality of first dummy core insulating patterns 155B and the plurality of dummy holes HC inside the plurality of contact holes HB. It may be separated into a plurality of inner second dummy core insulating patterns 155C. A central region of the channel hole HA may be filled with a preliminary core insulating pattern 155PA. Since the contact hole HB is formed wider than the channel hole HA, a central region of the contact hole HB may not be completely filled with the first dummy core insulating pattern 155B, but a portion thereof may be opened. Since the dummy hole HC is formed to be wider than the channel hole HA, a central region of the dummy hole HC may not be completely filled with the second dummy core insulating pattern 155C and a portion thereof may be opened.

Referring to FIGS. 20A and 20B , a first upper passivation layer 261 may be formed on the channel layer 153 . To define a void 263 in the central region of each of the contact hole HB and the dummy hole HC, the first upper protective film 261 is formed by using a deposition method with low step coverage. can be formed As an example, the first upper passivation layer 261 may be formed by plasma-enhanced chemical vapor deposition (PECVD). For example, the first upper passivation layer 261 may be formed of PETEOS (Plasma-Enhanced TetraEthyl OSilicate). Embodiments of the present invention are not limited thereto.

Referring to FIG. 21 , a portion of the first upper passivation layer 261 overlapping the cell region CAR of the preliminary stepped laminate 220 may be removed. To this end, a mask pattern (not shown) that opens the cell region CAR of the preliminary stepped laminate 220 and blocks the contact region CTR and the extension region may be used as an etch barrier. As a result, a part of the preliminary core insulating pattern 155PA shown in FIG. 20A may be exposed. Thereafter, by removing a portion of the exposed preliminary core insulating pattern, the core insulating pattern 155A and the core groove 265 may be defined. The mask pattern may be removed after forming the core insulating pattern 155A.

The first dummy core insulation pattern 155B passing through the contact region CTR of the preliminary stepped laminate 220 and the first dummy core insulating pattern 155B penetrating the extension region ER of the preliminary stepped laminate 220 shown in FIG. 20B. The second dummy core insulating pattern 155C may be protected by the first upper passivation layer 261 .

Referring to FIGS. 22A and 22B , a capping pattern 157 may be formed to fill the core groove 265 shown in FIG. 21 . Forming the capping pattern 157 may include filling the core groove 265 shown in FIG. 21 with a doped semiconductor material and planarizing the doped semiconductor material so that the filling insulating layer 131 is exposed. . As the first upper passivation layer 261 shown in FIG. 21 is removed by planarization, the central regions of each of the contact hole HB and the dummy hole HC may be opened.

By planarization, the channel layer 153 shown in FIG. 21 may be separated into a cell channel layer 153A, a plurality of first dummy channel layers 153B, and a plurality of second dummy channel layers 153C. . By planarization, the memory layer 151 shown in FIG. 21 may be separated into a memory pattern 151A, a plurality of first dummy memory patterns 151B, and a plurality of second dummy memory patterns 151C.

Through the above-described processes, the channel hole HA may be filled with the memory pattern 151A and the channel structure CH. The channel structure CH may include a cell channel layer 153A, a core insulating pattern 155A, and a capping pattern 157. In addition, the first support structure 150[1] may be formed inside the contact hole HB. The first support structure 150[1] may include a first dummy memory pattern 151B, a first dummy channel layer 153B, and a first dummy core insulating pattern 155B. In addition, the second support structure 150 [2] may be formed inside the dummy hole HC. The second support structure 150[2] may include a second dummy memory pattern 151C, a second dummy channel layer 153C, and a second dummy core insulating pattern 155C.

The first support structure 150[1] may pass through the contact region CTR of the preliminary stepped laminate 220 and extend into the corresponding preliminary contact structure 200B. The second support structure 150 [2] may pass through the extension region ER of the preliminary stepped stack 220 and extend into the corresponding preliminary dummy structure 200C. Each of the first support structure 150 [1] and the second support structure 150 [2] may be surrounded by the contact insulation pattern 141 and the sacrificial pad 241P. Since the first support structure 150[1] and the second support structure 150[2] are formed using the process of forming the memory pattern 151A and the channel structure CH, the manufacturing process of the semiconductor memory device is simplified. It can be.

23A, 23B, 24A, 24B, 25A, and 25B are cross-sectional views illustrating a method of forming a blocking insulating film and a conductive pattern according to an embodiment of the present invention.

Referring to FIGS. 23A and 23B , a second upper passivation layer 271 may be formed on the filling insulating layer 131 . The second upper passivation layer 271 may be formed by a deposition method with low step coverage so that a void 273 may be defined in the central region of each of the contact hole HB and the dummy hole HC. The second upper passivation layer 271 may cover the channel structure CH, the memory pattern 151A, the first support structure 150 [1] and the second support structure 150 [2].

Referring to FIGS. 24A and 24B , the first layer is formed by etching the plurality of interlayer insulating films IL and the plurality of sacrificial films SC in the cell region CAR of the preliminary stepped laminate 220 shown in FIG. 23A. One preliminary slit SI1 may be formed. Thereafter, the plurality of sacrificial layers SC and the plurality of sacrificial pads 241P shown in FIGS. 23A and 23B may be selectively removed through the first preliminary slit SI1 . As a result, the plurality of gate regions 275 may be opened. Each gate region 275 may be defined between interlayer insulating films IL adjacent to each other in the Z-axis direction, and may extend between the filling insulating film 131 and the interlayer insulating film IL adjacent to each other in the Z-axis direction. there is. The contact insulation pattern 141 , the first support structure 150 [ 1 ] and the second support structure 150 [ 2 ] may be exposed by the plurality of gate regions 275 .

The plurality of gate regions 275 may include an upper gate region 275U and a lower gate region 275L. The upper gate region 275U may be defined in a region from which the upper sacrificial layer USC shown in FIG. 23A and the sacrificial pad 241P at the same level are removed, and the lower gate region 275L and the sacrificial pad 241P shown in FIG. 23A are removed. The lower sacrificial layer LSC and the sacrificial pad 241P at the same level may be defined in the removed region.

Referring to FIGS. 25A and 25B , a second blocking insulating layer 161 may be formed along the surface of the gate region 275 shown in FIGS. 24A and 24B . The second blocking insulating layer 161 may have a first opening OP1 facing the first preliminary slit SI1. The second blocking insulating layer 161 may extend along sidewalls of each of the first support structure 150 [1] and the second support structure 150 [2]. The second blocking insulating layer 161 may extend along the sidewall of the contact insulating pattern 141 .

Subsequently, a central region of the gate region 275 opened by the second blocking insulating layer 161 may be filled with a first conductive material. The first conductive material may flow into the gate region 275 shown in FIGS. 24A and 24B through the first opening OP1 . Thereafter, by removing the first conductive material inside the first preliminary slit SI1, a plurality of conductive patterns CP disposed inside the plurality of gate regions 275 and separated from each other in the Z-axis direction are formed. can The plurality of conductive patterns CP include the upper conductive pattern UCP inside the upper gate area 275U shown in FIG. 24A and the lower conductive pattern LCP inside the lower gate area 275L shown in FIG. 24A. can do.

Each conductive pattern CP may include a base portion CB and an edge portion CE having a thickness smaller than that of the base portion CB. The base part CB may cover the channel structure CH and the memory pattern 151A. The edge portion CE may cover the corresponding first support structure 150 [1] and second support structure 150 [2].

A gap between interlayer insulating films IL adjacent to each other in the Z-axis direction may be stably maintained by the first support structure 150[1] and the second support structure 150[2].

26, 27, 28a, 28b, 29a, 29b, 30a, 30b, 31a, 31b, 32a, and 32b show a common source pattern and a conductive gate contact according to an embodiment of the present invention. and cross-sectional views illustrating a method of forming a dummy contact.

Referring to FIG. 26 , a second preliminary slit SI2 connected to the first preliminary slit SI1 may be formed. The second preliminary slit SI2 may extend through the second semiconductor pattern 111A. The slit SI may be defined by the first preliminary slit SI1 and the second preliminary slit SI2 connected to each other.

Referring to FIG. 27 , a sidewall insulating layer 171 may be formed on the sidewall of the slit SI. While the sidewall insulating layer 171 is etched to expose the bottom surface of the slit SI, a portion of the second passivation layer 109 of the preliminary horizontal pattern 200A shown in FIG. 26 may be removed. Thus, the preliminary horizontal film 201 of the preliminary horizontal pattern 200A shown in FIG. 26 may be exposed.

Subsequently, the preliminary horizontal film 201 of the preliminary horizontal pattern 200A shown in FIG. 26 may be selectively removed through the slit SI. Thus, the first passivation layer 107 and the second passivation layer 109 of the preliminary horizontal pattern 200A shown in FIG. 26 may be exposed. Thereafter, the cell channel layer 153A may be exposed by removing a portion of the memory pattern 151A through the region where the preliminary horizontal pattern 200A is removed.

While part of the memory pattern 151A is removed, the first passivation layer 107 and the second passivation layer 109 of the preliminary horizontal pattern 200A shown in FIG. 26 may be removed. As a result, the first semiconductor pattern 105A and the second semiconductor pattern 111A may be exposed.

Through the above-described processes, the horizontal space 275 between the first semiconductor pattern 105A and the second semiconductor pattern 111A may be opened. In addition, the memory pattern 151A may be separated into a first memory pattern 151P1 and a second memory pattern 151P2 by the horizontal space 275 .

Referring to FIGS. 28A and 28B , a doped semiconductor layer 173 may be formed to fill the horizontal space 275 and the slit SI shown in FIG. 27 . The doped semiconductor layer 173 may include n-type impurities. The doped semiconductor layer 173 may extend to overlap the second upper passivation layer 271 and may contact the cell channel layer 153A.

Referring to FIGS. 29A and 29B , a portion of the doped semiconductor film 173 on the first support structure 150[1] and the second support structure 150[2] shown in FIGS. 28A and 28B and 2 A portion of the upper passivation layer 271 may be removed. To this end, a mask pattern (not shown) is etched to block the doped semiconductor film 173 in the cell region CAR and expose the doped semiconductor film 173 in the contact region CTR and extension region ER. Can be used as a barrier. By etching the doped semiconductor film 173 and the second upper passivation film 271, the first support structure 150[1] and the second support structure 150[2] shown in FIGS. 28A and 28B are exposed. It can be. The mask pattern may be removed after etching the doped semiconductor layer 173 and the second upper passivation layer 271 .

Subsequently, the first support structure 150[1] and the second support structure 150[2] shown in FIGS. 28A and 28B may be removed. As a result, the contact hole HB and the dummy hole HC may be opened. The second blocking insulating layer 161 and the contact insulating pattern 141 may be exposed through the contact hole HB and the dummy hole HC.

FIG. 30A is an enlarged cross-sectional view of the AR3 region shown in FIG. 29A.

Referring to FIG. 30A, as the first support structure 150[1] shown in FIG. 28A is removed, the second blocking insulating layer 161 and the contact insulating pattern 141 are exposed through the contact hole HB. can

Although not shown in the enlarged cross-sectional view, as the second support structure 150[2] shown in FIG. 28B is removed, the second blocking insulating layer 161 and the contact insulating pattern are formed through the dummy hole HC shown in FIG. 29B. (141) may be exposed.

30B shows an embodiment of a subsequent process following the processes described with reference to FIGS. 29A, 29B, and 30A.

Referring to FIG. 30B , the exposed region of the second blocking insulating layer 161 may be removed through the contact hole HB. Thus, the second opening OP2 may be defined. The edge portion CE of the conductive pattern CP may be exposed through the second opening OP2 .

Although not shown in the enlarged cross-sectional view, the exposed region of the second blocking insulating layer 161 may be removed through the dummy hole HC shown in FIG. 29B. Accordingly, as shown in FIG. 31B , the third opening OP3 may be defined, and the edge portion CE of the conductive pattern CP corresponding thereto may be exposed through the third opening OP3 .

Even if a portion of the second blocking insulating layer 161 is removed, the contact insulating pattern 141 may remain to overlap the edge portion CE of the conductive pattern CP.

31A and 31B, the preliminary horizontal layer 201 of the preliminary contact structure 200B shown in FIG. 29A and the preliminary dummy structure shown in FIG. 29B are formed through the contact hole HB and the dummy hole HC ( 200C) may remove the preliminary horizontal film 201. In addition, the first semiconductor pattern 105B and the second semiconductor pattern 111B overlapped on the preliminary contact structure 200B shown in FIG. 29A and the first semiconductor pattern overlapped on the preliminary dummy structure 200C shown in FIG. 29B. 105C and the second semiconductor pattern 111C may be removed.

A first lower recess region 283A is defined in the region where each of the first semiconductor patterns 105B and 105C shown in FIGS. 29A and 29B are removed, and the preliminary horizontal film 201 shown in FIGS. 29A and 29B is formed. ) is removed, a second lower recess region 283B is defined, and a third lower recess region ( 283C) may be defined. While the first semiconductor patterns 105B and 105C, the preliminary horizontal layer 201, and the second semiconductor patterns 111B and 111C shown in FIGS. 29A and 29B are removed, on the second upper passivation layer 271 A portion of the disposed doped semiconductor layer 173 may be removed.

The first passivation layer 107 and the second passivation layer 109 may remain at the boundary between the first lower recess region 283A, the second lower recess region 283B, and the third lower recess region 283C. there is.

Referring to FIGS. 32A and 32B , the contact hole HB, the dummy hole HC, the first lower recess area 283A, the second lower recess area 283B and the second lower recess area 283B shown in FIGS. 31A and 31B 3 The lower recess region 283C may be filled with a second conductive material. After that, the second conductive material may be etched to expose the filling insulating layer 131 . Thus, the conductive gate contact 181A and the dummy contact 181B may be defined.

The doped semiconductor layer 173 shown in FIG. 31A may be planarized by a planarization process for forming the conductive gate contact 181A and the dummy contact 181B. Thus, the doped semiconductor layer 173 shown in FIG. 31A may remain as the common source pattern CSL. The common source pattern CSL may include a horizontal doped semiconductor pattern 173H and a conductive vertical contact 173VC. The horizontal doped semiconductor pattern 173H may contact the cell channel layer 153A of the channel structure CH and may be disposed between the first doped semiconductor pattern 105A and the second doped semiconductor pattern 111A. The conductive vertical contact 173VC may extend in the Z-axis direction from the horizontally doped semiconductor pattern 173H. The conductive vertical contact 173VC may be insulated from the plurality of conductive patterns CP by the sidewall insulating layer 171 .

The conductive gate contact 181A not only fills the contact hole HB shown in FIG. 31A, but also includes a first lower recess region 283A and a second lower recess region connected to the contact hole HB shown in FIG. 31A. 283B and the third lower recess area 283C may be filled. The conductive gate contact 181A may contact the corresponding edge portion CE of the conductive pattern CP through the second opening OP2 . The base portion CB of the conductive pattern CP may be spaced apart from the conductive gate contact 181A by the remaining contact insulating pattern 141 .

The dummy contact 181B not only fills the dummy hole HC shown in FIG. 31B, but also includes the first lower recess region 283A and the second lower recess region (connected to the dummy hole HC shown in FIG. 31B). 283B) and the third lower recess area 283C may be filled. The dummy contact 181B may contact the corresponding edge portion CE of the conductive pattern CP through the third opening OP3. The base portion CB of the conductive pattern CP may be spaced apart from the dummy contact 181B by the remaining contact insulating pattern 141 .

The first support structure 150[1] shown in FIG. 28A and the preliminary horizontal film 201 of the preliminary contact structure 200B shown in FIG. 29A are replaced with a conductive gate contact 181A, and the In the process of replacing the second support structure 150 [2] and the preliminary horizontal layer 201 of the preliminary dummy structure 200C shown in FIG. 29A with the dummy contact 181B, the first passivation layer 107 and the second The protective film 109 may remain without being removed.

Next, subsequent processes for forming the upper insulating layer UI, the bit line contact 193A, the upper contact 193B, the bit line BL, and the upper wiring UL shown in FIGS. 3A, 3B, and 3C are performed. can be done

33A to 33J are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention. 33A to 33J are cross-sectional views illustrating a modified embodiment of a process of forming sacrificial pads. 33A to 33J show the contact area CTR′ of the preliminary stepped laminate 320 . Although not shown in the drawing, the preliminary stepped laminate 320 includes an extension region extending from the contact region CTR', and the process for the extension region is similar to the process for the contact region CTR' described below. can proceed

Referring to FIG. 33A , as described with reference to FIGS. 7A and 7B , the first lower insulating layer 101 penetrated by the plurality of lower contacts 103A, the plurality of preliminary contact structures 200B, and the second lower An insulating film 104 may be formed.

Then, as described with reference to FIGS. 8A, 8B, 9A, 9B, 10A, and 10B , a preliminary stepped laminate 320 is formed on the second lower insulating layer 104 . The preliminary stepped laminate 320 may include a plurality of interlayer insulating films IL and a plurality of sacrificial films SC′ alternately disposed on the second lower insulating film 104 . A plurality of sacrificial pillars 225B may be buried in a portion of the contact region CTR′ of the preliminary stepped laminate 320 . The plurality of sacrificial pillars 225B may extend into each of the plurality of preliminary contact structures 200B.

The plurality of sacrificial layers SC' may be patterned to have a longer length in the contact region CTR' closer to the second lower insulating layer 104 . Each sacrificial layer SC' may include a base portion SB' and an edge portion SE' extending from the base portion SB'. The base portion SB' may be disposed between interlayer insulating films IL adjacent to each other in the Z-axis direction, and an upper surface of the edge portion SE' may be open. The plurality of edge portions SE' of the plurality of sacrificial layers SC' may form a stepped structure in the contact region CTR'. The sacrificial layer SC′ may be formed of a material having etch selectivity with respect to the interlayer insulating layer IL.

Subsequently, a spacer pattern 301 may be formed. The spacer pattern 301 may be disposed on the edge portion SE′ constituting each of the layers of the preliminary stepped stack 320 and sidewalls of the interlayer insulating layer IL. The spacer pattern 301 may be formed of a material having etch selectivity with respect to the sacrificial layer SC'. The plurality of edge portions SE' may include an area overlapping the spacer pattern 301 thereon and an area exposed and not overlapped by the spacer pattern 301 .

For example, the plurality of interlayer insulating layers IL may include a lower interlayer insulating layer LIL, a middle interlayer insulating layer MIL, and an upper interlayer insulating layer UIL sequentially disposed in the Z-axis direction. The plurality of sacrificial layers SC' may include a lower sacrificial layer LSC' between the lower interlayer insulating layer LIL and the middle interlayer insulating layer MIL, and an upper portion between the middle interlayer insulating layer MIL and the upper interlayer insulating layer UIL. A sacrificial layer USC′ may be included. At this time, the lower sacrificial layer LSC' is applied to the lower base part LB' between the lower interlayer insulating film LIL and the middle interlayer insulating film MIL, and from the lower base part LB' to the middle interlayer insulating film MIL. A lower edge portion LE′ protruding to the side may be included. The upper sacrificial layer USC′ is formed from the upper base portion UB′ between the middle interlayer insulating layer MIL and the upper interlayer insulating layer UIL, and from the upper base portion UB′ to the side compared to the upper interlayer insulating layer UIL. A protruding upper edge portion SE′ may be included. At least one of the plurality of spacer patterns may be disposed on the lower edge portion LE′. A portion of the upper surface of the lower edge portion LE′ may overlap the spacer pattern 301 , and another portion may be exposed without overlapping the spacer pattern 301 . The spacer pattern 301 overlapping a portion of the upper surface of the lower edge portion LE′ may extend along sidewalls of the intermediate interlayer insulating layer MIL and sidewalls of the upper edge portion UE′.

Referring to FIG. 33B , first sacrificial pads 303 may be formed on the plurality of edge portions SE′, respectively. The first sacrificial pad 303 may be made of the same material as the sacrificial layer SC'.

The first sacrificial pad 303 may overlap a portion of the upper surface of the edge SE' of the sacrificial layer SC' exposed by the spacer pattern 301 . The first sacrificial pad 303 may be spaced apart from the sacrificial layer SC′ by the spacer pattern 301 .

The process of forming the first sacrificial pad 303 is not limited to the above and may vary.

Referring to FIG. 33C , the spacer pattern 301 shown in FIG. 33B may be removed. Thereafter, as described with reference to FIGS. 11A and 11B , a first filling insulating layer 131A may be formed. The first filling insulating layer 131A may cover the preliminary stepped stacked body 320 and may include a protrusion 131P filling the removed region of the spacer pattern 301 shown in FIG. 33B. The present invention is not limited thereto. As an example, the spacer pattern 301 made of an insulating material may remain, and the first filling insulating layer 131A may cover the remaining spacer pattern 301 .

Referring to FIG. 33D , as described with reference to FIGS. 11A and 11B , a second filling insulating layer 131B may be formed on the first filling insulating layer 131A. Thus, the filling insulating layer 131 including the first filling insulating layer 131A and the second filling insulating layer 131B may be formed on the preliminary stepped stacked body 320 .

Subsequently, the filling insulating layer 131 and the preliminary stepped laminate 320 overlapping the plurality of sacrificial pillars 225B shown in FIG. 33C may be etched. After that, the plurality of sacrificial pillars 225B shown in FIG. 33C may be removed. As a result, a plurality of contact holes HB' may be formed.

The plurality of edge portions SE' of the plurality of sacrificial layers SC' may be respectively penetrated by a plurality of contact holes HB'. Each contact hole HB' may pass through the contact region CTR' of the preliminary stepped laminate 320, the corresponding second semiconductor pattern 111B and the preliminary contact structure 200B, and correspond thereto. may extend into the first semiconductor pattern 105B. Each of the first sacrificial pads 303 may be penetrated by a plurality of contact holes HB'.

As described with reference to FIG. 13A , the reference hole R' among the plurality of contact holes HB' may be spaced apart from the upper interlayer insulating film UIL, the middle interlayer insulating film MIL, and the upper sacrificial film USC. '), the lower sacrificial layer LSC', and the lower interlayer insulating layer LIL. For example, the reference hole R' may pass through the upper edge UE' of the upper sacrificial layer USC' and the lower base portion LB' of the lower sacrificial layer LSC'.

Referring to FIG. 33E , the plurality of edge portions SE' and the plurality of first sacrificial pads 303 of the plurality of sacrificial layers SC' shown in FIG. 33D are formed through the plurality of contact holes HB'. ) can be removed. Thus, a plurality of first recess regions 311 may be defined. While the plurality of first sacrificial pads 303 and the plurality of edge parts SE' shown in FIG. 33D are removed, the plurality of base parts SB' are etched through the plurality of contact holes HB'. It can be. Thus, a plurality of second recess regions 313 may be defined in the region where the plurality of base portions SB' are removed. Due to the removal of the first sacrificial pad 303 , the first recess region 311 may be defined with a wider width in the Z-axis direction than the second recess region 313 .

Referring to FIG. 33F , a contact insulating layer 141L may be formed along surfaces of the first recess region 311 , the second recess region 313 , and the contact hole HB′. The contact insulating layer 141L may extend along the surface of the filling insulating layer 131 . The contact insulating layer 141L may be formed of a material having etch selectivity with respect to the sacrificial layer SC'.

The contact insulating layer 141L may fill the relatively narrow second recess region 313 . The relatively wide first recess region 311 may not be completely filled with the contact insulating layer 141L, and a central region thereof may be opened.

Referring to FIG. 33G , the contact insulating layer 141L may be etched so that the contact insulating layer 141L shown in FIG. 33F is separated into a plurality of contact insulating patterns 141 . Each contact insulating pattern 141 may remain inside the corresponding second recess region 313 . Through the etching process of the contact insulating layer 141L, a plurality of first recess regions 311 may be opened.

Referring to FIG. 33H , the plurality of first recess regions 311 may be filled with a plurality of second sacrificial pads 331 through the plurality of contact holes HB'. The second sacrificial pad 331 may be formed of the same material as the sacrificial layer SC'. The second sacrificial pad 331 may be formed thicker in the Z-axis direction than the sacrificial layer SC'.

As described above, a part of the base portion SB' of the sacrificial film SC' shown in FIG. 33D may be replaced with the contact insulating pattern 141, and the sacrificial film SC' shown in FIG. The edge portion SE′ and the first sacrificial pad 303 may be replaced with the second sacrificial pad 331 . At this time, the difference between the total thickness of the edge portion SE' of the sacrificial layer SC' and the first sacrificial pad 303 shown in FIG. 33D and the thickness of the base portion SB' of the sacrificial layer SC' Using this, the contact insulation pattern 141 can be automatically aligned at the target position.

Referring to FIG. 33I, the support structure 150[1] inside the contact hole HB' using the processes described above with reference to FIGS. 19A, 19B, 20A, 20B, 21, 22A, and 22B. ) can be formed. The support structure 150[1] may include a dummy memory pattern 151B, a dummy channel layer 153B, and a dummy core insulating pattern 155B.

Thereafter, as described with reference to FIGS. 23A and 23B , an upper passivation layer 271 may be formed on the filling insulating layer 131 so that a void 273 may be defined inside the contact hole HB'.

Referring to FIG. 33J , the plurality of sacrificial layers SC′ and the plurality of second sacrificial pads 331 shown in FIG. 33I may be removed using the processes described with reference to FIGS. 24A and 24B . . As a result, the plurality of gate regions 375 may be opened.

Thereafter, the processes described with reference to FIGS. 25A, 25B, 26, 27, 28A, 28B, 29A, 29B, 30A, 30B, 31A, 31B, 32A, and 32B can be done

34A to 34O are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention. 34A to 34O show a manufacturing method for some regions of a semiconductor memory device corresponding to a cell region (CAR") and a contact region (CTR") of a gate stack. Although not shown in the drawings below, the gate laminate may include an extension region as described with reference to FIG. 2, and a manufacturing process in the extension region is similar to the manufacturing process in the contact region (CTR") below. Hereinafter, redundant descriptions of the same components as those in FIGS. 7A to 32B will be omitted.

Referring to FIG. 34A , a first semiconductor layer, a lower laminate, and a second semiconductor layer may be sequentially formed on the first lower insulating layer 101 . As described with reference to FIGS. 7A and 7B , the lower laminate includes a first protective film 107, a preliminary horizontal film 201 on the first protective film 107, and a second protective film 109 on the preliminary horizontal film 201. can include

Subsequently, as described with reference to FIGS. 7A and 7B , the second semiconductor layer, the lower laminate, and the first semiconductor layer may be etched. As a result, the first semiconductor layer may be separated into a plurality of first semiconductor patterns 105A and 105B overlapping the first lower insulating layer 101 . The second semiconductor layer may be separated into a plurality of second semiconductor patterns 111A and 111B overlapping the plurality of first semiconductor patterns 105A and 105B, respectively. Also, the lower laminate may be separated into a preliminary horizontal pattern 200A and a plurality of preliminary contact structures 200B. The preliminary horizontal pattern 200A may be disposed between the first semiconductor pattern 105A and the second semiconductor pattern 111A of the cell region CAR", and the plurality of preliminary contact structures 200B may be disposed in the contact region CTR. ") may be disposed between the plurality of first semiconductor patterns 105B and the plurality of second semiconductor patterns 111B.

After that, the space between the plurality of first semiconductor patterns 105A and 105B may be filled with the second lower insulating layer 104 . The second lower insulating layer 104 may fill between the preliminary horizontal pattern 200A and the plurality of preliminary contact structures 200B and between the plurality of second semiconductor patterns 111A and 111B.

Subsequently, a plurality of lower contacts 403A may be formed. Each lower contact 403A may pass through the second semiconductor pattern 111B, the preliminary contact structure 200B, the first semiconductor pattern 105B, and the first lower insulating layer 101 in the contact region CTR". .

Referring to FIG. 34B , as described with reference to FIGS. 8A and 8B , a plurality of first material layers 221 are formed on the second lower insulating layer 104 and the plurality of second semiconductor patterns 111A and 111B. And a plurality of second material layers 223 may be alternately stacked in the Z-axis direction.

Subsequently, a first preliminary channel passes through the plurality of first material films 221 and the plurality of second material films 223 in the cell array region CAR" and extends into the first semiconductor pattern 105A. The first preliminary channel hole H1A may pass through the second semiconductor pattern 111A and the preliminary horizontal pattern 200A, and may extend into the first semiconductor pattern 105A. can

After that, as described with reference to FIGS. 8A and 8B , the first preliminary channel hole H1A may be filled with the sacrificial pillar 225A. While forming the first preliminary channel hole H1A and the sacrificial pillar 225A, the plurality of first material layers 221 and the plurality of second material layers 223 in the contact region CTR" It may remain overlapped with the lower contacts 403A.

Subsequently, as described with reference to FIGS. 9A and 9B , a plurality of first material layers 221 and a plurality of second material layers 223 are stacked on the sacrificial pillar 225A. Three material layers 227 and a plurality of fourth material layers 229 may be alternately stacked in the Z-axis direction.

Referring to FIG. 34C , an etch stop layer 410 may be formed on a stack of a plurality of third material layers 227 and a plurality of fourth material layers 229 . The etch stop layer 410 may include a nitride layer. After forming the etch stop layer 410 , the etch stop layer 410 overlapping the sacrificial pillar 225A shown in FIG. 34B , the plurality of third material layers 227 and the plurality of fourth material layers 229 By etching, a second preliminary channel hole H2A may be formed. The second preliminary channel hole H2A penetrates the etch stop layer 410, the plurality of third material layers 227, and the plurality of fourth material layers 229 to form the sacrificial pillar 225A shown in FIG. 34B. can expose.

Subsequently, the sacrificial pillar 225A shown in FIG. 34B may be removed through the second preliminary channel hole H2A. Accordingly, the first preliminary channel hole H1A may be opened. The second preliminary channel hole H2A may be connected to the first preliminary channel hole H1A, thereby defining a channel hole HA". A plurality of channel holes HA" may be formed in the cell area CAR". first material layers 221, a plurality of second material layers 223, a plurality of third material layers 227, a plurality of fourth material layers 229, and a second semiconductor pattern 111A and may pass through the preliminary horizontal pattern 200A. In addition, the channel hole HA" may extend into the first semiconductor pattern 105A. While forming the channel hole HA", the plurality of first material layers 221, the plurality of second material layers 223, and the plurality of third material layers 227 in the contact region CTR" And the plurality of fourth material layers 229 may remain overlapping the plurality of lower contacts 403A.

Thereafter, a memory pattern 151A and a channel structure CH may be formed inside the channel hole HA". The channel structure CH includes the cell channel layer 153A, the core insulating pattern 155A, and the capping pattern. (157).

The forming of the memory pattern 151A and the channel structure CH may include forming a memory layer by sequentially stacking a first blocking insulating layer, a data storage layer, and a tunnel insulating layer along the surface of the channel hole HA". Forming a channel film along the surface of the film, filling the central region of the channel hole (HA") with the core insulating pattern 155A and the capping pattern 157, and performing a planarization process to expose the etch stop film 410. A step of removing portions of each of the memory layer and the channel layer may be included.

Referring to FIG. 34D , as described with reference to FIGS. 10A and 10B , a plurality of first material layers 221 and a plurality of second material layers 223 are defined so as to define the preliminary stepped laminate 220 . ), the plurality of third material layers 227 and the plurality of fourth material layers 229 may be etched. The plurality of first material films 221 and the remaining plurality of fourth material films 229 may remain as a plurality of interlayer insulating films IL, and the plurality of second material films 223 and the plurality of remaining fourth material films 229 may remain as a plurality of interlayer insulating films IL. The third material layers 227 of may remain as a plurality of sacrificial layers SC. As described with reference to FIGS. 10A and 10B , each sacrificial layer SC may include a base portion SB and an edge portion SE extending from the base portion SB. The edge portion SE may remain thinner than the base portion SB.

Subsequently, the remaining portion of the etch stop layer 410 shown in FIG. 34C may be removed. After that, the filling insulating layer 420 may be formed to cover the cell region CAR" and the contact region CTR" of the preliminary stepped laminate 220 .

Referring to FIG. 34E , the filling insulating layer 420 and the preliminary stepped laminate 220 may be etched to define the first preliminary slit SI1 and the plurality of contact holes HB". The first preliminary slit may be etched. While forming (SI1) and the plurality of contact holes HB", the second semiconductor pattern 111A of the cell region CAR" and the plurality of lower contacts 403A of the contact region CTR" are etched. It can be used as a stop film. Since the plurality of contact holes HB" are defined using the first preliminary slit SI1 forming process, the manufacturing method of the semiconductor memory device can be simplified.

The first preliminary slit SI1 may pass through the filling insulating layer 420 and the preliminary stepped stack 220 in the cell region CAR". The first preliminary slit SI1 may include a plurality of sacrificial layers SC. ) may pass through the plurality of base portions SB. The plurality of contact holes HB" form the filling insulating layer 420 in the contact region CTR" to expose the plurality of lower contacts 403A, respectively. and the preliminary stepped laminate 220. Each of the plurality of edge portions SE of the plurality of sacrificial layers SC may be penetrated by a plurality of contact holes HB".

Referring to FIG. 34F , a first upper passivation layer 431 may be formed on the filling insulating layer 420 . To define the void 433 in the central region of each of the first preliminary slit SI1 and the plurality of contact holes HB", the first upper passivation layer 431 is formed by using a deposition method with low step coverage. can be formed

Referring to FIG. 34G , a portion of the first upper passivation layer 431 overlapping the contact region CTR" of the stepped stack 220 may be removed. As a result, the plurality of contact holes HB" may be formed. The plurality of edge portions SE of the plurality of sacrificial layers SC may be exposed through the plurality of contact holes HB″.

Referring to FIG. 34H , as described with reference to FIGS. 14A and 14B , a plurality of first recess regions ( 231) and a plurality of second recess regions 233 may be defined.

Each of the first recess regions 231 may be defined in a region where the edge SE of the sacrificial layer SC shown in FIG. 34G is removed. Each of the second recess regions 233 may be defined in an area where a portion of the base portion SB of the sacrificial layer SC disposed below the edge portion SE shown in FIG. 34G is removed.

Subsequently, the sacrificial pad 241P may be formed inside the first recess region 231 by using the processes described with reference to FIGS. 15A and 15B and the processes described with reference to FIGS. 16A and 16B .

Referring to FIG. 34I , a contact insulating layer 441 may be formed along the surface of the contact hole HB″. The contact insulating layer 441 may fill the second recess region 233. The contact insulating layer 441 may fill the second recess region 233. The central region of ") may be open without being filled by the contact insulating layer 441 . The contact insulating layer 441 may extend along the surface of the filling insulating layer 420 in the contact region CTR" and may extend along the top surface of the first upper protective layer 431 in the cell region CAR". The contact insulating layer 441 may be formed of a material having etch selectivity with respect to the sacrificial layer SC. As an example, the contact insulating layer 441 may include an oxide layer.

Subsequently, a liner layer 443 may be formed on the contact insulating layer 441 . The liner layer 443 may include a material having etch selectivity with respect to the contact insulating layer 441 . As an example, the liner film 443 may include silicon. A central region of the contact hole HB″ may be opened without being filled with the liner layer 443 .

Referring to FIG. 34J , a second upper protective layer 445 may be formed on the liner layer 443 . The second upper passivation layer 445 may be formed using a deposition method with low step coverage so that the void 451 may be defined in the central region of each of the plurality of contact holes HB".

Referring to FIG. 34K , portions of each of the second upper protective layer 445, the liner layer 443, and the contact insulating layer 441 overlapping the cell region CAR" of the stepped stack 220 may be removed. Subsequently, a portion of the first upper passivation layer 431 may be removed to open the first preliminary slit SI1. To this end, the cell region CAR" of the stepped stack 220 is opened, and the contact A mask pattern (not shown) blocking the region CTR" may be used as an etch barrier. After opening the preliminary slit SI1, the mask pattern may be removed.

Referring to FIG. 34L , the plurality of sacrificial films SC and the plurality of sacrificial pads 241P of the preliminary stepped laminate 220 shown in FIG. 34K may be removed through the first preliminary slit SI1. there is. Thus, as shown in FIGS. 24A and 24B , a plurality of gate regions 275 may be defined. At this time, the contact insulating film 441 and the liner film 443 remaining inside the plurality of contact holes HB" are a support structure stably maintaining a gap between adjacent interlayer insulating films IL in the Z-axis direction. The contact insulating layer 441 of the support structure may extend between adjacent interlayer insulating layers IL.

After that, as described with reference to FIGS. 25A and 25B , the second blocking insulating layer 161 and the plurality of conductive patterns CP may be formed. As described with reference to FIGS. 25A and 25B , each conductive pattern CP may be exposed by the first opening OP1 of the second blocking insulating layer 161 . As described with reference to FIGS. 25A and 25B , each conductive pattern CP may include a base portion CB and an edge portion CE having a thickness smaller than that of the base portion CB. The base part CB may cover the channel structure CH and the memory pattern 151A.

Referring to FIG. 34M , as described with reference to FIG. 26 , the slit SI may be defined by forming the second preliminary slit SI2 penetrating the second semiconductor pattern 111A. Subsequently, as described with reference to FIG. 27, after forming the sidewall insulating film 171 on the sidewall of the slit SI, the preliminary horizontal pattern 200A shown in FIG. 34L and the memory pattern 151A shown in FIG. 34L part of can be removed. Thus, the horizontal space 275 may be opened, and the first memory pattern 151P1 and the second memory pattern 151P2 may be separated from each other by the horizontal space 275 . In addition, sidewalls of the cell channel layer 153A may be exposed by the horizontal space 275 .

Thereafter, as described with reference to FIGS. 28A and 28B , the doped semiconductor film 173 may be formed to fill the horizontal space 275 and the slit SI. The doped semiconductor layer 173 may extend to cover the first upper passivation layer 431 and the second upper passivation layer 445 .

Referring to FIG. 34N , a portion of the doped semiconductor film 173 is formed by an etching process using a mask pattern (not shown) that blocks the contact region CTR" and opens the cell region CAR" as an etch barrier. And the second upper protective layer 445 and the liner layer 443 shown in FIG. 34M may be sequentially removed. Subsequently, a portion of the second blocking insulating layer 161 may be exposed by removing a portion of the contact insulating layer 441 shown in FIG. 34M through an etching process such as an etch-back. At this time, a part of the second blocking insulating layer 161 facing the sidewall of the contact hole HB" shown in FIG. 34M may be exposed, and the contact insulating layer 441 between the interlayer insulating layers IL shown in FIG. 34M ) may remain as the contact insulating pattern 441P in the second recess region. In addition, a plurality of contact holes HB" may be opened.

After that, as described with reference to FIGS. 30A and 30B , the second opening OP2 may be defined by removing a portion of the second blocking insulating layer 161 . The edge portion CE of the conductive pattern CP may be exposed by the second opening OP2 of the second blocking insulating layer 161 . The mask pattern may be removed after forming the second opening OP2 .

Referring to FIG. 34O , after filling the plurality of contact holes HB″ shown in FIG. 34M with a conductive material, a planarization process may be performed to expose the filling insulating layer 420. Thus, the plurality of lower contacts A plurality of conductive gate contacts 181A respectively connected to 403A may be formed. In the contact region CTR", the second semiconductor pattern 111B, the preliminary contact structure 200B, and the first semiconductor pattern 105B ) may remain to surround each lower contact 403A.

The doped semiconductor layer 173 shown in FIG. 34M may remain as the common source pattern CSL by the planarization process described above. As described with reference to FIG. 32A , the common source pattern CSL may be divided into a horizontal doped semiconductor pattern 173H and a conductive vertical contact 173VC, and may contact the cell channel layer 153A.

Next, subsequent processes for forming the upper insulating layer UI, the bit line contact 193A, the upper contact 193B, the bit line BL, and the upper wiring UL shown in FIGS. 3A, 3B, and 3C are performed. can be done

34A to 34M describe an embodiment of a method for manufacturing a conductive pattern CP including a base portion CB and an edge portion CE having a thickness smaller than that of the base portion CB, but the present invention Examples are not limited thereto. As another embodiment, using the process shown in FIGS. 33A to 33J , the edge portion of the conductive pattern may be formed to be thicker than the base portion of the conductive pattern.

35 is a block diagram showing the configuration of a memory system according to an embodiment of the present invention.

Referring to FIG. 35 , a memory system 1100 includes a memory device 1120 and a memory controller 1110 .

The memory device 1120 may be a multi-chip package including a plurality of flash memory chips. The memory device 1120 may include a plurality of conductive patterns stacked in a stepped shape, and a conductive gate contact passing through and contacting an edge of one of the plurality of conductive patterns. The plurality of conductive patterns may include a lower conductive pattern disposed under an edge portion of the conductive pattern contacting the conductive gate contact, and the conductive gate contact may pass through the lower conductive pattern. The conductive gate contact may be insulated from the lower conductive pattern by the contact insulation pattern. Also, the memory device 1120 may include a horizontally doped semiconductor pattern disposed under the plurality of conductive patterns and a cell channel layer connected to the horizontally doped semiconductor pattern and extended to be surrounded by the plurality of conductive patterns. The conductive gate contact may extend to a level where the horizontally doped semiconductor pattern is disposed, and may have a groove in which a passivation layer is inserted at a level where the horizontally doped semiconductor pattern is disposed. Alternatively, the conductive gate contact may be extended to contact a lower contact extending at a level where the horizontally doped semiconductor pattern is disposed.

The memory controller 1110 is configured to control the memory device 1120, and includes a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, and an error correction block. block) 1114 and a memory interface 1115. The SRAM 1111 is used as an operating memory of the CPU 1112, the CPU 1112 performs various control operations for data exchange of the memory controller 1110, and the host interface 1113 is connected to the memory system 1100. It is equipped with the data exchange protocol of the host being used. The error correction block 1114 detects an error included in data read from the memory device 1120 and corrects the detected error. The memory interface 1115 performs interfacing with the memory device 1120 . The memory controller 1110 may further include a read only memory (ROM) for storing code data for interfacing with a host.

The above-described memory system 1100 may be a memory card or a solid state drive (SSD) in which the memory device 1120 and the memory controller 1110 are combined. For example, when the memory system 1100 is an SSD, the memory controller 1110 may include Universal Serial Bus (USB), MultiMedia Card (MMC), Peripheral Component Interconnection-Express (PCI-E), and Serial Advanced Technology Attachment (SATA). ), Parallel Advanced Technology Attachment (PATA), Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), etc. can communicate with

36 is a block diagram showing the configuration of a computing system according to an embodiment of the present invention.

Referring to FIG. 36 , a computing system 1200 includes a CPU 1220 electrically connected to a system bus 1260, a random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210. ) may be included. When the computing system 1200 is a mobile device, a battery for supplying an operating voltage to the computing system 1200 may be further included, and an application chipset, an image processor, a mobile DRAM, and the like may be further included.

The memory system 1210 may include a memory device 1212 and a memory controller 1211 .

The memory device 1212 may have the same configuration as the memory device 1120 described with reference to FIG. 35 .

181A: conductive gate contact 181B: dummy contact
141, 441P: contact insulation pattern UI: upper insulation layer
CP: Conductive pattern CSL: Common source pattern
CE: edge portion of conductive pattern CB: base portion of conductive pattern
CPL: cell plug 151: memory film
153: channel film 153A: cell channel film
155A: core insulation pattern 155B, 155C: dummy core insulation pattern
157: capping pattern IL: interlayer insulating film
161: blocking insulating film OP1, OP2, OP2': opening
ST: stepped laminate 220, 320: preliminary stepped laminate
CAR, CAR": cell area CTR, CTR', CTR": contact area
ER: extended area SI: slit
171: sidewall insulating film 173VC: conductive vertical contact
173H: horizontal doped semiconductor pattern 193A: bit line contact
193B: upper contact BL: bit line
UL: top wiring 107, 109: protective film
131, 420: filling insulating film 201: preliminary horizontal film
200A: preliminary horizontal pattern 200B: preliminary contact structure
200C: preliminary dummy structure 173: doped semiconductor film
150 [1], 150 [2]: support structure SC, SC': sacrificial film
SE, SE': Edge portion of the sacrificial film SB, SB': Base portion of the sacrificial film
HA, HA": channel hole HB, HB', HB": contact hole
HC: dummy hole 241P, 303, 331: sacrificial pad
231, 233, 311, 313: recess area 273, 433, 451: void
271, 431, 445: upper passivation layer 275, 375: gate region

Claims (42)

a first conductive gate contact;
a first contact insulation pattern surrounding the first conductive gate contact;
a first conductive pattern surrounding the first contact insulating pattern;
a second conductive pattern disposed on the first conductive pattern and surrounding the first conductive gate contact; and
A cell plug penetrating the first conductive pattern and the second conductive pattern;
The second conductive pattern,
a first edge portion overlapping the first contact insulating pattern and contacting the first conductive gate contact; and
and a first base portion that extends from the first edge portion toward the cell plug and is thicker than the first edge portion. According to claim 1,
The first conductive pattern,
a second base portion overlapping the first edge portion of the second conductive pattern and thicker than the first edge portion; and
and a second edge portion extending from the second base portion and thinner than the second base portion. According to claim 2,
and a second conductive gate contact surrounded by the second edge portion of the first conductive pattern and having a sidewall contacting the second edge portion. According to claim 1,
an interlayer insulating film between the first conductive pattern and the second conductive pattern;
a sidewall insulating layer extending along sidewalls of the first conductive pattern, the second conductive pattern, and the interlayer insulating layer;
a conductive vertical contact on the sidewall insulating layer; and
The semiconductor memory device further comprising a blocking insulating layer extending along surfaces of each of the first conductive pattern and the second conductive pattern. According to claim 4,
The blocking insulating layer includes a first opening facing the sidewall insulating layer and a second opening facing the first conductive gate contact;
The second opening is formed to be narrower than the first opening. According to claim 1,
a dummy contact penetrating the first conductive pattern and the second conductive pattern;
a second contact insulating pattern disposed between at least one of the first conductive pattern and the second conductive pattern and the dummy contact; and
The semiconductor memory device further comprising an upper insulating layer blocking an upper surface of the dummy contact. horizontally doped semiconductor patterns;
A staircase including a plurality of interlayer insulating films and a plurality of conductive patterns alternately stacked on the horizontally doped semiconductor pattern, and including a cell region overlapping the horizontally doped semiconductor pattern and a contact region extending from the cell region. mold laminate;
a cell channel film connected to the horizontally doped semiconductor pattern and penetrating the cell region of the stepped stack;
a plurality of conductive gate contacts penetrating the contact region of the stepped stack and extending to a level at which the horizontally doped semiconductor pattern is disposed; and
A semiconductor memory device comprising a passivation layer penetrating sidewalls of each of the conductive gate contacts. According to claim 7,
The plurality of conductive gate contacts include a first conductive gate contact and a second conductive gate contact spaced apart from each other;
The plurality of conductive patterns,
a first conductive pattern surrounding the first conductive gate contact and the second conductive gate contact; and
A semiconductor memory device comprising a second conductive pattern disposed on the first conductive pattern and spaced apart from the second conductive gate contact. According to claim 8,
The second conductive pattern includes a first edge portion surrounding the first conductive gate contact and a first base portion extending from the first edge portion toward the cell channel layer;
The first conductive pattern may include a second base portion overlapping the first edge portion of the second conductive pattern and surrounding the first conductive gate contact, and surrounding the second conductive gate contact from the second base portion. Including an extended second edge portion,
The first edge portion of the second conductive pattern has a sidewall in contact with the first conductive gate contact;
The semiconductor memory device of claim 1 , wherein the second edge portion of the first conductive pattern has a sidewall contacting the second conductive gate contact. According to claim 9,
The semiconductor memory device of claim 1 , wherein the first edge portion and the second edge portion are thinner than the first base portion and the second base portion. According to claim 9,
The first edge portion and the second edge portion are formed to be thicker than the first base portion and the second base portion. According to claim 9,
The semiconductor memory device further comprising a contact insulation pattern disposed between the first conductive pattern and the first conductive gate contact. According to claim 7,
a conductive vertical contact extending from the horizontally doped semiconductor pattern in parallel to the cell channel layer;
a side wall insulating layer between the conductive vertical contact and the stepped laminate; and
Further comprising a blocking insulating film extending along the surface of each of the plurality of conductive patterns,
The blocking insulating layer includes a first opening facing the sidewall insulating layer and a second opening facing a corresponding one of the plurality of conductive gate contacts. According to claim 13,
The semiconductor memory device of claim 1 , wherein a width of the second opening is narrower than a width of the first opening. According to claim 13,
The semiconductor memory device of claim 1 , wherein a width of the second opening is greater than a width of the first opening. According to claim 7,
The stepped stacked body further includes an extension region extending from the contact region. 17. The method of claim 16,
a plurality of upper contacts connected to the plurality of conductive gate contacts;
a plurality of upper wires connected to the upper contacts;
a plurality of dummy contacts penetrating the extension region of the stepped stack and extending to a level where the horizontally doped semiconductor pattern is disposed; and
and an upper insulating layer filling between the plurality of upper contacts and between the plurality of upper wires and covering the plurality of dummy contacts. a stepped laminate including a plurality of alternately stacked interlayer insulating films and a plurality of conductive patterns, and including a cell region and a contact region extending from the cell region;
a horizontally doped semiconductor pattern disposed under the cell region of the stepped stack;
a lower insulating layer disposed below the contact region of the stepped stack at a level where the horizontally doped semiconductor pattern is disposed;
a plurality of lower contacts penetrating the lower insulating layer;
a cell channel film connected to the horizontally doped semiconductor pattern and penetrating the cell region of the stepped stack; and
and a plurality of conductive gate contacts connected to the plurality of lower contacts and penetrating the contact region of the stepped stack. According to claim 18,
a first passivation layer, a preliminary horizontal layer, and a second passivation layer that surround each of the lower contacts and are sequentially stacked between each of the lower contacts and the lower insulating layer;
a first semiconductor pattern disposed under the first passivation layer and surrounding each of the lower contacts; and
The semiconductor memory device further comprises a second semiconductor pattern disposed on the second passivation layer and surrounding each of the lower contacts. According to claim 18,
The plurality of conductive gate contacts include a first conductive gate contact and a second conductive gate contact spaced apart from each other;
The plurality of conductive patterns,
a first conductive pattern surrounding the first conductive gate contact and the second conductive gate contact; and
A semiconductor memory device comprising a second conductive pattern disposed on the first conductive pattern and spaced apart from the second conductive gate contact. 21. The method of claim 20,
The second conductive pattern includes a first edge portion surrounding the first conductive gate contact and a first base portion extending from the first edge portion toward the cell channel layer;
The first conductive pattern may include a second base portion overlapping the first edge portion of the second conductive pattern and surrounding the first conductive gate contact, and surrounding the second conductive gate contact from the second base portion. Including an extended second edge portion,
The first edge portion of the second conductive pattern has a sidewall in contact with the first conductive gate contact;
The semiconductor memory device of claim 1 , wherein the second edge portion of the first conductive pattern has a sidewall contacting the second conductive gate contact. According to claim 21,
The semiconductor memory device of claim 1 , wherein the first edge portion and the second edge portion have different thicknesses from those of the first base portion and the second base portion. Including a lower interlayer insulating film, an intermediate interlayer insulating film, an upper interlayer insulating film, a lower base portion between the lower interlayer insulating film and the middle interlayer insulating film, and a lower edge portion that protrudes laterally from the lower base portion than the middle interlayer insulating film and is thinner than the lower base a lower sacrificial film, and an upper base portion between the intermediate interlayer insulating film and the upper interlayer insulating film, and an upper edge portion protruding from the upper base portion to the side of the upper interlayer insulating film and thinner than the upper base portion. forming a sieve;
forming a filling insulating film covering the preliminary stepped laminate;
forming a contact hole penetrating the filling insulating layer, the upper edge portion, the middle interlayer insulating layer, the lower base portion, and the lower interlayer insulating layer;
replacing the upper edge portion with a sacrificial pad through the contact hole;
replacing a part of the lower base portion with a contact insulation pattern through the contact hole; and
and forming a support structure surrounded by the contact insulating pattern and the sacrificial pad inside the contact hole. 24. The method of claim 23,
forming a channel hole penetrating the upper interlayer insulating film, the upper base portion, the middle interlayer insulating film, the lower base portion, and the lower interlayer insulating film;
forming a memory film along the surface of the channel hole;
forming a channel film along the surface of the memory film; and
The method of manufacturing a semiconductor memory device further comprising filling a central region of the channel hole with a core insulating pattern and a capping pattern on the core insulating pattern. 25. The method of claim 24,
The method of claim 1 , wherein the support structure includes the memory layer and the channel layer extending into the contact hole, and a dummy core insulating pattern disposed on the channel layer inside the contact hole. 26. The method of claim 25,
forming an upper protective layer covering the support structure and the capping pattern to define a void inside the contact hole;
forming a slit penetrating the upper passivation layer, the upper insulating interlayer, the upper base portion, the middle interlayer insulating layer, the lower base portion, and the lower interlayer insulating layer;
removing the lower sacrificial layer, the upper sacrificial layer, and the sacrificial pad through the slit to expose the support structure and the contact insulating pattern;
forming a blocking insulating layer along surfaces of each of the lower gate region from which the lower sacrificial layer is removed and the upper gate region from which the upper sacrificial layer and the sacrificial pad are removed; and
The method of manufacturing the semiconductor memory device further comprising filling a central region of each of the lower gate region and the upper gate region with a conductive pattern. 27. The method of claim 26,
exposing a portion of the blocking insulating layer and the contact insulating pattern by removing the support structure;
removing an exposed region of the blocking insulating layer to expose an edge portion of the conductive pattern overlapping the contact insulating pattern; and
and filling a region from which the support structure is removed with a conductive gate contact so as to contact the edge portion of the conductive pattern. Forming a lower laminate in which a preliminary horizontal film and a protective film are stacked;
Separating the lower laminate into a preliminary horizontal pattern and a preliminary contact structure;
forming a preliminary stepped stack including a lower interlayer insulating layer, a lower sacrificial layer, a middle interlayer insulating layer, an upper sacrificial layer, and an upper interlayer insulating layer sequentially stacked on the preliminary horizontal pattern and the preliminary contact structure;
forming a support structure penetrating the preliminary stepped laminate and extending into the preliminary contact structure;
replacing each of the lower sacrificial layer and the upper sacrificial layer with a conductive pattern; and
and replacing the preliminary horizontal film and the support structure of the preliminary contact structure with a conductive gate contact. 29. The method of claim 28,
The method of manufacturing a semiconductor memory device according to claim 1 , wherein the passivation layer of the lower stacked body remains inside the conductive gate contact. 29. The method of claim 28,
The lower sacrificial layer includes a lower base portion between the lower interlayer insulating layer and the intermediate interlayer insulating layer, and a lower edge portion protruding from the lower base portion to a side of the intermediate interlayer insulating layer,
The upper sacrificial layer includes an upper base portion between the middle interlayer insulating layer and the upper interlayer insulating layer, and an upper edge portion protruding from the upper base portion to a side than the upper interlayer insulating layer. Method of manufacturing a semiconductor memory device. 31. The method of claim 30,
The method of claim 1 , wherein the lower edge portion is thinner than the lower base portion, and the upper edge portion is formed to be thinner than the upper base portion. 32. The method of claim 31,
Forming the support structure,
forming contact holes penetrating the upper edge portion, the intermediate interlayer insulating layer, the lower base portion, and the lower interlayer insulating layer;
removing a portion of the lower base portion and the upper edge portion through the contact hole;
forming a sacrificial pad filling the first recessed area from which the upper edge portion was removed;
forming a contact insulation pattern filling a second recessed area from which a portion of the lower base portion is removed;
forming a memory layer along a sidewall of the contact hole to cover sidewalls of each of the sacrificial pad and the contact insulating pattern;
forming a channel film along the surface of the memory film; and
and forming a dummy core insulating pattern on the channel layer. 33. The method of claim 32,
The step of replacing each of the lower sacrificial layer and the upper sacrificial layer with the conductive pattern,
forming an upper protective layer covering the support structure to define a void inside the contact hole;
forming a slit through the upper passivation layer, the upper interlayer insulating layer, the upper base portion of the upper sacrificial layer, the middle interlayer insulating layer, the lower base portion of the lower sacrificial layer, and the lower interlayer insulating layer;
removing the lower sacrificial layer, the upper sacrificial layer, and the sacrificial pad through the slit to expose the support structure and the contact insulating pattern;
forming a blocking insulating layer along surfaces of each of the lower gate region from which the lower sacrificial layer is removed and the upper gate region from which the upper sacrificial layer and the sacrificial pad are removed; and
and filling a central region of each of the lower gate region and the upper gate region with a first conductive material. 34. The method of claim 33,
The step of replacing the preliminary horizontal film and the support structure of the preliminary contact structure with the conductive gate contact,
exposing a portion of the blocking insulating layer and the contact insulating pattern by removing the support structure;
removing a portion of the blocking insulating layer to expose an edge portion of the conductive pattern overlapping the contact insulating pattern; and
and filling a region from which the support structure is removed with a second conductive material so as to come into contact with an edge portion of the conductive pattern. 31. The method of claim 30,
The method of manufacturing a semiconductor memory device further comprising forming a first sacrificial pad on the upper edge portion. 36. The method of claim 35,
Forming the support structure,
forming contact holes penetrating the first sacrificial pad, the upper edge portion, the middle interlayer insulating layer, the upper base portion, and the lower interlayer insulating layer;
removing a portion of the lower base portion, the upper edge portion, and the first sacrificial pad through the contact hole;
forming a second sacrificial pad filling the upper edge portion and the first recessed area from which the first sacrificial pad is removed;
forming a contact insulation pattern filling a second recessed area from which a portion of the lower base portion is removed;
forming a memory layer along a sidewall of the contact hole to cover each sidewall of the second sacrificial pad and the contact insulating pattern;
forming a channel film along the surface of the memory film; and
and forming a dummy core insulating pattern on the channel layer. 37. The method of claim 36,
The step of replacing each of the lower sacrificial layer and the upper sacrificial layer with the conductive pattern,
forming an upper protective layer covering the support structure to define a void inside the contact hole;
removing the lower sacrificial layer, the upper sacrificial layer, and the second sacrificial pad to expose the support structure and the contact insulating pattern;
forming a blocking insulating layer along surfaces of each of the lower gate region from which the lower sacrificial layer is removed and the upper gate region from which the upper sacrificial layer and the second sacrificial pad are removed; and
and filling a central region of each of the lower gate region and the upper gate region with a first conductive material. 29. The method of claim 28,
forming a channel hole passing through the upper interlayer insulating film, the upper base portion, the middle interlayer insulating film, the lower base portion, and the lower interlayer insulating film and extending into the preliminary horizontal film of the preliminary horizontal pattern;
forming a memory film along the surface of the channel hole;
forming a channel film along the surface of the memory film;
filling a central region of the channel hole with a core insulating pattern and a capping pattern on the core insulating pattern;
forming a slit penetrating the preliminary stepped laminate and exposing the preliminary horizontal film of the preliminary horizontal pattern;
removing the preliminary horizontal layer of the preliminary horizontal pattern to expose a portion of the memory layer through the slit;
removing an exposed area of the memory layer to expose a portion of the channel layer; and
and filling a region from which the preliminary horizontal layer is removed with a doped semiconductor layer so as to contact the channel layer. Forming a lower laminate in which a preliminary horizontal film and a protective film are stacked;
Separating the lower laminate into a preliminary horizontal pattern and a preliminary contact structure;
forming a lower contact penetrating the preliminary contact structure;
forming a preliminary stepped laminate including a plurality of interlayer insulating films and a plurality of sacrificial films alternately stacked on a lower structure including the preliminary horizontal pattern, the preliminary contact structure, and the lower contact;
By etching the preliminary stepped laminate, a slit passing through the cell region of the preliminary stepped laminate overlapped with the preliminary horizontal film and a contact passing through the contact region of the preliminary stepped laminate overlapped with the lower contact forming a hole;
forming a support structure disposed inside the contact hole and extending between the interlayer insulating films;
replacing each of the sacrificial layers with a conductive pattern; and
and replacing a portion of the support structure inside the contact hole with a conductive gate contact connected to the lower contact. 40. The method of claim 39,
One of the plurality of sacrificial layers includes an edge portion overlapping the lower contact and a base portion extending from the edge portion toward a cell region of the preliminary stepped laminate and having a thickness different from that of the edge portion,
The method of manufacturing a semiconductor memory device in which the contact hole passes through the edge portion. 41. The method of claim 40,
Forming the support structure,
forming a first upper passivation film overlapping the cell region of the preliminary stepped laminate so as to define a void inside the slit;
removing a portion of a lower sacrificial layer overlapping the edge portion among the plurality of sacrificial layers and the edge portion through the contact hole;
filling the first recess area from which the edge portion is removed with a sacrificial pad;
forming a contact insulating layer along a sidewall of the contact hole to fill a second recess region in which the portion of the lower sacrificial layer is removed; and
A method of manufacturing a semiconductor memory device comprising forming a liner film on the contact insulating film. 42. The method of claim 41,
The step of replacing each of the sacrificial films with a conductive pattern,
forming a second upper passivation layer overlapping the contact area of the preliminary stepped laminate;
removing a portion of the first upper passivation layer to open the slit;
removing the plurality of sacrificial layers and the sacrificial pad through the slit; and
and filling each of the regions from which the plurality of sacrificial layers and the sacrificial pad are removed with a conductive material.

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