KR20220166003A - Integrated circuit device - Google Patents

Abstract

An integrated circuit device according to the technical idea of the present invention includes: a substrate; fin-type active regions spaced apart from each other in a first horizontal direction on the substrate and extended in a second horizontal direction perpendicular to the first horizontal direction; a dam structure extended in the second horizontal direction and alternately disposed with the fin-type active regions on the substrate; and a gate electrode extended in the first horizontal direction and intersecting the fin-type active region and the dam structure. A width where the gate electrode is in contact with the fin-type active region is greater than a width where the gate electrode is in contact with the dam structure.

Description

Integrated circuit device {INTEGRATED CIRCUIT DEVICE}

The technical field of the present invention relates to integrated circuit devices, and more particularly, to integrated circuit devices including fin-type active regions.

Recently, according to the trend of portability and high performance of electronic products, the demand for high integration of integrated circuit elements is increasing. There is a problem in that the reliability of the integrated circuit device is lowered because a short channel effect of the transistor occurs according to the downscaling of the integrated circuit device. In order to reduce this short-channel effect, an integrated circuit device including a fin-type active region has been proposed.

An object to be solved by the technical idea of the present invention is to provide an integrated circuit device including a gate electrode that provides reliable performance while having a reduced size as design rules decrease.

The problem to be solved by the technical idea of the present invention is not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

An integrated circuit device according to the technical idea of the present invention includes a substrate; fin-type active regions spaced apart from each other in a first horizontal direction on the substrate and extending in a second horizontal direction perpendicular to the first horizontal direction; dam structures disposed alternately with the fin-type active regions on the substrate and extending in the second horizontal direction; and a gate electrode that intersects the fin-type active region and the dam structure and extends in the first horizontal direction, wherein the contact width of the gate electrode with the fin-type active region is the contact width of the gate electrode with the dam structure wider than the width of

An integrated circuit device according to the technical concept of the present invention has an effect of increasing competitiveness of a product by including a gate electrode that provides reliable performance while having a reduced size as design rules decrease.

1A is a horizontal cross-sectional view illustrating an integrated circuit device according to an embodiment of the technical idea of the present invention, FIG. 1B is a vertical cross-sectional view taken along line BB′ of FIG. 1A, and FIG. 1C is an enlarged portion CC of FIG. 1A This is a partial magnification.
2 is a horizontal cross-sectional view illustrating an integrated circuit device according to another exemplary embodiment of the inventive concept.
3 is a block diagram showing a process sequence to explain a method of manufacturing an integrated circuit device according to an embodiment of the technical idea of the present invention.
Figure 4a, Figure 5a, ... , and FIG. 13a are plan views illustrating a manufacturing method of an integrated circuit device according to an embodiment of the present invention according to a process sequence, and FIGS. 4b, 5b, . . . , and FIG. 13B are respectively FIGS. 4A, 5A, . . . , and cross-sectional views taken along lines BB' of FIG. 13A.

Hereinafter, embodiments of the technical idea of the present invention will be described in detail with reference to the accompanying drawings.

1A is a horizontal cross-sectional view illustrating an integrated circuit device according to an embodiment of the technical idea of the present invention, FIG. 1B is a vertical cross-sectional view taken along line BB′ of FIG. 1A, and FIG. 1C is an enlarged portion CC of FIG. 1A. This is a partial magnification. Specifically, FIG. 1A is a horizontal cross-sectional view taken at the vertical level LV1 of FIG. 1B.

Referring to FIGS. 1A to 1C , the integrated circuit device 10 includes a substrate 101, a fin-type active region (FA), a device isolation film 110, a gate dielectric film 120, a dam structure 130, and a gate electrode. (140), and an inter-gate insulating film (150).

The substrate 101 may be a semiconductor wafer containing silicon (Si). In some embodiments, the substrate 101 may include a semiconductor element such as germanium (Ge) or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). It may be a wafer containing. Meanwhile, the substrate 101 may have a silicon on insulator (SOI) structure. In addition, the substrate 101 may include a conductive region, for example, a well doped with impurities or a structure doped with impurities.

The fin-type active region FA may protrude from the upper surface of the substrate 101 . The fin-type active regions FA are spaced apart from each other along a first horizontal direction (X direction) parallel to the upper surface of the substrate 101, and are spaced apart from each other in a second horizontal direction (Y direction) perpendicular to the first horizontal direction (X direction). ) can be extended along The width of the fin-type active region FA along the first horizontal direction (X direction) may gradually decrease as the distance from the upper surface of the substrate 101 in the vertical direction (Z direction) increases. That is, the fin-type active region FA may have a trapezoidal shape on the substrate 101 . The fin-type active region FA may be an active region constituting a pMOS transistor or an active region constituting an nMOS transistor.

The device isolation layer 110 may be disposed on the substrate 101 to cover lower portions of both sidewalls of the fin-type active region FA. Although not shown, an interface film may be further formed between the device isolation layer 110 and the fin-type active region FA to conformally cover sidewalls of the fin-type active region FA.

The gate dielectric layer 120 may be disposed on the device isolation layer 110 to cover the upper surface of the fin-type active region FA and upper portions of both sidewalls. The gate dielectric layer 120 may be disposed to extend along a first horizontal direction (X direction) on a bottom surface and a sidewall of a gate electrode 140 to be described later. In addition, the gate dielectric layer 120 may be interposed between the gate electrode 140 and the fin-type active region FA and between the gate electrode 140 and the upper surface of the device isolation layer 110 . The gate dielectric layer 120 may be formed of, for example, silicon oxide, silicon oxynitride, a high dielectric layer having a higher dielectric constant than silicon oxide, or a combination thereof. The high dielectric layer may be formed of a metal oxide or a metal oxynitride. For example, a high dielectric layer usable as the gate dielectric layer 120 may be HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, HfO ₂ -Al ₂ O ₃ alloys, or combinations thereof.

The dam structure 130 may be disposed between adjacent fin-type active regions FA. That is, the dam structures 130 may be spaced apart from each other along the first horizontal direction (X direction) and extend along the second horizontal direction (Y direction). The dam structure 130 may be disposed to contact one end of the lower portion of the gate electrode 140 . In addition, as the distance from the upper surface of the substrate 101 in the vertical direction (Z direction) increases, the width of the dam structure 130 in the first horizontal direction (X direction) may gradually increase. That is, the dam structure 130 may have an inverted trapezoidal shape on the substrate 101 . In addition, the level of the uppermost surface of the dam structure 130 is higher than the level of the uppermost surface of the fin-type active region FA, and the level of the lowermost surface of the dam structure 130 is the lowermost surface of the fin-type active region FA. may be higher than the level of The dam structure 130 may include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

The gate electrodes 140 may be spaced apart from each other along the second horizontal direction (Y direction) and extend along the first horizontal direction (X direction) so as to cross both the fin-type active region FA and the dam structure 130. there is. In some embodiments, the level of the uppermost surface of the gate electrode 140 is higher than the level of the uppermost surface of the dam structure 130, and the level of the lowermost surface of the gate electrode 140 is the lowermost surface of the dam structure 130. It may be substantially equal to the level of

The gate electrode 140 may include doped polysilicon, metal, or a combination thereof. For example, the gate electrode 140 may be made of Al, Cu, Ti, Ta, W, Mo, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, TiAlC, or a combination thereof. It may be made, but is not limited thereto.

In some embodiments, the gate electrode 140 may include a work function metal-containing layer and a gap-fill metal layer. The work function metal-containing layer may include at least one metal selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. The gap-fill metal layer may be made of tungsten (W) or aluminum (Al). In other embodiments, the gate electrode 140 has a stacked structure, such as a stacked structure of TiAlC/TiN/W, a stacked structure of TiN/TaN/TiAlC/TiN/W, or a stacked structure of TiN/TaN/TiN/TiAlC/TiN/ It may include a stacked structure of W.

In the integrated circuit device 10 of the present invention, when viewed in a horizontal cross-sectional view taken at the vertical level LV1, the gate electrode 140 is in contact with the fin-type active region FA along the second horizontal direction (Y direction). The first width 140A may be larger than the second width 140B along the second horizontal direction (Y direction) in which the gate electrode 140 contacts the dam structure 130 .

Specifically, the width of the gate electrode 140 along the second horizontal direction (Y direction) gradually decreases along the first horizontal direction (X direction) from the fin-type active region FA to the dam structure 130. can For example, when viewed from a plane, the gate electrode 140 disposed between the dam structures 130 facing each other may have an elliptical shape. Accordingly, the distance between the gate electrodes 140 facing each other in the second horizontal direction (Y direction) may be greater in the periphery of the dam structure 130 than in the periphery of the fin-type active region FA. As a result, parasitic capacitance at the periphery of the dam structure 130 may be effectively reduced.

An inter-gate insulating layer 150 may be disposed between adjacent gate electrodes 140 to cover a portion of the fin-type active region FA and source/drain regions (not shown). The inter-gate insulating layer 150 may include silicon nitride, silicon oxide, or silicon oxynitride.

Source/drain regions (not shown) may be disposed in the fin-type active region FA on both sides of the gate electrode 140 . The source/drain region may be formed of, for example, doped silicon germanium (SiGe), doped germanium (Ge), doped SiC, or doped InGaAs, but is not limited thereto.

Recently, with the trend of portability and high performance of electronic products, the demand for high integration of the integrated circuit device 10 is increasing. As the integrated circuit device 10 is down-scaled, a short channel effect of the transistor occurs, thereby reducing the reliability of the integrated circuit device 10 . In order to reduce this short-channel effect, an integrated circuit device 10 including a fin-type active region FA has been proposed.

In particular, in the integrated circuit device 10 of the present invention, the gate electrode 140 has a first width 140A in contact with the fin-type active region FA than a second width 140B in contact with the dam structure 130. By forming the contact structure larger, parasitic capacitance can be efficiently reduced, and a process margin can be further secured because a space in which a contact structure can be formed in a subsequent process is relatively large.

Ultimately, the integrated circuit device 10 of the present invention includes a gate electrode 140 that provides reliable performance while having a reduced size as the design rule decreases, thereby increasing the competitiveness of the product. there is

2 is a horizontal cross-sectional view illustrating an integrated circuit device according to another exemplary embodiment of the inventive concept.

Most of the components constituting the integrated circuit device 20 described below and materials constituting the components are substantially the same as or similar to those previously described with reference to FIGS. 1A to 1C. Therefore, for convenience of description, the description will focus on differences from the previously described integrated circuit device 10 .

Referring to FIG. 2 , the integrated circuit device 20 includes a substrate 101, a fin-type active region FA, a gate dielectric film 120, a dam structure 130, a gate electrode 240, and an inter-gate insulating film 150. ).

In the integrated circuit device 20 of the present invention, the gate electrodes 240 are spaced apart from each other along the second horizontal direction (Y direction) so as to cross the fin-type active region FA and the dam structure 130, and the first horizontal It may extend along the direction (X direction). In some embodiments, the level of the uppermost surface of the gate electrode 240 is higher than the level of the uppermost surface of the dam structure 130, and the level of the lowermost surface of the gate electrode 240 is the lowermost surface of the dam structure 130. It may be substantially equal to the level of In some embodiments, the gate electrode 240 may include a work function metal-containing layer and a gap-fill metal layer.

In the integrated circuit device 20 of the present invention, the width of the gate electrode 240 along the second horizontal direction (Y direction) is from the fin-type active region FA to the dam structure 130 in the first horizontal direction (X direction) can decrease linearly. For example, when viewed from a plan view, the shape of the gate electrode 240 disposed between the dam structures 130 facing each other may be a rectangle in which each corner portion is chamfered. Accordingly, the distance between the gate electrodes 240 facing each other in the second horizontal direction (Y direction) may be greater in the periphery of the dam structure 130 than in the periphery of the fin-type active region FA. As a result, parasitic capacitance at the periphery of the dam structure 130 may be effectively reduced.

3 is a block diagram showing a process sequence to explain a method of manufacturing an integrated circuit device according to an embodiment of the technical idea of the present invention.

The manufacturing method ( S10 ) of an integrated circuit device according to the technical idea of the present invention may include the following process sequence. When an embodiment is otherwise implementable, a specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously, or may be performed in an order reverse to the order described.

Referring to FIG. 3 , a first step of forming a first sacrificial layer on the fin-type active region (S110), a second step of forming a dam structure between the first sacrificial layer (S120), and etching a portion of the first sacrificial layer to A third step of forming a plurality of sacrificial holes (S130), a fourth step of forming a plurality of second sacrificial films to fill all of the plurality of sacrificial holes (S140), and a fifth step of removing the first sacrificial film and forming an inter-gate insulating film. Step S150, a sixth step of forming a third sacrificial film in a pattern and forming an interlayer insulating film therebetween (S160), and a seventh step of replacing the second and third sacrificial films with gate electrodes (S170). It shows a manufacturing method (S10) of the integrated circuit device including.

The technical characteristics of each of the first to seventh steps (S110 to S170) will be described in detail with reference to FIGS. 4A to 13B to be described later.

Figure 4a, Figure 5a, ... , and FIG. 13a are plan views illustrating a manufacturing method of an integrated circuit device according to an embodiment of the present invention according to a process sequence, and FIGS. 4b, 5b, . . . , and FIG. 13B are respectively FIGS. 4A, 5A, . . . , and cross-sectional views taken along lines BB' of FIG. 13A.

Referring to FIGS. 4A and 4B together, a fin-type active region FA may be formed on the substrate 101 .

The substrate 101 may be a semiconductor wafer. In some embodiments, the substrate 101 may include a logic cell region in which logic transistors constituting a logic circuit of an integrated circuit device are disposed. In other embodiments, the substrate 101 may include a memory cell region in which a plurality of memory cells for storing integrated circuit device data are formed.

A fin-type active region FA may be defined by patterning the substrate 101 . The fin-type active regions FA may be spaced apart from each other in a first horizontal direction (X direction) and may have a line shape extending in a second horizontal direction (Y direction). The fin-type active regions FA may be formed to be spaced apart from each other by substantially the same distance.

Next, an isolation layer 110 may be formed to fill a lower portion of the fin-type active region FA. The device isolation layer 110 may be formed to expose an upper portion of the fin-type active region FA.

Next, a gate dielectric layer 120 and a plurality of first sacrificial layers SL1 sequentially stacked on the substrate 101 may be formed. The gate dielectric layer 120 may include, for example, silicon oxide. The plurality of first sacrificial layers SL1 may include, for example, polysilicon. The plurality of first sacrificial layers SL1 may be formed by a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process.

Like the fin-type active region FA, the first sacrificial layer SL1 may have a line shape that is arranged to be spaced apart from each other in a first horizontal direction (X direction) and extends in a second horizontal direction (Y direction). there is. That is, the first sacrificial layer SL1 covers the upper surface and sidewalls of the fin-type active region FA and may extend onto the upper surface of the gate dielectric layer 120 .

Referring to FIGS. 5A and 5B together, a plurality of dam structures 130 extending while covering sidewalls of the plurality of first sacrificial films SL1 may be formed between the plurality of first sacrificial films SL1. there is.

The plurality of dam structures 130 may include, for example, silicon nitride. Alternatively, the plurality of dam structures 130 may include a low dielectric nitride such as SiCN or SiOCN. The plurality of dam structures 130 may be formed by a process such as CVD or PVD.

Next, a first photomask pattern PM1 may be formed on the plurality of first sacrificial layers SL1 and the plurality of dam structures 130 . The first photomask patterns PM1 may be spaced apart from each other in a second horizontal direction (Y direction) and may have a line-and-space shape extending in the first horizontal direction (X direction). The first photo mask pattern PM1 may include photoresist used for negative tone development.

In general, a photoresist used for negative tone development may be a chemically amplified photoresist material, an exposed portion (ie, a portion irradiated with light greater than a threshold amount of light) remains, and an unexposed portion (ie, A portion not irradiated with light equal to or greater than the threshold amount of light) may be removed by a solvent.

Referring to FIGS. 6A and 6B together, a portion of the first sacrificial layer SL1 is etched using the first photomask pattern PM1 (see FIG. 5A ) as an etch mask to form a plurality of sacrificial holes SLH. can do.

Anisotropic dry etching may be performed so that only a portion of the first sacrificial layer SL1 is etched using the etching selectivity. Since the dam structure 130 may have an inverted trapezoidal shape on the substrate 101 , etching residues may remain on the lower portion of the dam structure 130 in the anisotropic dry etching process. As a result, when viewed from a plan view, the etch width along the second horizontal direction (Y direction) may be narrowed in the periphery of the dam structure 130, unlike the periphery of the fin-type active region FA. Accordingly, each of the plurality of sacrificial holes SLH may have an elliptical shape.

Next, the first photomask pattern PM1 (refer to FIG. 5A ) may be completely removed using an ashing and stripping process.

Referring to FIGS. 7A and 7B together, a plurality of second sacrificial layers SL2 may be formed to fill all of the plurality of sacrificial holes SLH.

The plurality of second sacrificial layers SL2 may be formed of a material having an etch selectivity with respect to the first sacrificial layer SL1 . For example, the plurality of second sacrificial layers SL2 may be formed of polysilicon or a material containing carbon.

Referring to FIGS. 8A and 8B together, all of the first sacrificial layer SL1 (see FIG. 7A ) may be removed.

The first sacrificial layer SL1 (see FIG. 7A ) may be removed by a wet etching process using an etching solution.

Next, a portion of the gate dielectric layer 120 exposed by removing the first sacrificial layer SL1 (see FIG. 7A ) may be removed. As a result, an upper surface of the device isolation layer 110 may be exposed at a portion where the gate dielectric layer 120 is removed.

Referring to FIGS. 9A and 9B together, an inter-gate insulating layer 150 may be formed in a space created by removing the first sacrificial layer SL1 (see FIG. 7A ).

The inter-gate insulating layer 150 may be formed of a material having an etch selectivity with respect to the plurality of second sacrificial layers SL2 . For example, the inter-gate insulating layer 150 may include silicon nitride, silicon oxide, or silicon oxynitride.

Referring to FIGS. 10A and 10B together, a third sacrificial layer SL3 is formed to cover the upper surface of the dam structure 130, the upper surface of the inter-gate insulating layer 150, and the plurality of second sacrificial layers SL2. can form

The third sacrificial layer SL3 may be formed of substantially the same material as the plurality of second sacrificial layers SL2 . For example, the third sacrificial layer SL3 may be formed of polysilicon or a material containing carbon. Accordingly, the third sacrificial layer SL3 and the plurality of second sacrificial layers SL2 may constitute one body.

Referring to FIGS. 11A and 11B together, a second photo mask pattern PM2 may be formed on the third sacrificial layer SL3 .

The second photomask patterns PM2 may be spaced apart from each other in a second horizontal direction (Y direction) and may have a line-and-space shape extending in a first horizontal direction (X direction). Also, the second photo mask pattern PM2 may be formed to overlap the plurality of second sacrificial layers SL2 in a vertical direction (Z direction). The second photo mask pattern PM2 may include photoresist used for positive tone development.

Referring to FIGS. 12A and 12B together, a portion of the third sacrificial layer SL3 may be etched using the second photo mask pattern PM2 (see FIG. 11A ) as an etch mask.

According to the etching process, the third sacrificial layer SL3 may have a line-and-space pattern that is spaced apart from each other in a second horizontal direction (Y direction) and extends in a first horizontal direction (X direction). there is. Also, the third sacrificial layer SL3 may be formed to overlap the plurality of second sacrificial layers SL2 in a vertical direction (Z direction).

Next, the second photo mask pattern PM2 (refer to FIG. 11A ) may be completely removed using an ashing and stripping process.

Referring to FIGS. 13A and 13B together, an interlayer insulating layer 160 is formed around the third sacrificial layer SL3 (see FIG. 12A ) to cover the upper surface of the dam structure 130 and the upper surface of the inter-gate insulating layer 150. can do.

The interlayer insulating layer 160 may include silicon oxide, silicon nitride, silicon oxynitride, tetra ethyl ortho silicate (TEOS), or a low dielectric layer having a low dielectric constant.

Next, both the second sacrificial layer SL2 (see FIG. 12A) and the third sacrificial layer SL3 (see FIG. 12A) may be removed.

Next, the gate electrode 140 may be formed to fill all spaces created by removing the second sacrificial layer SL2 (see FIG. 12A) and the third sacrificial layer SL3 (see FIG. 12A). In some embodiments, the gate electrode 140 may be formed using a replacement metal gate (RMG) process. That is, by using the RMG process, the dummy gate formed of the second sacrificial layer SL2 (see FIG. 12A) and the third sacrificial layer SL3 (see FIG. 12A) is replaced with the gate electrode 140 including a metal material. can

The gate electrode 140 may be spaced apart from each other along a second horizontal direction (Y direction) and extend along a first horizontal direction (X direction) so as to intersect the fin-type active region FA and the dam structure 130. there is. In some embodiments, the level of the uppermost surface of the gate electrode 140 is higher than the level of the uppermost surface of the dam structure 130, and the level of the lowermost surface of the gate electrode 140 is the lowermost surface of the dam structure 130. It may be substantially equal to the level of In some embodiments, the gate electrode 140 may include a work function metal-containing layer and a gap-fill metal layer.

Through the manufacturing process described above, the integrated circuit device 10 according to an embodiment of the technical idea of the present invention can be completed.

In the above, the embodiments of the technical idea of the present invention have been described with reference to the accompanying drawings, but those skilled in the art to which the present invention pertains may change the technical idea or essential features of the present invention in other specific forms. It will be appreciated that this can be implemented. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

10, 20: integrated circuit element
101: substrate 110: device isolation film
120: gate dielectric film 130: dam structure
140: gate electrode 150: inter-gate insulating film
160: interlayer insulating film

Claims (10)

Board;
fin-type active regions spaced apart from each other in a first horizontal direction on the substrate and extending in a second horizontal direction perpendicular to the first horizontal direction;
dam structures disposed alternately with the fin-type active regions on the substrate and extending in the second horizontal direction; and
A gate electrode intersecting the fin-type active region and the dam structure and extending in the first horizontal direction;
A width at which the gate electrode contacts the fin-type active region is larger than a width at which the gate electrode contacts the dam structure.
integrated circuit element. According to claim 1,
The width of the gate electrode in the second horizontal direction,
An integrated circuit device according to claim 1 , characterized in that a gradual decrease along the first horizontal direction from the fin-shaped active region to the dam structure. According to claim 2,
The distance between the gate electrodes facing each other in the second horizontal direction,
The integrated circuit device, characterized in that larger at the periphery of the dam structure than at the periphery of the fin-type active region. According to claim 1,
The further away from the upper surface of the substrate in the vertical direction,
a width of the fin-shaped active region in the first horizontal direction gradually decreases;
The integrated circuit device, characterized in that the width of the first horizontal direction of the dam structure gradually increases. According to claim 4,
When viewed from a plane,
An integrated circuit device, characterized in that the shape of the gate electrode disposed between the dam structures facing each other is an elliptical shape. According to claim 1,
The level of the top surface of the fin-type active region is lower than the level of the top surface of the dam structure,
The integrated circuit device, characterized in that the level of the lowermost surface of the fin-type active region is lower than the level of the lowermost surface of the dam structure. According to claim 6,
The level of the top surface of the gate electrode is higher than the level of the top surface of the dam structure,
The level of the lowermost surface of the gate electrode is substantially the same as the level of the lowermost surface of the dam structure. According to claim 1,
The integrated circuit device, characterized in that the dam structure is composed of an insulating material. According to claim 1,
An integrated circuit device comprising source/drain regions disposed on both sides of the gate electrode. According to claim 1,
The integrated circuit device according to claim 1, wherein the gate electrode comprises a metal gate electrode.

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