KR20220162013A - Buffer circuit having offset blocking circuit and display device including the same - Google Patents

Abstract

A buffer circuit according to one aspect of a technical idea of the present disclosure comprises: an operation amplifier that amplifies an input voltage to generate an output voltage; a slew rate compensation circuit that generates a compensation current based on a difference of a voltage level of the input voltage and a voltage level of the output voltage, and provides the compensation current to the operation amplifier through a boosting transistor; and an offset blocking circuit that turns off the boosting transistor when the difference between the voltage level of the input voltage and the voltage level of the output voltage is less than a reference voltage level, by providing a blocking current to the slew rate compensation circuit. Therefore, the present invention is capable of providing the buffer circuit with an improved slew rate.

Description

A buffer circuit including an offset blocking circuit and a display device including the same

A buffer circuit including an offset blocking circuit and a display device including the same

Display devices used in electronic devices displaying images such as TVs, laptop computers, monitors and mobile devices include liquid crystal devices (LCDs) and organic light emitting devices (OLEDs). . In particular, since the liquid crystal display device is thinner and lighter than a cathode ray tube and has improved quality, it is widely used as an information processing device.

A display device may include a display panel having a plurality of pixels and a display driver for applying electrical signals to the plurality of pixels, and an image may be implemented by electrical signals provided to the plurality of pixels by the display driver. Recently, various studies have been conducted to improve the performance of display devices, such as resolution and slew rate.

An object to be solved by the technical idea of the present disclosure is to provide a buffer circuit that removes DC offset (OFFSET) and has an improved slew rate by including a slew rate compensation circuit and an offset blocking circuit.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description below.

In order to achieve the above object, a buffer circuit according to one aspect of the present disclosure provides an operational amplifier for generating an output voltage by amplifying an input voltage, and compensating current based on a difference between a voltage level of the input voltage and a voltage level of the output voltage. By generating and providing a blocking current to the slew rate compensation circuit and the slew rate compensation circuit for providing the compensating current to the operational amplifier through the boosting transistor, the difference between the voltage level of the input voltage and the voltage level of the output voltage is greater than the reference voltage level. It includes an offset blocking circuit that turns off the boosting transistor when small.

In order to achieve the above object, a display device according to one aspect of the present disclosure includes a display panel including a plurality of pixels formed at intersections of gate lines arranged in a row direction and source lines arranged in a column direction; A controller that generates a source control signal based on control signals received from the outside and converts the video data received from the outside, and converts the video data converted by the controller into a video signal in response to the source control signal received from the controller , a source driver providing video signals to source lines, the source driver comprising an operational amplifier generating an output voltage by amplifying an input voltage, and compensating based on a difference between a voltage level of the input voltage and a voltage level of the output voltage. By generating a current and providing a blocking current to the slew rate compensation circuit and the slew rate compensation circuit that provides the compensating current to the operational amplifier through the boosting transistor, the difference between the voltage level of the input voltage and the voltage level of the output voltage is the reference voltage level and a buffer circuit including an offset blocking circuit that turns off the boosting transistor when the voltage is less than

In order to achieve the above object, a method for controlling a buffer circuit according to an aspect of the present disclosure includes the steps of comparing a difference between an input voltage level and an output voltage level of an operational amplifier with a reference voltage level in a slew rate compensation circuit; generating a compensation current based on the difference between the input voltage level and the output voltage level in a slew rate compensation circuit and providing the compensation current to an operational amplifier when the difference between the input voltage level and the output voltage level is greater than the reference voltage level; and and turning off a boosting transistor of the slew rate compensation circuit by a blocking current provided to the slew rate compensation circuit by an offset blocking circuit when the difference between the level and the output voltage level is smaller than the reference voltage level.

According to the technical idea of the present disclosure, a buffer circuit having an improved slew rate and a DC offset OFFSET may be provided by including a slew rate compensation circuit and an offset blocking circuit.

According to the technical idea of the present disclosure, a buffer circuit with increased operating speed and reduced power consumption may be provided by generating a compensation current based on a difference between an input voltage level and an output voltage level.

Effects obtainable in the exemplary embodiments of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned are common knowledge in the art to which exemplary embodiments of the present disclosure belong from the following description. can be clearly derived and understood by those who have That is, unintended effects according to the implementation of the exemplary embodiments of the present disclosure may also be derived by those skilled in the art from the exemplary embodiments of the present disclosure.

1 is a block diagram of a buffer circuit according to exemplary embodiments of the present disclosure.
2 is a block diagram of a buffer circuit according to exemplary embodiments of the present disclosure.
3 is a circuit diagram of an operational amplifier according to exemplary embodiments of the present disclosure.
4 is a circuit diagram of a slew rate compensation circuit according to exemplary embodiments of the present disclosure.
5 is a circuit diagram of an offset blocking circuit according to exemplary embodiments of the present disclosure.
6 is a circuit diagram of an operational amplifier according to exemplary embodiments of the present disclosure.
7 is a circuit diagram of an operational amplifier according to exemplary embodiments of the present disclosure.
8 is a circuit diagram of a slew rate compensation circuit according to exemplary embodiments of the present disclosure.
9 is a circuit diagram of a slew rate compensation circuit according to exemplary embodiments of the present disclosure.
10 is a circuit diagram of a slew rate compensation circuit according to exemplary embodiments of the present disclosure.
11 is a circuit diagram of a slew rate compensation circuit according to exemplary embodiments of the present disclosure.
12 is a circuit diagram of a slew rate compensation circuit according to exemplary embodiments of the present disclosure.
13 is a circuit diagram of a slew rate compensation circuit according to exemplary embodiments of the present disclosure.
14 is a circuit diagram of an offset blocking circuit according to exemplary embodiments of the present disclosure.
15 is a diagram illustrating voltages measured at nodes of a buffer circuit according to exemplary embodiments of the present disclosure.
16 is a block diagram of a source driver including a buffer circuit according to exemplary embodiments of the present disclosure.
17 is a block diagram of a display device according to example embodiments of the present disclosure.
18 is a flowchart illustrating a method of operating a buffer circuit according to example embodiments of the present disclosure.

Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. In the drawings of this specification, only a part may be shown for convenience of illustration. When describing with reference to the drawings, the same or corresponding components are assigned the same reference numerals, and overlapping descriptions thereof will be omitted.

1 is a block diagram of a buffer circuit according to exemplary embodiments of the present disclosure.

Referring to FIG. 1 , the buffer circuit BF may include an operational amplifier 10 , a slew rate compensation circuit 20 and an offset blocking circuit 30 .

The operational amplifier 10 may amplify the voltage level of the input voltage VIN to generate the output voltage VOUT. The output voltage VOUT of the operational amplifier 10 may be input to an inverting input terminal of the operational amplifier 10 through a feedback loop. That is, the operational amplifier 10 may have a negative feedback structure in which an inverting input terminal and an output terminal are connected to each other. The operational amplifier 10 may have a rail-to-rail structure in which an input terminal has a dual structure.

The slew rate compensation circuit 20 may generate compensation currents I _PUSH and I _PULL based on a difference between the voltage level of the input voltage VIN and the voltage level of the output voltage VOUT. The slew rate compensation circuit 20 may generate compensation currents I _PUSH and I _PULL when the difference between the voltage level of the input voltage VIN and the voltage level of the output voltage VOUT is greater than the reference voltage level. The reference voltage level is the voltage level of the threshold voltage of the N-channel Field Effect Transistor (NFET) or the threshold voltage of the P-channel Field Effect Transistor (PFET) constituting the slew rate compensation circuit 20. can include The slew rate compensation circuit 20 may provide compensating currents I _PUSH and I _PULL to the operational amplifier 10 .

The offset blocking circuit 30 may generate a blocking current I _BLK based on the turn-on voltage V _ON provided from the operational amplifier 10 and convert the blocking current I _BLK to the slew rate compensation circuit 20 can be provided to The offset blocking circuit 30 may share a specific node with the operational amplifier 10 . The offset blocking circuit 30 may receive the turn-on voltage V _ON through the specific node. The voltage level of the turn-on voltage V _ON may be equal to or higher than the threshold voltage level of the transistors constituting the offset blocking circuit 30 . The specific node may be described as a 'push connection node' or a 'pull connection node' below, but is not limited thereto, and among the plurality of nodes of the operational amplifier 10, the transistors constituting the offset blocking circuit 30 Any node capable of providing a voltage equal to or greater than the threshold voltage level of the transistors constituting the offset blocking circuit 30 may correspond to the threshold voltage level.

The buffer circuit BF according to the present disclosure includes the offset blocking circuit 30 providing the blocking current I _BLK to the slew rate compensation circuit 20, thereby removing the DC offset and improving the slew rate. Hereinafter, the relationship between components of the operational amplifier 10 and the slew rate compensation circuit 20 and the offset blocking circuit 30 will be described in detail with reference to FIG. 2 .

2 is a block diagram of a buffer circuit according to exemplary embodiments of the present disclosure. In detail, FIG. 2 is a diagram for explaining the operational amplifier 10 of FIG. 1 in detail.

Referring to FIG. 2, the operational amplifier 10 includes an input stage 11, an upper bias circuit 12, a lower bias circuit 13, and a load stage 14. and an output stage (15).

The input terminal 11 may receive an input voltage VIN and an output voltage VOUT. The output voltage VOUT may be input to the input terminal 11 through a feedback loop. The input terminal 11 may compare the voltage level of the input voltage VIN and the voltage level of the output voltage VOUT. The input terminal 11 may include a first input terminal IS1 and a second input terminal IS2. The first input terminal IS1 may receive a pulling load current (I _PLLI , I _PLLO ) from the load terminal 14 , and the second input terminal IS2 may receive a push load from the load terminal 14 . Current (pushing load current, I _PSLI , I _PSLO ) can be received.

The upper bias circuit 12 and the lower bias circuit 13 may provide bias current required to drive the operational amplifier 10 . The upper bias circuit 12 and the lower bias circuit 13 may provide bias currents I _BU and I _BL to the input terminal 11 .

The load stage 14 may receive compensation currents I _PUSH and I _PULL provided from the slew rate compensation circuit 20 . The load stage 14 may perform a slew rate compensation operation using the compensation currents I _PUSH and I _PULL . The load stage 14 may generate load currents I _PSLI , I _PSLO , I _PLLI , and I _PLLO based on the difference between the voltage level of the input voltage VIN and the voltage level of the output voltage VOUT. The load stage 14 may generate load currents I _PSLI , I _PSLO , I _PLLI , _{and I PLLO using} the compensating currents I _PUSH and I PULL . The load terminal 14 may provide load currents I _PSLI , I _PSLO , I _PLLI , and I _PLLO to the input terminal 11 .

The load stage 14 may provide a turn-on voltage V _ON to the offset blocking circuit 30 . The load stage 14 may share a specific node with the offset blocking circuit 30 and the output stage 15 . A specific node may be described as a 'push connection node' and a 'pull connection node' with reference to FIG. 5 described later. However, it is not limited thereto, and the load stage 14 and the offset blocking circuit 30 have a voltage equal to or higher than the threshold voltage level of transistors included in the offset blocking circuit 30 among a plurality of nodes of the load stage 14. Nodes that can provide levels can be shared.

The output terminal 15 may be connected to the load terminal 14 . The output terminal 15 may be connected to the load terminal 14 through at least one of a 'push connection node' and a 'pull connection node'. That is, the load stage 14, the output stage 15, and the offset blocking circuit 30 may share at least one of a 'push connection node' and a 'pull connection node'. The output stage 15 can generate an output voltage by buffering the output signal of the load stage 14 . The output terminal 15 may output an output voltage to the outside of the buffer circuit BF.

Hereinafter, the operation of the buffer circuit BF will be described in detail with reference to a circuit diagram of the buffer circuit BF.

3 to 5 are circuit diagrams of buffer circuits according to exemplary embodiments of the present disclosure. In detail, FIG. 3 is a circuit diagram of the operational amplifier 10 of FIGS. 1 and 2 , FIG. 4 is a circuit diagram of the slew rate compensation circuit 20 of FIGS. 1 and 2 , and FIG. 5 is a circuit diagram of the operational amplifier 10 of FIGS. 1 and 2 . It is a circuit diagram of the offset blocking circuit 30 of Hereinafter, description will be made with reference to the aforementioned drawings.

Referring to Figure 3, The operational amplifier 10 may include an input stage 11 , an upper bias circuit 12 , a lower bias circuit 13 , a load stage 14 and an output stage 15 .

The input terminal 11 may have a rail-to-rail structure having a dual structure. The input terminal 11 may include a first input terminal IS1 connected to the transistors P1 and P2 and a second input terminal IS2 connected to the transistors N1 and N2. The first input terminal IS1 may receive the full load current I _PLLI and I _PLLO from the load terminal 14, and the second input terminal IS2 may receive the push load current I _PSLI from the load terminal 14. , I _PSLO ) can be received. 3 and below, since the push _load currents I _PSLI and I _PSLO flow from the input terminal 11 to the load terminal ₁₄ , the push load current I _PSLI , I _PSLO ) are shown in the direction of the load stage 14 .

The upper bias circuit 12 may provide a first bias current I _BU to the transistors P1 and P2 based on the first bias voltage VB1 . The upper bias circuit 12 may include a transistor P3 that is gated on the first bias voltage VB1 and provides the power supply voltage VDD to the input terminal 11 . Specifically, the drain terminal of the transistor P3 may be connected to the source terminals of the transistors P1 and P2 of the input terminal 11 .

The lower bias circuit 13 may provide the second bias current I _BL to the transistors N1 and N2 based on the second bias voltage VB2 . The lower bias circuit 13 may include a transistor N3 that connects the ground voltage and the input terminal 11 by being gated to the second bias voltage VB2 . Specifically, the drain terminal of the transistor N3 may be connected to the source terminals of the transistors N1 and N2 of the input terminal 11 .

The load stage 14 may include a push load circuit PS, a full load circuit PL, a connection circuit CC, a first capacitor C1 and a second capacitor C2.

The push load circuit PS is connected between transistors P4 and P5 connected in a current mirror form and between the transistors P4 and P5 and the connection circuit CC, and is connected to a third bias voltage VB3. It may include transistors P6 and P7 that operate in response.

The push load circuit PS may receive the push compensation current I _PUSH from the slew rate compensation circuit 20 through the first upper node NU1 . The push load circuit PS may generate push load currents I _PSLI and I _PSLO based on the push compensation current I _PUSH . The push load circuit PS may provide the push load currents I _PSLI and I _PSLO to the second input terminal IS2 through the drain terminal of the transistor P5 and the source terminal of the transistor P6, respectively.

The full load circuit PL is connected between the transistors N4 and PN connected in a current mirror form and between the transistors N4 and N5 and the connection circuit CC, and operates in response to the fourth bias voltage VB4. Transistors N6 and N7 may be included.

The full load circuit PL may receive the full compensation current I _PULL through the first lower node NL1 . The full load circuit PL may generate the full load currents I _PLLI and I _PLLO based on the pull compensation current I _PULL . The full load currents I _PLLI and I _PLLO may flow from the first input terminal IS1 to the drain terminal of the transistor N5 and the source terminal of the transistor N6.

The connection circuit CC may be disposed between the push load circuit PS and the pull load circuit PL. The connection circuit CC may electrically connect the second upper node NU2 of the push load circuit PS and the second lower node NL2 of the pull load circuit PL, and 3 The upper node NU3 and the third lower node NL3 of the full load circuit PL may be electrically connected. The third upper node NU3 of the push load circuit PS may be referred to as a 'push connection node', and the third lower node NL3 of the full load circuit PL may be referred to as a 'pull connection node'. have.

The connection circuit CC may include transistors P8, P9, N8, and N9, and the transistors P8, P9, N8, and N9 respond to fifth to eighth bias voltages VB5 to VB8, respectively. so it can work. The fifth to eighth bias voltages VB5 to VB8 may be the same as or different from each other. For example, the fifth to eighth bias voltages VB5 to VB8 may all have different voltage levels. In another embodiment, at least two of the fifth to eighth bias voltages VB5 to VB8 may have the same voltage level.

The first capacitor C1 may be connected between the first upper node NU1 and the output node NOUT of the push load circuit PS, and the second capacitor C2 may be connected to the first lower portion of the pull load circuit PL. It may be connected between the node NL1 and the output node NOUT.

The output stage 15 may include transistors P10 and N10. A gate of the transistor P10 may be connected to the third upper node NU3 of the push load circuit PS. One end of the transistor P10 is connected to the output node NOUT, and the power voltage VDD may be applied from the other end. A gate of the transistor N10 may be connected to the third lower node NL3 of the full load circuit PL. One end of the transistor N10 is connected to the output node NOUT, and a ground voltage may be applied from the other end.

In one embodiment according to the present disclosure, the transistors P1 to P10 may include PFETs, and the transistors N1 to N10 may include NFETs, but the present invention is not limited thereto.

Referring to FIG. 4 , the slew rate compensation circuit 20 may include a comparison circuit 21 , a pull compensation current circuit 22 and a push compensation current circuit 23 .

The comparator circuit 21 may receive an input voltage VIN and an output voltage VOUT. The comparison circuit 21 may include transistors N11 and P11 to which the input voltage VIN is applied to gates. An output voltage VOUT may be applied to the source terminal of the transistor N11 and the drain terminal of the transistor P11. The comparison circuit 21 may compare the voltage level of the input voltage VIN and the voltage level of the output voltage VOUT, and generate comparison currents I _DIFR and I _DIFF according to the comparison result. That is, the comparison currents I _DIFR and I _DIFF may be currents corresponding to the difference between the voltage level of the input voltage VIN and the voltage level of the output voltage VOUT.

When the difference between the voltage level of the input voltage (VIN) and the voltage level of the output voltage (VOUT) of the operational amplifier 10 is greater than the reference voltage level, and the magnitude of the input voltage (VIN) is greater than the magnitude of the output voltage (VOUT) , can be expressed as 'the input voltage (VIN) rises'. For example, when the input voltage VIN rises, the input voltage VIN may transition from a logical low level to a logical high level. The reference voltage level may be the threshold voltage level of the transistors N11 and P11.

When the input voltage VIN rises, the comparator circuit 21 turns on the transistor N11 and turns off the transistor P11. That is, the pull compensation current circuit 22 can be activated and the push compensation current circuit 23 can be deactivated. As the transistor N11 is turned on, the comparison circuit 21 may generate a rising comparison current I _DIFR .

In addition, the difference between the voltage level of the input voltage VIN and the output voltage VOUT of the operational amplifier 10 is greater than the reference voltage level, and the magnitude of the input voltage VIN is greater than the magnitude of the output voltage VOUT. When it is small, it can be expressed as 'the input voltage (VIN) is polling'. For example, when the input voltage VIN is polling, the input voltage VIN may transition from a logic high level to a logic low level.

When the input voltage VIN falls, the comparator circuit 21 can turn on the transistor P11 and turn off the transistor N11. That is, the pull compensation current circuit 22 may be inactivated and the push compensation current circuit 23 may be activated. As the transistor P11 is turned on, the comparison circuit 21 may generate a polling comparison current I _DIFF .

The full compensation current circuit 22 may perform a current mirror operation based on the rising comparison current I _DIFR . Accordingly, the pull compensation current circuit 22 may generate a pull compensation current (I _PULL ) and provide the pull compensation current (I _PULL ) to the operational amplifier 10 .

In detail, the full compensation current circuit 22 may include transistors P12, P13, N12, and N13. The transistors P12 and P13 may be connected in a current mirror form, and a power supply voltage VDD may be applied from one end. The transistors N12 and N13 may be connected in a current mirror form, and a ground voltage VSS may be applied from one end.

A drain node of the transistor P13, a drain node of the transistor N12, and gates of the transistors N12 and N13 may be connected. A node to which the drain node of the transistor P13, the drain node of the transistor N12, and the gates of the transistors N12 and N13 are connected may be referred to as a pulling node N _PULL . The transistor N13 may be referred to as a 'boosting transistor'.

The pull compensation current circuit 22 may output the pull compensation current I _PULL through the boosting transistor N13. Hereinafter, the pull compensation current (I _PULL ) is shown to flow from the first lower node NL1 to the transistor N13 according to the flow of current as shown in FIG. 4, but is not compensated by the operation of the pull compensation current circuit 22. Since the current I _PULL is generated, the pull compensation current circuit 22 can be described as outputting the full compensation current I _PULL . That is, the pull compensation current I _PULL from the pull compensation current circuit 22 may be supplied to the first lower node NL1 . Since the pull compensation current I _PULL flows from the first lower node NL1 to the boosting transistor N13, the pull compensation current circuit 22 sinks the pull compensation current I _PULL from the load terminal 14. ) can do.

The voltage level of the first lower node NL1 may be further lowered by the pull compensation current I _PULL . Therefore, the transistor N10 of the output terminal ( 15 in FIG. 3 ) can be quickly turned off by the pull compensation current I _PULL . That is, since the voltage level of the output voltage VOUT rapidly rises, the slew rate can be improved.

The push compensation current circuit 23 may perform a current mirror operation based on the polling comparison current I _DIFF . Accordingly, the push compensation current circuit 23 can generate the push compensation current I _PUSH and provide the push compensation current I _PUSH to the operational amplifier 10 .

In detail, the push compensation current circuit 23 may include transistors N14, N15, P14, and P15. Transistors N14 and N15 may be connected in a current mirror form, and a ground voltage VSS may be applied from one end. The transistors P14 and P15 may be connected in a current mirror form, and a power supply voltage VDD may be applied from one end.

A drain node of the transistor N15, a drain node of the transistor P14, and gates of the transistors P14 and P15 may be connected. A node to which the drain node of the transistor N15, the drain node of the transistor P14, and the gates of the transistors P14 and P15 are connected may be referred to as a push node N _PUSH . The transistor P15 may be referred to as a 'boosting transistor'.

The push compensation current circuit 23 may output the push compensation current I _PUSH through the boosting transistor P15. That is, the push compensation current I _PUSH from the push compensation current circuit 23 may be supplied to the first upper node NU1. Since the push compensation current I _PUSH flows from the boosting transistor P15 to the first upper node NU1, the push compensation current circuit 23 may supply the push compensation current I _PUSH to the load terminal 14. .

The voltage level of the first upper node NU1 may be further increased by the push compensation current I _PUSH . Therefore, the transistor P10 of the output terminal 15 can be quickly turned off by the push compensation current I _PUSH . That is, since the voltage level of the output voltage VOUT falls quickly, the slew rate can be improved.

In one embodiment according to the present disclosure, the transistors P11 to P15 may include PFETs, and the transistors N11 to N15 may include NFETs, but the present invention is not limited thereto.

Referring to Figure 5, The offset blocking circuit 30 may include a push blocking transistor P16 and a full blocking transistor N16.

A gate of the push blocking transistor P16 may be connected to the third upper node NU3 of the push load circuit PS. In other words, the gate of the push blocking transistor P16 may be connected to the push connection node. Accordingly, the push blocking transistor P16 may be operated by the voltage provided from the operational amplifier 10 . More specifically, the push blotting transistor P16 may be operated by a voltage provided from the load terminal 14 of the operational amplifier 10 .

The push blocking transistor P16 may be turned on according to the voltage of the third upper node NU3. That is, the voltage level of the third upper node NU3 may be a voltage level capable of turning on the push blocking transistor P16. The voltage level of the third upper node NU3 may be equal to or higher than the voltage level of the threshold voltage of the push blocking transistor P16. Accordingly, the push blocking transistor P16 may be turned on, and the push blocking current I _{BLK_PUSH} may be generated.

One end of the push blocking transistor P16 may be connected to the push node N _PUSH of the push compensation current circuit 23, and the power supply voltage VDD may be applied from the other end. As the push blocking transistor P16 is turned on by the voltage provided from the load terminal 14 , the push blocking current I _{BLK_PUSH} may flow to the push node N _PUSH . Accordingly, the push blocking transistor P16 may provide the push blocking current I _{BLK_PUSH} to the gates of the transistors P15 and P14 of the push compensation current circuit 23 .

When the input voltage VIN polls, and the difference between the voltage level of the input voltage VIN and the voltage level of the output voltage VOUT is greater than the threshold voltage of the transistor P11, the push compensation current circuit 23 compares the polling The push compensation current I _PUSH may be generated based on the current I _DIFF , and the push compensation current I _PUSH may be provided to the operational amplifier 10 . At this time, the push blocking current I _{BLK_PUSH} may be provided from the push blocking transistor P16 to the boosting transistor P15, but the boosting transistor P15 is turned on because the push compensation current I _PUSH is strongly generated. can keep

When the input voltage VIN polls and the difference between the voltage level of the input voltage VIN and the voltage level of the output voltage VOUT is smaller than the threshold voltage of the transistor P11, the push compensation current circuit 23 is deactivated. can Accordingly, since the push compensation current circuit 23 does not generate the polling comparison current I _DIFF , the push compensation current I _PUSH may not be generated either. At this time, since the push blocking current (I _{BLK_PUSH} ) can be provided to the boosting transistor P15 from the push blocking transistor P16, the gate voltage of the boosting transistor P15 rises and the boosting transistor P15 is turned off. state can be maintained. Therefore, even if leakage current is generated in the push compensation current circuit 23, the transistors P15 and P14 are turned off by the push blocking current I _{BLK_PUSH} , so that the first upper node NU1 of the push load circuit PS Leakage current flowing to can be removed. In addition, DC offset can be removed, the operating speed of the buffer circuit can be improved, and it can be driven with low power.

A gate of the full blocking transistor N16 may be connected to the third lower node NL3 of the full load circuit PL. In other words, the gate of the full blocking transistor N16 may be connected to the full connection node. Accordingly, the full blocking transistor N16 may be operated by the voltage provided from the operational amplifier 10 . More specifically, the full blocking transistor N16 may be operated by a voltage provided from the load terminal 14 of the operational amplifier 10 .

A gate of the full blocking transistor N16 may be turned on according to the voltage of the third lower node NL3. A voltage level of the third lower node NL3 may have a voltage level capable of turning on the full blocking transistor N16. That is, the voltage level of the third lower node NL3 may be equal to or higher than the threshold voltage of the blocking transistor N16 or higher than that of the full blocking transistor N16. Accordingly, the full blocking transistor N16 may be turned on, and a full blocking current I _{BLK_PULL} may be generated.

One end of the pull blocking transistor N16 may be connected to the full node N _PULL of the pull compensation current circuit 23, and the ground voltage VSS may be applied from the other end. As the full blocking transistor N16 is turned on by the voltage provided from the load terminal 14 , the full blocking current I _{BLK_PULL} may flow from the full node N _PULL . Accordingly, the full blocking current I _{BLK_PULL} may flow from the gates of the transistors N12 and N13 of the pull compensation current circuit 22 toward the full blocking transistor N16. In the following, including FIG. 5 , the full blocking current (I _{BLK_PULL} ) flows in the direction of the ground voltage (VSS) at the full node (N _PULL ) according to the flow of the full blocking current (I _{BLK_PULL} ), but the full blocking current (I _{BLK_PULL} ) is generated by the full blocking transistor N16 and thus affects the slew rate compensation circuit 20, so that the full blocking transistor N16 provides the full blocking current I _{BLK_PULL} to the full compensation current circuit 22. can be explained as

When the input voltage VIN rises and the difference between the voltage level of the input voltage VIN and the voltage level of the output voltage VOUT is greater than the threshold voltage of the transistor N11, the full compensation current circuit 22 compares the rising The pull compensation current I _PULL may be generated based on the current I _DIFR , and the pull compensation current I _PULL may be provided to the operational amplifier 10 . At this time, the full blocking current (I _{BLK_PULL} ) may be provided to the boosting transistor (N13) from the full blocking transistor (N16), but since the full compensation current (I _PULL ) is strongly generated, the boosting transistor (N13) is turned on. can keep

When the input voltage VIN rises and the difference between the voltage level of the input voltage VIN and the voltage level of the output voltage VOUT is smaller than the threshold voltage of the transistor N11, the full compensation current circuit 22 compares the rising Since the current (I _DIFR ) is not generated, the full compensation current (I _PULL ) may not be generated either. At this time, since the full blocking current I _{BLK_PULL} is generated, the full blocking current I _{BLK_PULL} may flow from the boosting transistor N13 to the full blocking transistor N16. Accordingly, since the gate voltage level of the boosting transistor N13 is lowered, the boosting transistor N13 may remain turned off. Therefore, even if leakage current is generated in the pull compensation current circuit 22, the boosting transistor N13 is turned off by the pull blocking current I _{BLK_PULL} , so that the current flowing to the first lower node NL1 of the pull load circuit PL Leakage current can be eliminated. In addition, DC offset can be removed, the operating speed of the buffer circuit can be improved, and it can be driven with low power.

In an embodiment according to the present disclosure, the gate of the push blocking transistor P16 is connected to the third upper node NU3 and the gate of the full blocking transistor N16 is connected to the third lower node NL3. It is not limited thereto. For example, the gates of the push blocking transistor P16 and the full blocking transistor N16 are voltages capable of turning on the push blocking transistor P16 and the full blocking transistor N16 among nodes of the load terminal 14 can be connected to any node that provides For example, the gate of the push blocking transistor P16 may be connected to a node providing a voltage level higher than the threshold voltage of the push blocking transistor P16 among nodes of the load terminal 14 . For example, the gate of the full blocking transistor N16 may be connected to a node providing a voltage level higher than the threshold voltage of the full blocking transistor N16 among the nodes of the load terminal 14 .

In an embodiment according to the present disclosure, the push blocking transistor P16 may include a PFET, and the full blocking transistor N16 may include an NFET, but is not limited thereto. Hereinafter, various embodiments of the buffer circuit BF will be described.

6 is a circuit diagram of an operational amplifier according to exemplary embodiments of the present disclosure. In detail, FIG. 6 is a circuit diagram for explaining an operational amplifier 10a as another embodiment of FIGS. 2 and 3 . Hereinafter, description will be made with reference to FIGS. 1 to 3, and overlapping descriptions will be omitted.

Referring to FIG. 6 , the operational amplifier 10a may include an input stage 11a, a lower bias circuit 13, a load stage 14a, and an output stage 15.

The input terminal 11a may have a single structure in which the transistors P1 and P2 are omitted. The input terminal 11a may be connected to the transistors N1 and N2 and may receive the push load currents I _PSLI and I _PSLO from the load terminal 14a.

The lower bias circuit 13 may generate the second bias current I _BL at the input terminal 11a based on the second bias voltage VB2 . Unlike the operational amplifier 10 of FIG. 3 , the upper bias circuit 12 may be omitted.

The load stage 14a may include a push load circuit PS, a full load circuit PLa, a connection circuit CC, a first capacitor C1 and a second capacitor C2. The push load circuit PS may receive the push compensation current I _PUSH from the slew rate compensation circuit 20 through the first upper node NU1, and based on the push compensation current I _PUSH , the push load current (I _PSLI , I _PSLO ) can be created. The push load circuit PS may provide the push load currents I _PSLI and I _PSLO to the second input terminal IS2 through the drain terminal of the transistor P4 and the drain terminal of the transistor P5 . The full load circuit PLa may receive the full compensation current I _PULL through the first lower node NL1 , but may not provide the full load currents I _PLLI and I _PLLO shown in FIG. 3 .

7 is a circuit diagram of an operational amplifier according to exemplary embodiments of the present disclosure. In detail, FIG. 7 is a circuit diagram for explaining an operational amplifier 10b as another embodiment of FIG. 2 . Hereinafter, description will be made with reference to FIG. 3, and overlapping descriptions will be omitted.

Referring to FIG. 7 , the operational amplifier 10b may include an input stage 11b, an upper bias circuit 12, a load stage 14b, and an output stage 15.

The input terminal 11b may have a unitary structure. The input terminal 11 may be connected to the transistors P1 and P2 and may receive full load currents I _PLLI and I _PLLO from the load terminal 14b.

The upper bias circuit 12 may provide the first bias current I _BU to the input terminal 11b based on the first bias voltage VB1 . Unlike the operational amplifier 10 of FIG. 3 , the lower bias circuit 13 may be omitted.

The load stage 14b may include a push load circuit PSa, a full load circuit PL, a connection circuit CC, a first capacitor C1 and a second capacitor C2. The push load circuit PS may receive the push compensation current I _PUSH through the first upper node NU1 , but may not provide the push load currents I _PSLI and I _PSLO shown in FIG. 3 . The full load circuit PL may receive the full compensation current I _PULL from the slew rate compensation circuit 20 through the first lower node NL1 and the full load current I _PULL based on the full compensation current I PULL . (I _PLLI , I _PLLO ). The full load circuit PL may provide the full load currents I _PLLI and I _PLLO to the input terminal 11b through the drain terminal of the transistor N4 and the drain terminal of the transistor N5.

8 is a circuit diagram of a slew rate compensation circuit according to exemplary embodiments of the present disclosure. In detail, FIG. 8 is a circuit diagram for explaining the slew rate compensation circuit 20a as another embodiment of FIG. 4 . Hereinafter, a description will be made with reference to FIG. 4, and overlapping descriptions will be omitted.

Referring to FIG. 8 , the slew rate compensation circuit 20a may include a comparison circuit 21 , a pull compensation current circuit 22 , a push compensation current circuit 23 and variable resistors R1 and R2 .

The first variable resistor R1 may be connected between the comparator circuit 21 and the full compensation current circuit 22 . The second variable resistor R2 may be connected between the comparator circuit 21 and the push compensation current circuit 23 . The slew rate compensation circuit 20a may control the amount of current of the rising comparison current I _DIFR and the falling comparison current I _DIFF by including the variable resistors R1 and R2 . That is, the slew rate compensation circuit 20a can control the operating speed of the slew rate compensation circuit 20a by including the variable resistors R1 and R2, and accordingly, the operating speed of the operational amplifier 10 can be controlled. can

9 is a circuit diagram of a slew rate compensation circuit according to exemplary embodiments of the present disclosure. In detail, FIG. 9 is a circuit diagram for explaining the slew rate compensation circuit 20b as another embodiment of FIG. 4 . Hereinafter, a description will be made with reference to FIG. 4, and overlapping descriptions will be omitted.

Referring to FIG. 9 , the slew rate compensation circuit 20b may include a comparator circuit 21, a pull compensation current circuit 22, a push compensation current circuit 23, and control transistors P17 and N17.

A ninth bias voltage VB9 is applied to a gate of the first control transistor P17 , one end may be connected to the comparator circuit 21 and the other end may be connected to the full compensation current circuit 22 . The current amount of the rising comparison current I _DIFR may be controlled by varying the ninth bias voltage VB9 .

The second control transistor N17 has a gate to which a tenth bias voltage VB10 is applied, one end connected to the comparator circuit 21 and the other end connected to the push compensation current circuit 23 . The amount of current of the polling comparison current I _DIFF can be controlled by varying the tenth bias voltage VB10 .

That is, the slew rate compensation circuit 20b may control the operating speed of the slew rate compensation circuit 20b by including the control transistors P17 and N17, and thus control the operating speed of the operational amplifier 10. can

10 is a circuit diagram of a slew rate compensation circuit according to exemplary embodiments of the present disclosure. In detail, FIG. 10 is a circuit diagram for explaining the slew rate compensation circuit 20c as another embodiment of FIG. 4 . Hereinafter, a description will be made with reference to FIG. 4, and overlapping descriptions will be omitted.

Referring to FIG. 10 , the slew rate compensation circuit 20c may include a comparison circuit 21 , a pull compensation current circuit 22c and a push compensation current circuit 23c.

The full compensation current generation circuit 22c may include transistors P12 , P13 , N12 , N13 , P18 , and P19 and a first current source I1 . The first current source I1 may generate a first supply current in response to the first control signal CNT1. The first control signal CNT1 may be a signal provided from the outside of the slew rate compensation circuit 20d.

The transistors P18 and P19 may be connected in a current mirror form. One end of the transistor P18 may be connected to the transistor P12 and the power supply voltage VDD may be applied from the other end. One end of the transistor P19 may be connected to the first current source I1, and the power supply voltage VDD may be applied from the other end.

The push compensation current generating circuit 23c may include transistors N14, N15, P14, P15, N18, and N19 and a second current source I2. The second current source I2 may generate a second power supply current in response to the second control signal CNT2. The second control signal CNT2 may be a signal provided from the outside of the slew rate compensation circuit 20d.

Transistors N18 and N19 may be connected in a current mirror form. One end of the transistor N18 may be connected to the transistor N14 and a ground voltage VSS may be applied from the other end. One end of the transistor N19 may be connected to the second current source I2, and the ground voltage VSS may be applied from the other end.

11 is a circuit diagram of a slew rate compensation circuit according to exemplary embodiments of the present disclosure. In detail, FIG. 11 is a circuit diagram for explaining a slew rate compensation circuit 20d as another embodiment of FIG. 4 . Hereinafter, description will be made with reference to FIGS. 3 and 4, and overlapping descriptions will be omitted.

Referring to FIG. 11 , the slew rate compensation circuit 20d may include a comparison circuit 21 , a pull compensation current circuit 22d and a push compensation current circuit 23d.

The full compensation current generation circuit 22d may include transistors P12, P13, N12, N13, and P20. A gate of the transistor P20 may be connected to the second upper node NU2 of the push load circuit PS. One end of the transistor P20 may be connected to the transistor P12 and the power supply voltage VDD may be applied from the other end.

The push compensation current generation circuit 23d may include transistors N14, N15, P14, P15, and N20. A gate of the transistor N20 may be connected to the second lower node NL2 of the full load circuit PL. One end of the transistor N20 may be connected to the transistor N14 and a ground voltage VSS may be applied from the other end.

12 is a circuit diagram of a slew rate compensation circuit according to exemplary embodiments of the present disclosure. In detail, FIG. 12 is a circuit diagram for explaining a comparison circuit 21a as another embodiment of a comparison circuit included in the slew rate compensation circuit of FIG. 4 . Hereinafter, a description will be made with reference to FIG. 4, and overlapping descriptions will be omitted.

Referring to FIG. 12 , the comparison circuit 21a may include transistors N11 , P11 , N21 , P21 , N22 , P22 , N23 , and P23 .

The transistor P21 may receive the first inverted enable signal EN1b through a gate, and one end may be connected to the gate terminal of the transistor N11 and the input voltage VIN may be applied from the other end.

The transistor N21 may receive the first enable signal EN1 through a gate, and one end may be connected to the gate terminal of the transistor N11 and the input voltage VIN may be applied from the other end. The first inverted enable signal EN1b may be an inverted signal of the first enable signal EN1. For example, when the first enable signal EN1 has a high level, the first inversion enable signal EN1b can have a low level.

The transistor P22 may receive the second inverted enable signal EN2b through a gate, and one end may be connected to the gate terminal of the transistor P11 and the input voltage VIN may be applied from the other end.

Transistor N22 may receive the second enable signal EN2 through a gate, and one end may be connected to the gate terminal of transistor P11 and the input voltage VIN may be applied from the other end. The second inverted enable signal EN2b may be an inverted signal of the second enable signal EN2. For example, when the second enable signal EN2 has a high level, the second inverted enable signal EN2b has a low level.

The first enable signal EN1, the first inverted enable signal EN1b, the second enable signal EN2, and the second inverted enable signal EN2b may be control signals for controlling the comparator circuit 21a. have. The first enable signal EN1, the first inverted enable signal EN1b, the second enable signal EN2, and the second inverted enable signal EN2b are provided from the outside of the slew rate compensation circuit 20. could be a signal The first enable signal EN1 and the second enable signal EN2 may have the same level. The first inversion enable signal EN1b and the second inversion enable signal EN2b may have the same level.

A gate of the transistor N23 may receive the first inversion enable signal EN1b, one end may be connected to the gate of the transistor N11, and a ground voltage VSS may be applied from the other end. A gate of the transistor P23 may receive the second enable signal EN2, one end may be connected to the gate of the transistor P11, and a power supply voltage VDD may be applied from the other end.

Comparing circuit 21a includes transistors N21, P21, N22, P22, N23, and P23, so that when pull compensation current circuit 22 or push compensation current circuit 23 is inactivated, comparison current I _DIFR , I _DIFF ) from being created. When the first and second enable signals EN1 and EN2 have a low level and the first and second inverted enable signals EN1b and EN2b have a high level, the gates of the transistors N11 and P11 are floating ( may not be floating.

13 is a circuit diagram of a slew rate compensation circuit according to exemplary embodiments of the present disclosure. In detail, FIG. 13 is a circuit diagram for explaining a comparison circuit 21b as another embodiment of a comparison circuit included in the slew rate compensation circuit of FIG. 4 . Hereinafter, a description will be made with reference to FIG. 4, and overlapping descriptions will be omitted.

Referring to FIG. 13 , the comparison circuit 21b may include transistors N11 and P11. Gates of the transistors N11 and P11 may be electrically connected, and bodies of the transistors N11 and P11 may be electrically connected to the output node N0UT. In addition, source terminals of the transistors N11 and P11 may be electrically connected to the output node N0UT.

As the bodies of the transistors N11 and P11 are electrically connected to the source terminals of the transistors N11 and P11, even if the back-bias voltage applied to the bodies of the transistors N11 and P11 changes. Levels of threshold voltages of the transistors N11 and P11 may be maintained constant.

14 is a circuit diagram of an offset blocking circuit according to exemplary embodiments of the present disclosure. In detail, FIG. 14 is a circuit diagram for explaining an offset blocking circuit 30a as another embodiment of FIG. 5 . Hereinafter, a description will be made with reference to FIG. 5, and redundant descriptions will be omitted.

Referring to FIG. 14 , the offset blocking circuit 30a may include a push blocking transistor P16 and a full blocking transistor N16.

An eleventh bias voltage VB11 may be applied to the gate of the push blocking transistor P16, one end may be connected to the full node N _PULL , and a power supply voltage VDD may be applied from the other end. The level of the eleventh bias voltage VB11 may be equal to or higher than the threshold voltage level of the push blocking transistor P16.

A twelfth bias voltage VB12 may be applied to the gate of the full blocking transistor N16, one end may be connected to the push node N _PUSH , and a ground voltage VSS may be applied from the other end. The level of the twelfth bias voltage VB12 may be equal to or higher than the threshold voltage level of the full blocking transistor N16.

The offset blocking circuit 30a can be controlled by applying bias voltages VB11 and VB12 to gates of the push blocking transistor P16 and the pull blocking transistor N16.

15 is a diagram illustrating voltages measured at nodes of a buffer circuit according to exemplary embodiments of the present disclosure. Specifically, (a) graph is a diagram showing the waveform of the output voltage (VOUT) of the buffer circuit (BF) according to the present disclosure compared to the conventional buffer circuit, (b) graph is the input voltage (VIN) In the case of rising, the push node N in the buffer circuit BF according to the present disclosure_PUSH) of voltage (V_PUSH) is a diagram showing a comparison of the waveform of a conventional buffer circuit, and (c) graph shows a full node (N in a buffer circuit (BF) according to the present disclosure when the input voltage (VIN) is polled._PULL) of voltage (V_PULL) is a diagram showing a comparison of the waveform of a conventional buffer circuit. In FIG. 15 , a horizontal axis may represent time and a vertical axis may represent voltage. Hereinafter, description will be made with reference to FIGS. 2 to 5 .

Referring to FIG. 15, (a) in the graph, the output voltage (V1) of the buffer circuit (BF) including the operational amplifier 10, the slew rate compensation circuit 20 and the offset blocking circuit 30 according to the present disclosure The transition time is shorter than the output voltage V2 of the buffer circuit in which the slew rate compensation circuit 20 and the offset blocking circuit 30 are omitted. That is, (a) the rate of change of the output voltage represented by the slope of the graph is greater in the output voltage V1 than in the output voltage V2. Since the output voltage changes faster at the output voltage V1, the slew rate of the buffer circuit BF according to the present disclosure is improved than that of the buffer circuit in which the slew rate compensation circuit 20 and the offset blocking circuit 30 are omitted.

In addition, in the graph (b), when the difference between the voltage level of the input voltage VIN and the voltage level of the output voltage VOUT is smaller than the threshold voltage level of the transistor N11 included in the comparison circuit 21, this According to the disclosure, the voltage level of the push node N _PUSH 1 of the buffer circuit BF including the slew rate compensation circuit 20 and the offset blocking circuit 30 may be equal to the voltage level of the ground voltage VSS. . However, the voltage level of the push node N _PUSH 2 of the buffer circuit in which the slew rate compensation circuit 20 and the offset blocking circuit 30 are omitted may be the same as the voltage level of the threshold voltage V _THN of the transistor N11. have.

(c) In the graph, when the difference between the voltage level of the input voltage VIN and the voltage level of the output voltage VOUT is smaller than the threshold voltage level of the transistor P11 included in the comparison circuit 21, according to the present disclosure Accordingly, the voltage level of the pull node N _PULL 1 of the buffer circuit BF including the slew rate compensation circuit 20 and the offset blocking circuit 30 may be equal to the voltage level of the power supply voltage VDD. However, the voltage level of the full node N _PULL 2 of the buffer circuit in which the slew rate compensation circuit 20 and the offset blocking circuit 30 are omitted is equal to the voltage level of the threshold voltage V _THP of the transistor P11. can

According to an embodiment according to the present disclosure, after the input voltage VIN rises or falls, the boosting transistors N13 and P15 may be turned off by the offset blocking circuit 30 . Accordingly, since the DC offset can be removed, the slew rate can be improved.

16 is a block diagram of a source driver including a buffer circuit according to exemplary embodiments of the present disclosure. In detail, referring to FIGS. 1 to 14, it is a diagram for explaining a source driver including a buffer circuit (BF).

Referring to FIG. 16 , the source driver 100 may include a shift register 110 , a sampling latch 120 , a holding latch 130 , a decoder 140 and an output buffer circuit 150 .

The shift register 110 may control operation timing of each of the plurality of sampling circuits included in the sampling latch 120 in response to the horizontal synchronizing signal Hysnc. The horizontal synchronization signal Hsync may be a signal having a constant period.

The sampling latch 120 may sample image data according to the shift order of the shift register 110 . Image data sampled by the sampling latch 120 may be stored in the holding latch 130 .

The decoder 140 may include a digital-to-analog converter (DAC) and may receive a plurality of gamma voltages (VG). The decoder 140 may select at least one of the plurality of gamma voltages VG based on image data stored in the holding latch 130 . The number of gamma voltages VG may be determined according to the number of bits of image data. For example, when the image data is 8-bit data, the number of gamma voltages (VG) may be 256 or less, and when the image data is 10-bit data, the number of gamma voltages (VG) may be 1024 or less. have.

The output buffer circuit 150 may include a plurality of output buffers implemented as operational amplifiers, and the plurality of output buffers may be connected to a plurality of source lines SL. Each of the plurality of output buffers may have a plurality of input terminals. The decoder 140 may select at least some of the gamma voltages VG based on the image data and provide the selected voltage as an input voltage to input terminals of each of the plurality of output buffers. Each of the plurality of output buffers may output the input voltage received from the decoder unit 140 as a source line.

Each of the plurality of output buffers may include the operational amplifier, the slew rate compensation circuit 151 and the offset blocking circuit 152 described above with reference to FIGS. 1 to 14 . Each of the plurality of output buffers includes the slew rate compensation circuit 151 and the offset blocking circuit 152 to remove DC offset, operate with low power, and increase the slew rate.

17 is a block diagram of a display device according to example embodiments of the present disclosure. In detail, it is a diagram for explaining the display device 200 including the source driver 100 of FIG. 16 .

Referring to FIG. 17 , the display device 200 may include a display panel 210 , a controller 220 , a gate driver 230 and a source driver 240 .

The display panel 210 may include a plurality of pixels PXs arranged in a matrix form and display an image in units of frames. The display panel 210 includes a liquid crystal display (LCD), a light emitting diode (LED) display, an organic LED (OLED) display, an active-matrix OLED (AMOLED) display, a micro LED display, an electrochromic display (ECD), and a digital display (DMD). Mirror Device), AMD (Actuated Mirror Device), GLV (Grating Light Value), PDP (Plasma Display Panel), ELD (Electro Luminescent Display), VFD (Vacuum Fluorescent Display) It can be implemented as a flat panel display or a flexible display. Hereinafter, an OLED panel will be described as an example, but is not limited thereto.

The display panel 210 includes gate lines GL1 to GLn arranged in a row direction, source lines SL1 to SLm arranged in a column direction, and the gate lines GL1 to GLn and the source lines SL1 ~SLm) may be provided with pixels PX formed at intersections.

In the display panel 210 , pixels PXs emitting red (R), green (G), and blue (B) lights may be repeatedly arranged. For example, the pixels PX may be repeatedly arranged in the order of R,G,B or B,G,R. Alternatively, the pixels PX may be repeatedly arranged in the order of R,G,B,G or B,G,R,G.

The pixels PX may include a light emitting diode and a driving circuit independently driving the light emitting diode. Specifically, the pixel PX may include a diode driving circuit connected to one gate line and a source line, and a light emitting diode connected between the diode driving circuit and a power supply voltage (eg, a ground voltage).

The diode driving circuit may include a switching element, for example a thin film transistor, connected to the gate line. When a gate-on signal is applied from the gate line and the switching element is turned on, the diode driving circuit may supply an image signal received from a source line connected to the diode driving circuit to the light emitting diode. The diode may output an optical signal corresponding to the video signal.

The controller 220 may receive a control signal from the outside. For example, the controller 220 may receive a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, a clock signal DCLK, and a data enable signal DE from the outside. The controller 220 may generate control signals CONT1 , CONT2 , and CLS for controlling the gate driver 230 and the source driver 240 based on the received control signals. Various operation timings of the gate driver 230 and the source driver 240 may be controlled according to the control signals CONT1 , CONT2 , and CLS.

In addition, the controller 220 may receive image data RGB from the outside, process the received image data RGB, or convert the image data RGB to conform to the structure of the display panel 210. . The controller 220 may transmit the converted image data DATA to the source driver 240 .

The controller 220 according to an embodiment of the present disclosure may determine a driving order of pixel groups of one horizontal line of the display panel 210 . That is, the controller 220 may time-divide one horizontal period to drive each of the plurality of pixel groups.

The gate driver 230 may sequentially supply a gate-on signal to the gate lines GL1 to GLn in response to the gate control signal CTRL1 received from the controller 220 . For example, the gate control signal CTRL1 includes a gate start pulse (GSP) indicating the start of output of the gate-on signal and a gate shift clock (GSC) controlling the output timing of the gate-on signal. etc. may be included. When the gate start pulse GSP is applied, the gate driver 230 sequentially generates a gate-on signal (eg, a gate voltage at a logic low level) in response to the gate shift clock GSC, and generates the gate-on signal may be sequentially supplied to the gate lines GL1 to GLn. In this case, during a period in which the gate-on signal is not supplied to the gate lines GL1-GLn, a gate-off signal (eg, a gate voltage of a logic high level) may be supplied to the gate lines GL1-GLn.

The source driver 240 converts the image data DATA into image signals (eg, grayscale voltages corresponding to pixel data) in response to the source control signal CTRL2 received from the controller 220, and Signals may be output through a plurality of channels CH1 to CHk. For example, the source control signal CTRL2 may include a source start pulse (SSP), a source shift clock (SSC), a source output enable (SOE) signal, and the like. have. The source driver 240 may include a plurality of driving units that provide image signals of one horizontal line to the source lines SL1 to SLm during one horizontal period. Each driving unit may activate source lines connected to each driving unit.

The source driver 240 may include the source driver 100 described above with reference to FIG. 16 . Accordingly, the output buffer included in the source driver 240 may include a slew rate compensation circuit 241 and an offset blocking circuit 242 .

Meanwhile, although not shown, the display device 200 may further include a voltage generating circuit and an interface. The voltage generating circuit may generate various voltages used in the display panel 210 and driving circuits. The interface is, for example, an RGB interface, a CPU interface, a serial interface, a mobile display digital interface (MDDI), an inter integrated circuit (I2C) interface, a serial peripheral interface (SPI), a micro controller unit (MCU) interface, MIPI ( Mobile industry processor interface), embedded displayport (eDP) interface, D-sub (D-subminiature), optical interface (4076), or one of D-sub (D-subminiature) or high-definition multimedia interface (HDMI) can include In addition, the interface may include various other serial or parallel interfaces.

According to example embodiments, the controller 220 and the source driver 240 may be implemented on a single semiconductor chip, and the gate driver 230 may be integrated on the display panel 210 .

According to an embodiment, the semiconductor chip may include a semiconductor substrate including single crystal silicon. Accordingly, the display device 200 may include a driving element and/or a switch composed of a single crystal silicon thin film transistor.

According to an embodiment, the display panel 210 may include a semiconductor substrate including amorphous Si (a-Si) or polycrystalline Si (poly-Si). Accordingly, the display panel 210 may include a driving element and/or a switch made of an amorphous silicon thin film transistor, or a driving element and/or a switch made of a polycrystalline silicon thin film transistor.

Depending on the embodiment, a pad connecting the source driver 240 and the display panel 210 may be provided. For example, the source driver 240 may include a plurality of output pads, and the display panel 210 may include a plurality of input pads.

18 is a flowchart illustrating a method of operating a buffer circuit according to example embodiments of the present disclosure. In detail, it is a flowchart illustrating an operating method of the buffer circuit BF described above with reference to FIGS. 1 to 5 . Hereinafter, it demonstrates with reference to FIGS. 1-5.

Referring to FIG. 18 , in step S10 , the difference between the input voltage level VL _IN and the output voltage level VL _OUT may be compared with the reference voltage level VL1 . The difference between the input voltage level (VL _IN ) and the output voltage level (VL _OUT ) may be compared in the comparator 21 . The reference voltage level VL1 may include threshold voltage levels of the transistors N11 and P11 constituting the comparator 21 .

In step S20, when the difference between the input voltage level (VL _IN ) and the output voltage level (VL _OUT ) is greater than the reference voltage level (VL1), the input voltage level (VL _IN ) and the output voltage level (VL _OUT ) Based on the difference, the slew rate compensation circuit 20 may generate compensation currents I _PULL and I _PUSH . For example, when the input voltage rises, the slew rate compensation circuit 20 can generate a pull compensation current (I _PULL ), and when the input voltage falls, the slew rate compensation circuit 20 generates a push compensation current (I _PUSH ). can create The slew rate compensation circuit 20 may provide compensation currents I _PULL and I _PUSH to the load stage 14 of the operational amplifier 10 .

In step S30, the load stage 14 may perform slew rate compensation operation using the compensation currents I _PUSH and I _PULL provided from the slew rate compensation circuit 20. That is, the load stage 14 may generate load currents I _PSLI , I _PSLO , I _PLLI , and I _{PLLO based} on the compensation currents I PUSH and I _PULL . The load stage 14 may provide load currents I _PSLI , I _PSLO , I _PLLI , and I _PLLO to the input stage 11 of the operational amplifier 10 .

In step S40, an output voltage may be generated by buffering the input voltage.

In step S50 , when the difference between the input voltage level VL _IN and the output voltage level VL _OUT is less than the reference voltage level VL1 , the slew rate compensation circuit 20 may be deactivated. Regardless of whether the slew rate compensation circuit 20 is deactivated, the offset blocking circuit 30 may be activated by a turn-on voltage provided from the operational amplifier 10 or an external bias voltage.

In step S60 , the offset blocking circuit 30 may generate blocking currents I _{BLK_PUSH} and I _{BLK_PULL} and may provide them to the slew rate compensation circuit 20 . Specifically, the blocking currents I _{BLK_PUSH} and I _{BLK_PULL} may be provided to the gates of the boosting transistors N13 and P15 of the slew rate compensation circuit 20 .

In step S70, the boosting transistors N13 and P15 of the slew rate compensation circuit 20 may be turned off. Accordingly, the leakage current generated in the slew rate compensation circuit 20 may not flow to the operational amplifier 10, and the DC offset may be removed. In addition, it is possible to provide a buffer circuit having an increased slew rate and driven with low power.

As above, exemplary embodiments have been disclosed in the drawings and specifications. Although the embodiments have been described using specific terms in this specification, they are only used for the purpose of explaining the technical idea of the present disclosure, and are not used to limit the scope of the present disclosure described in the claims. . Therefore, those of ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical scope of protection of the present disclosure should be determined by the technical spirit of the appended claims.

Claims (20)

an operational amplifier that amplifies an input voltage to generate an output voltage;
a slew rate compensation circuit generating a compensation current based on a difference between a voltage level of the input voltage and a voltage level of the output voltage, and providing the compensation current to the operational amplifier through a boosting transistor; and
A buffer circuit including an offset blocking circuit which provides a blocking current to the slew rate compensation circuit to turn off the boosting transistor when a difference between a voltage level of the input voltage and a voltage level of the output voltage is less than a reference voltage level. . According to claim 1,
The offset blocking circuit,
Buffer circuit, characterized in that for generating the blocking current based on the turn-on voltage provided from the operational amplifier or a bias voltage input from the outside, and providing the blocking current to the gate of the boosting transistor. According to claim 1,
The reference voltage level is,
Buffer circuit, characterized in that the voltage level of the threshold voltage of the transistor constituting the slew rate compensation circuit is the same level. According to claim 1,
The slew rate compensation circuit,
and providing the compensating current to the operational amplifier when a difference between the voltage level of the input voltage and the voltage level of the output voltage is greater than the reference voltage level. According to claim 1,
The slew rate compensation circuit,
a comparator that compares a voltage level of the input voltage with a voltage level of the output voltage and generates a comparison current corresponding to a difference between the voltage level of the input voltage and the voltage level of the output voltage;
a push compensation current circuit generating a push compensation current supplying current to the operational amplifier by performing a current mirror operation on the comparison current; and
and a full compensation current circuit for generating a full compensation current that sinks (syncs) the current of the operational amplifier by performing a current mirror operation with respect to the comparison current. According to claim 5,
When the difference between the voltage level of the input voltage and the voltage level of the output voltage is greater than the reference voltage level and the input voltage rises, the full compensation current circuit is activated, so that the slew rate compensation circuit providing a full compensation current to the operational amplifier;
When the difference between the voltage level of the input voltage and the voltage level of the output voltage is greater than the reference voltage level and the input voltage is falling, as the push compensation current circuit is activated, the slew rate compensation circuit Buffer circuit characterized in that for providing the push compensation current to the operational amplifier. According to claim 5,
The operational amplifier,
an input stage that receives the input voltage and output voltage and includes a first input terminal composed of PFETs and a second input terminal composed of NFETs;
A pull load circuit providing a full load current generated based on the pull compensation current to the first input terminal, a push load circuit providing a push load current generated based on the push compensation current to the second input terminal, and a load stage including a connection circuit connecting a pull connection node of the pull load circuit and a push connection node of the push load circuit; and
and an output stage electrically connected to the pull connection node and the push connection node and generating the output voltage by buffering an output signal of the load stage. According to claim 7,
The boosting transistor is included in the push compensation current circuit and the pull compensation current circuit, respectively;
The offset blocking circuit,
a P-channel Field Effect Transistor (PFET) having a gate connected to the push connection node, one end connected to the gate of the boosting transistor included in the push compensation current circuit, and a power supply voltage applied from the other end; and
An N-channel Field Effect Transistor (NFET) having a gate connected to the full connection node, one end connected to the gate of the boosting transistor included in the full compensation current circuit, and a ground voltage applied from the other end. A buffer circuit, characterized in that. a display panel including a plurality of pixels formed at intersections of gate lines arranged in a row direction and source lines arranged in a column direction;
a controller for generating a source control signal based on control signals received from the outside and converting image data received from the outside; and
a source driver converting video data converted by the controller into video signals in response to a source control signal received from the controller and providing the video signals to the source lines;
The source driver,
an operational amplifier that amplifies an input voltage to generate an output voltage;
a slew rate compensation circuit generating a compensation current based on a difference between a voltage level of the input voltage and a voltage level of the output voltage, and providing the compensation current to the operational amplifier through a boosting transistor; and
A buffer circuit including an offset blocking circuit which provides a blocking current to the slew rate compensation circuit to turn off the boosting transistor when a difference between a voltage level of the input voltage and a voltage level of the output voltage is less than a reference voltage level. A display device comprising a. According to claim 9,
The offset blocking circuit,
The display device, characterized in that generating the blocking current based on the turn-on voltage provided from the operational amplifier, and providing the blocking current to the gate of the boosting transistor. According to claim 9,
The reference voltage level is,
The display device, characterized in that the voltage level is the same as the voltage level of the threshold voltage of the transistor constituting the slew rate compensation circuit. According to claim 9,
The slew rate compensation circuit,
and providing the compensating current to the operational amplifier when a difference between the voltage level of the input voltage and the voltage level of the output voltage is greater than the reference voltage level. According to claim 9,
The slew rate compensation circuit,
a comparator that compares a voltage level of the input voltage with a voltage level of the output voltage and generates a comparison current corresponding to a difference between the voltage level of the input voltage and the voltage level of the output voltage;
a push compensation current circuit generating a push compensation current supplying current to the operational amplifier by performing a current mirror operation on the comparison current; and
and a full compensation current circuit generating a full compensation current that sinks the current of the operational amplifier by performing a current mirror operation with respect to the comparison current. According to claim 13,
When the difference between the voltage level of the input voltage and the voltage level of the output voltage is greater than the reference voltage level and the input voltage rises, the full compensation current circuit is activated, so that the slew rate compensation circuit providing a full compensation current to the operational amplifier;
When the difference between the voltage level of the input voltage and the voltage level of the output voltage is greater than the reference voltage level and the input voltage is falling, as the push compensation current circuit is activated, the slew rate compensation circuit The display device characterized in that for providing the push compensation current to the operational amplifier. According to claim 13,
The operational amplifier,
an input stage that receives the input voltage and output voltage and includes a first input terminal composed of PFETs and a second input terminal composed of NFETs;
A pull load circuit providing a full load current generated based on the pull compensation current to the first input terminal, a push load circuit providing a push load current generated based on the push compensation current to the second input terminal, and a load stage including a connection circuit connecting a pull connection node of the pull load circuit and a push connection node of the push load circuit; and
and an output stage electrically connected to the pull connection node and the push connection node and generating the output voltage by buffering an output signal of the load stage. According to claim 15,
The boosting transistor is included in the push compensation current circuit and the pull compensation current circuit, respectively;
The offset blocking circuit,
a P-channel Field Effect Transistor (PFET) having a gate connected to the push connection node, one end connected to the gate of the boosting transistor included in the push compensation current circuit, and a power supply voltage applied from the other end; and
A gate is connected to the full connection node, one end is connected to the gate of the boosting transistor included in the full compensation current circuit, and an N-channel Field Effect Transistor (NFET) to which a ground voltage is applied from the other end A display device, characterized in that. comparing a difference between an input voltage level and an output voltage level of an operational amplifier with a reference voltage level in a slew rate compensation circuit;
When the difference between the input voltage level and the output voltage level is greater than the reference voltage level, the slew rate compensation circuit generates a compensation current based on the difference between the input voltage level and the output voltage level, and the operational amplifier generates the compensation current. providing an electric current; and
When the difference between the input voltage level and the output voltage level is less than the reference voltage level, the boosting transistor of the slew rate compensation circuit is turned off by a blocking current provided to the slew rate compensation circuit by an offset blocking circuit. Buffer circuit control method comprising: According to claim 17,
The step of turning off the boosting transistor of the slew rate compensation circuit,
generating the blocking current by the offset blocking circuit based on a turn-on voltage provided from the operational amplifier or a bias voltage input from the outside; and
The buffer circuit control method comprising the step of inputting the blocking current to the gate of the boosting transistor. According to claim 17,
The reference voltage level is,
The buffer circuit control method according to claim 1 , wherein the voltage level of the threshold voltage of the transistor constituting the slew rate compensation circuit is the same as that of the threshold voltage. According to claim 17,
generating a push compensation current supplying a current to the operational amplifier from among the compensation current when a difference between the input voltage level and the output voltage level is greater than the reference voltage level and the input voltage rises;
Generating a full compensation current that sinks a current of an operational amplifier from among the compensation current when the difference between the input voltage level and the output voltage level is greater than the reference voltage level and the input voltage is falling. Buffer circuit control method further comprising a.

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