KR20220157334A - Display panel and fabricating method of the same - Google Patents

Abstract

A display device comprises: a base layer including a first region and a second region bent from the first region; at least one inorganic layer in which a lower groove overlapping the second region is defined; a first thin film transistor including a silicon semiconductor pattern overlapping the first region; a second thin film transistor including an oxide semiconductor pattern; insulation layers in which the lower groove and an extended upper groove are defined; a signal line including a plurality of parts disposed on different layers, electrically connected to the second thin film transistor, and overlapping the first region and the second region; an organic layer overlapping the first region and the second region and disposed inside the lower groove and the upper groove; and a light emitting element disposed on the organic layer to overlap the first region. Accordingly, the flexibility of the bending area of the display panel is improved.

Description

Display panel and its manufacturing method {DISPLAY PANEL AND FABRICATING METHOD OF THE SAME}

The present invention relates to a display panel and a manufacturing method thereof, and relates to a display panel including two types of semiconductor materials and a manufacturing method thereof.

The display device includes a plurality of pixels and a driving circuit (eg, a scan driving circuit and a data driving circuit) that control the plurality of pixels. Each of the plurality of pixels includes a display element and a pixel driving circuit that controls the display element. A driving circuit of a pixel may include a plurality of organically connected thin film transistors.

An object of the present invention is to provide a display panel with improved pixel operating characteristics and improved flexibility.

An object of the present invention is to provide a manufacturing method of a display panel in which the number of masks used in the manufacturing process is reduced.

A display device according to an exemplary embodiment of the present invention includes: a base layer including a first area and a second area bent from the first area; at least one inorganic layer defined with a lower groove overlapping the second area; A first thin film transistor including a silicon semiconductor pattern overlapping a first region, an oxide semiconductor pattern overlapping the first region, a control electrode disposed on the oxide semiconductor pattern, an input electrode and an output electrode disposed on the semiconductor pattern A second thin film transistor including an electrode, insulating layers in which the lower groove and an extended upper groove are defined, and a plurality of parts disposed on other layers and electrically connected to the second thin film transistor, the first region and a signal line overlapping the second region, a light blocking pattern disposed between the at least one inorganic layer and the oxide semiconductor pattern of the second thin film transistor, and overlapping the oxide semiconductor pattern of the second thin film transistor. An organic layer overlapping the first region and the second region and disposed inside the lower groove and the upper groove, and a light emitting device disposed on the organic layer to overlap the first region.

The light blocking pattern may have conductivity. The light blocking pattern may receive a bias voltage. The light blocking pattern may be electrically connected to the control electrode of the second thin film transistor.

The organic layer may further include a connection electrode disposed on the organic layer and connected to the output electrode of the first thin film transistor through a contact hole penetrating the organic layer.

A passivation layer disposed on the organic layer and overlapping the first region and the second region may be further included.

An electrode of the light emitting device may be connected to the connection electrode through a contact hole penetrating the passivation layer.

The passivation layer may be disposed on the signal line, and a portion of the passivation layer overlapping the second region may contact a portion overlapping the second region among the plurality of portions of the signal line.

The second area may include a curvature area connected to the first area and forming a predetermined curvature, and an opposing area connected to the curvature area and facing the first area. The plurality of portions of the signal line include a first portion overlapping the first region and electrically connected to the second thin film transistor, a second portion overlapping the curvature region and disposed on a different layer from the first portion; and a third portion overlapping the opposing region and disposed on a different layer from the second portion.

The second portion of the signal line may be disposed on the organic layer.

The insulating layers may include: a first insulating layer covering the silicon semiconductor pattern of the first thin film transistor; a second insulating layer disposed on the first insulating layer and covering a control electrode of the first thin film transistor; A third insulating layer disposed on the second insulating layer and a fourth insulating layer disposed on the third insulating layer and covering the control electrode of the second thin film transistor overlapping the oxide semiconductor pattern of the second thin film transistor. may contain layers.

An upper electrode disposed between the second insulating layer and the third insulating layer and overlapping the control electrode of the first thin film transistor may be further included.

The second thin film transistor may further include an insulating pattern disposed between the oxide semiconductor pattern and the control electrode of the second thin film transistor. The insulating pattern may partially overlap the oxide semiconductor pattern of the second thin film transistor.

The insulating layers are disposed between the third insulating layer and the fourth insulating layer, partially cover the oxide semiconductor pattern of the second thin film transistor, and expose both ends of the oxide semiconductor pattern of the second thin film transistor. It may further include an intermediate insulating layer in which openings are defined.

An upper electrode disposed between the third insulating layer and the fourth insulating layer and overlapping the control electrode of the first thin film transistor may be further included.

An insulating pattern disposed between the third insulating layer and the upper electrode may be further included.

The light blocking pattern may be disposed between the at least one inorganic layer and the first insulating layer, and may include the same material as the silicon semiconductor pattern.

The light blocking pattern may be disposed between the first insulating layer and the second insulating layer, and may include the same material as the control electrode of the first thin film transistor.

The second insulating layer may include silicon oxide and may contact the light blocking pattern.

An upper electrode disposed between the second insulating layer and the third insulating layer and overlapping the control electrode of the first thin film transistor may be further included.

The light blocking pattern may be disposed between the second insulating layer and the third insulating layer, and may include the same material as the upper electrode.

A portion of an upper surface of the at least one inorganic layer may be in contact with the organic layer.

A method of manufacturing a display panel according to an exemplary embodiment of the present invention includes at least one layer overlapping the first area and the second area on a base layer including a first area and a second area extending from the first area. Forming an inorganic layer, forming a silicon semiconductor pattern on the at least one inorganic layer to overlap the first region, and overlapping the silicon semiconductor pattern with a first insulating layer interposed therebetween. Forming a first control electrode to overlap the first control electrode, forming an upper electrode overlapping the first control electrode with a second insulating layer interposed therebetween, forming a light-shielding pattern to overlap the first region Forming a third insulating layer covering the upper electrode, forming an oxide semiconductor pattern on the third insulating layer to overlap the light blocking pattern, and forming the oxide semiconductor pattern on the oxide semiconductor pattern forming a second control electrode overlapping the second control electrode, forming a fourth insulating layer covering the second control electrode, a first contact hole exposing a first part and a second part of the silicon semiconductor pattern, and a first etching step of partially removing the first to fourth insulating layers to form a second contact hole and an upper groove exposing a portion overlapping the second region of the at least one inorganic layer; The fourth insulating layer is partially removed to form a third contact hole and a fourth contact hole exposing the first and second portions of the oxide semiconductor pattern, respectively, in the second region of the at least one inorganic layer. A second etching step of partially removing the at least one inorganic layer to form a lower groove continuous with the upper groove, a first input electrode connected to the first part and the second part of the silicon semiconductor pattern, respectively; and An electrode forming step of forming a first output electrode, and forming a second input electrode and a second output electrode respectively connected to the first portion and the second portion of the oxide semiconductor pattern, the first input electrode, forming an organic layer covering the first output electrode, the second input electrode, and the second output electrode and disposed inside the upper groove and the lower groove; a fifth contact exposing the first output electrode; A third etching step of partially removing the organic layer to form a hole, forming a part of a signal line electrically connected to the first output electrode on the organic layer, and electrically connecting the first output electrode to the organic layer. It may include forming a light emitting element connected to.

According to the above, the leakage current of the thin film transistor directly connected to the signal line is reduced. Voltage-current characteristics of the thin film transistor controlling the driving current of the light emitting device may be maintained.

By disposing the organic layer in the bending area of the display panel, the flexibility of the bending area of the display panel is improved.

The number of masks used in the manufacturing process can be reduced because the process of forming a contact hole exposing a portion of the semiconductor pattern disposed in the display area and the process of removing the insulating layer and the inorganic layer of the bending area are performed in a single process. .

1A and 1B are perspective views of a display panel according to an exemplary embodiment of the present invention.
2 is a plan view of a display panel according to an exemplary embodiment of the present invention.
3A is an equivalent circuit diagram of a pixel according to an embodiment of the present invention.
3B and 3C are cross-sectional views corresponding to a portion of a pixel according to an exemplary embodiment.
4A and 4B are cross-sectional views corresponding to a bending area of a display panel according to an exemplary embodiment of the present invention.
5A to 5M are cross-sectional views illustrating a manufacturing process of a display panel according to an embodiment of the present invention.
6 to 9 are cross-sectional views corresponding to portions of a display panel according to an exemplary embodiment of the present invention.
10A to 10G are cross-sectional views corresponding to portions of a display panel according to an exemplary embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this specification, when an element (or region, layer, section, etc.) is referred to as being “on,” “connected to,” or “coupled to” another element, it is directly connected/connected to the other element. It means that they can be combined or a third component can be placed between them.

Like reference numerals designate like components. Also, in the drawings, the thickness, ratio, and dimensions of components are exaggerated for effective description of technical content. “And/or” includes any combination of one or more that the associated elements may define.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. These terms are only used for the purpose of distinguishing one component from another. For example, a first element may be termed a second element, and similarly, a second element may be termed a first element, without departing from the scope of the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise.

In addition, terms such as "below", "lower side", "above", and "upper side" are used to describe the relationship between components shown in the drawings. The above terms are relative concepts and will be described based on the directions shown in the drawings.

Terms such as "include" or "have" are intended to indicate that a feature, number, step, operation, component, part, or combination thereof described in the specification exists, but that one or more other features, numbers, or steps are present. However, it should be understood that it does not preclude the possibility of existence or addition of operations, components, parts, or combinations thereof.

1A and 1B are perspective views of a display panel DP according to an exemplary embodiment of the present invention. 2 is a plan view of a display panel DP according to an exemplary embodiment of the present invention. 2 briefly illustrates the connection relationship between the pixels PX, the driving circuit GDC, and the signal line SGL of the display panel.

In an unfolded state, the front surface DP-FS of the display panel DP is parallel to the plane defined by the first and second directional axes DR1 and DR2. The third direction axis DR3 indicates the normal direction of the front surface DP-FS of the display panel DP, that is, the thickness direction of the display panel DP. The upper surface (or front surface) and the lower surface (or rear surface) of each of the layers constituting the display panel DP are divided by the third directional axis DR3. Hereinafter, the first to third directions refer to the same reference numerals as directions indicated by the first to third direction axes DR1 , DR2 , and DR3 , respectively.

As shown in FIG. 1A , the display panel DP has a display area DP-DA where pixels PX are displayed on the front surface DP-FS and a non-display area adjacent to the display area DP-DA. DP-NDA). The non-display area DP-NDA is an area in which the pixels PX are not disposed. Some of the signal lines SGL and/or the driving circuit GDC may be disposed in the non-display area DP-NDA.

As shown in FIG. 1A , the display area DP-DA may have a rectangular shape. The non-display area DP-NDA may surround the display area DP-DA. However, it is not limited thereto, and the shape of the display area DP-DA and the shape of the non-display area DP-NDA can be designed relatively. For example, the non-display area DD-NDA may be disposed only in an area facing in the first direction DR1. The display area DP-DA may have a circular shape.

According to this embodiment, a portion of the non-display area DP-NDA may have a narrower width (length along the second direction DR2) than the display area DP-DA. As will be described later, this is to reduce the area of the bending region.

As shown in FIG. 1B, the display panel DP may be bent, and as the display panel DP is bent, the display panel DP has a first area (NBA, or non-bending area) and a second area (BA, or bending area). ) can be distinguished. The second area BA may include a curvature area CA having a predetermined curvature in a bent state and an opposing area FA to face the first area NBA in a bent state.

As shown in FIG. 2 , the display panel DP includes a driving circuit (GDC), a plurality of signal lines (SGL, hereinafter referred to as signal lines), a plurality of signal pads (DP-PD, hereinafter referred to as signal pads), and It may include a plurality of pixels PX (hereinafter referred to as pixels).

The pixels PX may be classified into a plurality of groups according to displayed colors. The pixels PX may include, for example, red pixels, green pixels, and blue pixels. The pixels PX may further include white pixels. Even if the pixels are classified into different groups according to displayed colors, the pixel driving circuits of the pixels may be the same.

The driving circuit GDC may include a scan driving circuit. The scan driving circuit generates a plurality of scan signals (hereinafter, scan signals) and sequentially outputs the scan signals to a plurality of scan lines (GL, hereinafter, scan lines) to be described later. The scan driving circuit may further output another control signal to the driving circuits of the pixels PX.

The scan driving circuit may include a plurality of thin film transistors formed through the same process as the driving circuit of the pixels PX, for example, a low temperature polycrystaline silicon (LTPS) process or a low temperature polycrystalline oxide (LTPO) process.

The signal lines SGL include scan lines GL, data lines DL, power line PL, and control signal line CSL. The scan lines GL are respectively connected to corresponding pixels PX among the pixels PX, and the data lines DL are respectively connected to corresponding pixels PX among the pixels PX. The power line PL is connected to the pixels PX. The control signal line CSL may provide control signals to the scan driving circuit. The signal pads DP-PD are connected to corresponding signal lines among the signal lines SGL.

A circuit board electrically connected to the display panel DP is not shown in FIG. 2 . The circuit board may be a rigid circuit board or a flexible circuit board. A driving chip may be mounted on the circuit board.

Although not shown, the driving chip may be mounted on the display panel DP. When the driving chip is mounted on the display panel DP, the design of the signal lines SGL may be changed. The driving chip may be connected to the data lines DL, and signal lines connecting the driving chip and the signal pads DP-PD may be further disposed.

3A is an equivalent circuit diagram of a pixel PX according to an embodiment of the present invention. 3B and 3C are cross-sectional views corresponding to a portion of a pixel PX according to an exemplary embodiment. 4A and 4B are cross-sectional views corresponding to the bending area BA of the display panel DP according to an exemplary embodiment of the present invention.

3A illustrates one scan line GL, one data line DL, one power supply line PL, and a pixel PX connected thereto. The pixel PX according to an exemplary embodiment of the present invention may be an emission type pixel and is not particularly limited. For example, the pixel PX may include an organic light emitting diode or a quantum dot light emitting diode as a light emitting device. The light emitting layer of the organic light emitting diode may include an organic light emitting material. The light emitting layer of the quantum dot light emitting diode may include quantum dots, quantum rods, and the like. Hereinafter, the pixel PX will be described as an organic light emitting pixel.

The pixel PX includes an organic light emitting diode (OLED) and a pixel driving circuit for driving the organic light emitting diode (OLED). The organic light emitting diode (OLED) may be a front light emitting diode or a bottom light emitting diode. In this embodiment, the pixel driving circuit includes a first thin film transistor (T1, or driving transistor), a second thin film transistor (T2, or switching transistor), and a capacitor (Cst). The first power supply voltage ELVDD is applied to the first thin film transistor T1 and the second power supply voltage ELVSS is applied to the organic light emitting diode OLED. The second power voltage ELVSS may be lower than the first power voltage ELVDD.

The first thin film transistor T1 is connected to the organic light emitting diode OLED. The first thin film transistor T1 controls the driving current flowing through the organic light emitting diode OLED in response to the amount of charge stored in the capacitor Cst. The second thin film transistor T2 outputs a data signal applied to the data line DL in response to a scan signal applied to the scan line GL. The capacitor Cst is charged with a voltage corresponding to the data signal received from the second thin film transistor T2.

The configuration of the pixel PX is not limited to that of FIG. 3A and may be modified and implemented. The pixel circuit that controls the organic light emitting diode (OLED) may include three or more, for example, six or seven thin film transistors, unlike that shown in FIG. 3A. The organic light emitting diode OLED may be connected between the power line PL and the second thin film transistor T2.

FIG. 3B shows a cross section corresponding to the first thin film transistor T1 , the second thin film transistor T2 , and the organic light emitting diode OLED as part of the pixel PX. As shown in FIG. 3B , the display panel DP may include a base layer BL, a circuit element layer DP-CL disposed on the base layer, a display element layer DP-OLED, and a thin film encapsulation layer. can The display panel DP may further include functional layers such as an antireflection layer and a refractive index control layer. The circuit element layer DP-CL includes at least a plurality of insulating layers and circuit elements. Hereinafter, the insulating layers may include an organic layer and/or an inorganic layer.

Circuit elements include signal lines, driving circuits of pixels, and the like. A circuit element layer may be formed through a process of forming an insulating layer, a semiconductor layer, and a conductive layer by coating, deposition, or the like, and a patterning process of the insulating layer, the semiconductor layer, and the conductive layer by a photolithography process. The display element layer DP-OLED includes a light emitting element. The display element layer DP-OLED may further include an organic layer such as a pixel defining layer PDL.

The base layer BL may include a synthetic resin film. The synthetic resin layer may include a thermosetting resin. In particular, the synthetic resin layer may be a polyimide-based resin layer, and the material thereof is not particularly limited. The synthetic resin layer may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin, and perylene resin. . In addition, the base layer may include a glass substrate, a metal substrate, or an organic/inorganic composite material substrate.

Areas of the display panel DP described with reference to FIGS. 1A to 2 may be equally defined in the base layer BL. For example, the base layer BL may include a first area NBA and a second area BA bent from the first area NBA.

At least one inorganic layer is formed on the upper surface of the base layer BL. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed in multiple layers. The multi-layered inorganic layers may constitute a barrier layer (BRL) and/or a buffer layer (BFL) to be described later. The barrier layer BRL and the buffer layer BFL may be selectively disposed.

The barrier layer BRL prevents foreign substances from entering from the outside. The barrier layer BRL may include a silicon oxide layer and a silicon nitride layer. Each of these may be provided in plurality, and silicon oxide layers and silicon nitride layers may be alternately stacked.

The buffer layer BFL may be disposed on the barrier layer BRL. The buffer layer BFL improves bonding strength between the base layer BL and the conductive patterns or semiconductor patterns. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

A first semiconductor pattern OSP1 is disposed on the buffer layer BFL. The first semiconductor pattern OSP1 may include a silicon semiconductor. The first semiconductor pattern OSP1 may be a polysilicon semiconductor. However, it is not limited thereto, and the first semiconductor pattern OSP1 may include amorphous silicon. The first semiconductor pattern OSP1 may include an input region (or first portion), an output region (or second portion), and a channel region (or third portion) defined between the input and output regions. A channel region of the first semiconductor pattern OSP1 may be defined to correspond to a first control electrode GE1 described later. The input region and the output region are doped with a dopant and have relatively high conductivity compared to the channel region. The input region and the output region may be doped with an n-type dopant. Although the n-type first thin film transistor T1 is exemplarily described in this embodiment, the first thin film transistor T1 may also be a p-type transistor.

A first insulating layer 10 is disposed on the buffer layer BFL. The first insulating layer 10 commonly overlaps the plurality of pixels PX (see FIG. 1A ) and covers the first semiconductor pattern OSP1 . The first insulating layer 10 may be an inorganic layer and/or an organic layer, and may have a single-layer or multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the first insulating layer 10 may be a single-layer silicon oxide layer.

A first control electrode GE1 is disposed on the first insulating layer 10 . The first control electrode GE1 overlaps the channel region of the first semiconductor pattern OSP1.

A second insulating layer 20 covering the first control electrode GE1 is disposed on the first insulating layer 10 . The second insulating layer 20 commonly overlaps the plurality of pixels PX (see FIG. 1 ). The second insulating layer 20 may be an inorganic layer and/or an organic layer, and may have a single-layer or multi-layer structure. The second insulating layer 20 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the second insulating layer 20 may be a single-layer silicon oxide layer.

An upper electrode UE may be further disposed on the second insulating layer 20 . The upper electrode UE may overlap the first control electrode GE1.

A third insulating layer 30 covering the upper electrode UE is disposed on the second insulating layer 20 . The third insulating layer 30 may be an inorganic layer and/or an organic layer, and may have a single-layer or multi-layer structure. The third insulating layer 30 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the third insulating layer 30 may be a single-layer silicon oxide layer.

A second semiconductor pattern OSP2 is disposed on the third insulating layer 30 . The second semiconductor pattern OSP2 may include an oxide semiconductor. The second semiconductor pattern OSP2 may include a crystalline or amorphous oxide semiconductor. For example, the oxide semiconductor is a metal oxide such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), or zinc (Zn), indium (In), gallium (Ga) , tin (Sn), may include a mixture of metals such as titanium (Ti) and their oxides. Oxide semiconductors include indium-tin oxide (ITO), indium-gallium-zinc oxide (IGZO), zinc oxide (ZnO), indium-zinc oxide (IZnO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium-zinc-tin oxide (IZTO), zinc-tin oxide (ZTO), and the like.

The second semiconductor pattern OSP2 may include an input region (or first portion), an output region (or second portion), and a channel region (or third portion) defined between the input and output regions. The input region and the output region may contain impurities. A channel region of the second semiconductor pattern OSP2 may be defined to correspond to a second control electrode GE2 described later.

Impurities of the second semiconductor pattern OSP2 may be reduced metal materials. The input region and the output region may include metal materials reduced from metal oxide constituting the channel region. Accordingly, the second thin film transistor T2 can reduce leakage current and function as a switching element with improved on-off characteristics.

An insulating pattern GIP is disposed on the channel region of the second semiconductor pattern OSP2. A second control electrode GE2 is disposed on the insulating pattern GIP. The second control electrode GE2 overlaps at least the insulating pattern GIP. An edge of the insulating pattern GIP may be aligned with an edge of the second control electrode GE2. The second control electrode GE2 may have the same shape as the insulating pattern GIP on a plane. The second control electrode GE2 may be disposed inside the insulating pattern GIP.

A fourth insulating layer 40 covering the second semiconductor pattern OSP2 and the second control electrode GE2 is disposed on the third insulating layer 30 . The fourth insulating layer 40 may be an inorganic layer and/or an organic layer, and may have a single-layer or multi-layer structure. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the fourth insulating layer 40 may include a silicon oxide layer and a silicon nitride layer. The fourth insulating layer 40 may include a plurality of alternately stacked silicon oxide layers and silicon nitride layers.

A first input electrode DE1 , a first output electrode SE1 , a second input electrode DE2 , and a second output electrode SE2 are disposed on the fourth insulating layer 40 . The first input electrode DE1 and the first output electrode SE1 are formed through the first contact hole CH1 and the second contact hole CH2 exposing the input and output regions of the first semiconductor pattern OSP1, respectively. It is connected to the first semiconductor pattern OSP1. The first contact hole CH1 and the second contact hole CH2 pass through the first insulating layer 10 to the fourth insulating layer 40 .

The second input electrode DE2 and the second output electrode SE2 are formed through the third contact hole CH3 and the fourth contact hole CH4 exposing the input and output regions of the second semiconductor pattern OSP2, respectively. It is connected to the second semiconductor pattern OSP2. The third contact hole CH3 and the fourth contact hole CH4 pass through the fourth insulating layer 40 .

A fifth insulating layer 50 covering the first input electrode DE1, the first output electrode SE1, the second input electrode DE2, and the second output electrode SE2 on the fourth insulating layer 40. this is placed The fifth insulating layer 50 may be an organic layer and may have a single-layer or multi-layer structure.

A connection electrode CNE is disposed on the fifth insulating layer 50 . The connection electrode CNE may be connected to the first output electrode SE1 through the fifth contact hole CH5 penetrating the fifth insulating layer 50 . A sixth insulating layer 60 (or passivation layer) covering the connection electrode CNE is disposed on the fifth insulating layer 50 . The sixth insulating layer 60 may be an organic layer and may have a single-layer or multi-layer structure.

In this embodiment, the fifth insulating layer 50 and the sixth insulating layer 60 may be a single-layer polyimide-based resin layer. The fifth insulating layer 50 and the sixth insulating layer 60 are not limited thereto, and the fifth insulating layer 50 and the sixth insulating layer 60 may include acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, and siloxane resin. , It may include at least any one of a polyamide-based resin and a perylene-based resin.

An organic light emitting diode (OLED) is disposed on the sixth insulating layer 60 . An anode AE of the organic light emitting diode (OLED) is disposed on the sixth insulating layer 60 . The anode AE is connected to the connection electrode CNE through the sixth contact hole CH6 penetrating the sixth insulating layer 60 . A pixel defining layer PDL is disposed on the sixth insulating layer 60 .

The opening OP of the pixel defining layer PDL exposes at least a portion of the anode AE. The opening OP of the pixel defining layer PDL may define an emission area PXA of a pixel. For example, the plurality of pixels PX (see FIG. 1A) may be arranged in a regular pattern on the plane of the display panel DP (see FIG. 1A). An area where the plurality of pixels PX is disposed may be defined as a pixel area, and one pixel area may include an emission area PXA and a non-emission area NPXA adjacent to the emission area PXA. The non-emission area NPXA may surround the emission area PXA.

The display area DP-DA shown in FIG. 1A and FIG. 1B includes a plurality of pixel areas. In other words, the display area DP-DA may include a plurality of light emitting areas PXA and a non-emission area NPXA surrounding the plurality of light emitting areas PXA. Area PXA and non-emission area NPXA may be disposed in common. A common layer such as the hole control layer HCL may be formed in common with the plurality of pixels PX. The hole control layer (HCL) may include a hole transport layer and a hole injection layer.

An organic light emitting layer (EML) is disposed on the hole control layer (HCL). The organic light emitting layer EML may be disposed only in an area corresponding to the opening OP. The organic light emitting layer EML may be separately formed in each of the plurality of pixels PX.

Although the patterned organic light emitting layer EML is illustrated as an example in this embodiment, the organic light emitting layer EML may be commonly disposed in a plurality of pixels PX. In this case, the organic light emitting layer EML may generate white light. Also, the organic light emitting layer EML may have a multilayer structure.

An electronic control layer (ECL) is disposed on the organic light emitting layer (EML). The electron control layer (ECL) may include an electron transport layer and an electron injection layer. A cathode CE is disposed on the electronic control layer ECL. The electronic control layer ECL and the cathode CE are commonly disposed in the plurality of pixels PX.

A thin film encapsulation layer TFE is disposed on the cathode CE. The thin film encapsulation layer TFE is commonly disposed in the plurality of pixels PX. In this embodiment, the thin film encapsulation layer TFE directly covers the cathode CE. In one embodiment of the present invention, a capping layer covering the cathode CE may be further disposed. In one embodiment of the present invention, the stacked structure of organic light emitting diodes (OLEDs) may have a structure that is upside down inverted from the structure shown in FIG. 3B.

The thin film encapsulation layer TFE includes at least an inorganic layer or an organic layer. In one embodiment of the present invention, the thin film encapsulation layer (TFE) may include two inorganic layers and an organic layer disposed therebetween. In one embodiment of the present invention, the thin film encapsulation layer may include a plurality of inorganic layers and a plurality of organic layers that are alternately stacked.

The encapsulating inorganic layer protects the organic light emitting diode (OLED) from moisture/oxygen, and the encapsulating organic layer protects the organic light emitting diode (OLED) from foreign substances such as dust particles. The encapsulation inorganic layer may include a silicon nitride layer, a silicon oxy nitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, and the like, but is not particularly limited thereto. The encapsulating organic layer may include an acryl-based organic layer, and is not particularly limited.

According to this embodiment, the first thin film transistor T1 may have high electron mobility by including a silicon semiconductor, particularly a polysilicon semiconductor. Leakage current is reduced because the second thin film transistor T2 includes an oxide semiconductor. Accordingly, the driving voltage of the pixel PX (see FIG. 3A) is reduced and malfunction is prevented.

According to an embodiment of the present invention, the first electrode E1 and the second electrode E2 of the capacitor Cst are formed through the same process as the configurations of the first thin film transistor T1, as shown in FIG. 3C. can be formed through

The first electrode E1 of the capacitor Cst may be disposed on the first insulating layer 10 . The first electrode E1 may be formed through the same process as the first control electrode GE1. Although not shown in cross section, the first electrode E1 may be connected to the first control electrode GE1. The second insulating layer covers the first electrode E1. The second electrode E2 of the capacitor Cst is disposed on the second insulating layer 20 .

Although not separately shown, in one embodiment of the present invention, the upper electrode UE may be electrically connected to the second electrode E2. Also, the upper electrode UE and the second electrode E2 may have an integral shape by being formed through the same process. A third insulating layer 30 covering the second electrode E2 and the upper electrode UE is disposed on the second insulating layer 20 .

Each of FIGS. 4A and 4B shows a cross section along the first direction DR1 of the curvature area CA of FIG. 2 . FIG. 4A shows a cross section overlapping the signal line DL, and FIG. 4B shows a cross section of an area where no signal line is disposed. 4A shows the data line DL as the signal line SGL.

As shown in FIGS. 4A and 4B , the second area BA has a stacked structure similar to that of the first area NBA, particularly the display area DP-DA, in cross section. The barrier layer BRL, the buffer layer BFL, and the first to sixth insulating layers 10 to 60 are sequentially disposed on the upper surface of the base layer BL.

A groove GV-1 (hereinafter referred to as a lower groove) overlapping the second region BA is defined in the barrier layer BRL and/or the buffer layer BFL. The lower groove GV-1 is defined in the curvature area CA. In other words, the inorganic layers BRL and BFL disposed below the first semiconductor pattern OSP1 (see FIGS. 3B and 3C ) overlap the display area DP-DA and extend into the second area BA. do. A lower groove GV-1 is defined in the inorganic layers BRL and BFL. The width of the base layer BL exposed by the lower groove GV- 1 in the first direction DR1 may be smaller than the width of the curvature area CA in the first direction DR1.

A groove GV-2 (hereinafter referred to as an upper groove) overlapping the second region BA is defined in the first to fourth insulating layers 10 to 40 . The upper groove GV-2 is defined in the curvature area CA. An upper surface of an uppermost inorganic layer among inorganic layers constituting the barrier layer BRL and the buffer layer BFL may be partially exposed from the first to fourth insulating layers 10 to 40 .

Side surfaces of the barrier layer BRL and the buffer layer BFL defining the lower groove GV- 1 may have a predetermined slope in cross section. Side surfaces of the first to fourth insulating layers 10 to 40 defining the upper groove GV- 2 may have a predetermined slope in cross section.

Although not separately shown, according to an embodiment of the present invention, unlike those shown in FIGS. 4A and 4B , the width of the upper groove GV-2 in the first direction DR1 corresponding to the fourth insulating layer 40 is may be greater than the width of the curvature area CA in the first direction DR1.

A fifth insulating layer 50 as an organic layer is disposed inside the lower groove GV-1 and the upper groove GV-2. The fifth insulating layer 50 contacts the upper surface of the base layer BL, the inclined surface of the lower groove GV-1, and the inclined surface of the upper groove GV-2. The fifth insulating layer 50 may contact a portion of the upper surface of the buffer layer BFL exposed from the first to sixth insulating layers 10 to 60 . By disposing the organic layer in the bending area, flexibility of the bending area is improved.

At least a portion of the signal line DL may be disposed on the fifth insulating layer 50 . The sixth insulating layer 60 covers the signal line DL to protect the signal line DL. Although not shown in FIG. 4A , another part of the signal line DL, particularly another part disposed in the display area DP-DA, may be disposed on another layer. For example, another part of the signal line DL may be disposed on the fourth insulating layer 40 . The part of the signal line DL and the other part may be connected through a contact hole penetrating the fifth insulating layer 50 . Such a contact hole may be disposed in the non-display area DP-NDA of the first area NBA.

In one embodiment of the present invention, a layer extending from the layer disposed in the display area DP-DA may be further disposed on the upper surface of the sixth insulating layer 60.

5A to 5M are cross-sectional views illustrating a manufacturing process of the display panel DP according to an embodiment of the present invention. 5A to 5M each show a comparison of regions corresponding to FIGS. 3B and 4A. Hereinafter, a detailed description of the same configuration as the configuration described with reference to FIGS. 1 to 4B will be omitted.

As shown in FIG. 5A , at least one inorganic layer is formed on the first area NBA and the second area BA of the base layer BL. Although not separately shown, in the manufacturing process, the base layer BL may be disposed on the working substrate. After the display panel is manufactured, the work substrate may be removed.

Inorganic layers may be formed by depositing, coating, or printing an inorganic material. The barrier layer BRL may be formed by sequentially forming a silicon oxide layer and a silicon nitride layer. The buffer layer BFL may be formed by sequentially forming a silicon oxide layer and a silicon nitride layer on the barrier layer BRL.

As shown in FIG. 5A , first preliminary semiconductor patterns OSP1-P are formed on the inorganic layer. After the semiconductor layer is formed, it is patterned to form the first preliminary semiconductor pattern OSP1-P. The semiconductor layer may be crystallized before/after patterning. Although not separately shown, doping may be performed on the first preliminary semiconductor pattern OSP1 -P.

Then, as shown in FIG. 5B , the first insulating layer 10 is formed on the first area NBA and the second area BA of the inorganic layer. The first insulating layer 10 may be formed by deposition, coating, or printing. Insulating layers disposed on the first insulating layer 10 may also be formed by deposition, coating, or printing.

A first control electrode GE1 is formed on the first insulating layer 10 . A conductive layer is formed on the first insulating layer 10 and then patterned to form the first control electrode GE1. The first electrode E1 of the capacitor Cst may be formed through the same process as the first control electrode GE1.

Thereafter, the first preliminary semiconductor pattern OSP1-P may be doped using the first control electrode GE1 as a mask. A region overlapping the first control electrode GE1 (hereinafter referred to as a channel region) is undoped, and regions on both sides of the channel region (an input region and an output region) are doped. In this embodiment, doping may be performed using an n-type dopant, that is, a pentavalent element. Accordingly, the first semiconductor pattern OSP1 is formed.

Then, as shown in FIG. 5C , a second insulating layer 20 is formed on the first area NBA and the second area BA of the first insulating layer 10 to cover the first control electrode GE1. form An upper electrode UE is formed on the second insulating layer 20 . The second electrode E2 of the capacitor Cst may be formed through the same process as the upper electrode UE.

Then, as shown in FIG. 5D , a third insulating layer 30 covering the upper electrode UE is formed on the first and second regions NBA and BA of the second insulating layer 20 . do. A second preliminary semiconductor pattern OSP2 - P is formed on the third insulating layer 30 . A second preliminary semiconductor pattern OSP2-P is formed from the semiconductor layer through a photolithography process.

Then, as shown in FIG. 5E , an intermediate insulating layer covering the second preliminary semiconductor pattern OSP2-P on the first and second regions NBA and BA of the third insulating layer 30 ( 35) form. A second control electrode GE2 is formed on the middle insulating layer 35 . The second control electrode GE2 is formed from the conductive layer through a photolithography process.

Then, as shown in FIG. 5F, an insulating pattern GIP is formed from the intermediate insulating layer 35 (FIG. 5E). The insulating pattern GIP may be formed by patterning the intermediate insulating layer 35 using an etching gas. At this time, the middle insulating layer 35 may be patterned using the second control electrode GE2 as a mask. Accordingly, the edges of the insulating pattern GIP and the second control electrode GE2 may be aligned.

Then, as shown in FIG. 5G , a fourth insulating layer 40 covering the second control electrode GE2 is formed on the first and second regions NBA and BA of the third insulating layer 30 . form A silicon oxide layer and a silicon nitride layer may be sequentially formed.

In the process of forming the fourth insulating layer 40 , regions exposed to the outside of the second preliminary semiconductor pattern OSP2 -P (refer to FIG. 5F ) may be reduced. Regions on both sides of the second preliminary semiconductor pattern OSP2 -P are reduced and defined as an input region and an output region. The input region and the output region may include a metal material reduced from a metal oxide semiconductor. A region overlapping the insulating pattern GIP disposed between the input region and the output region may be defined as a channel region. Accordingly, the second semiconductor pattern OSP2 is formed. Unlike the present embodiment, a separate reduction process may be additionally performed on the externally exposed regions of the second preliminary semiconductor pattern OSP2-P (refer to FIG. 5F).

Next, portions of the above-described insulating layers 10 to 40 are removed (hereinafter, a first etching step). Contact holes CH1 and CH2 exposing the input and output regions of the first semiconductor pattern OSP1 are formed. In the same process, the upper groove GV- 2 is formed by partially removing the second area BA of the first to fourth insulating layers 10 to 40 .

Then, as shown in FIG. 5H, other portions of the above-described insulating layers 10 to 40 and portions of the inorganic layers are removed (hereinafter, a second etching step). Contact holes CH3 CH4 exposing the input and output regions of the second semiconductor pattern OSP2 are formed. In the same process, the barrier layer BRL and the second region BA of the buffer layer BFL are partially removed. to form the lower groove (GV-1).

As shown in FIGS. 5G and 5H, contact holes CH1, CH2, CH3, and CH4 and grooves GV-1 and GV-2 may be formed using a mask and an etching gas or using a laser beam. can Since the corresponding contact hole and groove among the contact holes CH1, CH2, CH3, and CH4 and the grooves GV-1 and GV-2 are formed by the same process, the number of masks used in the manufacturing process can be reduced. have. Since the upper groove GV- 2 and the lower groove GV- 1 are formed by different processes, a step difference may be formed and a portion of the upper surface of the buffer layer BFL may be exposed from the insulating layers 10 to 40 .

Then, as shown in FIG. 5I , electrodes DE1 , SE1 , SE2 , and DE2 are formed on the fourth insulating layer 40 . The electrodes DE1 , SE1 , SE2 , and DE2 may be formed through a deposition process.

Then, as shown in FIG. 5J , a fifth insulating layer 50 covering the electrodes DE1 , SE1 , SE2 , and DE2 is formed on the fourth insulating layer 40 . A fifth insulating layer 50 is formed to overlap the first area NBA and the second area BA. The fifth insulating layer 50 is disposed inside the lower groove GV-1 and the upper groove GV-2. A fifth contact hole CH5 exposing the first output electrode SE1 may be formed in the fifth insulating layer 50 .

Then, as shown in FIG. 5K , a connection electrode CNE is formed on the fifth insulating layer 50 . A portion overlapping the second area BA of the signal line DL is formed through the same process as the connection electrode CNE.

Thereafter, as shown in FIG. 5L, the sixth insulating layer 60 covers a portion overlapping the connection electrode CNE and the second area BA of the signal line DL on the fifth insulating layer 50. ) to form A sixth contact hole CH6 exposing an upper surface of the connection electrode CNE may be formed in the sixth insulating layer 60 .

Next, as shown in FIG. 5M , an organic light emitting diode (OLED) is formed on the sixth insulating layer 60 . An anode AE connected to the connection electrode CNE through the sixth contact hole CH6 is formed on the sixth insulating layer 60 . A pixel defining layer PDL exposing a central portion of the anode AE is formed on the sixth insulating layer 60 . A pre-pixel defining layer is formed on the sixth insulating layer 60 . An opening OP is formed in the pre-pixel defining layer.

Thereafter, a hole control layer HCL, an emission layer EML, an electron control layer ECL, and a cathode CE are sequentially formed on the first region NBA of the pixel defining layer PDL. The hole control layer (HCL), the light emitting layer (EML), the electron control layer (ECL), and the cathode (CE) overlap at least the display area (DP-DA, see FIG. 2) on a plane.

A thin film encapsulation layer TFE is formed on the cathode CE. An encapsulation organic layer and/or an encapsulation inorganic layer is formed by a vapor deposition process, an inkjet printing process, or the like. The thin film encapsulation layer TFE is formed on the first area NBA and is not disposed on the second area BA.

6 to 9 are cross-sectional views corresponding to portions of the display panel DP according to an exemplary embodiment. 6 to 9 show cross-sections corresponding to FIG. 5M. Hereinafter, a detailed description of the same configuration as the configuration described with reference to FIGS. 1 to 5M will be omitted.

As shown in FIG. 6 , the connection electrode CNE and the sixth insulating layer 60 may be omitted. The anode AE may be directly disposed on the fifth insulating layer 50 and connected to the first output electrode SE1 through the fifth contact hole CH5. A portion of the signal line DL overlapping the second area BA is also directly disposed on the fifth insulating layer 50 .

A portion of the signal line DL overlapping the second area BA may be formed through the same process as that of the anode AE. A portion of the signal line DL overlapping the second area BA and the anode AE may include the same material and have the same layer structure.

As shown in FIG. 7 , an intermediate insulating layer 35 may be further disposed between the third insulating layer 30 and the fourth insulating layer 40 . The middle insulating layer 35 may overlap the first area NBA and the second area BA.

Openings 35 -OP corresponding to the input and output regions of the second semiconductor pattern OSP2 may be formed in the middle insulating layer 35 . As shown in FIG. 5E , after forming the middle insulating layer 35 and the second control electrode GE2 , openings 35 -OP are formed. After that, a fourth insulating layer is formed. The upper groove GV- 2 is formed by removing the middle insulating layer 35 as well as the first to fourth insulating layers 10 to 40 .

In one embodiment of the present invention, the openings 35 -OP of the middle insulating layer 35 are not formed through a separate process, and the third openings 35 -OP pass through the middle insulating layer 35 and the fourth insulating layer 40 . A contact hole CH3 and a fourth contact hole CH4 may be formed.

As shown in FIG. 8 , the upper electrode UE and the second control electrode GE2 may include the same material and have the same stacked structure. The upper electrode UE and the second control electrode GE2 may be formed from the same conductive layer.

The upper electrode UE may not be formed in the step shown in FIG. 5c but may be formed in the process of FIG. 5e. However, after forming the intermediate insulating layer 35 shown in FIG. 5E and before forming the conductive layer, the insulating pattern GIP is formed by patterning the intermediate insulating layer 35 . A conductive layer covering the insulating pattern GIP may be formed on the third insulating layer 30 , and the conductive layer may be patterned to form the upper electrode UE and the second control electrode GE2 . Although not shown, the second electrode E2 may also be formed through the same process as the upper electrode UE.

As shown in FIG. 9 , the upper electrode UE and the second control electrode GE2 may be disposed on the same layer, include the same material, and have the same stacked structure. The upper electrode UE and the second control electrode GE2 may be formed from the same conductive layer.

In order to form the display panel DP shown in FIG. 9 , the upper electrode UE may be formed in the process of FIG. 5E instead of being formed in the step shown in FIG. 5C . When the second control electrode GE2 is formed from the conductive layer after the conductive layer is formed on the intermediate insulating layer 35, the upper electrode UE is formed in the same process as the second control electrode GE2. Thereafter, the middle insulating layer 35 may be etched using the second control electrode GE2 and the upper electrode UE as a mask.

A first insulating pattern GIP1 and a second insulating pattern GIP2 overlapping the second control electrode GE2 and the upper electrode UE, respectively, are formed from the middle insulating layer 35 shown in FIG. 5E. An edge of the second insulating pattern GIP2 may be aligned with an edge of the upper electrode UE. The upper electrode UE may have the same shape as the second insulating pattern GIP2 on a plane.

10A to 10G are cross-sectional views corresponding to portions of the display panel DP according to an exemplary embodiment. 10A to 10G show cross-sections corresponding to those in FIG. 5M. Hereinafter, a detailed description of the same configuration as the configuration described with reference to FIGS. 1 to 9 will be omitted.

As shown in FIGS. 10A to 10G , the display panel DP is disposed between the buffer layer BFL and the first insulating layer 10 and includes a light blocking pattern LSP overlapping the second semiconductor pattern OSP2. can include more.

The light blocking pattern LSP may include a material having high light absorptivity or a material having high light reflectance. The light blocking pattern LSP is disposed under the second semiconductor pattern OSP2 to block light incident from the outside from reaching the second semiconductor pattern OSP2. This is to prevent external light from changing the voltage-current characteristics of the second semiconductor pattern OSP2 to generate leakage current.

As shown in FIG. 10A , the light blocking pattern LSP may include the same material as the first semiconductor pattern OSP1. Specifically, the light blocking pattern LSP may include a doped crystalline semiconductor pattern.

The light-blocking pattern LSP may be formed in the same process as the first preliminary semiconductor pattern OSP1-P shown in FIG. 5A. After that, the light blocking pattern LSP may be doped in the process shown in FIG. 5B.

As shown in FIG. 10B , the light blocking pattern LSP may include the same material as the first control electrode GE1. The light blocking pattern LSP may be formed in the same process as the first control electrode GE1 shown in FIG. 5B. As shown in FIG. 10C , the light blocking pattern LSP may include the same material as the upper electrode UE. The light blocking pattern LSP may be formed in the same process as that of the upper electrode UE shown in FIG. 5C. The light blocking pattern LSP may have a single-layer or multi-layer structure. The light blocking pattern LSP may have the same stack structure as the first control electrode GE1 or the same stack structure as the upper electrode UE. The light blocking pattern LSP may include a molybdenum layer similar to the first control electrode GE1.

In FIGS. 10A to 10C , the light blocking pattern LSP may be a floating electrode. Unlike those shown in FIGS. 10A to 10C , the light blocking pattern LSP described below may receive a predetermined voltage/a predetermined signal.

As shown in FIGS. 10D to 10F , the light blocking pattern LSP may be connected to the signal line SGL-P. A signal line SGL-P disposed on the same layer as the first input electrode DE1 and formed in the same process is illustrated as an example. The light blocking pattern LSP and the signal line SGL-P may be connected through the seventh contact hole CH7 penetrating the first to fourth insulating layers 10 to 40 .

As shown in FIG. 10E , the light blocking pattern LSP is disposed on the first insulating layer 10 , and the light blocking pattern LSP and the signal line SGL-P are disposed on the second to fourth insulating layers 20 to 40) may be connected through the seventh contact hole CH7 penetrating through. As shown in FIG. 10F , the light blocking pattern LSP is disposed on the second insulating layer 20 , and the light blocking pattern LSP and the signal line SGL-P are disposed on the third and fourth insulating layers 30 to 40) may be connected through the seventh contact hole CH7 penetrating through.

The light-shielding pattern LSP shown in FIG. 10E forms a lower step in the third insulating layer 30 than the light-shielding pattern LSP shown in FIG. 10F. In addition, diffusion of impurities from the light blocking pattern LSP into the third insulating layer 30 contacting the second semiconductor pattern OSP2 may be prevented. As shown in FIG. 10E , since the light blocking pattern LSP is covered by the second insulating layer 20 , a pure third insulating layer 30 may be deposited. The second insulating layer 20 may be a silicon nitride layer, and the third insulating layer 30 may be a silicon oxide layer.

The threshold voltage of the second thin film transistor T2 may have a different value from a desired value due to process errors. At this time, the threshold voltage of the second thin film transistor T2 may be controlled by applying a predetermined bias voltage to the light blocking pattern LSP shown in FIGS. 10D to 10F. For example, when the threshold voltage of the second thin film transistor T2 is negative than a desired value, leakage current of the second thin film transistor T2 may increase. At this time, a negative shift phenomenon of the threshold voltage of the second thin film transistor T2 may be compensated for by applying a bias voltage to the light blocking pattern LSP of the second thin film transistor T2.

As shown in FIG. 10G , the signal line SGL-P may be connected to the second control electrode GE2 through the eighth contact hole CH8. The signal line SGL-P may electrically connect the light blocking pattern LSP of the crystalline semiconductor pattern and the second control electrode GE2. At this time, the light blocking pattern LSP may serve as a control electrode for controlling the movement of charges in the channel region of the second semiconductor pattern OSP2. In other words, the second thin film transistor T2 includes two control electrodes electrically connected to each other. The two control electrodes receive the same signal. Although not separately shown, the light blocking pattern LSP shown in FIG. 10G may be disposed on another layer as shown in FIGS. 10E and 10F.

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art or those having ordinary knowledge in the art do not deviate from the spirit and technical scope of the present invention described in the claims to be described later. It will be understood that the present invention can be variously modified and changed within the scope not specified.

Therefore, the technical scope of the present invention is not limited to the contents described in the detailed description of the specification, but should be defined by the claims.

T1: first thin film transistor T2: first thin film transistor
OLED: organic light emitting diode DE1, DE2: input electrode
SE1, SE2: output electrode GE1, GE2: control electrode
OSP1, OSP2: semiconductor pattern

Claims (19)

a base layer including a first region and a second region bent from the first region;
at least one inorganic layer overlapping the first region and the second region and disposed on the base layer;
a first thin film transistor disposed on the at least one inorganic layer and including a silicon semiconductor pattern overlapping the first region;
A second layer comprising an oxide semiconductor pattern overlapping the first region, a control electrode disposed on the oxide semiconductor pattern, an input electrode and an output electrode disposed on the semiconductor pattern, and disposed on the at least one inorganic layer. thin film transistor;
insulating layers overlapping the first region and the second region;
a signal line electrically connected to the second thin film transistor;
a light blocking pattern disposed between the at least one inorganic layer and the oxide semiconductor pattern of the second thin film transistor and overlapping the oxide semiconductor pattern of the second thin film transistor;
an organic layer overlapping the first region; and
A light emitting device disposed on the organic layer to overlap the first region,
A display panel in which openings are defined in the at least one inorganic layer and the insulating layers to overlap the second region. According to claim 1,
The light blocking pattern is a display panel having conductivity. According to claim 2,
The light blocking pattern is a display panel that receives a bias voltage. According to claim 2,
The light blocking pattern is electrically connected to the control electrode of the second thin film transistor. According to claim 1,
The signal line overlaps the first area and the second area. According to claim 1,
The display panel further includes a connection electrode disposed on the organic layer and connected to an output electrode of the first thin film transistor through a contact hole penetrating the organic layer. According to claim 6,
Further comprising a passivation layer disposed on the organic layer,
The electrode of the light emitting element is connected to the connection electrode through a contact hole penetrating the passivation layer. According to claim 1,
The insulating layers are
a first insulating layer covering the silicon semiconductor pattern of the first thin film transistor;
a second insulating layer disposed on the first insulating layer and covering the control electrode of the first thin film transistor;
a third insulating layer disposed on the second insulating layer; and
and a fourth insulating layer disposed on the third insulating layer and covering the control electrode of the second thin film transistor overlapping the oxide semiconductor pattern of the second thin film transistor. According to claim 8,
The display panel further includes an upper electrode disposed between the second insulating layer and the third insulating layer and overlapping the control electrode of the first thin film transistor. According to claim 9,
An insulating pattern disposed between the oxide semiconductor pattern of the second thin film transistor and the control electrode of the second thin film transistor,
The insulating pattern partially overlaps the oxide semiconductor pattern of the second thin film transistor. According to claim 9,
The insulating layers are
It is disposed between the third insulating layer and the fourth insulating layer, partially covers the oxide semiconductor pattern of the second thin film transistor, and defines openings exposing both ends of the oxide semiconductor pattern of the second thin film transistor. A display panel further comprising an insulating layer. According to claim 9,
The display panel further includes an upper electrode disposed between the third insulating layer and the fourth insulating layer and overlapping the control electrode of the first thin film transistor. According to claim 12,
The display panel further comprises an insulating pattern disposed between the third insulating layer and the upper electrode. According to claim 8,
The light blocking pattern is disposed between the at least one inorganic layer and the first insulating layer, and includes the same material as the silicon semiconductor pattern. According to claim 8,
The light blocking pattern is disposed between the first insulating layer and the second insulating layer, and includes the same material as the control electrode of the first thin film transistor. According to claim 8,
The second insulating layer includes silicon oxide and contacts the light blocking pattern. According to claim 8,
Further comprising an upper electrode disposed between the second insulating layer and the third insulating layer and overlapping the control electrode of the first thin film transistor,
The light blocking pattern is disposed between the second insulating layer and the third insulating layer, and includes the same material as the upper electrode. According to claim 1,
The at least one inorganic layer includes a plurality of inorganic layers,
The plurality of inorganic layers include silicon oxide layers and silicon nitride layers alternately disposed with the silicon oxide layers. a base layer including a first region and a second region bent from the first region;
at least one inorganic layer overlapping the first region and the second region and disposed on the base layer;
a first thin film transistor disposed on the at least one inorganic layer and including a silicon semiconductor pattern overlapping the first region;
A second layer comprising an oxide semiconductor pattern overlapping the first region, a control electrode disposed on the oxide semiconductor pattern, an input electrode and an output electrode disposed on the semiconductor pattern, and disposed on the at least one inorganic layer. thin film transistor;
insulating layers overlapping the first region and the second region;
a signal line electrically connected to the second thin film transistor;
a light blocking pattern disposed between the at least one inorganic layer and the oxide semiconductor pattern of the second thin film transistor and overlapping the oxide semiconductor pattern of the second thin film transistor;
an organic layer overlapping the first region; and
A light emitting element disposed on the organic layer to overlap the first region,
A display panel in which grooves are defined in the at least one inorganic layer and the insulating layers to overlap the second region.

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