KR20220155847A - Nonvolatile memory device - Google Patents

Abstract

One embodiment relates to a non-volatile memory device, which includes: a substrate; and a memory cell array provided on the substrate. The memory cell array includes: a connector block through which a contact passes; a first memory block disposed adjacent to the connector block; and a second memory block spaced apart from the connector block with the first memory block interposed therebetween and having a higher importance than the first memory block.

Description

Non-volatile memory device {NONVOLATILE MEMORY DEVICE}

[0001] The present invention relates to semiconductor technology, and more particularly to non-volatile memory devices.

In non-volatile memory devices, data retention is an important reliability concern. The charge stored in the memory cell may be lost by various mechanisms such as thermal ion release, charge diffusion, program disturb stress, and the like. Loss of charge in memory cells can cause data retention problems.

As lifespan increases, memory cells may face data retention problems. When a threshold voltage distribution of a memory cell is degraded due to a data retention problem, stored data may be damaged or the nonvolatile memory device may become inoperable and reliability may deteriorate. Therefore, efforts are required to suppress the reliability degradation of the nonvolatile memory device due to the data retention problem.

Embodiments of the present invention may provide a non-volatile memory device capable of improving reliability.

A non-volatile memory device according to an embodiment of the present invention includes a substrate; and a memory cell array provided on the substrate, wherein the memory cell array includes: a connector block through which a contact passes; a first memory block disposed adjacent to the connector block; and a second memory block that is spaced apart from the connector block with the first memory block interposed therebetween and has a higher importance than the first memory block.

A non-volatile memory device according to an embodiment of the present invention includes a memory structure including a memory cell array; and a peripheral structure overlapping the memory structure in a vertical direction and including a peripheral circuit for controlling the memory cell array, wherein the memory cell array includes: a connector block through which a contact passes; a first memory block disposed adjacent to the connector block; and a second memory block having a higher priority than the first memory block and spaced apart from the connector block with the first memory block interposed therebetween. can include

In one embodiment, the first memory block may include a dummy block that does not store data, and the second memory block may include a data block that stores data. Exemplarily, the data blocks include a CAM block for storing cam data, a user block for storing user data, and a reserved block for replacing user blocks that have become bad blocks. can include

In another embodiment, the first memory block may include a spare block, and the second memory block may include a cam block. In another embodiment, the first memory block may include a spare block, and the second memory block may include a user block.

According to embodiments of the present invention, data retention characteristics of data blocks for storing data may be improved, and thus reliability degradation of a nonvolatile memory device due to data corruption may be prevented.

According to the embodiments of the present invention, since the data retention characteristics of the cam block can be improved, reliability degradation and malfunction of the non-volatile memory device due to cam data corruption can be prevented.

According to the exemplary embodiments of the present invention, since the data retention characteristics of the user block can be improved, deterioration of the threshold voltage distribution of memory cells of the user block can be suppressed or prevented. Therefore, the performance of the nonvolatile memory device can be improved by reducing the time required for a read retry operation in which a read voltage is changed and read in order to determine the threshold voltage distribution of deteriorated memory cells.

1 is a block diagram illustrating a block arrangement of a memory cell array of a nonvolatile memory device according to an exemplary embodiment of the present invention.
2 is a plan view illustrating a portion of a memory cell array of a nonvolatile memory device according to an exemplary embodiment of the present invention.
FIG. 3 is a cross-sectional view taken along line II' of FIG. 2 .
4 is a block diagram of a non-volatile memory device according to an embodiment of the present invention.
5 is a schematic perspective view of a nonvolatile memory device according to an embodiment of the present invention.
6 is a plan view illustrating an internal arrangement of the periphery structure of FIG. 5 and a page buffer circuit included in the periphery structure.
FIG. 7 is a plan view illustrating block arrangement of the cell structure and memory cell array of FIG. 5 .
8 is a block diagram illustrating a memory system including a nonvolatile memory device according to an embodiment of the present invention.
9 is a block diagram schematically illustrating a computing system including a non-volatile memory device according to an embodiment of the present invention.

Advantages and features of the present invention, and methods for achieving them, will become clear with reference to the detailed description of the following embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be embodied in a variety of different forms, and only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention pertains. It is provided to completely inform the person who has the scope of the invention, and the present invention is only defined by the scope of the claims.

In addition, since the shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, the present invention is not limited to the matters shown. Like reference numbers designate like elements throughout the specification. In addition, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in this specification is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, it may include the case of including the plural unless specifically stated otherwise.

In addition, in interpreting the components in the embodiments of the present invention, even if there is no separate explicit description, it should be interpreted as including an error range.

Also, terms such as first, second, A, B, (a), and (b) may be used in describing the components of the present invention. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the corresponding component is not limited by the term. Also, components in the embodiments of the present invention are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may also be the second component within the technical spirit of the present invention.

When an element is described as being “connected,” “coupled to,” or “connected” to another element, that element is or may be directly connected to that other element, but intervenes between each element. It will be understood that may be "interposed", or each component may be "connected", "coupled" or "connected" through other components. In the case of a description of a positional relationship, for example, 'on top of', 'on top of', 'at the bottom of', 'next to', etc. Or, unless 'directly' is used, one or more other parts may be located between the two parts.

In addition, the features (configurations) in the embodiments of the present invention can be partially or entirely combined, combined or separated from each other, technically various interlocking and driving operations are possible, and each embodiment is implemented independently of each other. It may be possible or it may be possible to implement together in an association relationship.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a block arrangement of a memory cell array of a nonvolatile memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 1 , a nonvolatile memory device (NVM device) 100 may include a memory cell array (Memory Cell Array) 110 including a plurality of memory cells that store data.

The non-volatile memory device 100 includes a NAND flash memory device, a NOR flash memory device, a ferroelectric random access memory (FRAM) using a ferroelectric capacitor, and a Tunneling Magneto-Resistive (TMR) film. Magnetic Random Access Memory (MRAM) using chalcogenide alloys, Phase Change Random Access Memory (PCRAM) using chalcogenide alloys, Resistive Random Access RAM using transition metal oxide Memory, ReRAM), etc. may be configured as any one of various types of non-volatile memory devices. In this specification, for convenience of description, it will be described assuming that the nonvolatile memory device 100 is a vertical NAND flash memory.

The memory cell array 110 includes a connector block CONNECT BLK through which contacts pass, first memory blocks MEMORY BLK1 disposed adjacent to the connector block CONNECT BLK, and the first memory block MEMORY BLK1. It may include second memory blocks MEMORY BLK2 that are spaced apart from the connector block CONNECT BLK and have a higher importance than the first memory blocks MEMORY BLK1.

As described below with reference to FIGS. 2 and 3 , the first memory blocks MEMORY BLK1 and the second memory blocks MEMORY BLK2 may include a plurality of memory cells. The number and arrangement structure of memory cells of the first memory block MEMORY BLK1 may be substantially the same as the number and arrangement structure of memory cells of the second memory block MEMORY BLK2 . The first memory blocks MEMORY BLK1 and the second memory blocks MEMORY BLK2 may be designed to have substantially the same or similar structures and shapes.

The connector block CONNECT BLK serves to provide a contact arrangement space, and as will be described later with reference to FIGS. 2 and 3, the first memory blocks MEMORY BLK1 and the second memory blocks MEMORY BLK2 ) and may have a different structure and shape.

In one embodiment, the connector block CONNECT BLK may not include memory cells. In another embodiment, the connector block CONNECT BLK may include a dummy cell. A dummy cell has the same or similar structure and shape as a memory cell, but does not perform a practical function and exists only as a pattern, and does not store data. The number and arrangement structure of dummy cells in the connector block CONNECT BLK may be different from the number and arrangement structure of memory cells in the first memory block MEMORY BLK1, and the number of memory cells in the second memory block MEMORY BLK2. and an array structure.

Due to the influence of the connector block CONNECT BLK having a different structure and shape from the first memory blocks MEMORY BLK1 and the second memory blocks MEMORY BLK2, the first memory adjacent to the connector block CONNECT BLK The blocks MEMORY BLK1 may have different pattern densities from the second memory blocks MEMORY BLK2 that are not adjacent to the connector block CONNECT BLK.

Due to the difference in pattern density, a loading effect may occur throughout the manufacturing process of the memory cell array 110, such as a photolithography process, an etching process, a chemical mechanical polishing process, a deposition process, and a cleaning process. The loading effect means a process imbalance caused by a difference in pattern density. Due to the loading effect, the memory cells of the first memory blocks MEMORY BLK1 may have non-uniform critical dimensions, and the first memory block may have a non-uniform critical dimension. The memory cells of MEMORY BLK1 may be vulnerable to a data retention problem. On the other hand, the memory cells of the second memory blocks MEMORY BLK2 may have a uniform critical dimension, and the memory cells of the second memory blocks MEMORY BLK2 may correspond to the memory cells of the first memory blocks MEMORY BLK1. It may have excellent data retention characteristics compared to

In an embodiment, the first memory block MEMORY BLK1 may be a dummy block that does not store data, and the second memory block MEMORY BLK2 may be a data block that stores data. have. Exemplarily, the data blocks include a CAM block for storing cam data, a user block for storing user data, and a reserved block for replacing user blocks that have become bad blocks. may include one of

A dummy block has the same or similar structure and shape as a data block, but does not perform a practical function and exists only as a pattern. Data is not stored in the dummy block.

Since no data is stored in the dummy block, data stored in the nonvolatile memory device 100 will not be damaged even if the dummy block has a structure vulnerable to a data retention problem. Data retention characteristics of dummy blocks may not affect reliability and performance of the nonvolatile memory device 100 . On the other hand, data stored in the non-volatile memory device 100 may be damaged if the data block has a structure vulnerable to a data retention problem. Data retention characteristics of data blocks may directly affect reliability and performance of the nonvolatile memory device 100 . A data block may be defined as having a higher importance than a dummy block.

According to an embodiment, since data is not stored in the first memory blocks MEMORY BLK1, which are vulnerable to the data retention problem, and data is stored in the second memory blocks MEMORY BLK2, which have excellent data retention characteristics, Reliability and performance of the nonvolatile memory device 100 may be improved by suppressing data corruption caused by a data retention problem.

In another embodiment, the second memory block MEMORY BLK2 may store data having a higher importance than the data stored in the first memory block MEMORY BLK1. For example, the second memory block MEMORY BLK2 may be a cam block, and the first memory block MEMORY BLK1 may be a spare block.

CAM data may include parameters related to the operation of the non-volatile memory device 100 . For example, the cam data may include parameters related to at least one operation among a read operation, a program operation, and an erase operation. Parameters related to at least one operation may include a read voltage, a program voltage, an initial voltage of an incremental step pulse program (ISPP), an increase voltage of the ISPP, an erase voltage, and voltage application time information. Cam data may include repair information.

When power is supplied and a reset command is input from the memory controller. The nonvolatile memory device 100 may load the cam data stored in the cam block into a system register in response to a reset command, and thus the cam data stored in the cam block may be used for the operation of the nonvolatile memory device 100. .

As lifespan elapses, memory cells of the nonvolatile memory device 100 may face a data retention problem. CAM data stored in the CAM block may be damaged due to data retention problems. If the cam data is corrupted, the non-volatile memory device 100 may become inoperable. Although user data stored in the spare block may be damaged due to a data retention problem, the non-volatile memory device 100 may not become inoperable due to user data corruption.

A higher tolerance for data corruption can be tolerated for user data compared to cam data. The effect of the data retention problem of the CAM block on the reliability of the nonvolatile memory device 100 is greater than the effect of the data retention problem of the spare block on the reliability of the nonvolatile memory device 100 . Cam data may be defined as having a higher importance than user data, and cam blocks may be defined as having a higher importance than preliminary blocks.

According to another embodiment, data of high importance is stored in the second memory block MEMORY BLK2 having excellent data retention characteristics, and data of low importance is stored in the first memory block MEMORY BLK1 which is vulnerable to the data retention problem. Therefore, the reliability of the nonvolatile memory device 100 can be improved and the possibility of occurrence of a functional error of the nonvolatile memory device 100 can be reduced under the same resource.

In another embodiment, the second memory block MEMORY BLK2 may be a user block, and the first memory block MEMORY BLK1 may be a spare block.

When a read operation fails due to a change in threshold voltage distribution of a memory cell, the nonvolatile memory device 100 may perform a read retry operation in which a read voltage level is changed and read again. When the number of error bits generated by performing the read operation with the changed read voltage becomes less than or equal to the number of correctable error bits, the read operation may be passed. When the number of error bits is greater than the number of correctable error bits, a read retry operation may be additionally performed by changing the read voltage level. A user block having an error out of tolerance becomes a bad block, and the user block that becomes a bad block may be replaced with a spare block.

User blocks are used first, and user blocks that have become bad blocks due to failure to pass the read retry operation are replaced with spare blocks, so if user blocks are vulnerable to data retention problems, the time required for the read retry operation increases. , the probability of occurrence of a bad block will increase and the number of spare blocks required will increase. On the other hand, when the user blocks have excellent data retention characteristics, the time required for the read retry operation is shortened, and the probability of occurrence of a bad block is reduced, resulting in a small number of required preliminary blocks. If the time required for the read retry operation increases, the performance of the nonvolatile memory device 100 deteriorates, and if the number of spare blocks increases under the same resource, the number of user blocks decreases, thereby reducing the availability of the nonvolatile memory device 100. capacity will decrease.

The effect of the data retention problem of the user block on the performance of the nonvolatile memory device 100 is greater than the effect of the data retention problem of the spare block on the performance of the nonvolatile memory device 100 . A user block may be defined as having a higher importance than a preliminary block.

According to another embodiment, the second memory block MEMORY BLK2, which has excellent data retention characteristics, is configured as a user block, and the first memory block (MEMORY BLK1), which is vulnerable to the data retention problem, is constituted as a spare block, so that the read recovery Since the time required for the try operation can be reduced and the probability of bad block occurrence can be reduced, performance of the nonvolatile memory device 100 can be improved and usable capacity of the nonvolatile memory device 100 can be improved.

FIG. 2 is a plan view illustrating a portion of a memory cell array of a nonvolatile memory device according to an exemplary embodiment of the present invention, and FIG. 3 is a cross-sectional view taken along line II′ of FIG. 2 .

Referring to FIGS. 2 and 3 , a nonvolatile memory device according to an embodiment of the present invention may include a substrate 10 and a memory cell array 110 provided on the substrate 10 .

The substrate 10 may have an upper surface extending in the first direction FD and the second direction SD. For example, the first direction FD may be an extension direction of bit lines and an arrangement direction of word lines, and a second direction SD may be an arrangement direction of bit lines and an extension direction of word lines. The first direction FD and the second direction SD may be orthogonal to each other. A direction that protrudes vertically from the upper surface of the substrate 10 may be defined as a vertical direction (VD).

The memory cell array 110 may be provided on the upper surface of the substrate 10 . The memory cell array 110 may include a plurality of electrode layers 20 and a plurality of interlayer insulating layers 22 alternately stacked on the top surface of the substrate 10 . The electrode layers 20 may include a semiconductor (ex, doped silicon, etc.), a metal (ex, tungsten, copper, aluminum, etc.), a conductive metal nitride (ex, titanium nitride, tantalum nitride, etc.) or a transition metal (ex, titanium, tantalum, etc.) and the like. The interlayer insulating layers 22 may include silicon oxide.

The plurality of electrode layers 20 and the plurality of interlayer insulating layers 22 are separated in block units by the plurality of slits SLT, thereby forming a connector block CONNECT BLK and first memory blocks MEMORY BLK1. and second memory blocks MEMORY BLK2 may be configured.

Each of the first memory blocks MEMORY BLK1 may be disposed adjacent to the connector block CONNECT BLK. A pair of first memory blocks MEMORY BLK1 may be disposed adjacent to both edges of the connector block CONNECT BLK in the first direction FD.

Each of the second memory blocks MEMORY BLK2 may be spaced apart from the connector block CONNECT BLK with at least one first memory block MEMORY BLK1 interposed therebetween.

Each of the first memory blocks MEMORY BLK1 and the second memory blocks MEMORY BLK2 may include a plurality of cell plugs CP. The cell plug CP may extend to the substrate 10 by penetrating the plurality of electrode layers 20 and the plurality of interlayer insulating layers 22 in the vertical direction VD.

The cell plug CP may include a filling layer FI, a channel layer CL surrounding the filling layer FI, and a memory layer ML surrounding the channel layer CL. The filling layer FI, the channel layer CL, and the memory layer ML may extend in the vertical direction VD to pass through the plurality of electrode layers 22 and the plurality of interlayer insulating layers 24 .

The filling layer FI may include an insulating material. For example, the filling layer FI may include oxide. The channel layer CL may include a semiconductor material. For example, the channel film CL may include polysilicon. The memory layer ML may include a tunnel insulating layer surrounding the channel layer CL, a data storage layer surrounding the tunnel insulating layer, and a blocking layer surrounding the data storage layer. The tunnel insulating layer may include a material capable of charge tunneling. For example, the tunnel insulating layer may include oxide. In one embodiment, the data storage layer may include a material capable of trapping charges. For example, the data storage layer may include nitride. In another embodiment, the data storage layer may include various materials according to data storage methods. For example, the data storage layer may include silicon, a phase change material, or nanodots. The blocking layer may include a material capable of blocking the movement of charges. For example, the blocking layer may include oxide.

The electrode layers 22 may include at least one source select line, at least one drain select line, and a plurality of word lines. At least one source selection transistor, a plurality of memory cells, and at least one drain selection transistor may be disposed along one cell plug CP in a vertical direction VD to form one cell string.

The memory cells are single-level cells (SLC) each storing one data bit, multi-level cells (MLC) storing two data bits, and triple-level cells storing three data bits. It can be composed of a Triple Level Cell (TLC) or a Quad Level Cell (QLC) capable of storing four data bits.

A plurality of cell plugs CP may be provided in a plurality of rows in each of the first memory blocks MEMORY BLK1 and MEMORY BLK2 . The number of cell plugs CP of the first memory block MEMORY BLK1 and the number of cell plugs CP of the second memory block MEMORY BLK2 may be substantially equal to each other. The arrangement structure of the cell plugs CP of the first memory block MEMORY BLK1 and the arrangement structure of the cell plugs CP of the second memory block MEMORY BLK2 may be substantially the same.

2 illustrates that each of the first and second memory blocks MEMORY BLK1 and MEMORY BLK2 includes four cell plug rows, but is not limited thereto. As another example, the number of cell plug rows included in each of the first memory blocks MEMORY BLK1 and the second memory blocks MEMORY BLK2 may vary, such as 8, 12, 16, or 19.

The connector block CONNECT BLK may include a plurality of interlayer insulating layers 22 and a plurality of insulating layers 24 that are alternately stacked. The contact CNT may pass through the plurality of interlayer insulating layers 22 and the plurality of insulating layers 24 in the vertical direction VD. The plurality of insulating layers 24 may insulate between the contact CNT and the plurality of electrode layers 20 . As shown in FIGS. 2 and 3 , the connector block CONNECT BLK may not include cell plugs and memory cells.

Although not shown, the connector block CONNECT BLK may include dummy cell plugs. The dummy cell plug has the same or similar structure and shape as the cell plug, but exists only as a pattern and does not have a practical function. The number of dummy cell plugs of the connector block CONNECT BLK corresponds to the number of cell plugs CP of the first memory block MEMORY BLK1 and the number of cell plugs CP of the first memory block MEMORY BLK2. can be different. The arrangement structure of the dummy cell plugs of the connector block CONNECT BLK is the arrangement structure of the cell plugs CP of the first memory block MEMORY BLK1 and the cell plugs CP of the second memory block MEMORY BLK2. It can be different from the array structure.

As such, since the connector block CONNECT BLK has a different structure and shape from the first memory blocks MEMORY BLK1 and the second memory blocks MEMORY BLK2, the first memory adjacent to the connector block CONNECT BLK The blocks MEMORY BLK1 may have a pattern density different from that of the second memory blocks MEMORY BLK2 .

As described above with reference to FIG. 1 , memory cells of the first memory blocks MEMORY BLK1 may have non-uniform critical dimensions due to a loading effect according to a pattern density difference, and the first memory blocks MEMORY BLK1 The memory cells of may be vulnerable to data retention problems. Meanwhile, the memory cells of the second memory blocks MEMORY BLK2 may have a uniform critical dimension, and the memory cells of the second memory blocks MEMORY BLK2 may correspond to the memory cells of the first memory blocks MEMORY BLK1. It may have excellent data retention characteristics compared to

4 is a block diagram of a non-volatile memory device according to an embodiment of the present invention.

Referring to FIG. 4 , a nonvolatile memory device 100 according to an exemplary embodiment may include a memory cell array 110 and a peripheral circuit 120 . The peripheral circuit 120 includes a row decoder (X-DEC, 121), a page buffer circuit (PB circuit, 122), a control logic (Control Logic, 123), a voltage generator (Voltage Generator, 124), and an input/output circuit (IO circuit, 125) may be included.

As described above with reference to FIGS. 1 to 3 , the memory cell array 110 may include a connector block and a plurality of memory blocks. The plurality of memory blocks may include a plurality of first memory blocks and a plurality of second memory blocks having a higher importance than the first memory blocks.

The memory cell array 110 may be connected to the row decoder 121 through a plurality of word lines WL. The memory cell array 110 may be connected to the page buffer circuit 122 through a plurality of bit lines BL. The memory cell array 110 stores data received through the page buffer circuit 122 through the bit lines BL during a program operation, and stores the stored data through the bit lines BL during a read operation. (122).

The row decoder 121 may select one of a plurality of memory blocks in response to the row address RADD from the control logic 123, and convert the operating voltage Vop from the voltage generator 124 to a word of the selected memory block. It can be transmitted to the lines WL.

The page buffer circuit 122 may be connected to the memory cell array 110 through bit lines BL. The page buffer circuit 122 can receive the page buffer control signal PBCON from the control logic 123 and transmit and receive the data signal DATA to and from the input/output circuit 125 .

The page buffer circuit 122 may control the bit line BL connected to the memory cell array 110 in response to the page buffer control signal PBCON. For example, the page buffer circuit 122 senses the signal of the bit line BL of the memory cell array 110 in response to the page buffer control signal PBCON, thereby data stored in the memory cells of the memory cell array 110. may be detected, and the data signal DATA may be transmitted to the input/output circuit 125 according to the detected data. The page buffer circuit 122 may apply a signal to the bit line BL based on the data signal DATA received from the input/output circuit 125 in response to the page buffer control signal PBCON, and thus apply a signal to the memory cell. Data may be written to the memory cells of the array 110 . The page buffer circuit 122 may write data to or read data from a memory cell connected to a word line activated by the row decoder 121 .

The control logic 123 may output a voltage control signal VCON for generating a voltage necessary for the operation of the nonvolatile memory device 100 in response to the command CMD input through the input/output circuit 125 . The control logic 123 may output a page buffer control signal PBCON for controlling the page buffer circuit 122 . The control logic 123 may output row address signals RADD and column address signals CADD in response to the address signals ADD input through the input/output circuit 125 .

The voltage generator 124 may generate various operating voltages Vop used for program, read, or erase operations in response to the voltage control signal VCON of the control logic 123 . For example, the voltage generator 124 may generate program voltages, pass voltages, read voltages, and erase voltages of various levels in response to the voltage control signal VCON.

The input/output circuit 125 may transfer a command CMD or an address ADD input from the outside to the control logic 123 or exchange data DATA with the page buffer circuit 122 . The input/output circuit 125 may transmit/receive data DATA to/from an external device of the nonvolatile memory device 100, for example, a memory controller, through the input/output path IO. The input/output path IO may include 2 ^N (N is a natural number greater than or equal to 2) data input/output pins. Typically, N=3, and the input/output path IO may include 8 data input/output pins represented by IO<0> to IO<7>.

All or part of the peripheral circuit 120 may be disposed below the memory cell array 110 . This structure may be defined as PUC (Peri Under Cell). The nonvolatile memory device 100 according to the present invention may be applied to a PUC structure.

5 is a perspective view schematically illustrating a nonvolatile memory device according to an embodiment of the present invention, FIG. 6 is a plan view illustrating the internal arrangement of a peripheral structure and a page buffer circuit included in the peripheral structure of FIG. 5, and FIG. It is a plan view showing the block arrangement of the cell structure and memory cell array of FIG. 5 .

Referring to FIG. 5 , the nonvolatile memory device 100 may include a peripheral structure PERI and a cell structure CELL stacked on the peripheral structure PERI.

The nonvolatile memory device 100 may have a multi-plane structure including a plurality of planes. The cell structure CELL may include a plurality of memory cell arrays 110 respectively included in a plurality of planes.

5 shows a 4-plane structure, in which four memory cell arrays 110 are arranged in a 2X2 matrix form. Although, in the embodiment described with reference to FIG. 5, the non-volatile memory device 100 has a multi-plane structure, the non-volatile memory device 100 may have a single-plane structure including one plane. .

Although not shown in detail, a plurality of bit lines BL and a plurality of word lines WL may be arrayed in each of the plurality of memory cell arrays 110 . The plurality of bit lines BL may extend in the first direction FD and may be arranged along the second direction SD. The plurality of word lines WL may extend in the second direction SD and may be arranged along the first direction FD.

Referring to FIG. 6 , the ferry structure PERI may include a plurality of row decoders 121 and a plurality of page buffer circuits 122 . Although not shown, the ferry structure PERI may further include a control logic, a voltage generator, and an input/output circuit.

Each of the plurality of row decoders 121 may correspond to the plurality of memory cell arrays 110 shown in FIG. 5 . In order to reduce the delay of signals provided from the row decoder 121 to the word lines, the row decoder 121 may be arranged to have a shape extending in the first direction FD, which is a direction in which word lines are arranged, It may be configured to have substantially the same or similar length as the corresponding memory cell array ( 110 in FIG. 5 ) in the first direction FD.

The plurality of page buffer circuits 122 may respectively correspond to the plurality of memory cell arrays 110 shown in FIG. 5 . Each of the plurality of page buffer circuits 122 may overlap a corresponding memory cell array ( 110 in FIG. 5 ) in the vertical direction VD. In order to reduce the delay of signals applied to the bit lines from the page buffer circuit 122 or signals received from the bit lines to the page buffer circuit 122, the page buffer circuit 122 is arranged in the direction in which the bit lines are arranged. It may be configured to have substantially the same or similar length as the memory cell array 110 in two directions (SD).

One memory cell array ( 110 in FIG. 5 ), one row decoder 121 and one page buffer circuit 122 corresponding thereto may be included in a single plane.

The page buffer circuit 122 includes a plurality of page buffer high voltage regions PB HV, a plurality of page buffer low voltage regions PB LV, a plurality of cache latch regions Cache, and a plurality of column decoder regions CS DEC. ) may be included.

The plurality of page buffer high voltage regions PB HV may be spaced apart from each other along the first direction FD. One column decoder region CS DEC may be disposed in the center between two page buffer high voltage regions PB HV neighboring in the first direction FD. One page buffer low voltage region PB LV and one cache latch region Cache may be disposed between the page buffer high voltage region PB HV and the column decoder region CS DEC adjacent to each other. The page buffer low voltage region PB LV may be adjacent to the page buffer high voltage region PB HV, and the cache latch region Cache may be adjacent to the column decoder region CS DEC.

The page buffer circuit 122 may include a plurality of page buffer high voltage units connected to the memory cell array ( 110 in FIG. 5 ) through bit lines. A plurality of page buffer high voltage units may be divided into a plurality of groups and disposed in one page buffer high voltage region PB HV corresponding to each group.

The page buffer circuit 122 may include a plurality of page buffer low voltage units. A plurality of page buffer low voltage units may be divided into a plurality of groups and disposed in one page buffer low voltage region PB LV corresponding to each group. Each page buffer low voltage unit may be connected to a page buffer high voltage unit of an adjacent page buffer high voltage region PB HV through a connection line.

The page buffer low voltage unit may apply a voltage to the connection line based on the stored data. A voltage applied to the connection line may be transferred to the bit line through the page buffer high voltage unit. The page buffer low voltage unit may perform a latch based on the voltage of the connection line. The page buffer low voltage unit may perform a latch based on a voltage transferred from the bit line to the connection line through the page buffer high voltage unit.

The page buffer circuit 122 may include a plurality of cache latches. A plurality of cache latches may be divided into a plurality of groups and disposed in one cache latch area Cache corresponding to each group. Each cache latch may be connected to a page buffer low voltage unit of an adjacent page buffer low voltage region PB LV through a page line.

The cache latch may exchange data with the input/output circuit ( 125 in FIG. 4 ) through the data line. The cache latch may store data received from the page buffer low voltage unit through a page line, and transmit the stored data to an input/output circuit through a data line in response to a column decoder signal. The cache latch may exchange data with the page buffer low voltage circuit or the input/output circuit (125 of FIG. 4) in response to the page buffer control signal (PBCON of FIG. 4) received from the control logic (123 of FIG. 4).

The page buffer circuit 122 may include a plurality of column decoder units. A plurality of column decoder units may be divided into a plurality of groups and disposed in one column decoder area CS DEC corresponding to each group. The column decoder may be connected to cache latches of an adjacent cache latch area Cache through a column line.

Column decoders may generate column selection signals in response to column addresses provided from control logic ( 123 of FIG. 4 ). When 8 data input/output pins are used, 8 cache latches may be selected from among a plurality of cache latches included in the page buffer circuit 122 in response to a column select signal, and data stored in the selected 8 cache latches may be transmitted to the input/output circuit through the data line.

According to this arrangement structure, each connection line can be configured as a short length connecting the page buffer high voltage region (PB HV) and the page buffer low voltage region (PB LV) adjacent to each other, and each page line is connected to the page buffer low voltage region adjacent to the page buffer. It can be configured with a short length connecting the (PB LV) and the cache latch area (Cache), and each column line can be configured with a short length connecting the adjacent cache latch area (Cache) and the column decoder area (CS DEC). . Accordingly, the number of lines routed between the adjacent page buffer high voltage region PB HV and the page buffer low voltage region PB LV, and the number of lines routed between the adjacent page buffer low voltage region PB LV and the cache latch region Cache. The number of lines connected between the adjacent cache latch area (Cache) and the column decoder area (CS DEC) is reduced, and it is possible to arrange a large number of lines in one wiring layer, thereby improving the utilization efficiency of the wiring layer. can be raised

Referring to FIG. 7 , the memory cell array 100 may include a plurality of connector blocks CONNECT BLK, a plurality of first memory blocks MEMORY BLK1 and a plurality of second memory blocks MEMORY BLK2. can Although not shown, the plurality of connector blocks CONNECT BLK may be disposed to overlap each of the plurality of page buffer high voltage regions (PB HV of FIG. 6 ) in the vertical direction VD.

A contact (not shown) connecting the bit line BL and the page buffer high voltage region (PB HV of FIG. 6 ) may pass through the connector block CONNECT BLK. The page buffer high voltage area (PB HV in FIG. 6) and the bit are connected to the page buffer high voltage area (PB HV in FIG. 6) by a contact (not shown) penetrating the connector block (CONNECT BLK) overlapping in the vertical direction (VD). A line BL may be connected. Since the connector block (CONNECT BLK) through which the contact passes overlaps the page buffer high voltage region (PB HV in FIG. 6) in the vertical direction (VD), the bit line (BL) and the page buffer high voltage region (PB HV in FIG. 6) The electrical path connecting the can be configured with a short length.

As described with reference to FIG. 1, memory cells formed in an area adjacent to the connector block (CONNECT BLK) may have non-uniform critical dimensions due to a loading effect according to a difference in pattern density and are vulnerable to data retention problems. can do. For a similar reason, memory cells formed at both ends of the memory cell array 110 may have non-uniform critical dimensions and may be vulnerable to a data retention problem.

The first memory blocks MEMORY BLK1 may be disposed in an area vulnerable to a data retention problem, that is, an area adjacent to both ends of the memory cell array 110 and the connector block CONNECT BLK. Each of the second memory blocks MEMORY BLK2 may be spaced apart from the connector block CONNECT BLK with at least one first memory block MEMORY BLK1 interposed therebetween.

As described with reference to FIG. 1 , the second memory block MEMORY BLK2 may have a higher importance than the first memory block MEMORY BLK1 . For example, the first memory block MEMORY BLK1 may be a dummy block that does not store data, and the second memory block MEMORY BLK2 may be a data block that stores data. As another example, the second memory block MEMORY BLK2 may be a cam block storing cam data, and the first memory block MEMORY BLK1 may be a spare block replacing a user block that has become a bad block. As another example, the second memory block MEMORY BLK2 may be a user block, and the first memory block MEMORY BLK1 may be a spare block.

8 is a block diagram schematically illustrating a memory system including a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 8 , the memory system 1000 may include a nonvolatile memory device (NVM device) 100 and a memory controller 200 that controls an operation of the nonvolatile memory device 100 .

The memory system 1000 may be a device that stores data under the control of a host, such as a mobile phone, smart phone, MP3 player, laptop computer, desktop computer, game machine, TV, tablet PC, or in-vehicle infotainment system. can

The memory system 1000 may be manufactured as one of various types of storage devices according to a host interface, which is a communication method with the host. For example, the memory system 1000 includes a multimedia card in the form of SSD, MMC, eMMC, RS-MMC, and micro-MMC, secure digital in the form of SD, mini-SD, and micro-SD. card, USB (Universal Serial Bus) storage device, UFS (Universal Flash Storage) device, PCMCIA (Personal Computer Memory Card International Association) card type storage device, PCI (Peripheral Component Interconnection) card type storage device, PCI-E ( It may be composed of any one of various types of storage devices such as a PCI Express (PCI Express) card type storage device, a CF (Compact Flash) card, a smart media card, a memory stick, and the like.

The memory system 1000 may be manufactured in any one of various types of packages. For example, the memory system 1000 includes a package on package (POP), a system in package (SIP), a system on chip (SOC), a multi-chip package (MCP), a chip on board (COB), and a wafer- level fabricated package), wafer-level stack package (WSP), and the like.

The memory controller 200 may control the nonvolatile memory device 100 to perform a program operation, a read operation, or an erase operation according to a request of a host. During a program operation, the memory controller 200 may provide a write command, a physical block address, and data to the nonvolatile memory device 100 . During a read operation, the memory controller 200 may provide a read command and a physical block address to the nonvolatile memory device 100 . During an erase operation, the memory controller 200 may provide an erase command and a physical block address to the nonvolatile memory device 100 .

In one embodiment, the memory controller 200 may generate commands, addresses, and data on its own regardless of a request from a host and transmit them to the nonvolatile memory device 100 . For example, the memory controller 200 converts commands, addresses, and data into non-volatile data to perform background operations such as a program operation for wear leveling and a program operation for garbage collection. It may be provided as the memory device 100 .

The memory controller 200 may perform address conversion so that user data is written in the user block. When one of the user blocks becomes a bad block, the memory controller 200 may replace one of the spare blocks with a user block. That is, the memory controller 200 may replace user blocks that have become bad blocks with spare blocks. Such an operation is called a "remap operation".

The nonvolatile memory device 100 may operate in response to control of the memory controller 200 . The nonvolatile memory device 100 may be configured to receive a command and an address from the memory controller 200 and access a region selected by the address in the memory cell array. That is, the nonvolatile memory device 100 may perform an operation indicated by a command for an area selected by an address. For example, the nonvolatile memory device 100 may perform a write operation (program operation), a read operation, and an erase operation. During a program operation, the non-volatile memory device 100 will program data into an area selected by an address. During a read operation, the nonvolatile memory device 100 will read data from an area selected by an address. During an erase operation, the nonvolatile memory device 100 erases data stored in an area selected by an address.

9 is a schematic block diagram of a computing system including a non-volatile memory device according to an embodiment of the present invention.

Referring to FIG. 9 , a computing system 700 according to the present invention includes a memory system 710 electrically connected to a system bus 760, a microprocessor 720, a RAM 730, a user interface 740, and a baseband. When the computing system 700 according to the present invention is a mobile device, a battery (not shown) for supplying an operating voltage of the computing system 700 may include a modem 750 such as a baseband chipset. additional will be provided. Although not shown in the drawing, it is typical in the field that an application chipset, a camera image processor (CIS), a mobile DRAM, and the like may be further provided to the computing system 700 according to the present invention. It is self-evident to those who have acquired human knowledge. The memory system 710 may constitute, for example, a Solid State Drive/Disk (SSD) using a non-volatile memory to store data. Alternatively, the memory system 710 may be provided as a fusion flash memory (eg, OneNAND flash memory).

The embodiments of the present invention described above are not implemented only through devices and methods, but may also be implemented through a program that realizes functions corresponding to the configuration of the embodiments of the present invention or a recording medium on which the program is recorded. Implementation will be easily implemented by an expert in the technical field to which the present invention belongs based on the description of the above-described embodiment.

Although the detailed description of the present invention described above has been described with reference to embodiments of the present invention, those skilled in the art or those having ordinary knowledge in the art will find the spirit and spirit of the present invention described in the claims to be described later. It will be understood that the present invention can be variously modified and changed without departing from the technical scope.

Claims (16)

Board; and
A memory cell array provided on the substrate; includes,
The memory cell array,
a connector block through which contacts pass;
a first memory block disposed adjacent to the connector block; and
a second memory block spaced apart from the connector block with the first memory block interposed therebetween;
Non-volatile memory device comprising a. According to claim 1,
The first memory block includes a dummy block that does not store data,
The second memory block comprises a data block for storing data. According to claim 2,
The data block includes a cam block for storing cam data, a user block for storing user data, and a spare block for replacing a user block that has become a bad block. According to claim 1,
The second memory block stores data having a higher importance than the data stored in the first memory block. According to claim 1,
The non-volatile memory device of claim 1 , wherein the first memory block includes a spare block replacing a user block that has become a bad block, and the second memory block includes a cam block storing cam data. According to claim 1,
The first memory block includes a spare block replacing a user block that has become a bad block;
The second memory block comprises a user block. According to claim 1,
The memory cell array,
a plurality of electrode layers and a plurality of interlayer insulating layers alternately stacked on the substrate;
a plurality of cell plugs passing through the plurality of electrode layers and the plurality of interlayer insulating layers in the first memory block and the second memory block; and
and a plurality of insulating layers alternately disposed with the plurality of interlayer insulating layers in the connector block to insulate and isolate between the contact and the plurality of electrode layers. a memory structure including a memory cell array; and
A peripheral structure overlapping the memory structure in a vertical direction and including a peripheral circuit for controlling the memory cell array;
The memory cell array,
a connector block through which contacts pass;
a first memory block disposed adjacent to the connector block; and
a second memory block spaced apart from the connector block with the first memory block interposed therebetween;
Non-volatile memory device comprising a. According to claim 8,
the peripheral circuit includes a page buffer circuit;
The non-volatile memory device of claim 1 , wherein the contact connects a bit line of the memory cell array and the page buffer circuit. According to claim 9,
The page buffer circuit includes a page buffer high voltage region;
The connector block overlaps the page buffer high voltage region in the vertical direction. According to claim 8,
The first memory block includes a dummy block that does not store data,
The second memory block comprises a data block for storing data. According to claim 11,
The data block includes a cam block for storing cam data, a user block for storing user data, and a spare block for replacing a user block that has become a bad block. According to claim 8,
The second memory block stores data having a higher importance than the data stored in the first memory block. According to claim 8,
The first memory block includes a spare block replacing a user block that has become a bad block;
The second memory block comprises a cam block for storing cam data. According to claim 8,
The first memory block includes a spare block replacing a user block that has become a bad block;
The second memory block comprises a user block. According to claim 8,
The memory cell array,
a plurality of electrode layers and a plurality of interlayer insulating layers alternately stacked on the substrate;
a plurality of cell plugs passing through the plurality of electrode layers and the plurality of interlayer insulating layers in the first memory block and the second memory block; and
and a plurality of insulating layers alternately disposed with the plurality of interlayer insulating layers in the connector block to insulate and isolate between the contact and the plurality of electrode layers.

Images