KR20220141364A - Etching apparatus and method of manufacturing display panel using the same - Google Patents

Abstract

The present invention relates to an etching device and a manufacturing method of a display panel using the same. A method of manufacturing a display panel according to an embodiment includes the steps of: arranging a target substrate including a conductive layer on a susceptor; providing an etching gas containing chlorine and hydrogen on the target substrate; plasma etching using the etching gas; measuring the temperature of the target substrate, during a plasma etching step; and calculating an etch endpoint to stop the etching step. The present invention provides the etching device for performing an etching process with improved reliability.

Description

Etching apparatus and method for manufacturing display panel using same

The present invention relates to an etching apparatus and a method of manufacturing a display panel using the same, and more particularly, to a dry etching apparatus and a method of manufacturing a display panel using the dry etching method.

The display device may be used in various multimedia devices such as a television, a mobile phone, a tablet computer, a game machine, and the like in order to provide image information to a user. The display device may include a circuit formed of wires to display an image. A display device may require a circuit composed of high-density wirings to display a high-resolution image.

The wirings of the display device may be manufactured by an etching process. For example, the etching process may include a wet etching process using a wet etching apparatus. However, in the wet etching process, it is difficult to precisely control a critical dimension and uniformly etch, so it is difficult to manufacture a wiring having a thin width.

An object of the present invention is to provide an etching apparatus for performing an etching process with improved reliability.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a display panel with improved reliability.

In one embodiment, disposing a target substrate including a conductive layer on a susceptor, providing an etching gas containing chlorine and hydrogen on the target substrate, plasma etching using the etching gas, the plasma The method of manufacturing a display panel includes measuring a temperature of the target substrate during an etching step and stopping the etching step by calculating an etching end point.

The etching end point may be calculated based on a change in intensity of an emission spectrum of a product generated in the plasma etching step.

The product may include at least one of CuCl, CuCl ₂ and CuH.

During the plasma etching step, the temperature of the target substrate may be maintained at 100 degrees or less.

The method of manufacturing a display panel according to an embodiment may further include an etching inspection step, wherein the target substrate further includes an insulating layer disposed under the conductive layer, wherein the etching testing step includes irradiating incident light to the target substrate; It may include measuring the reflected light reflected from the target substrate and calculating the thickness of the layer on which the incident light is incident based on the incident light and the reflected light.

The incident light is incident on the conductive layer, and the thickness of the conductive layer may be calculated by measuring interference between the incident light and the reflected light.

The incident light is incident on the conductive layer, the incident light is polarized light, and the thickness of the conductive layer may be calculated by measuring a polarization amount of the reflected light from the incident light.

The incident light may be incident on the insulating layer, and the thickness of the insulating layer may be calculated based on the incident light and the reflected light.

The etching end point may be calculated based on a change in intensity of an emission spectrum of a product generated in the plasma etching step and a thickness of a layer on which the incident light is incident.

Another exemplary embodiment includes a chamber providing a processing space in which an etching process is performed, a susceptor disposed in the processing space and supporting a target substrate including a conductive layer, a plasma source module disposed on the chamber, the chamber and and a window connected to the conductive layer and disposed to face the conductive layer on the window, and a spectrum measuring module configured to measure an emission spectrum of an etching product, wherein the product includes CuCl and CuH. provide the device.

Further comprising a temperature measuring module disposed on the window to face the conductive layer, the temperature measuring module may measure the temperature of the conductive layer.

Further comprising a control unit connected to the spectrum measuring module and the plasma source module, wherein the control unit calculates an etching end point based on the emission spectrum of the product, and when the etching end point is reached, it can control the plasma source module .

Further comprising an inspection module disposed on the window, the inspection module may measure a change in the thickness of the conductive layer.

The inspection module may include a light irradiator for irradiating light onto the target substrate and a light sensing unit for sensing reflected light reflected from the target substrate, wherein the incident direction of the light intersects a normal direction of the incident surface of the light. .

The light irradiation unit may further include a polarizer.

The plasma source module may include an electron cyclotron resonance (ECR) source module.

A cooling module for cooling the susceptor may be further included.

In one embodiment, a chamber providing a processing space in which an etching process is performed, a susceptor disposed in the processing space and supporting a target substrate including a conductive layer, a plasma source module disposed on the chamber, and connection with the chamber and a window disposed to face the conductive layer and a spectrum measuring module, a thermal imaging camera module and an inspection module disposed on the window to face the conductive layer, wherein the spectrum measuring module measures the emission spectrum of the etching product and, the thermal imaging camera module measures the temperature of the conductive layer, and the inspection module provides an etching apparatus for measuring a thickness change of the conductive layer.

The inspection module may include a spectral reflectometer or an ellipsometer.

A control unit connected to the spectrum measuring module, the thermal imaging camera module, the inspection module, and the plasma source module, wherein the control unit is configured to include an emission spectrum of the product, a temperature of the conductive layer and a thickness of the conductive layer during an etching process. It is possible to control the plasma source module by monitoring the change.

The display panel manufacturing method and etching apparatus according to an exemplary embodiment of the present invention may manufacture a display panel through uniform etching and precise critical dimension control.

The display panel manufacturing method and the etching apparatus according to the exemplary embodiment of the present invention may manufacture a display panel including high-density wirings and having high resolution and reliability.

1 is a perspective view of a display device according to an exemplary embodiment.
2 is an exploded perspective view of a display device according to an exemplary embodiment.
3 is a plan view of a display panel according to an exemplary embodiment.
4 is a cross-sectional view of a display panel according to an exemplary embodiment.
5 is a flowchart of a method of manufacturing a display panel according to an exemplary embodiment.
6A to 6C are cross-sectional views of an etching apparatus according to an embodiment of the present invention.
7A to 7C are cross-sectional views illustrating a step of a method of manufacturing a display panel according to an exemplary embodiment.
8A to 8C are cross-sectional views illustrating a step of a method of manufacturing a display panel according to an exemplary embodiment.
9 is a cross-sectional view illustrating a step of a method of manufacturing a display panel according to an exemplary embodiment.
10 is a graph illustrating a temperature change according to an etching time of a conductive layer according to an embodiment of the present invention.
11 is a graph illustrating the intensity of an emission spectrum according to an embodiment according to an etching time.
12 is an enlarged graph of one area shown in FIG. 11 .

Since the present invention can have various changes and can have various forms, specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents and substitutes included in the spirit and scope of the present invention.

In this specification, when an element (or region, layer, portion, etc.) is referred to as being “on,” “connected to,” or “coupled to” another element, it is placed/directly placed on the other element. It means that it can be connected/coupled or a third component can be placed between them.

Like reference numerals refer to like elements. In addition, in the drawings, thicknesses, ratios, and dimensions of components are exaggerated for effective description of technical content. “and/or” includes any combination of one or more that the associated elements may define.

Terms such as first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component. The singular expression includes the plural expression unless the context clearly dictates otherwise.

In addition, terms such as "below", "below", "above", and "upper side" are used to describe the relationship between the components shown in the drawings. The above terms are relative concepts, and are described with reference to directions indicated in the drawings.

Terms such as “comprise” or “have” are intended to designate that a feature, number, step, operation, component, part, or combination thereof described in the specification is present, and includes one or more other features, number, or step. , it should be understood that it does not preclude in advance the possibility of the presence or addition of an operation, component, part, or combination thereof.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. In addition, terms such as terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related art, and unless explicitly defined herein, it should be interpreted in a too idealistic or overly formal sense. shouldn't be

Hereinafter, an etching apparatus according to an embodiment of the present invention and a method of manufacturing a display panel using the same will be described with reference to the drawings.

1 is a perspective view of a display device according to an exemplary embodiment; 2 is an exploded perspective view of a display device according to an exemplary embodiment.

Referring to FIG. 1 , the display device DD may be activated according to an electrical signal to provide an image IM. The display device DD may be used in various electronic devices to display the image IM. For example, the display device DD may be used in large electronic devices such as televisions and monitors, and small and medium-sized electronic devices such as mobile phones, tablets, car navigation systems, and game machines. However, unless departing from the concept of the present invention, the display device DD is not limited to the above-described examples and may be used in various electronic devices.

The display device DD may display the image IM in the third direction DR3 through the display surface FS parallel to each of the first and second directions DR1 and DR2 . The display surface FS on which the image IM is displayed may correspond to a front surface of the display device DD. The image IM may include a static image as well as a dynamic image. 1 illustrates a clock widget and icons as an example of an image IM.

In this embodiment, the front (or upper surface) and the rear (or lower surface) of each member are defined based on the direction in which the image IM is displayed. The front surface and the rear surface may be opposed to each other in the third direction DR3 , and a normal direction of each of the front surface and the rear surface may be parallel to the third direction DR3 . A separation distance between the front surface and the rear surface defined along the third direction DR3 may correspond to the thickness of the members. In the present specification, "on a plane" may correspond to when the configuration is viewed in the third direction DR3.

Meanwhile, the first to third directions DR1 , DR2 , and DR3 described herein are relative concepts and may be converted into other directions. Directions indicated by the first to third directions DR1 , DR2 , and DR3 are illustrated using the same reference numerals in each drawing of the present specification.

In a plan view, the display device DD may have a short side extending along the first direction DR1 , a long side extending along the second direction DR2 , and may have a rectangular shape with rounded corners. However, the shape of the display device DD is not limited thereto, and various shapes may be provided.

The display surface FS may include a transmission area TA and a bezel area BZA. The display surface FS of the display device DD may correspond to the front surface of the cover window WM.

The transmission area TA may be an optically transparent area. The transmission area TA may transmit the image IM, and the user may view the image IM through the transmission area TA. The bezel area BZA may be an area having relatively low light transmittance compared to the transmission area TA. For example, a printed layer having a predetermined color may be formed to overlap the bezel area BZA.

The bezel area BZA may be an area adjacent to the transmission area TA. For example, the bezel area BZA may surround the transmission area TA. Accordingly, the shape of the transmission area TA may be substantially defined by the bezel area BZA. In the present exemplary embodiment, the transmission area TA has a rectangular shape with rounded vertices. However, this is illustrated by way of example, and the transmission area TA and the bezel area BZA may have various shapes. Meanwhile, the bezel area BZA may be adjacent to only one side of the transmission area TA or may be omitted.

Meanwhile, although the cross-sectional display surface FS defined on the front surface of the display device DD is illustrated as an example, the present invention is not limited thereto, and the display surface FS may be defined on both the front and rear surfaces of the display device DD. can Accordingly, the display device DD may have a single-sided or double-sided display surface and is not limited to one embodiment.

1 and 2 , the display device DD may include a cover window WM, a display module DM, and a housing HU. The cover window WM and the housing HU may be combined to form an exterior of the display device DD.

The cover window WM may be disposed on the display module DM. The cover window WM may cover the entire upper surface of the display module DM. The cover window WM may prevent the display module DM from being damaged or malfunctioning due to an external impact.

The cover window WM may include an optically transparent material. For example, the cover window WM may include glass, sapphire, plastic, or the like. The image output from the display module DM may be provided to the user through the cover window WM.

The cover window WM may have a single-layer structure or a multi-layer structure. For example, the cover window WM may include a plurality of plastic films bonded to each other or a glass substrate and a plastic film bonded to each other.

The cover window WM may be flexible. For example, the cover window WM may be folded or bent with a predetermined curvature. However, the present invention is not limited thereto, and the cover window WM may be rigid.

The display module DM may be disposed between the cover window WM and the housing HU. The display module DM may display an image according to an electrical signal, and may transmit and receive information about an external input. The display module DM may include a display panel DP, a connection circuit board CF, a driving chip IC, and a main circuit board MB.

The display panel DP according to an exemplary embodiment may be a liquid crystal display panel or a light emitting display panel, but is not particularly limited. For example, the light emitting display panel may be an organic light emitting display panel or a quantum dot light emitting display panel. The light emitting layer of the organic light emitting display panel may include an organic light emitting material. The emission layer of the quantum dot light emitting display panel may include quantum dots, quantum rods, and the like.

The display panel DP may be flexible. The term “flexible” refers to a property that can be bent, and the flexible display panel DP may include everything from a fully foldable structure to a structure in which a portion can be bent. For example, the display panel DP may be a curved display panel or a foldable display panel. The present invention is not limited thereto, and the display panel DP may be a rigid one.

The display panel DP may include a display area DA and a non-display area NDA. The display area DA may be defined as an area for displaying an image. The non-display area NDA may be defined as an area that does not display an image.

The non-display area NDA may be adjacent to the display area DA. For example, the non-display area NDA may surround the display area DA. However, the present invention is not limited thereto, and the non-display area NDA may be defined in various forms such as adjacent to only one side of the display area DA.

The display panel DP may include a plurality of pixels disposed to overlap the display area DA and a circuit unit disposed to overlap the non-display area NDA. The circuit unit may provide an electrical signal to the pixels to drive the pixels. The pixels may emit light in response to an electrical signal, and may output an image through the display area DA.

The display area DA may correspond to at least a portion of the transmission area TA. The image emitted through the display area DA may be viewed by the user through the transmission area TA. The non-display area NDA may correspond to at least a portion of the bezel area BZA. The circuit part disposed to overlap the non-display area NDA may not be viewed from the outside by the bezel area BZA.

The connection circuit board CF and the main circuit board MB may be electrically connected to the display panel DP. The connection circuit board CF may be disposed on the display panel DP to be adjacent to one side of the display panel DP. The connection circuit board CF may connect the display panel DP and the main circuit board MB. The connection circuit board CF may provide an electrical signal generated by the connection circuit board CF or the main circuit board MB to the display panel DP to drive the display panel DP. The connection circuit board CF may be a flexible printed circuit board. Meanwhile, a plurality of connection circuit boards CF may be provided to be connected to the display panel DP or may be omitted.

The driving chip IC may be mounted on the connection circuit board CF. The driving chip IC may include driving elements for driving the pixels of the display panel DP. For example, the driving chip IC may include a driving circuit configured as an integrated circuit, and the driving circuit may include a driving controller, a data driver, a voltage generator, and the like. Meanwhile, the present invention is not limited thereto, and the driving chip IC may be mounted on the display panel DP.

The main circuit board MB may be disposed on one side of the connection circuit board CF to be electrically connected to the connection circuit board CF. The main circuit board MB may include a main controller and signal wires. The signal wires of the main circuit board MB may transmit control signals and image signals received from the main controller to the connection circuit board CF and the display panel DP. The main circuit board MB may be a rigid printed circuit board or a flexible printed circuit board. Meanwhile, the main circuit board MB may be directly connected to the display panel DP, and the embodiment is not limited thereto.

The connection circuit board CF and the main circuit board MB may include a plurality of wires for transmitting electrical signals. The plurality of wirings included in the connection circuit board CF and the main circuit board MB may be formed through deposition and etching of a conductive layer. The plurality of wirings may be manufactured by using an etching apparatus to be described later, or by an etching method to be described later.

Meanwhile, although not shown separately, the display module DM may further include at least one functional layer disposed on the display panel DP. For example, the functional layer may include an anti-reflection layer that reduces the reflectance of external light incident from the upper side of the cover window WM, an input sensing layer that senses an external input, and the like, but is not limited to any one embodiment. .

The housing HU may be coupled to the cover window WM to provide an internal space for accommodating elements of the display device DD. For example, the housing HU may accommodate the display module DM. The housing HU may protect the display module DM accommodated in the internal space from external impact, and may prevent foreign substances or moisture from penetrating into the display module DM.

Meanwhile, the display device DD includes an electronic module including various functional modules for operating the display module DM, a power supply module for supplying power necessary for the overall operation of the display device DD, a display module DM, and /or a bracket that is coupled to the housing HU to divide an internal space of the display device DD may be further included.

3 is a plan view of a display panel according to an exemplary embodiment. 4 is a cross-sectional view of a display panel according to an exemplary embodiment. FIG. 3 shows only a plan view of the display panel DP among the configurations of the display module DM shown in FIG. 2 . 4 exemplarily illustrates a cross-section of the display panel DP corresponding to one pixel PX.

Referring to FIG. 3 , the display panel DP includes a scan driver (SDV), an emission driver (EDV), a plurality of pixels PX, a plurality of pads PD, and a plurality of It may contain lines. The plurality of lines includes a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, a plurality of light emitting lines EL1 to ELm, and first and second control lines CSL1 and CSL2. , first and second power lines PL1 and PL2 , and connection lines CNL. Here, m and n are natural numbers.

The pixels PX may be disposed in the display area DA. Each of the pixels PX may include a light emitting device and a transistor electrically connected to the light emitting device. For example, the light emitting device may include an organic light emitting diode. However, the present invention is not limited thereto, and some of the pixels PX may be disposed in the non-display area NDA.

The pixels PX may be arranged in a matrix form along a first direction DR1 and a second direction DR2 that are orthogonal to each other. In an embodiment of the present invention, the pixels PX may include first to third pixels each displaying a red color, a green color, and a blue color. However, embodiments of the pixels PX are not limited thereto.

The scan driver SDV and the light emission driver EDV may be disposed adjacent to one side of the non-display area NDA. For example, the scan driver SDV and the light emission driver EDV may be disposed in the non-display area NDA adjacent to the long sides of the display panel DP, respectively.

The scan lines SL1 to SLm may extend along the first direction DR1 to be connected to a corresponding one of the pixels PX and the scan driver SDV. The data lines DL1 to DLn may extend along the second direction DR2 to be connected to a corresponding one of the pixels PX. The emission lines EL1 to ELm may extend along the first direction DR1 to be connected to a corresponding one of the pixels PX and the emission driver EDV.

The first power line PL1 may extend along the second direction DR2 and be disposed in the non-display area NDA. The first power line PL1 may be disposed adjacent to the light emission driver EDV, but is not limited thereto, and the first power line PL1 may be disposed adjacent to the scan driver SDV.

The connection lines CNL may extend along the first direction DR1 and may be arranged along the second direction DR2 . The connection lines CNL may be connected to the first power line PL1 and the pixels PX. The first voltage may be applied to the pixels PX through the first power line PL1 and the connection lines CNL connected to each other.

The connection lines CNL may be integrally formed with the first power line PL1 to extend from the first power line PL1 . However, the present invention is not limited thereto, and the connection lines CNL may be disposed on a different layer from the first power line PL1 and may be connected to the first power line PL1 through separate connection electrodes.

The second power line PL2 may be disposed in the non-display area NDA. The second power line PL2 may be disposed to be adjacent to the outside of the non-display area NDA than the scan driver SDV and the light emission driver EDV. Although not shown separately, the second power line PL2 may extend toward the display area DA and be connected to the pixels PX. A second voltage having a level lower than the first voltage may be applied to the pixels PX through the second power line PL2 .

The first control line CSL1 may be connected to the scan driver SDV, and the second control line CSL2 may be connected to the light emission driver EDV. In a plan view, the first control line CSL1 and the second control line CSL2 may extend toward the pads PD of the display panel DP.

The pads PD are adjacent to one side of the display panel DP and may be arranged in one direction on the non-display area NDA. For example, the pads PD may be adjacent to the short side of the display panel DP and may be arranged in the first direction DR1 . The first power line PL1 , the second power line PL2 , the first control line CSL1 , and the second control line CSL2 may be connected to the pads PD. The above-described connection circuit board CF of FIG. 2 may be electrically connected to the pads PD.

The scan driver SDV may generate a plurality of scan signals in response to a scan control signal, and the scan signals may be applied to the pixels PX through the scan lines SL1 to SLm. The emission driver EDV may generate a plurality of emission signals in response to the emission control signal, and the emission signals may be applied to the pixels PX through the emission lines EL1 to ELm. A plurality of data voltages corresponding to the image signals may be applied to the pixels PX through the data lines DL1 to DLn in response to the data control signal.

The pixels PX may receive data voltages in response to scan signals. The pixels PX may display an image by emitting light having a luminance corresponding to the data voltages in response to the emission signals. The emission time of the pixels PX may be controlled by the emission signals.

The plurality of wires and the plurality of pads PD of the display panel DP may be formed through deposition and etching of a conductive layer. The plurality of wires and the plurality of pads PD of the display panel DP may be manufactured using an etching apparatus to be described later, or an etching method to be described later.

Referring to FIG. 4 , the display panel DP may include a substrate SUB, a circuit element layer DP-CL, a display element layer DP-OL, and an encapsulation layer TFE. 4 exemplarily illustrates a cross section of one light emitting area PA overlapping the display area DA and a non-emission area NPA adjacent to the light emitting area PA.

The substrate SUB may include the display area DA and the non-display area NDA described above. The substrate SUB may be a display substrate on which the circuit element layer DP-CL and the display element layer DP-OL are disposed. The substrate SUB may include at least one of a silicon substrate, a plastic substrate, and a glass substrate. The substrate SUB may be an insulating film or a laminate structure including a plurality of insulating layers.

The circuit element layer DP-CL and the display element layer DP-OL may be disposed on the substrate SUB. The circuit element layer DP-CL and the display element layer DP-OL may constitute the pixels PX illustrated in FIG. 3 . Each of the pixels PX may include a transistor disposed on the circuit device layer DP-CL and a light emitting device disposed on the display device layer DP-OL and connected to the transistor.

The display area DA may include an emission area PA corresponding to each of the pixels PX and a non-emission area NPA adjacent to the emission area PA. The light emitting area PA may correspond to an area in which the light emitting device OL of the display device layer DP-OL is disposed.

The circuit element layer DP-CL may include a buffer layer BFL, a plurality of transistors T1 and T2 , and a plurality of insulating layers INS1 to INS6 . The transistors T1 and T2 may include a semiconductor pattern. 4 exemplarily illustrates the first and second transistors T1 and T2.

The buffer layer BFL may be disposed on the substrate SUB. The buffer layer BFL may allow the semiconductor patterns of the transistors T1 and T2 to be disposed on the buffer layer BFL to be well deposited. The buffer layer BFL may prevent impurities present in the substrate SUB or moisture introduced from the outside from diffusing into the semiconductor patterns of the transistors T1 and T2 . The buffer layer BFL may include an inorganic layer.

The semiconductor pattern of the transistors T1 and T2 may include polysilicon, but is not limited thereto, and the semiconductor pattern may include amorphous silicon or metal oxide. Electrical properties of the semiconductor pattern may vary depending on doping. The semiconductor pattern may include a doped region and a non-doped region. The doped region may be doped with an N-type dopant or a P-type dopant. The doped region is more conductive than the undoped region and can substantially act as electrodes, such as the source and drain of a transistor. The undoped region may substantially correspond to the active (or channel) of the transistor.

The source S1, active A1, and drain D1 of the first transistor T1 and the source S2, active A2, and drain D2 of the second transistor T2 may be formed from a semiconductor pattern. have. A first insulating layer INS1 may be disposed on the semiconductor pattern. Gates G1 and G2 of the first and second transistors T1 and T2 may be disposed on the first insulating layer INS1 . A second insulating layer INS2 may be disposed on the gates G1 and G2 . A dummy electrode DME may be disposed on the second insulating layer INS2 . A third insulating layer INS3 may be disposed on the dummy electrode DME.

A connection electrode CNE may be disposed between the second transistor T2 and the light emitting device OL. The connection electrode CNE may electrically connect the second transistor T2 and the light emitting device OL. The connection electrode CNE may include a first connection electrode CNE1 and a second connection electrode CNE2 disposed on the first connection electrode CNE1. The first connection electrode CNE1 may be connected to the second transistor T2 and the second connection electrode CNE2, and the second connection electrode CNE2 may be connected to the first connection electrode CNE1 and the light emitting device OL. have.

The first connection electrode CNE1 is disposed on the third insulating layer INS3 , and the drain D2 of the second transistor T2 is formed through contact holes defined in the first to third insulating layers INS1 to INS3 . ) can be connected to The fourth insulating layer INS4 may be disposed on the first connection electrode CNE1 . A fifth insulating layer INS5 may be disposed on the fourth insulating layer INS4 . The second connection electrode CNE2 may be disposed on the fifth insulating layer INS5 . The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through contact holes defined in the fourth and fifth insulating layers INS4 and INS5 . A sixth insulating layer INS6 may be disposed on the second connection electrode CNE2 . The second connection electrode CNE2 may be connected to the first electrode AE of the light emitting device OL through a contact hole defined in the sixth insulating layer INS6 . The first to sixth insulating layers INS1 to INS6 may be an inorganic layer or an organic layer.

The connection line CNL connected to the above-described first power line PL1 may be disposed on the third insulating layer INS3 . The fourth insulating layer INS4 may be disposed on the connection line CNL. The connection line CNL may include at least one of copper, aluminum, silver, molybdenum, chromium, tantalum, and titanium. The connection line CNL may be disposed on the same layer as the first connection electrode CNE1 . The connection line CNL may be formed by being simultaneously patterned with the same material as the first connection electrode CNE1 . For example, the connection line CNL and the first connection electrode CNE1 may include copper and may be patterned using the etching apparatus of the present invention.

The data line DL may be disposed on the fifth insulating layer INS5 . The sixth insulating layer INS6 may be disposed on the data line DL. The data line DL may include at least one of copper, aluminum, silver, molybdenum, chromium, tantalum, and titanium. The data line DL may be disposed on the same layer as the second connection electrode CNE2 . The data line DL may be formed by being simultaneously patterned with the same material as the second connection electrode CNE2 . For example, the data line DL and the second connection electrode CNE2 may include copper, and may be patterned using the etching apparatus of the present invention.

The display element layer DP-OL may be disposed on the circuit element layer DP-CL. The display element layer DP-OL includes a first electrode AE, a second electrode CE, a hole control layer HCL, an electron control layer ECL, an emission layer EML, and a pixel defining layer PDL. can do.

The first electrode AE may be disposed on the sixth insulating layer INS6 of the circuit element layer DP-CL. The first electrode AE may be connected to the second connection electrode CNE2 through a contact hole defined in the sixth insulating layer INS6 . A portion of the first electrode AE may be disposed on the sixth insulating layer INS6 and may be exposed by the pixel defining layer PDL having an opening defined therein.

The hole control layer HCL may be disposed on the first electrode AE and the pixel defining layer PDL. The hole control layer HCL may be commonly disposed in the light emitting area PA and the non-emission area NPA. The hole control layer HCL may include a hole transport layer and a hole injection layer.

The emission layer EML may be disposed on the hole control layer HCL. The emission layer EML may be disposed in a region corresponding to the opening of the pixel defining layer PDL. The emission layer EML may include an organic material and/or an inorganic material. The emission layer EML may generate any one of red, green, and blue light.

The electronic control layer ECL may be disposed on the emission layer EML. The electronic control layer ECL may be commonly disposed in the light emitting area PA and the non-emission area NPA. The electron control layer (ECL) may include an electron transport layer and an electron injection layer.

The second electrode CE may be disposed on the electronic control layer ECL. The second electrode CE may be disposed in common with the pixels PX.

A first voltage may be applied to the first electrode AE, and a second voltage may be applied to the second electrode CE. Holes and electrons injected into the light emitting layer EML combine to form an exciton, and the light emitting device OL may emit light while the exciton transitions to a ground state. As the light emitting element OL emits light, an image may be displayed.

The encapsulation layer TFE may be disposed on the circuit element layer DP-CL to cover the display element layer DP-OL. The encapsulation layer TFE may be disposed on the light emitting device OL. The encapsulation layer TFE may include a plurality of sequentially stacked inorganic layers and at least one organic layer disposed between the inorganic layers. The inorganic layer may protect the pixels from moisture/oxygen. The organic layer may protect the pixels from foreign substances such as dust particles.

Meanwhile, FIG. 4 exemplarily shows a cross-section of the display panel DP, and is displayed according to the configuration of the circuit element layer DP-CL and the display element layer DP-OL included in the display panel DP. The shape of the cross-section of the panel DP may vary.

5 is a flowchart of a method of manufacturing a display panel according to an exemplary embodiment. A method of manufacturing a display panel according to an embodiment may be performed using an etching apparatus of the present invention, which will be described later. A method of manufacturing a display panel according to an exemplary embodiment includes disposing a target substrate on a susceptor (S10), providing an etching gas (S20), plasma etching (S30), measuring a temperature of the target substrate (S40), and It may include an etching stop step (S50).

In the step of disposing the target substrate on the susceptor ( S10 ), the target substrate may include at least one conductive layer to be etched. At least one conductive layer may include copper. The target substrate may be disposed on the susceptor and provided inside the chamber of the etching apparatus. The target substrate may be disposed under the plasma source module to perform an etching process.

The target substrate may correspond to a substrate provided to form a circuit or device of a display panel including wirings or electrodes. The conductive layer may correspond to a laminate deposited on the substrate of the display panel to form wirings or electrodes through patterning by etching.

The etching gas provided in step S21 of providing the etching gas on the target substrate may include chlorine and hydrogen for dry etching the conductive layer. For example, the etching gas may be a mixed gas including hydrogen chloride (HCl).

In the plasma etching step ( S30 ), the conductive layer of the target substrate may be etched by plasma. The etching gas provided in the step of providing the etching gas ( S21 ) may be plasmaized by a plasma source module to be described later. For example, chlorine and hydrogen of the etching gas may be plasmaized by the plasma source module to react with copper of the conductive layer in the form of ions or radicals.

The step of measuring the target substrate temperature ( S40 ) may correspond to measuring the temperature change of the target substrate during the etching process. Specifically, the target substrate temperature measurement step ( S40 ) may measure a temperature change of the conductive layer. The target substrate temperature measurement step S40 may be performed by a temperature measurement module to be described later. The temperature of the target substrate may be increased by reaction with the etching gas converted into plasma, and the target substrate temperature measurement step (S40) is to continuously monitor the temperature of the target substrate so that the temperature of the target substrate does not exceed a specific temperature value. can Accordingly, the reliability of the etching process may be improved.

Meanwhile, the method of manufacturing a display panel according to an embodiment may further include cooling the susceptor so that the temperature of the target substrate does not exceed a specific temperature value. For example, when the temperature of the target substrate measured in the target substrate temperature measuring step S40 approaches a specific temperature value, the susceptor may be cooled to reduce the temperature of the target substrate. The temperature of the target substrate may be controlled by controlling the temperature of the susceptor.

The etch stop step S50 may correspond to the step of calculating an etch end point and stopping the etching at the etch end point. The calculation of the etching endpoint may be calculated based on the measurement of the intensity of the emission spectrum of a product generated in the etching process. In the etching stop step ( S50 ), the etching process may be terminated by stopping the driving of the plasma source module, which will be described later, based on the etching end point.

The intensity of the emission spectrum may be measured by a spectrum measuring module, which will be described later. The conductive layer may be etched through several chemical reaction steps, and the reaction step may be changed according to an etching time and an etching gas. For example, a product produced in one reaction step can act as a reactant in the next step. Accordingly, the reaction step of the etching process can be predicted by measuring the intensity of the emission spectrum of the product, which varies according to the etching time.

The calculated etching end point may be calculated by, for example, measuring a degree of change in intensity of an emission spectrum of a specific product based on a predetermined etching time. However, the present invention is not limited thereto, and an etching end point may be calculated based on when the emission spectrum of a specific product reaches a specific absolute value. The etch endpoint can be easily calculated using the intensity of the emission spectrum.

Meanwhile, the method of manufacturing a display panel according to an embodiment may further include an etching inspection step. In the etching inspection step, a change in the thickness of the conductive layer or the insulating layer included in the target substrate may be measured to determine whether the etching of the conductive layer proceeds to a set value. At the calculated etching end point, it can be checked whether the etching is sufficiently performed by measuring the thickness of the conductive layer or the insulating layer. The reliability of the calculated etch endpoint may be improved by calculating the etch endpoint based on the thickness of the conductive layer or the insulating layer measured in real time and the emission spectrum intensity of the product.

Hereinafter, steps of an etching apparatus used for manufacturing a display panel according to an embodiment of the present invention and a method of manufacturing a display panel will be described with reference to each of the drawings.

6A to 6C are cross-sectional views illustrating etching apparatuses according to an exemplary embodiment. 7A to 7C are cross-sectional views illustrating a step of a method of manufacturing a display panel according to an exemplary embodiment.

The etching apparatuses ED of FIGS. 6A to 6C include substantially the same components, but differ in some components. A description of each configuration of the etching apparatuses ED will be described later with reference to the respective drawings.

Referring to FIG. 6A , the etching apparatus ED according to an embodiment includes a chamber CH, a susceptor SU, a plasma source module ES, a window CW, a spectrum measurement module OES, and a temperature measurement module. (IR) and a cooling module (CO). FIG. 6A illustrates a plasmaized etching gas PG provided on the target substrate SB for convenience of description, which may correspond to the step S21 of providing the etching gas of FIG. 5 .

The chamber CH may provide a processing space in which an etching process is performed. The chamber CH may provide a processing space in a vacuum state during an etching process. For example, the pressure of the processing space of the chamber CH may be 10 ^-4 to 10 ^-2 torr. Plasmaized etching gas PG may be formed in the processing space of chamber CH. The chamber CH may include a ceramic material having resistance to plasma.

The target substrate SB may correspond to a substrate provided to form the above-described wirings and/or electrodes of the display panel. The target substrate SB may include at least one conductive layer and an insulating layer depending on a configuration to be etched. For example, in order to form the data line DL shown in FIG. 4 , the target substrate SB provided to the etching apparatus ED is the transistors T1 and T2 stacked on the substrate SUB of FIG. 4 . ) may correspond to the semiconductor pattern of the plurality of insulating layers INS1 to INS5 , and the conductive layer of the target substrate SB to be etched is copper deposited on the insulating layer to be patterned into the data line DL. It may correspond to a layer. The present invention is not limited thereto, and electrodes such as the gate electrodes G1 and G2 of the display panel DP, the data line DL, and the power lines PL1 and PL2 of the display panel DP by the etching apparatus ED of the present invention are not limited thereto. Wirings may be formed, and the configuration of the target substrate SB may vary depending on the configuration to be formed.

The susceptor SU may be disposed in a processing space provided by the chamber CH. The susceptor SU may be disposed such that the target substrate SB is positioned under the plasma source module ES. The susceptor SU may support and transport the target substrate SB. The susceptor SU may support the target substrate SB so that the conductive layer of the target substrate SB to be etched is exposed in the third direction DR3 . The susceptor SU may linearly move the target substrate SB. For example, the susceptor SU may transport the target substrate SB in a manner such as belt driving, chain driving, or cylinder driving, but is not limited to any one embodiment.

The plasma source module ES may be disposed on the chamber CH. The plasma source module ES may be disposed above the chamber CH. The plasma source module ES may be disposed with one region of the processing space of the chamber CH interposed therebetween. The plasma source module ES may convert the etching gas supplied into the processing space of the chamber CH into plasma. Meanwhile, although not separately illustrated, the etching gas may be provided into the processing space by a gas supply module connected to the chamber CH.

The plasma source module ES may include an electron cyclotron resonance plasma source module (hereinafter, referred to as an ECR plasma source module). For example, the ECR plasma source module may include a microwave generator and a magnetic field generator. The ECR plasma source module can generate a high-density plasma having a high plasma electron temperature by using an electric field and a magnetic field at the same time.

The magnetic field generator may generate a magnetic field in the processing space of the chamber CH between the plasma source modules ES. The micro generator may provide microwaves in the region where the magnetic field is formed. Due to this, an electron cyclotron resonance phenomenon may occur by matching the microwave frequency with the rotation frequency of electrons due to the magnetic field, and the etching gas in the chamber CH may be formed as a plasma etching gas PG. The ECR plasma source module can form a plasma having a large energy by resonance. Since diffusion loss is reduced by the magnetic field and ionization continues well, the ECR plasma source module can form high-density plasma.

Meanwhile, the plasma source module ES may be a linear source module extending in one direction. The plasma source module ES may perform an etching process while moving in a direction crossing the extended direction. Through this, the target substrate SB having a large area can be easily etched. However, the shape of the plasma source module ES is not limited to any one embodiment.

7A to 7C illustrate steps corresponding to the plasma etching step S30 of the conductive layer by the plasma source module ES. Hereinafter, one step of the plasma etching step S30 will be described later with reference to each drawing.

Referring to FIG. 7A , the target substrate SB may include a conductive layer P-CL1 before being etched and a lower layer UL disposed under the conductive layer P-CL1. The conductive layer P-CL1 may be formed on the lower layer UL through a deposition process such as sputtering. As described above, the lower layer UL may be formed of a plurality of stacked bodies, and the configuration of the lower layer UL may be changed according to a structure to be formed by etching the conductive layer P-CL1.

The conductive layer P-CL1 may include copper (Cu). Copper can have high conductivity. For example, when wiring is manufactured by etching the conductive layer P-CL1 including copper, wiring having high conductivity can be formed even with a narrow wiring width. Specifically, a wiring having a width of about 2 μm or less may be formed by etching the conductive layer P-CL1 including copper. However, the width of the wiring to be manufactured is not limited to the above-described numerical example. When the wiring or electrode is manufactured by etching the conductive layer P-CL1 including copper, the manufacturing cost may be relatively reduced.

A mask PM may be disposed on the conductive layer P-CL1 . The mask PM may be a hard mask formed of a metal, silicon oxide, or the like, or a photoresist, and is not limited to any one embodiment. The mask PM may define a region of the conductive layer P-CL1 to be etched. The mask PM may expose a portion of the conductive layer P-CL1 to be patterned and etched to the plasmaized etching gas PG, and an etching reaction within the exposed portion of the conductive layer P-CL1 may be performed. This can happen.

The etching gas provided to etch the conductive layer may include a halogen element. For example, the etching gas may include fluorine (F) or chlorine (Chlorine, Cl). The etching gas may further include at least one of hydrogen (H), nitrogen (N), helium (He), and argon (Ar) as necessary.

Specifically, when an etching gas containing chlorine is provided, chlorine ions and chlorine radicals may be generated by plasmaization, and the chlorine ions and chlorine radicals react with copper to form copper chloride (I) (Copper (I), chloride, CuCl) or copper(II) chloride (Copper(II), chloride, CuCl ₂ ).

FIG. 7B illustrates a state in which the conductive layer exposed to the plasma-ized etching gas PG is plasma-etched. Referring to FIG. 7B , a copper chloride layer R-CL may be formed between the conductive layers P-CL2 on which the etching process has been performed. CuCl may be formed by a radical reaction between copper and chlorine, and CuCl may react with chlorine radicals by continuously supplied chlorine gas to be saturated with CuCl ₂ . Accordingly, as shown in FIG. 7B , a portion of the conductive layer P-CL2 in the region that does not overlap the mask PM may be saturated with the copper chloride layer R-CL, that is, CuCl ₂ .

The formed CuCl and CuCl ₂ may have a vaporization point of about 1000 degrees at normal pressure, and about 150 degrees or more at a pressure at which an etching process is performed (eg, about 10 ^-2 to 10 ^-4 Torr). When CuCl and CuCl ₂ having high vaporization points are vaporized and discharged to the outside of the chamber (CH), they may be redeposited on the surface of the chamber (CH) having a relatively lower surface temperature than the vaporization points of CuCl and CuCl ₂ . The redeposited CuCl and CuCl ₂ may contaminate the inside of the chamber or the target substrate SB, and may block the pipe of the etching device ED. This may reduce process reliability.

Accordingly, in order to prevent contamination of the chamber CH by the etching products CuCl and CuCl ₂ , a plasma-ized etching gas PG may be further provided on CuCl and CuCl ₂ to form a product having a low vaporization point. For example, copper hydride (CuH) and copper chloride compound (Cu ₃ Cl ₃ ) that can be vaporized at room temperature by providing an etching gas containing chlorine and hydrogen may be formed. The etching reaction rate may be controlled by adjusting the ratio of hydrogen gas included in the etching gas.

7C exemplarily illustrates a cross-section of the conductive layer CL etched by providing an etching gas PG plasmaized on the copper chloride layer R-CL generated by the etching process. Referring to FIG. 7C , the etched conductive layer CL may correspond to the etching of a portion of the conductive layer P-CL1 that does not overlap the mask PM of FIG. 7A .

The copper chloride layer R-CL and the plasma-ized etching gas PG may react to form a product gas RG that can be vaporized at room temperature. Specifically, the copper chloride layer R-CL exposed by not overlapping the mask PM may react with hydrogen radicals to generate CuH and Cu ₃ Cl ₃ . CuH and Cu ₃ Cl ₃ may be vaporized at room temperature and pressure. Accordingly, the product gas RG may include CuH and Cu ₃ Cl ₃ . The copper chloride layer R-CL formed in the region that does not overlap the mask PM may be vaporized as a product gas RG as an etching process is performed, and a portion of the conductive layer CL may be etched. The vaporized product gas RG may be discharged to the outside through a piping device.

The conductive layer CL etched by the plasma source module ES may be etched uniformly and precisely. Accordingly, the reliability of the conductive layer CL etched by the plasma source module ES may be improved.

Referring back to FIG. 6A , the window CW may be connected to the upper side of the chamber CH. The window CW may be disposed between the plasma source modules ES. The window CW may be disposed to face the upper surface of the susceptor SU. Accordingly, the window CW may be disposed to face the conductive layer to be etched disposed on the susceptor SU.

The window CW may include an optically transparent silicon material such as quartz. The conductive layer to be etched may be visually recognized through the window CW. Various modules such as a spectrum measurement module OES and a temperature measurement module IR disposed on the window CW may face the conductive layer of the target substrate SB and measure data required for an etching process. Since several modules disposed on the window CW may directly irradiate a light source for data measurement on the target substrate SB through the window CW, data measurement may be facilitated and measurement reliability may be improved.

The spectrum measurement module OES may be disposed on the window CW. The spectrum measuring module OES may measure the intensity of the emission spectrum using optical emission spectroscopy. The spectrum measuring module OES may be disposed to face the conductive layer of the target substrate SB outside the processing space of the chamber CH. The spectrum measurement module (OES) may measure the intensity of the emission spectrum of the product generated during the etching process in real time. The spectrum measurement module (OES) may measure the intensity of the emission spectrum of the product on the region where the etching reaction of the conductive layer occurs, so that measurement reliability may be improved.

The intensity of the emission spectrum of the product measured by a spectral measurement module (OES) can be used to calculate an etch endpoint. The spectrum measurement module (OES) may measure the emission spectral intensity of a product generated in an etching process in real time, and may predict a reaction step according to an etching time using this. For example, the degree of change in the intensity of the emission spectrum of a specific product may be measured based on a predetermined etching time by the spectrum measurement module (OES), and an etching end point may be easily calculated using this. By calculating an appropriate etching endpoint, it is possible to prevent the conductive layer from being insufficiently etched (under-etched) or excessively etched (over-etched).

The spectrum measurement module (OES) can monitor the change in intensity of the emission spectrum of the product in real time through the change in intensity of the peak measured at a specific wavelength value. For example, the intensity of the emission spectrum of a compound of copper and chlorine such as CuCl and CuCl ₂ (hereinafter, referred to as an emission spectrum of CuCl) generated through an etching process has a wavelength value of about 435 nm, specifically a wavelength of about 435.8 nm. It can be measured through the intensity of the peak measured in the value. The emission spectrum intensity of a compound of copper and hydrogen, such as CuH, generated through the etching process may be measured through the intensity of a peak measured at a wavelength value of about 427 nm, specifically, a wavelength value of about 427.5 nm. An etching end point may be calculated based on the emission spectral intensities of CuCl and CuH, which will be described later with reference to FIGS. 11A and 12 .

The temperature measurement module IR may be disposed on the window CW. The temperature measuring module IR may be disposed to face the conductive layer of the target substrate SB outside the processing space of the chamber CH. Accordingly, the temperature measuring module IR may be an optical system module that measures the temperature by irradiating light on the conductive layer of the target substrate SB through the window CW. For example, the temperature measurement module (IR) may include a thermal imaging camera that measures the temperature by detecting a wave of infrared rays. The temperature measurement module IR may measure the temperature change of the target substrate, in particular, the temperature change of the conductive layer in real time. The temperature measuring module IR may measure the temperature of the target substrate, particularly the conductive layer, on the region where the etching reaction of the conductive layer occurs, so that measurement reliability may be improved.

During the etching process, the temperature of the conductive layer at which the plasmad etching gas PG and the reaction occurs may increase. At this time, when the temperature of the conductive layer approaches the vaporization point of CuCl and CuCl ₂ described above, CuCl and CuCl ₂ may be vaporized, which may cause a redeposition problem. Therefore, in order to prevent this, the temperature measurement module IR may monitor whether the etching is performed while the temperature of the conductive layer is maintained below a specific temperature. For example, the specific temperature may be about 100 degrees. Through this, process reliability of the etching process may be improved.

The cooling module CO may be connected to the susceptor SU to control the temperature of the susceptor SU. The temperature of the target substrate SB may be controlled by adjusting the temperature of the susceptor SU. The cooling module CO may reduce the temperature of the susceptor SU by cooling the susceptor SU, and the temperature of the target substrate SB disposed on the susceptor SU may also be reduced. The cooling module CO may prevent the temperature of the target substrate SB from increasing to approach the vaporization points of CuCl and CuCl ₂ , thereby improving process reliability.

The temperature of the susceptor SU may be lower than room temperature. For example, the temperature of the susceptor SU may be 10 degrees or less. However, the temperature of the susceptor SU is not limited thereto and may vary depending on the process environment or the temperature of the target substrate SB. If the temperature of the susceptor SU is too low, condensation may occur. For example, the temperature of the susceptor SU may be higher than minus 50 degrees Celsius. Process reliability may be improved by maintaining the temperature of the susceptor SU within an appropriate range.

As the temperature of the target substrate SB is lowered by the susceptor SU, a photoresist weak at high temperature may be used as the mask PM. When the target substrate SB includes a plastic substrate, as the temperature of the target substrate SB decreases, damage to the target substrate SB due to high temperature may be prevented.

Meanwhile, although not shown separately, the temperature measuring module IR and the cooling module CO may be connected to a control device, and the control device determines the etching process temperature of the target substrate SB by using the values measured by the respective modules. can be controlled For example, when the temperature of the conductive layer measured by the temperature measurement module (IR) approaches or exceeds 100 degrees, the control device operates the cooling module (CO) to activate the susceptor (SU) and the target substrate ( SB) can be lowered.

Referring to FIG. 6B , the etching apparatus ED according to an embodiment may further include an inspection module LM. The inspection module LM may be disposed on the window CW. The inspection module LM may be disposed to face the conductive layer of the target substrate SB. The inspection module LM may measure a thickness of a conductive layer or an insulating layer included in the target substrate SB. The inspection module LM may include devices for measuring a thickness using light, for example, the inspection module LM may include a spectral reflectometer or an ellipsometer.

The inspection module LM may include a light emitting unit LS and a light sensing unit LD. The light irradiator LS may irradiate the light LL onto the target substrate SB, and the light LL may correspond to the incident light. Hereinafter, the light LL will be referred to as an incident light LL. For example, the incident light LL may be laser light. Although not shown separately, the light irradiation unit LS may further include a polarizer disposed on the light source, and the incident light LL may be polarized light. However, the present invention is not limited thereto, and the shape of the incident light LL irradiated from the light irradiation unit LS may vary according to a thickness measurement method.

The incident light LL incident on the target substrate SB may be partially reflected by meeting the conductive layer or insulating layer included in the target substrate SB. Hereinafter, light reflected from the target substrate SB will be referred to as reflected light RL. The light sensing unit LD may detect the reflected light RL incident toward the light sensing unit LD. The reflected light RL may be polarized light according to the shape of the incident light LL, but is not limited thereto. The light irradiation module LM may calculate a thickness change of the conductive layer or the insulating layer of the target substrate SB based on the incident light LL and the reflected light RL.

The light irradiation unit LS and the light sensing unit LD may be disposed on the window CW to face the target substrate SB. Accordingly, without an additional light path control device, the light irradiator LS may irradiate the light LL on the target substrate SB through the window CW, and the light detector LD may irradiate the window CW. It is possible to detect the reflected light RL transmitted through the .

It may be inspected whether the etching process is properly performed through the thickness of the conductive layer or the insulating layer measured by the inspection module LM. By using the change in the thickness of the conductive layer, it may be checked whether the etching of the conductive layer is performed with a set value. By overlapping a portion of the etched conductive layer, the insulating layer disposed under the conductive layer may be exposed to the outside, and by measuring the thickness of the exposed insulating layer, it can be checked whether the etching of the conductive layer is complete. can Hereinafter, a description of the inspection step by the inspection module LM will be described later with reference to FIGS. 8A to 8C .

Referring to FIG. 6C , the etching apparatus ED according to an embodiment may further include a controller CP. The controller CP may be respectively connected to a temperature measurement module IR, a spectrum measurement module OES, an inspection module LM, and a plasma source module ES included in the etching apparatus ED. The controller CP may receive temperature information of the target substrate SB measured by the temperature measurement module IR. The control unit CP may receive intensity information of the emission spectrum of the product measured by the spectrum measurement module OES. The control unit CP may receive thickness information of the conductive layer or the insulating layer measured by the inspection module LM. The controller CP may receive information measured by each module in real time during the etching step.

The controller CP may calculate an etching end point based on intensity information of the emission spectrum of the product and thickness information of the conductive layer or insulating layer. For example, the control unit CP may calculate the etching end point using the degree of change in the intensity of the emission spectrum of the product and the measurement time of the thickness of the insulating layer disposed under the conductive layer. Through this, the calculation reliability of the etch end point may be improved. However, the present invention is not limited thereto, and the controller CP may calculate an etch end point based on any one information of intensity information of an emission spectrum and thickness information of a conductive layer or an insulating layer.

The controller CP may control the plasma source module ES at the etching end point. The controller CP may stop driving the plasma source module ES at the etching end point. Due to this, the plasma etching step S30 by the plasma source module ES may be stopped.

6C exemplarily shows an embodiment of the control unit CP. The controller CP may be connected to some of the illustrated modules to control the connected modules. Alternatively, a plurality of control units CP may be provided and each may be connected to each module, and the plurality of control units may each control the connected modules, and the embodiment is not limited thereto.

The configurations of the etching apparatuses ED shown in FIGS. 6A to 6C are schematically illustrated, and the etching apparatus ED of the present invention includes various devices for controlling and operating the apparatus in addition to the illustrated configurations, or It can be connected to various devices and is not limited to any one embodiment.

8A to 8C are cross-sectional views illustrating a step of a method of manufacturing a display panel according to an exemplary embodiment. The steps illustrated in FIGS. 8A to 8C may correspond to the above-described inspection step.

8A to 8C , the target substrate SB may include at least one conductive layer P-CL1 and an insulating layer INS. The target substrate SB may include a conductive layer P-CL1 and an underlayer ULa disposed under the insulating layer INS. The lower layer ULa may include a plurality of stacked bodies. The configuration of the lower layer ULa may vary depending on the configuration to be formed by etching the conductive layer P-CL1. For example, when the connection line CNL of FIG. 4 is formed by etching the conductive layer P-CL1, the insulating layer INS may correspond to the second insulating layer INS2 of FIG. The lower layer ULa may correspond to stacks disposed under the insulating layer INS2 of FIG. 4 .

The above-described inspection module LM may measure the thickness of the layer on which the incident light LL is incident. As illustrated in FIG. 8A , the incident light LL may be incident on the conductive layer P-CL1 . In this case, the inspection module LM may measure the thickness of the conductive layer P-CL1 . The present invention is not limited thereto, and as illustrated in FIGS. 8B and 8C , the incident light LL may be incident on the insulating layer INS. In this case, the inspection module LM may measure the thickness of the insulating layer INS.

The incident light LL may be incident at an angle with respect to a surface to which the incident light LL is irradiated. That is, the incident light LL may be incident in a direction that intersects the direction of the normal NL of the surface to which the incident light LL is irradiated. One surface of the conductive layer P-CL1 on which the incident light LL is incident may correspond to a surface parallel to each of the first and second directions DR1 and DR2, and a normal line of the conductive layer P-CL1 (NL) may be defined along the third direction DR3. Accordingly, the incident light LL may be irradiated along one direction crossing the third direction DR3 . The incident light LL may be incident with an incident angle greater than 0 degrees with respect to the normal NL of the incident surface.

8A and 8B exemplarily show a cross-section in which the thickness of the conductive layer P-CL1 or the insulating layer INS is measured using an inspection module LM including a spectral reflectometer. will be.

Referring to FIG. 8A , the incident light LL may be incident on the conductive layer P-CL1 . A portion of the incident light LL may be refracted in the conductive layer P-CL1 . Light transmitted through the conductive layer P-CL1 may be reflected on an interface between the conductive layer P-CL1 and the insulating layer INS. A portion of the incident light LL may be reflected on the upper surface of the conductive layer P-CL1 .

The inspection module LM according to an exemplary embodiment may calculate a thickness change of the conductive layer P-CL1 based on the interference between the incident light LL and the reflected light RL. Specifically, the thickness change of the conductive layer P-CL1 may be calculated by measuring the offset and constructive interference according to the wavelengths of the incident light LL and the reflected light RL. The inspection module LM may calculate the thickness of the conductive layer P-CL1 by using destructive and constructive interference information according to the measured wavelength, and a refractive index and extinction coefficient of the conductive layer P-CL1 . The present invention is not limited thereto, and the inspection module LM may calculate the thickness of the conductive layer P-CL1 using a model equation such as Cauchy or Sellmeier.

Referring to FIG. 8B , as the etching process proceeds, a portion of the conductive layer CL that does not overlap the mask PM may be etched, and the insulating layer INS may be etched according to the etching of the conductive layer CL. can be exposed to the outside. In this case, the incident light LL may be incident on the insulating layer INS. A portion of the incident light LL may be reflected on the upper surface of the insulating layer INS, and a portion of the incident light LL may be reflected on an interface between the insulating layer INS and the lower layer ULa. Similarly to the step of calculating the thickness of the conductive layer P-CL1 , the inspection module LM may calculate the thickness of the insulating layer INS based on the interference between the incident light LL and the reflected light RL.

FIG. 8C illustrates a cross-section in which the thickness of the insulating layer INS is measured by using the inspection module LM including an ellipsometer. Although FIG. 8C illustrates a step in which the thickness of the insulating layer INS is calculated, the present invention is not limited thereto, and conduction is performed using the inspection module LM including an ellipsometer according to the layer on which the incident light LL-P is incident. The thickness of the layer P-CL1 can be measured.

Referring to FIG. 8C , the incident light LL-P may be polarized light, and for example, the incident light LL-P may be linearly polarized light. A portion of the polarized incident light LL-P may be reflected on the insulating layer INS. The reflected light RL-P reflected from the insulating layer INS may be polarized light, for example, the reflected light RL-P may be elliptically polarized light.

The thickness of the insulating layer INS may be calculated by measuring the amount of change in polarization of the incident light LL-P and the reflected light RL-P. The thickness of the insulating layer INS may be calculated using a phase difference between the incident light LL-P and the reflected light RL-P and a reflection amplitude ratio angle (an angle at which a tangent value becomes an amplitude ratio of the reflected light).

The conductive layer CL, which has been sufficiently etched, may expose a portion of the insulating layer INS, and the inspection module LM may measure the thickness of the insulating layer INS. A point at which the thickness of the insulating layer INS is measured may be calculated as an etching end point. Accordingly, an etch end point may be calculated based on a change in the thickness of the conductive layer P-CL1 or the insulating layer INS. Alternatively, whether the etch endpoint calculated based on the emission spectral intensity is reliable may be checked by measuring the thickness of the conductive layer P-CL1 or the insulating layer INS. Using the thickness of the conductive layer P-CL1 or the insulating layer INS, it is possible to predict whether the etching has been sufficiently performed, and through this, it can be checked whether the etching is stopped by an appropriate etching end point.

9 is a cross-sectional view of a target substrate according to an exemplary embodiment after an etching step is completed. 9 exemplarily illustrates a cross-section of the target substrate SB separated from the susceptor. Referring to FIG. 9 , a portion of the conductive layer CL of the target substrate SB on which the etching step has been completed may be etched and patterned. The patterned conductive layer CL may correspond to the above-described wirings or electrodes of the display panel DP. The conductive layer CL etched using the etching apparatus ED according to an embodiment of the present invention may be etched uniformly and precisely, and reliability may be improved.

10 is a graph illustrating a temperature change according to an etching time of a conductive layer according to an embodiment. Referring to FIG. 10 , in an etching process, the temperature TC of the conductive layer may gradually increase as an etching time passes. The copper in the conductive layer can generate heat when it reacts with chlorine ions and chlorine radicals to form products. Accordingly, the temperature TC of the conductive layer may increase with the lapse of etching time due to heat generated by product formation or energy of plasma. At this time, when the temperature (TC) of the conductive layer is higher than a specific temperature value (TP) adjacent to the vaporization point of CuCl and CuCl ₂ , CuCl and CuCl ₂ - formed in the conductive layer may be vaporized, and as described above, CuCl and CuCl ₂ − may cause a problem of lowering process reliability due to redeposition.

Therefore, the etching apparatus of the present invention can check whether the process reliability is maintained by measuring the temperature (T-C) of the conductive layer in real time, and control the temperature of the susceptor to set the temperature (T-C) of the conductive layer to a specific temperature value ( T-P) or less.

11 is a graph illustrating the intensity of an emission spectrum according to an etching time. 12 is an enlarged graph of one area AA illustrated in FIG. 11 .

11 exemplarily illustrates emission spectra of Cu(I), Cu(II), CuCl and CuH according to etching time. As described above, emission spectra of Cu(I), Cu(II), CuCl and CuH may be measured by changing the intensity of the peak measured at each specific wavelength value.

The first point ET0 of FIG. 11 may correspond to a stage before the etching process is performed. The second point ET1 of FIG. 11 may correspond to a point where the plasma etching step S30 of FIG. 5 starts by driving the plasma source module. Intensities of emission spectra of Cu(I), Cu(II), CuCl, and CuH may hardly change at a stage between the first point ET0 and the second point ET1 before the plasma source module is driven. .

After the second point ET1 of FIG. 11 , intensities of emission spectra of Cu(I), CuCl, and CuH may rapidly increase due to a radical reaction between copper and chlorine. In particular, the intensity of the emission spectrum of CuCl may increase most rapidly, and the intensity of the emission spectrum of CuCl may have a peak value at the third point ET2 of FIG. 11 . Intensities of emission spectra of Cu(I), CuCl, and CuH may each increase in a step between the second point ET1 and the third point ET2 . The step between the second point ET1 and the third point ET2 may correspond to a step in which the copper and chlorine radicals of the conductive layer react, and the third point ET2 is the CuCl ₂ , as shown in FIG. 7B . It may correspond to a point where growth has reached saturation. Thereafter, CuCl ₂ may react with hydrogen radicals to be vaporized into CuH and Cu ₃ Cl ₃ . Therefore, after CuCl is formed, the intensity of the emission spectrum of CuH may also increase.

After the third point ET2 of FIG. 11 , CuCl ₂ is saturated and is no longer formed, and may be vaporized into CuH and Cu ₃ Cl ₃ . Accordingly, the intensity of the emission spectrum of CuCl after the third point ET2 may be decreased. As the intensity of the emission spectrum of CuCl decreases, the intensity of the emission spectrum of CuH may also decrease.

The fourth point ET3 of FIG. 11 may correspond to an etching end point. In a step corresponding to between the third point ET2 and the fourth point ET3 , CuCl ₂ may be vaporized into CuH and Cu ₃ Cl ₃ , and the conductive layer of copper may be etched and patterned. At the fourth point ET3 of FIG. 11 , the driving of the plasma source module may be stopped, and an additional plasma source may not be provided in the apparatus. In a step corresponding to between the fourth point ET3 and the fifth point ET4 after the etching end point, the generated CuH and Cu ₃ Cl ₃ may be discharged to the outside of the chamber through a piping device of the etching apparatus.

Referring to FIG. 12 , an etching end point may be calculated using a change in intensity of an emission spectrum of a product. The product may comprise at least one of CuCl and CuH. FIG. 12 shows only the intensity of the emission spectrum of CuCl corresponding to the area AA of FIG. 11 . Hereinafter, the etching end point calculated based on the intensity of the emission spectrum of CuCl will be described as an example.

Referring to FIG. 12 , the intensity of the emission spectrum according to the etching time may be calculated using the intensity of the emission spectrum measured by the spectrum measurement module. Using this, the degree of change in the intensity of the emission spectrum of CuCl based on a predetermined time (ΔET) may be measured. That is, by differentiating the intensity of the emission spectrum of CuCl according to the etching time, the degree of change in the intensity of the emission spectrum of CuCl may be measured. The value of the predetermined time (ΔET), which is a reference for measuring the degree of change in the intensity of the emission spectrum, may be adjusted by setting.

The intensity of the emission spectrum of CuCl corresponding to a specific time shown in FIG. 12 is briefly referred to as "intensity" hereinafter, and the change in the intensity of the emission spectrum of CuCl changed in response to a predetermined time (ΔET) is briefly referred to as "change amount". call it

Referring to FIG. 12 , the first change amount ΔI1 may correspond to a change from the first intensity E1 to the second intensity E2 for a predetermined time ΔET. The second change amount ΔI2 may correspond to a change from the second intensity E2 to the third intensity E3 for a predetermined time ΔET. The third change amount ΔI3 may correspond to a change from the third intensity E3 to the fourth intensity E4 for a predetermined time ΔET. Based on the embodiment illustrated in FIG. 12 , the value of the change amount may be large in the order of the third change amount ΔI3 , the first change amount ΔI1 , and the second change amount ΔI2 .

In order to calculate the etching end point, a point at which the amount of change becomes greater than or equal to a specific specified value may be selectively calculated. The specific designated value may be set in consideration of an etching process condition, a measurement error range, and the like. For example, when a specific designated value is designated as a value greater than the first change amount ΔI1 of FIG. 12 and smaller than the third change amount ΔI3 of FIG. 12 , the fourth intensity E4 at which the third change amount ΔI3 is calculated. ) may be calculated as an etch end point. If the specific designated value is designated as a value greater than the third change amount ΔI3, after the point corresponding to the fourth intensity E4, an intensity point having a change amount corresponding to the designated value may be calculated.

Although the description has been made based on the intensity of the emission spectrum of CuCl, it is not limited thereto, and a degree of change in the intensity of the emission spectrum of CuH may be used to calculate the etch end point. A specific designated value of the change amount set for calculating the etching endpoint may be different depending on the type of product. Meanwhile, the intensity graphs of the emission spectra shown in FIGS. 11 and 12 are exemplary, and the shape of the graph may vary according to etching process conditions.

The etching apparatus according to an embodiment may include a spectrum measurement module. The spectrum measurement module may measure an emission spectrum of a product generated in the etching process, and may calculate an etching end point using the emission spectrum of the product. By calculating an appropriate etch endpoint, under-etching or over-etching can be prevented.

The etching apparatus according to an embodiment may include a temperature measuring module. The temperature measurement module may monitor the temperature change of the conductive layer during the etching process. Through this, it can be confirmed whether the etching of the conductive layer is performed below a specific temperature, and the reliability of the etching process can be improved.

The etching apparatus according to an embodiment may include an inspection module for measuring a change in thickness of a conductive layer or an insulating layer. By measuring the thickness of the conductive layer or the insulating layer, it can be confirmed whether the conductive layer is sufficiently etched. In particular, by measuring the thickness of the conductive layer or the insulating layer at the etching end point, the etching process reliability can be improved.

A method of manufacturing a display panel according to an embodiment may include a plasma etching step using the etching apparatus of the present invention. The method of manufacturing a display panel according to an exemplary embodiment may improve process reliability by measuring the emission spectrum of a product, measuring the temperature of the conductive layer, and measuring the thickness of the conductive layer, and may manufacture a display panel with improved reliability.

Although the above has been described with reference to the preferred embodiment of the present invention, those skilled in the art or those having ordinary knowledge in the technical field will not depart from the spirit and technical scope of the present invention described in the claims to be described later. It will be understood that various modifications and variations of the present invention can be made without departing from the scope of the present invention.

Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

DP: Display panel ED: Etching device
SB: target substrate P-CL1, P-CL2, CL: conductive layer
INS: insulating layer SU: susceptor
CH: chamber ES: plasma source module
IR: Temperature measurement module OES: Spectrum measurement module
CW: Window CO: Cooling module
LM: Inspection module LS: Light irradiator
LD: light sensing unit CP: control unit
PM: Mask

Claims (20)

disposing a target substrate including a conductive layer on a susceptor;
providing an etching gas including chlorine and hydrogen on the target substrate;
Plasma etching using the etching gas;
measuring a temperature of the target substrate during the plasma etching step; and
Calculating an etching end point and stopping the etching step. The method of claim 1,
The etching end point is calculated based on a change in intensity of an emission spectrum of a product generated in the plasma etching step. 3. The method of claim 2,
The method for manufacturing a display panel, wherein the product includes at least one of CuCl, CuCl ₂ and CuH. The method of claim 1,
A method of manufacturing a display panel in which a temperature of the target substrate is maintained at 100 degrees C or less during the plasma etching step. The method of claim 1,
Further comprising an etch check step,
The target substrate further includes an insulating layer disposed under the conductive layer,
The etching inspection step is
irradiating incident light to the target substrate;
measuring reflected light reflected from the target substrate; and
and calculating a thickness of a layer on which the incident light is incident based on the incident light and the reflected light. 6. The method of claim 5,
The incident light is incident on the conductive layer,
The thickness of the conductive layer is calculated by measuring interference between the incident light and the reflected light. 6. The method of claim 5,
The incident light is incident on the conductive layer,
The incident light is polarized light,
The thickness of the conductive layer is calculated by measuring a polarization amount of the reflected light from the incident light. 6. The method of claim 5,
The incident light is incident on the insulating layer,
A method of manufacturing a display panel for calculating a thickness of the insulating layer based on the incident light and the reflected light. 6. The method of claim 5,
The etching end point is calculated based on a change in intensity of an emission spectrum of a product generated in the plasma etching step and a thickness of a layer on which the incident light is incident. a chamber providing a processing space in which an etching process is performed;
a susceptor disposed in the processing space and configured to support a target substrate including a conductive layer;
a plasma source module disposed on the chamber;
a window connected to the chamber and disposed to face the conductive layer; and
and a spectrum measuring module disposed to face the conductive layer on the window and measuring an emission spectrum of an etching product,
The product is an etching device comprising CuCl and CuH. 11. The method of claim 10,
Further comprising a temperature measuring module disposed on the window to face the conductive layer,
The temperature measuring module is an etching device for measuring the temperature of the conductive layer. 11. The method of claim 10,
Further comprising a control unit connected to the spectrum measurement module and the plasma source module,
The control unit calculates an etching end point based on the emission spectrum of the product, and when the etching end point is reached, the etching apparatus controls the plasma source module. 11. The method of claim 10,
Further comprising an inspection module disposed on the window,
The inspection module is an etching device for measuring a change in the thickness of the conductive layer. 14. The method of claim 13,
The inspection module is
a light irradiator for irradiating light onto the target substrate; and
And a light sensing unit for detecting the reflected light reflected from the target substrate,
An etching apparatus in which the incident direction of the light intersects a normal direction of the incident surface of the light. 14. The method of claim 13,
The light irradiator further comprises a polarizer. 11. The method of claim 10,
and the plasma source module includes an electron cyclotron resonance (ECR) source module. 11. The method of claim 10,
Etching apparatus further comprising a cooling module for cooling the susceptor. a chamber providing a processing space in which an etching process is performed;
a susceptor disposed in the processing space and configured to support a target substrate including a conductive layer;
a plasma source module disposed on the chamber;
a window connected to the chamber and disposed to face the conductive layer; and
a spectrum measuring module, a thermal imaging camera module and an inspection module disposed on the window to face the conductive layer;
The spectrum measurement module measures the emission spectrum of the etching product,
The thermal imaging camera module measures the temperature of the conductive layer,
The inspection module is an etching device for measuring a change in the thickness of the conductive layer. 19. The method of claim 18,
The inspection module is an etching apparatus including a spectral reflectometer or an ellipsometer. 19. The method of claim 18,
Further comprising a control unit connected to the spectrum measuring module, the thermal imaging camera module, the inspection module and the plasma source module,
The controller controls the plasma source module by monitoring an emission spectrum of the product, a temperature of the conductive layer, and a change in a thickness of the conductive layer during an etching process.

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