KR20220110487A - Pulse generating circuit and electrosurgical generator including same - Google Patents

Abstract

The present invention relates to a bipolar pulse generating circuit for an electrosurgical generator for generating a waveform suitable for inducing electroporation of living tissue. A bipolar pulse generating circuit includes a coaxial power transmission line having a voltage source connectable to a load through a switching element, and an inner conductor separated from an outer conductor by a dielectric material. The inner conductor has a first end connected between the input of the switching element and a voltage source and a second end in an open circuit state, such that the coaxial transmission line is charged by the voltage source when the switching element is in an OFF state and the switching element It will be discharged when it is in the ON state. the bipolar pulse generating circuit comprises a first output connectable to the load, the first output being located between the output of a switching element and ground to support a positive pulse when the coaxial transmission line is discharged, and a first output connectable to the load The second output further includes a second output located between the outer conductor of the coaxial power line and ground to support a negative pulse when the coaxial power line is discharged. The impedance of the coaxial transmission line is configured to match the sum of (i) the impedance of the switching element, (ii) the impedance of the load at the first output, and (iii) the impedance of the load at the second output.

Description

Pulse generating circuit and electrosurgical generator including same

The present invention relates to an electrosurgical generator for generating a waveform suitable for inducing electroporation of living tissue. In particular, the present invention relates to a pulse generating circuit for an electrosurgical generator, wherein the pulse generating circuit is configured to generate a high voltage pulse having a duration of less than 10 ns.

Electrosurgical generators are widespread throughout hospital operating rooms for use in open and laparoscopic procedures, and are increasingly used in endoscopic laboratories as well. In endoscopic procedures, an electrosurgical accessory is typically inserted through a lumen inside the endoscope. Considering equivalent access channels for laparoscopic surgery, these lumens are relatively narrower and longer in length.

WO 2019/185331 A1 discloses an electrosurgical generator capable of supplying energy with a waveform for causing electroporation in living tissue. The electrosurgical generator may comprise an electroporation waveform supply unit incorporating means for generating microwave electromagnetic signals and radiofrequency electromagnetic signals for treatment. The electrosurgical generator may be configured to deliver different types of energy along a common feed cable. The electroporation waveform supply unit includes a DC power supply and a DC pulse generator. The DC power supply may include a DC-DC converter for up-converting the voltage output by the adjustable voltage supply. Each DC pulse may have a duration of 1 ns to 10 ms and a maximum amplitude of 10 V to 10 kV.

In recent years, many microwave electric field pulse generators have been developed [1]. Ultrashort electric field pulses in the nanosecond region have a variety of applications. Applications include particle measurement, photography, ultra-wideband radar detection, and medical applications [2]-[3].

There are many methods for generating high-amplitude, nanosecond pulsed electric fields with rise and fall times of 2 ns. Traditionally, coaxial transmission line-based implementations such as spark-gap, Marx bank, or Bloomlein correlated with diode and laser open switch techniques have been used to generate high voltage nanosecond pulses [ One].

Most generally, the present invention provides a pulse generating circuit for an electrosurgical generator configured to generate a high voltage pulse having a duration of less than 10 ns suitable for inducing electroporation of living cells. In particular, the pulse generation circuit disclosed herein may be suitable for generating bipolar pulses exhibiting a 'flat-top' profile, ie, with steep (eg, less than 2 ns) rise and fall times with minimal ringing. As will be explained in more detail below, this can be achieved through open circuit transmission line techniques, along with placing a pair of load outputs (for positive and negative pulses) in appropriate locations relative to the transmission line and high-speed switching elements. have.

According to the present invention there is provided a bipolar pulse generating circuit for an electrosurgical generator, the bipolar pulse generating circuit comprising a voltage source connectable to a load through a switching element, a coaxial transmission line having an inner conductor separated from an outer conductor by a dielectric material - The inner conductor has a first end connected between the input of the switching element and a voltage source and a second end in an open circuit state such that the coaxial transmission line is charged by the voltage source when the switching element is in an OFF state and the switching element is in an OFF state. discharged when ON, a first output connectable to the load, the first output being located between the output of a switching element and ground to support a positive pulse when the coaxial power line is discharged, and the a second output connectable to a load, the second output being located between the outer conductor of the coaxial transmission line and ground to support a negative pulse when the coaxial transmission line is discharged, wherein the impedance of the coaxial transmission line is (i) a switching element; is configured to match the sum of the impedance of (ii) the impedance of the load at the first output, and (iii) the impedance of the load at the second output. Using this structure, the circuit can generate bipolar pulses of very short (eg, less than 10 ns) duration in which the positive and negative portions of the pulse are symmetrical. Matching the impedances ensures that reflections are minimized or eliminated. This circuit configuration is capable of producing flat top pulses (due to matched impedance states) with short durations (controlled by the length of the coaxial transmission line).

As one example, a delay line may be connected to either the first output or the second output, such that the supply of positive and negative pulses at the first output and the second output occurs sequentially. For example, a delay line may be connected between the second output and the outer conductor of the coaxial power transmission line. The length of the delay line is selectable (or adjustable) to control how much a negative pulse appears in the second output for the beginning of a positive pulse. It is possible to include a delay line connected to each of the first output and the second output to provide full control of the profile of the output bipolar waveform. Specifically, it may be desirable to provide a delay line having an adjustable length so that the spacing of the positive and negative pulses can be controlled independently. The delay line may have any suitable structure. For example, it could be another length of coaxial power transmission line.

The switching element may include a plurality of series-connected avalanche transistors, and a trigger pulse generator configured to generate a trigger pulse to activate the plurality of series-connected avalanche transistors. This allows positive and negative pulses to have very short rise and fall times and amplitudes suitable for electroporation due to the cascading effect of series-connected avalanche transistors. In particular, the amplitude of the output may be 500V or greater, such as 1kV or greater, without exceeding the collector-base breakdown voltage across any of the plurality of series-connected avalanche transistors.

The coaxial transmission line may have a length selected to provide a line delay of 5 ns or less. The pulse duration is twice the line delay, so the output pulse can have a duration of 10 ns or less.

A coaxial transmission line can be charged by a voltage source through a resistor with high impedance, for example 1 MΩ. The circuit can thus be considered to include a first loop when the switching element is in an OFF state and a second loop when the switching element is in an ON state. In the first loop, current may flow from a voltage source through the resistor to charge the coaxial power line. In the second loop, current flows from the coaxial transmission line through the switching element to the load.

The trigger pulse may include a TTL signal. The trigger pulse generator may be any source suitable for generating such a signal, such as a microprocessor or the like. The trigger pulse may have a voltage lower than the emitter-base breakdown voltage of each of the plurality of avalanche transistors. The duration of the trigger pulse may be longer than the duration of the pulse from the coaxial power line to ensure that the switching element is in the ON state long enough for the coaxial power line to fully discharge. In one example, the trigger pulse has a voltage of 5V and a duration of 600ns.

The trigger pulse generator may be coupled to a plurality of series-connected avalanche transistors via a transformer. This means that the trigger signal is floating between the base and emitter, and thus is independent of the voltage across the transistor and on the load. In one example, the trigger pulse may be applied between the collector and the emitter of a first transistor of the plurality of series-connected avalanche transistors. The first transistor may be the one farthest from the coaxial transmission line.

A diode may be coupled in parallel with each avalanche transistor of the plurality of series coupled avalanche transistors to clamp the voltage across each transistor below its collector-base breakdown voltage. This protects the transistor.

Each transistor in the plurality of series-connected avalanche transistors may be identical so that the voltage of the voltage source is equally divided among the transistors.

As mentioned above, the present invention is particularly suitable for use in electrosurgery. The load thus includes an electrosurgical instrument capable of delivering monopolar pulses for electroporation of living tissue.

In another example, the present invention may provide an electrosurgical generator having a pulse generating circuit as provided above. The pulse generating circuit may be configured to generate an electroporation waveform, ie, a burst of energy suitable to cause electroporation of biological tissue. The electroporation waveform may include one or more rapid high voltage pulses. Each pulse may have a pulse width of 1 ns to 10 μs, preferably 1 ns to 10 ns, although the present invention need not be limited to these ranges. Pulses of shorter duration (eg, 10 ns or less) may be preferred for reversible electroporation.

Preferably, the rise time of each pulse is no more than 90% of the pulse duration, more preferably no more than 50% of the pulse duration, and most preferably no more than 10% of the pulse duration.

Each pulse may have an amplitude of 10V to 10kV, preferably 1kV to 10kV. Each pulse may be a positive pulse from ground potential.

The electroporation waveform may be a single pulse or a plurality of pulses, such as pulses of a periodic train. The waveform may have a duty cycle of 50% or less, such as between 0.5% and 50%.

BRIEF DESCRIPTION OF THE DRAWINGS Embodiments of the present invention are described below with reference to the accompanying drawings.
1 is a schematic diagram illustrating the principle of a discharge line generator with an ideal switch.
FIG. 2A is a graph showing voltage waveforms in (i) a power transmission line and (ii) a load of FIG. 1 .
Fig. 3a is a schematic diagram showing the open circuit power transmission line of Fig. 1 in a DC model;
Fig. 3b is a schematic diagram showing the open circuit transmission line of Fig. 1 in a transmission line model;
FIG. 4 is a schematic diagram showing the open circuit power line of FIG. 1 with avalanche transistors to generate positive ultrashort electric field pulses;
5 is a diagram of a simulated LTSpice circuit of a monopolar ultrashort electric field pulse generator.
FIG. 6 is a graph illustrating pulses of various durations generated from the LTSpice circuit of FIG. 5;
FIG. 7 is a monopolar positive pulse observed with a matched 35Ω load, from the circuit of FIG. 5 .
8 is a schematic diagram showing the open circuit power line of FIG. 1 with an avalanche transistor to generate a negative ultrashort electric field pulse;
9 is a diagram of a simulated LTSpice circuit of a monopolar ultrashort electric field pulse generator configured to generate a negative pulse.
FIG. 10 is a monopolar negative pulse observed with a matched 35Ω load, from the circuit of FIG. 9 .
11A is a diagram of a simulated LTSpice circuit of a bipolar ultrashort electric field pulse generator without a delay line.
11B is a diagram of a simulated LTSpice circuit of a bipolar ultrashort electric field pulse generator with a delay line before load.
12A is a graph showing voltages observed at various points in the circuit of FIG. 11A.
12B is a graph showing voltages observed at various points in the circuit of FIG. 11A.

,

의 길이, 및 유전 상수

를 갖는 동축 송전 선이 고 임피던스 저항기

를 통해 전압 레벨

까지 충전된다. 선은 다음의 수학식에 의해 주어진 연관된 딜레이 시간

을 가질 것이다:It is possible to generate ultra-short pulses by using an open circuit coaxial transmission line as a high-Q storage element consisting of a distributed series inductor and shunt capacitor with minimum resistance and shunt conductance. Discharging an open-ended delay line through a fast switching element provides a means to generate a 'flat-top' square pulse with a steep fall time of less than 2 ns in a simple and inexpensive manner. characteristic impedance,

,

length, and dielectric constant

A coaxial transmission line with a high impedance resistor

voltage level through

is charged up to The line is the associated delay time given by

will have:

는 빛의 속도(2.99Х10⁸ m/s)이다.here

is the speed of light (2.99Х10 ⁸ m/s).

From this it is derived that the pulse duration associated with the transmission line is:

를 통해 송전 선을 방전시킴으로써, 초단 전기장 펄스가 부하,

에서 생성될 수 있다. 송전 선이 펄스 지속시간(또는 폭) 및 하강 시간을 결정하는 동안 스위칭 요소는 초단 전기장 펄스의 상승 시간을 결정한다.By closing the switching element,

By discharging the transmission line through

can be created in While the transmission line determines the pulse duration (or width) and fall time, the switching element determines the rise time of the ultrashort electric field pulse.

As explained above, the duration of the pulse at the load will be twice the associated delay time of the transmission line.

1 illustrates the principle of an open circuit power transmission line technique with an ideal switch as a switching element.

및 (ii) 부하

에서의 도 1의 시스템으로부터 획득된 전압 파형을 보여준다.2 is (i) a power transmission line

and (ii) load

shows the voltage waveform obtained from the system of FIG.

및 부하

의 특성 임피던스 간 관계가 개방 회로 동축 송전 선 기법의 성능에 두 가지 방식으로 중요하며, 이는 직접 회로(DC) 이론 및 송전 선 이론을 이용해 구성을 모델링함으로써 이해될 수 있다.transmission line

and load

The relationship between the characteristic impedances of is important in two ways for the performance of the open circuit coaxial transmission line technique, which can be understood by modeling the configuration using integrated circuit (DC) theory and transmission line theory.

와

간 관계가 전위 분압기(potential divider)를 모방한다. 이들 관계는 부하에서의 펄스 폭

을 결정한다:In DC theory, as shown in Fig. 3a

Wow

The interrelationship mimics a potential divider. These relationships are the pulse width at the load

to determine:

가

와 동일한 경우, 부하에서의 펄스의 최대 진폭

이 송전 선이 충전되는 전압의 절반일 것이다:impedance

go

If equal to, the maximum amplitude of the pulse at the load

This will be half the voltage at which the transmission line is charged:

인 때,

when it is,

와

간 관계가 반사 계수를 결정하고, 따라서 부하에서의 펄스 형태를 결정한다.

가

와 동일한 경우, 반사 계수가 0일 것이며 일차 펄스 어떠한 이차 펄스 또는 반사도 부하에서 보여지지 않을 것이다.Using the transmission line model, the system can be represented as shown in Figure 3b. In this model,

Wow

The relationship between the two determines the reflection coefficient and thus the shape of the pulse at the load.

go

, the reflection coefficient will be zero and no secondary pulses or reflections will be seen in the load.

와

의 관계가 부하에서의 펄스의 두 개의 핵심 양태를 결정한다: (i) 펄스 진폭, 및 (ii) (임의의 반사에 의해 야기된) 펄스 형태. 상기의 분석으로부터, 송전 선

및 부하

의 최상 펄스 형태 및 파라미터, 특성 임피던스가 정합될 것이다.therefore,

Wow

The relationship of s determines two key aspects of the pulse at the load: (i) pulse amplitude, and (ii) pulse shape (caused by random reflections). From the above analysis, the transmission line

and load

The best pulse shape and parameters of , and characteristic impedance will be matched.

Other characteristics of the pulse are controlled by other parameters of the circuit. For example, the pulse rise time is determined by the behavior of the switching element, and the pulse width, as mentioned above, is determined by the length of the transmission line.

= 0 A이고 이미터 전류

= 0 A일 때 콜렉터 이미터(

)와 콜렉터 베이스(

) 전압 사이에 애벌랜치 영역이 존재한다.Preferably, this switching element in an embodiment of the invention is provided by a stacked array of avalanche transistors. Avalanche transistors are known to provide reliable, repeatable, high-speed switching of high voltages with a rise time of 300 ps, which can be implemented in practice when microwave component layout techniques are considered in circuit implementation. The avalanche transistor utilizes the negative-resistive characteristic region of a bipolar junction transistor, which is derived from operation in the common-emitter breakdown region. base current

= 0 A and emitter current

= 0 when the collector emitter (

) and collector base (

), there is an avalanche region between the voltages.

로의 개방-회로 송전 선의 방전에 기초한다.4 is a schematic diagram of a pulse generation circuit 100 using an open circuit power transmission line technique in combination with an avalanche transistor as a fast switching element. The circuit functions load across the avalanche transistor

It is based on the discharge of an open-circuit transmission line into a furnace.

인 경우 출력에서의 최대 펄스 진폭이 트랜지스터의 콜렉터-이미터 항복 전압

의 값의 절반으로 한정된다. 트랜지스터의

보다 높은 공급 전압

이 영구적으로 항복할 것이며 스위칭 요소로서의 애벌랜치 트랜지스터를 손상시킬 것이다. A single avalanche transistor circuit may be configured to have bi-stable operation, wherein:

If the maximum pulse amplitude at the output is the collector-emitter breakdown voltage of the transistor

is limited to half the value of transistor's

higher supply voltage

This will permanently yield and damage the avalanche transistor as a switching element.

상에 펄스를 생성한다. 베이스 상의 트리거의 폭이

, 즉, 부하에서 필요한 펄스 폭보다 길다.First, energy is stored in the coaxial transmission line through a small current flow in loop 1. A positive trigger on the base of the transistor will abruptly switch the transistor 'on'. The energy stored in the transmission line will be simultaneously released as a high current along loop 2, which

generate a pulse on the the width of the trigger on the base

, that is, longer than the required pulse width at the load.

이 직렬 체인 내 각각의 애벌랜치 트랜지스터에 걸쳐 동일하게 분산되도록 각각의 애벌랜치 트랜지스터가 동일하다.5 shows a pulse generating circuit 200 which is one embodiment of the present invention. Pulse generation circuit 200 is similar to the circuit shown in FIG. 4 except that instead of a single avalanche transistor, there are a plurality (five in this example) series-connected avalanche transistors. A plurality of series-connected avalanche transistors are effectively combined and operated as a single avalanche transistor. This causes a cascade effect in which the discharge of an open-circuit power line is made across the stacked transistors to the load, resulting in a relatively high pulse amplitude at the load. In this example, the supply voltage

Each avalanche transistor is identical so that it is distributed equally across each avalanche transistor in this series chain.

에 따라 달라진다. 특정 펄스 진폭

을 생성하는 데 요구되는 애벌랜치 트랜지스터의 수가 다음과 같이 표현될 수 있다In this arrangement, the maximum pulse amplitude that can be generated is the number of stacked avalanche transistors.

depends on specific pulse amplitude

The number of avalanche transistors required to generate

는 각각의 애벌랜치 트랜지스터의 콜렉터-베이스 항복 전압이다.

인 경우, 따라서, 최대 펄스 진폭

이 다음과 같이 표현될 수 있다here

is the collector-base breakdown voltage of each avalanche transistor.

If , then, the maximum pulse amplitude

This can be expressed as

및 320V의 콜렉터-베이스 항복 전압

을 가진다. 도 5에 도시된 회로는 LTSpice 모델을 이용해 시뮬레이션되었다. FMMT417의 Spice 모델이 제조업체의 웹사이트로부터 직접 얻어졌다. 소스 저항

이 1 MΩ이고, 송전 선의 특성 임피던스

가 50 Ω이며, 소스 전압

이 1.5kV이다.Five FMMT417 avalanche transistors are stacked in the pulse generating circuit 200 . Each transistor has a collector-emitter breakdown voltage of 100V.

and a collector-base breakdown voltage of 320V.

have The circuit shown in Fig. 5 was simulated using the LTSpice model. A Spice model of the FMMT417 was obtained directly from the manufacturer's website. source resistance

This is 1 MΩ, and the characteristic impedance of the transmission line

is 50 Ω, and the source voltage

This is 1.5 kV.

The circuit may include a diode (not shown) connected in parallel with each transistor to clamp the voltage to ensure that the voltage across each transistor does not exceed its collector-base breakdown voltage. By doing so, the lifetime of the transistor can be increased and it is ensured that triggering occurs by the trigger signal.

The trigger signal may be provided by any suitable source. Preferably the trigger signal is generated by a TTL source or microcontroller. In this example, the trigger signal has a duration of 600 ns and an amplitude of 5 V and a pulse period (repeat period) of 20 ms. It is desirable to have a 5V trigger signal because it is below the emitter-base breakdown voltage of the transistor.

It is arranged so that the pulse width of the trigger signal is longer than the pulse desired to be generated from the power line. In this case, a duration of 600 ns can be chosen to provide a safe margin to allow the entire transmission line to discharge.

The trigger signal repetition rate (pulse period) is limited by the time it takes an open-circuit charged transmission line to recharge to full capacity.

A transformer is placed between the trigger signal generator and the base and emitter of the first transistor in the stack (ie, the transistor furthest from the transmission line). This configuration means that the trigger pulse is floating and therefore must be the same between the base and emitter of the first transistor regardless of the voltage across the transistor onto the load. Therefore, the amplitude of the pulses at the load should increase linearly with the number of transistors in the stack. The transformer may be a 1-EMR-046 gate drive transformer with a 1:1 turns ratio and high voltage isolation.

). 양의 트리거 신호가 첫 번째 트랜지스터 Q1의 베이스에 적용될 때, Q1은 '온(on)'이 되고 자신의 콜렉터 전압을 접지 전위에 가깝게 만든다. 이로 인해 제2 트랜지스터 Q2가 콜렉터-이미터 전압의 두 배를 갖고, 따라서 과전압의 측면에서 바람직한 상태를 만듦으로써 Q2의 비-파괴적 애벌랜칭을 야기하고 자신의 콜렉터를 접지 전위에 가깝게 만든다. 이는 체인의 다음 트랜지스터에 순차적인 '노크온(knock-on)' 효과를 생성하여 첫 번째 애벌런치 트랜지스터 Q1가 충전된 개방 회로 전송 라인 근처의 최종 애벌랜치 트랜지스터 Q5로 과전압을 발생시킨다. Q5가 '온'이 될 때, 고속 상승 시간이 부하에서 생성되며(< 2ns), 따라서,

인 경우 충전된 개방 회로 송전 선이

의 폭 및

의 최대 진폭을 갖는 펄스를 생성하는 부하를 통해 방전될 수 있다. In use, the five stacked avalanche transistors are initially off-state, with each transistor having 300V across it (i.e.,

). When a positive trigger signal is applied to the base of the first transistor Q1, Q1 turns 'on' and brings its collector voltage close to ground potential. This causes the second transistor Q2 to have twice the collector-emitter voltage, thus creating a desirable state in terms of overvoltage, causing non-destructive avalanching of Q2 and bringing its collector close to ground potential. This creates a sequential 'knock-on' effect on the next transistor in the chain, causing an overvoltage to the last avalanche transistor Q5 near the open circuit transmission line where the first avalanche transistor Q1 is charged. When Q5 is 'on', a fast rise time is generated at the load (< 2ns), thus,

If a charged open circuit transmission line is

width of and

can be discharged through a load that generates a pulse with a maximum amplitude of

Accordingly, the pulse generating circuit 200 may be used to generate a monopolar ultrashort electric field pulse.

에 의해 특징지어진다. 그래프는 송전 선 길이가

의 펄스 폭을 결정하고, 즉, 5ns, 25ns, 50ns 및 100ns의 라인 딜레이를 갖는 송전 선이 각각 10ns, 50ns, 100ns 및 200ns의 펄스 폭을 생성함을 보여준다. 또한, 모든 4개의 펄스의 상승 시간이 2ns 이하인데, 이는 스위칭 요소, 즉, 5개의 애벌랜치 트랜지스터가 이 인자를 결정함을 강조한다. 6 is a graph showing voltage pulses obtained over a range of transmission line lengths. In Figure 6, the transmission line length is the line delay

characterized by The graph shows that the transmission line length is

Determine the pulse width of , i.e., show that a transmission line with line delays of 5 ns, 25 ns, 50 ns and 100 ns produces pulse widths of 10 ns, 50 ns, 100 ns, and 200 ns, respectively. Also, the rise times of all four pulses are less than 2 ns, highlighting that the switching element, i.e., the five avalanche transistors, determines this factor.

를 암시한다. 본 발명자는 펄스 생성 회로를 최적화하기 위해 트랜지스터의 임피던스를 보상하는 것이 필요함을 밝혔다. 도 5에 나타난 예시에서, 각각의 개별 트랜지스터는 ~3Ω의 임피던스를 가진다. 따라서, 총 ~15Ω가 트랜지스터 적층에 걸쳐 있다. 따라서 반사 계수는 다음과 같이 표현될 수 있다 The graph of FIG. 6 suggests that the 50Ω load does not match the transmission line characteristic impedance because secondary pulses of lower amplitude than the primary pulses appear in each signal. This is a mismatched load due to reflection, i.e.

implies The inventors have found that it is necessary to compensate the impedance of the transistor in order to optimize the pulse generating circuit. In the example shown in Figure 5, each individual transistor has an impedance of ~3Ω. Thus, a total of ~15Ω spans the transistor stack. Therefore, the reflection coefficient can be expressed as

는 회로의 총 임피던스이고

는 신호 애벌랜치 트랜지스터의 임피던스이다.here,

is the total impedance of the circuit

is the impedance of the signal avalanche transistor.

=0.13일 때 도 6에서 도시된 펄스에서 반사가 관찰되고, 반사 펄스의 진폭이 일차 펄스의 ~13%임을 설명한다(

= 50Ω,

= (3Ω×5) = 15Ω 및

= 50Ω).

의 추가 임피던스가 또한 설계의 DC 구성요소에 영향을 미치며, 이는 다음과 같이 다시 써질 수 있다:this is

A reflection is observed in the pulse shown in Fig. 6 when =0.13, demonstrating that the amplitude of the reflection pulse is ~13% of the primary pulse (Fig.

= 50Ω,

= (3Ω×5) = 15Ω and

= 50Ω).

The additional impedance of also affects the DC component of the design, which can be rewritten as:

가 35Ω로 조정되었다. 이는 도 7에 도시된 바와 같이, 부하에서 반사가 0이고 이차 펄스가 없는 단일 모노폴라 펄스를 도출했다.Taking this into account, the impedance of the load

was adjusted to 35Ω. This resulted in a single monopolar pulse with zero reflection at the load and no secondary pulses, as shown in FIG. 7 .

가 연결된다는 점에서 도 8의 회로(150)는 도 4의 회로와 상이하다. 도 9는 본 발명의 하나의 실시예인 펄스 생성 회로(250)를 도시한다. 동축 송전 선이 방전될 때 전류가 도 5와 반대 방향으로 흐르도록 부하

가 연결되는 것을 제외하고, 펄스 생성 회로(250)는 도 5에서 나타난 회로와 유사하다. 도 10은 도 9에 도시된 회로(250)를 이용해 획득된 정합된 35Ω 부하를 갖고 관측된 음의 모노폴라 펄스의 그래프를 도시한다.The circuit previously shown in Figures 4 and 5 is configured to generate a positive monopolar pulse. However, the circuit may be further configured to generate a negative monopolar pulse by changing the location to which the load is connected. 8 is a schematic diagram of a pulse generation circuit 150 using an open circuit power transmission line technique in combination with an avalanche transistor as a fast switching element similar to circuit 100 of FIG. 4 . When the coaxial transmission line is discharged, load it so that the current flows in the opposite direction as in Fig.

The circuit 150 of FIG. 8 is different from the circuit of FIG. 4 in that is connected. 9 shows a pulse generation circuit 250, which is one embodiment of the present invention. When the coaxial transmission line is discharged, load it so that the current flows in the opposite direction as in Fig.

Except that is connected, the pulse generating circuit 250 is similar to the circuit shown in FIG. 5 . FIG. 10 shows a graph of negative monopolar pulses observed with a matched 35Ω load obtained using circuit 250 shown in FIG. 9 .

Developing the concept mentioned above, the pulse generating circuit can be configured as a bipolar pulse generating circuit. The operation of this circuit may be the same as the monopolar design of FIGS. 4 and 9 .

및

로 마킹된 두 개의 개별 부하 상에서 생성되는 것을 제외하면, 도 4 및 9에 나타난 회로와 유사하다. 이들 부하 위치는 앞서 언급된 양 및 음의 펄스에 대한 위치에 대응한다.11A is a schematic diagram of a pulse generating circuit 300 that is one embodiment of the bipolar pulse generating circuit 300 . This means that the pulse is

and

Similar to the circuit shown in Figures 4 and 9, except that it is created on two separate loads marked with . These load positions correspond to the positions for the positive and negative pulses mentioned above.

양단의 전압 차이가 양의 펄스일 때 바이폴라 펄스 생성 회로(300)가 바이폴라 펄스를 생성하고, 이때

양단의 전압 차이가 음의 펄스를 생성한다. 회로(300)가 사용될 때, 이들 펄스가

및

에서 동시에 관측되고 대칭이다, 즉, 펄스 폭, 상승 시간, 진폭, 반복률이 동일하나 극성이 상이하다.

When the voltage difference between both ends is a positive pulse, the bipolar pulse generating circuit 300 generates a bipolar pulse, at this time

The voltage difference across both ends produces a negative pulse. When circuit 300 is used, these pulses

and

is observed simultaneously and is symmetric, i.e., the pulse width, rise time, amplitude, and repetition rate are the same, but the polarity is different.

, 가 송전 선의 외부 전도체와 애벌랜치 트랜지스터 Q1의 이미터 간 임피던스이고

와

의 합 임피던스이다. 따라서 반사 계수는 송전 선 이론을 이용해 다음과 같이 표현될 수 있다:When there are two loads in this circuit, the optimization equation must be modified to reduce reflections. Total load impedance for bipolar designs,

, is the impedance between the outer conductor of the transmission line and the emitter of the avalanche transistor Q1,

Wow

is the sum impedance of Therefore, the reflection coefficient can be expressed using the transmission line theory as:

이 DC 이론을 이용해 다음과 같이 표현될 수 있다:Similarly, peak-to-peak voltage across the load

Using this DC theory, it can be expressed as:

및

는 각각 양의 펄스 및 음의 펄스의 진폭이다.here,

and

are the amplitudes of the positive and negative pulses, respectively.

및

값이 0 반사(

= 0), 및

의 동시 대칭 펄스 폭 및 상승 시간 <2ns을 갖는 단일 펄스의 바이폴라 펄스를 생성할 것이다. 달리 말하면, 바이폴라 펄스 생성 회로(300)가 2T의 펄스 폭 및 0 반사를 갖고,

를 가로질러 송전 선의 외부 전도체와 애벌랜치 트랜지스터 Q1의 이미터 간 진폭

의 단일 양의 펄스를 생성하도록 동작한다.From the above, 17.5Ω of

and

A value of 0 reflection (

= 0), and

will generate a single-pulse bipolar pulse with a simultaneous symmetric pulse width and rise time <2 ns. In other words, the bipolar pulse generation circuit 300 has a pulse width of 2T and zero reflection,

Amplitude between the outer conductor of the transmission line and the emitter of the avalanche transistor Q1 across

operates to generate a single positive pulse of

에서 관측된 펄스(310),

에서 관측된 펄스(312), 및

에서 관측된 펄스(314)를 보여주는 그래프이다. 이들 관측은 앞서 제공된 이론을 검증한다. 도 12a에서, 5ns 송전 선이 동일한 상승 시간(<2ns)을 갖는 모든 3개의 부하에서 10ns 펄스를 생성한다.

= 17.5Ω일 때, 반사가 없다, 즉12a is

Pulse 310 observed in

Pulse 312 observed in , and

It is a graph showing the pulse 314 observed in . These observations validate the theory presented previously. In Figure 12a, a 5 ns transmission line generates 10 ns pulses at all three loads with the same rise time (<2 ns).

= 17.5Ω, there is no reflection, i.e.

및

의 크기가 262.5V이며, 따라서 피크간 전압

이 520V이고, 이는 균등 모노폴라 설계와 동일하다.

and

is 262.5 V, so the peak-to-peak voltage

This is 520V, which is equivalent to an equivalent monopolar design.

및

) 전에 딜레이 라인을 제공함으로써 도 11b의 회로는 도 11a와 상이하다. 하나 또는 둘 모두의 부하 전에 딜레이 라인을 배치함으로써 두 펄스 간 딜레이의 조작이 가능해진다. 딜레이된 펄스는 딜레이 시간에서 펄스 폭을 뺀 만큼 딜레이되지 않은 페어링된 펄스를 따를 것이다. 도 11b에서, 20ns 딜레이 라인은

전에 배치된다. 11B is a schematic diagram of a bipolar pulse generating circuit 350 that is another embodiment of the present invention. each load (

and

), the circuit of Fig. 11b differs from Fig. 11a by providing a delay line before. Placing the delay line before one or both loads allows manipulation of the delay between the two pulses. The delayed pulse will follow the undelayed paired pulse by the delay time minus the pulse width. In Figure 11b, the 20ns delay line is

placed before

에서 관측된 펄스(310),

에서 관측된 펄스(312), 및

에서 관측된 펄스(314)를 보여주는 도 12a와 유사한 그래프이다. 도 12b는 도 12b의 모든 세 개의 펄스로서 딜레이 라인을 도입하는 효과를 확인하며 이들 파라미터가 도 12a와 동일하다. 유일한 차이점은

를 가로지르는 음의 펄스가 10ns(즉, 20ns - 10ns)만큼 양의 펄스를 따른다는 것이다.12b is

Pulse 310 observed in

Pulse 312 observed in , and

A graph similar to FIG. 12A showing the observed pulse 314 at Fig. 12b confirms the effect of introducing a delay line as all three pulses of Fig. 12b, and these parameters are the same as Fig. 12a. the only difference is

That is, a negative pulse that crosses A is followed by a positive pulse by 10 ns (ie 20 ns - 10 ns).

Thus, the bipolar pulse generation circuit configuration referred to herein may produce:

- a symmetrical bipolar pulse, in which the positive and negative parts are generated simultaneously or sequentially (i.e. with different delays)

조건이 충족되면 반사는 0으로 유지될 것이기 때문에, 0 반사 그러나 조정 가능한 및

및

진폭.- the amplitude is controlled by the ratio of R _L+ and R _L-

0 reflection but adjustable and

and

amplitude.

In a further aspect, one or both of the delay lines may have an adjustable length allowing the introduced delay to be controlled. This allows the spacing of the positive and negative pulses to be adjusted on the fly, allowing the instrument to generate a variety of electroporation waveforms.

references

[One] W. Meiling and F. Stary, Nanosecond pulse techniques. New York: Gordon and Breach, 1970, p. 304.

[2] Q. Yang, X. Zhou, Q.-g. Wang and M. Zhao, “Comparative analysis on the fast rising edge pulse source with two kinds of avalanche transistor,” in Cross Strait Quad-Regional Radio Science and Wireless Technology Conference, Chengdu, 2013.

[3] G. Yong-sheng et al., "High-speed, high-voltage pulse generation using avalanche transistor," Review of Scientific Instruments, vol. 87, no. 5, p. 054708, 2016.

Claims (16)

A bipolar pulse generating circuit for an electrosurgical generator, the bipolar pulse generating circuit comprising:
a voltage source connectable to the load via a switching element,
A coaxial transmission line having an inner conductor separated from an outer conductor by a dielectric material, the inner conductor having a first end connected between an input of a switching element and a voltage source and a second end in an open circuit condition, whereby the coaxial transmission line is switched Charged by the voltage source when the element is in the OFF state and discharged when the switching element is in the ON state - ,
a first output connectable to the load, the first output being positioned between the output of a switching element and ground to support a positive pulse when the coaxial transmission line is discharged; and
a second output connectable to the load, the second output being located between an outer conductor of the coaxial power line and ground to support a negative pulse when the coaxial power line is discharged;
and an impedance of the coaxial power transmission line is configured to match a sum of (i) an impedance of the switching element, (ii) an impedance of the load at the first output, and (iii) an impedance of the load at the second output. 2. The bipolar pulse generation circuit of claim 1, wherein a delay line is connected to the first output or the second output, whereby the supply of positive and negative pulses at the first output and the second output sequentially occurs. 3. The circuit of claim 1 or 2, wherein the delay line has an adjustable length. 4. The circuit of claim 2 or 3, wherein the delay line is a coaxial power transmission line of different length. 5. The switching element according to any one of the preceding claims, wherein the switching element is
a plurality of series-connected avalanche transistors, and
A bipolar pulse generation circuit comprising a trigger pulse generator configured to generate a trigger pulse to activate a plurality of series-connected avalanche transistors. 6. The circuit of claim 5, wherein the trigger pulse generator comprises a TTL device. 7. The circuit of claim 5 or claim 6, wherein the trigger pulse has a voltage lower than the emitter-base breakdown voltage of each of the plurality of avalanche transistors. 8. A circuit according to any one of claims 5 to 7, wherein the trigger pulse generator is connected via a transformer to a plurality of series-connected avalanche transistors. 9. The circuit of any one of claims 5 to 8, wherein the trigger pulse is applied between the collector and emitter of a first one of the plurality of series-connected avalanche transistors. 10. The circuit of claim 9, wherein the first transistor is furthest from the coaxial transmission line. 11. A diode as claimed in any of claims 5 to 10, wherein a diode is connected in parallel with each avalanche transistor of the plurality of series connected avalanche transistors to clamp the voltage across each transistor below its collector-base breakdown voltage. which is a bipolar pulse generating circuit. 12. The circuit of any of claims 5-11, wherein each transistor in the plurality of series-connected avalanche transistors is the same. 13. The circuit of any preceding claim, wherein the coaxial power transmission line has a length selected to provide a line delay of 5 ns or less. 14. A circuit according to any one of the preceding claims, wherein the coaxial power transmission line is charged by a voltage source through a resistor. 15. A circuit according to any one of the preceding claims, wherein the load is an electrosurgical instrument. An electrosurgical generator having a bipolar pulse generating circuit according to claim 1 .

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