KR20220095833A - Display device - Google Patents

Abstract

A display device of the present invention comprises: a substrate including a display area having a deformed side, and a non-display area which includes a notch area defined by the shape of the deformed side of the display area and is placed to surround the display area; a plurality of gate lines placed on a first display area on a lower side of the notch area and a second display area on both sides of the notch area in the display area; a compensation gate line placed on the notch area and connecting the plurality of gate lines placed by being separated on the second display area on both sides of the notch area; and a compensation data line placed on the notch area to be overlapped with the compensation gate line, and extended from the data line placed on the first display area on a lower side of the notch area. The present invention is able to improve the lowered display quality due to the deformed side.

Description

display device {DISPLAY DEVICE}

The present invention relates to a display device, and more particularly, to a display device having a heterogeneous structure.

Currently, various display devices are being developed and marketed. For example, a liquid crystal display (LCD), a field emission display (FED), an electrophoretic display (EPD), an electro-wetting display (EWD) ) and display devices such as organic light emitting displays (OLEDs) and quantum dot displays (QDs).

The display device includes a display area in which a plurality of pixels are arranged to display an image, and a non-display area in which an image is not displayed, which surrounds the display area. In this case, a plurality of pixels may be defined in the display area. Also, wirings and circuits for transmitting various signals to the plurality of pixels are disposed in the non-display area.

As the technology for implementing such a display device develops and many products are mass-produced, the display device develops mainly on a technology for realizing a design desired by a consumer. One of them is the diversification of the form of a display area in which an image is implemented. Specifically, the display area is required to have a variety of shapes other than the rectangular shape.

The inventors of the present invention have found that in a display device having a heterogeneous structure, a difference occurs between the RC load of the display region including the heterogeneous structure, that is, the RC load of the display region including the abnormal side, and the RC load of the display region not including the heterogeneous side, Due to this, the problem that the display quality of the display device deteriorates was recognized.

Accordingly, the inventors of the present invention have developed a display device having a new structure to solve a problem caused by a difference in RC load that may occur in a display device having a heterogeneous structure.

Specifically, an object of the present invention is to provide a display device capable of compensating for a difference in RC load in a display area due to the formation of an irregular edge by arranging an RC load compensation pattern in a notch region formed due to an irregular edge.

Another object of the present invention is to provide a display device capable of preventing loss of a compensation data line by forming a step compensation structure in a compensation gate line.

Another object of the present invention is to provide a display device capable of maintaining the same RC load even if the alignment of a compensation gate line and a compensation data line is misaligned.

The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

A display device according to an embodiment of the present invention includes a display area having an irregular side and a non-display area including a notch area defined by a shape of the irregular side of the display area to surround the display area. a plurality of gate lines disposed in a substrate, a first display area under the notch area, and a second display area on left and right sides of the notch area of the display area; A compensation gate line connecting a plurality of separately disposed gate lines and a compensation gate line disposed to overlap the compensation gate line in the notch region and extending from a data line disposed in a first display region under the notch region It may contain data lines.

A display device according to another exemplary embodiment includes a non-display area disposed to surround the display area including a display area having an irregular side and a notch area defined by a shape of the irregular side of the display area a plurality of gate lines disposed in a first display area under the notch area and a second display area on left and right sides of the notch area of the display area; Compensation gate lines connecting a plurality of gate lines separately disposed in It may include an extended compensation data line.

Details of other embodiments are included in the detailed description and drawings.

According to the present invention, by arranging the RC load compensation pattern in the notch area to reduce the RC load difference from the display area due to the anomaly side, it is possible to improve display quality deterioration due to the anomaly side.

According to the present invention, loss of the compensation data line can be prevented by forming a step compensation structure on the compensation gate line overlapping the compensation data line, and the RC load can be maintained the same even if the alignment is misaligned. there is an advantage

The effect according to the present invention is not limited by the contents exemplified above, and more various effects are included in the present invention.

1 is a plan view of a display device according to an exemplary embodiment.
FIG. 2 is an enlarged view of area A of FIG. 1 .
FIG. 3 is an enlarged view of area B of FIG. 2 .
4 is a cross-sectional view illustrating a pixel structure of a display device according to an exemplary embodiment.
5 and 6 are plan views illustrating a compensation pattern according to an exemplary embodiment of the present invention.
7A and 7B are plan views for explaining compensation of the RC load according to the misalignment.
8 is a table showing a change in a gate load according to a position of a gate line.
9 is a graph showing the result of FIG. 8 .
10 is a table showing variations in data load according to positions of data lines.
11 is a graph showing the result of FIG. 10 .

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be embodied in various different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the art to which the present invention pertains It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative and the present invention is not limited to the illustrated matters. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. When 'include', 'having', 'consisting', etc. are used in this specification, other parts may be added unless 'only' is used. When a component is expressed in the singular, cases including the plural are included unless otherwise explicitly stated.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'next to', 'right' or One or more other parts may be placed between two parts unless 'directly' is used.

When a device or layer is referred to as "on" another device or layer, it includes cases in which another layer or other device is interposed directly on or in the middle of another device.

Although first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

Like reference numerals refer to like elements throughout.

The size and thickness of each component shown in the drawings are illustrated for convenience of description, and the present invention is not necessarily limited to the size and thickness of the illustrated component.

Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, and as those skilled in the art will fully understand, technically various interlocking and driving are possible, and each embodiment may be implemented independently of each other, It may be possible to implement together in a related relationship.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view of a display device according to an exemplary embodiment.

Referring to FIG. 1 , a display device 100 according to an exemplary embodiment includes a substrate 110 , a first gate driver 111 , a second gate driver 112 , a data driver 120 , and a gate line GL. ), a data line DL, a high potential voltage supply line VDDL, and a low potential voltage supply line (not shown).

The substrate 110 is for supporting and protecting various components of the display device 100 , and may be made of glass or a plastic material having flexibility. When the substrate 110 is made of a plastic material, for example, it may be made of polyimide (PI), but is not limited thereto.

In this case, the display area AA and the non-display area NA surrounding the display area AA may be defined in the substrate 110 .

The display area AA is an area in which an image is displayed in the display device 100 , and various driving elements and signal wires for driving the display unit and the display unit may be disposed in the display area AA. For example, the display unit may be an organic light emitting display including an organic light emitting device including an anode, an organic light emitting layer, and a cathode. However, the present invention is not limited thereto, and the display unit may be a liquid crystal display unit that drives the liquid crystal by an electric field generated by a voltage applied to the pixel electrode and the common electrode. In addition, various driving devices such as thin film transistors and capacitors for driving the display unit may be disposed in the display area AA. Also, as shown in FIG. 1 , a plurality of signal lines such as a gate line GL, a data line DL, and a high potential voltage supply line VDDL may be disposed in the display area AA.

A plurality of pixels are disposed in the display area AA. The plurality of pixels is a minimum unit emitting light and may include a red pixel, a green pixel, and a blue pixel. In addition, the plurality of pixels may further include a white pixel. Each of the plurality of pixels in the display area AA may be connected to the gate line GL, the data line DL, and the high potential voltage supply line VDDL.

Referring to FIG. 1 , the display area AA may be a heterogeneous side having a heterogeneous structure at one side among four sides constituting the display area AA. Here, the irregular side may be one of an upper and lower side having a long side among the four sides and an upper and lower side having a long side among left and right sides having a short side. However, the present invention is not limited thereto. The irregular side means a side having a curved shape rather than a straight side. In addition, in an embodiment of the present invention, a heterogeneous structure is a structure generated by a heterogeneous side, and a deformed shape and display area (AA ) refers to a form in which pixels are not arranged inside, so that when an image is displayed, an area in which no pixels are arranged can be viewed.

Referring to FIG. 1 , an upper side among the upper side, lower side, left side, and right side of the display area AA corresponds to the heterogeneous side. In an embodiment according to the present invention, the lower area of the display area not including the irregular side is referred to as a first display area AA1 , and the upper area of the display area AA including the irregular side is referred to as the second display area ( AA2).

The second display area AA2 may include a 2-1 th display area A21 and a 2-2 nd display area A22 that are separated into left and right sides due to the irregular sides disposed in the central portion. The 2-1 th display area AA21 may receive a gate signal from the first gate driver 111 . The 2-2nd display area AA22 may receive a gate signal from the second gate driver 112 . Since the irregular side of the second display area AA2 has a shape that is concavely recessed in the downward direction of the display area AA, a different structure having a concave shape corresponding to the irregular side may be defined. Since no pixel is disposed at a position where the irregular edge of the second display area AA2 is concave, an image is not displayed and may be defined as a notch area (NTA). Accordingly, the second display area AA2 may have a display area having a size different from that of the first display area AA1 . That is, for example, the display area of the second display area AA2 may be smaller than the display area of the first display area AA1 with respect to the same vertical width.

Since the notch area NTA is an area in which an image is not displayed, it may be included in the non-display area NA. Physical components 130 , for example, buttons, speakers, cameras, and switches, may be disposed in the notch area NTA in which the deformed side is concave, so that other functions of the display device 100 may be implemented. In particular, since one of the four sides of the display area AA of the gate line GL according to an exemplary embodiment is configured as a heterogeneous side having a heterogeneous structure, the first display area ( AA1) and the length of the wiring in the second display area AA2 in which the heterogeneous structure is disposed are different. That is, since the second display area AA2 is separated into the 2-1 display area AA21 and the 2-2 display area AA22 due to the notch area NTA in which no pixels are disposed, the length of the wiring is increased. It may be shorter than the first display area AA1 . Accordingly, a difference occurs in the RC load of the gate line GL disposed in the first display area AA1 and the gate line GL of the second display area AA2 . In addition, in the data line DL according to an exemplary embodiment, the length of the wiring is different from the lower portion of the notch area NTA in which the heterogeneous structure is not disposed and the left and right sides of the notch area NTA in which the heterogeneous structure is disposed. That is, the length of the wiring may be shorter than the left and right sides of the notch area NTA in the lower portion of the notch area NTA due to the notch area NTA in which no pixels are disposed. Accordingly, a difference occurs in the RC loads of the data line DL disposed under the notch area NTA and the data line DL disposed on the left and right sides of the notch area NTA.

To compensate for this, the RC load compensation pattern of the present invention may be disposed in the compensation area CA of the notch area NTA.

In FIG. 1 , as a modified example of the display area AA having a substantially rectangular shape, a shape in which a part of one side of the square is concave is illustrated, but the present invention is not limited thereto and may be implemented in various shapes. For example, a plurality of sides of the display area AA may be implemented as different sides, and various types of holes may be formed in the display area AA. The area in the hole is an area in which no image is displayed because pixels are not arranged, and thus may be included in the non-display area NA.

The non-display area NA is an area in which an image is not displayed and may be defined as an area surrounding the display area AA. Various components for driving a plurality of pixels disposed in the display area AA may be disposed in the non-display area NA. For example, as shown in FIG. 1 , the first and second gate drivers 111 and 112 may be disposed in the non-display area NA of the substrate 110 . Also, as described above, as the display area AA has a heterogeneous structure, the non-display area NA may also have a heterogeneous structure. That is, as illustrated in FIG. 1 , the non-display area NA may also have a shape that follows the heterogeneous structure of the display area AA, and this area may be referred to as a notch area NTA.

The first and second gate drivers 111 and 112 output a gate signal to the plurality of gate lines GL of the display area AA based on a gate control signal output from the timing controller, and a pixel to which a data voltage is charged. can be selected. For example, the first gate driver 111 outputs a gate signal to the plurality of gate lines GL disposed in the 2-1 th display area AA21 , and the second gate driver 112 outputs the 2-2 th display area AA21 . The gate signal may be output to the plurality of gate lines GL disposed in the display area AA22 .

Although not shown, a plurality of high potential power link wires may be disposed to surround the display area AA. The high potential power link wiring may receive the high potential voltage from the data driver 120 and transmit it to the high potential voltage supply line VDDL of the display area AA. A low potential power link wiring may be disposed to surround the display area AA. The low potential power link wiring may receive a low potential voltage from the data driver 120 and transmit it to the low potential voltage supply line. However, the present invention is not limited thereto.

The high potential voltage supply line VDDL and the low potential voltage supply line may be made of the same material. For example, the high potential voltage supply line VDDL and the low potential voltage supply line may be formed of the same material as the source electrode and the drain electrode of the thin film transistor disposed in the display area AA. However, the present invention is not limited thereto. For example, the high potential voltage supply line VDDL may be made of the same material as the source electrode and the drain electrode of the thin film transistor, and the low potential voltage supply line may be made of the same material as the gate electrode of the thin film transistor.

A plurality of data lines DL are disposed in the display area AA. The plurality of data lines DL are wirings for transferring a data voltage to each pixel of the display area AA. The plurality of data lines DL are connected to the data driver 120 through a data link line.

The data driver 120 outputs a data signal generated based on the data driving control signal transmitted from the timing controller to the data line DL of the display area AA. As shown in FIG. 1 , the data driver 120 may be included in the flexible substrate 110 and may be disposed in the form of a chip on film. Although not shown in detail in FIG. 1 , the chip-on-film form may be a form in which a data driving chip is disposed on a flexible base film. The chip-on-film data driver 120 is disposed to be electrically connected to a data driving pad disposed on the substrate 110 , and is disposed outside the substrate 110 and printed through a plurality of signal wires disposed on the base film. The circuit board may be electrically connected.

Meanwhile, in the display device 100 according to an embodiment of the present invention, the link wiring area LA, the compensation area CA, and the common electrode are in the notch area NTA on the first display area AA1 from the bottom in order. An area CEA and an antistatic circuit area ESA are disposed. Also, according to an exemplary embodiment, the link wiring area LA, the common electrode area CEA, and the antistatic circuit area ESA are sequentially arranged from the bottom in the non-display area NA on the left and right sides of the notch area NTA. characterized by being However, the present invention is not limited thereto, and any one of the link wiring area LA, the common electrode area CEA, and the antistatic circuit area ESA may be deleted or disposed in a different order.

The link wiring area LA is an area in which the data line DL and the high potential voltage supply line VDDL of the display area AA extend to the non-display area NA, and the compensation area CA is for RC load compensation. This is the area where the pattern is placed. The common electrode area CEA is an area in which a common electrode is disposed, and the antistatic circuit area ESA is an area in which an antistatic circuit is disposed.

FIG. 2 is an enlarged view of area A of FIG. 1 .

FIG. 3 is an enlarged view of area B of FIG. 2 .

4 is a cross-sectional view illustrating a pixel structure of a display device according to an exemplary embodiment.

5 and 6 are plan views illustrating a compensation pattern according to an exemplary embodiment of the present invention.

7A and 7B are plan views for explaining compensation of the RC load according to the misalignment.

First, referring to FIG. 2 , a substrate 110 according to an exemplary embodiment may include a display area AA and a non-display area NA. In particular, the display area AA may include a first display area AA1 in which a non-uniform side is not disposed and a second display area AA2 in which a variation side is disposed. The second display area AA2 may include a notch area NTA formed by including an irregular side, and a 2-1 th display area and a 2-2 th display area that are separated left and right due to the notch area NTA It may include a display area.

A plurality of pixels may be disposed in the first display area AA1 and the second display area AA2 , and an image may be displayed by the plurality of pixels. Each of the plurality of pixels, as shown in FIG. 4 , includes a thin film transistor TR, an organic light emitting diode OLED, a light blocking layer LS, a gate insulating layer GI, and first and second insulating layers ILD1 and ILD2. , a bank BNK, an encapsulation layer EN, and the like.

A buffer layer BUF may be disposed on a substrate SUB made of an insulating material such as transparent glass or plastic, and an active layer ACT made of any one of polycrystalline silicon, amorphous silicon, and an oxide semiconductor material may be disposed thereon. In this case, when the thin film transistor TR has a top gate structure, a predetermined light blocking layer LS may be disposed under the active layer ACT to block the characteristics of the thin film transistor TR from being affected by external light. have. The light blocking layer LS may be formed of a low-resistance opaque conductive material capable of blocking light. For example, aluminum-based metals such as aluminum (Al) or aluminum alloys, silver-based metals such as silver (Ag) or silver alloys, copper-based metals such as copper (Cu) or copper alloys, molybdenum (Mo) ) or a molybdenum-based metal such as a molybdenum alloy, and a low-resistance opaque conductive material such as chromium (Cr), tantalum (Ta), or titanium (Ti). A gate insulating layer GI may be disposed on the substrate SUB including the light blocking layer LS and the active layer ACT.

The gate insulating layer GI is a layer for insulating the active layer ACT and the gate electrode GE, and is composed of a single layer or multiple layers of an insulating material, for example, a silicon nitride layer (SiNx) or a silicon oxide layer (SiO ₂ ). may be, but is not limited thereto.

A gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may be disposed on the active layer ACT. The gate electrode GE may be formed of a low-resistance opaque conductive material. For example, the gate electrode GE may include an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, or copper such as copper (Cu) or a copper alloy. It may be formed of a series metal, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, and a low-resistance opaque conductive material such as chromium (Cr), tantalum (Ta), or titanium (Ti). A first insulating layer ILD1 made of an insulating material may be disposed on the gate electrode GE.

A source electrode SE and a drain electrode DE spaced apart from the source electrode SE are disposed on the first insulating layer ILD1 , and the source electrode SE and the drain electrode DE include the gate insulating layer GI and the first It may be electrically connected to the active layer ACT through a contact hole formed in the insulating layer ILD1. The source electrode SE and the drain electrode DE may include an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, copper (Cu) or a copper alloy, etc. of a copper-based metal, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, and a low-resistance opaque conductive material such as chromium (Cr), tantalum (Ta), or titanium (Ti). In this way, the thin film transistor TR including the active layer ACT, the gate electrode GE, the source electrode SE, and the drain electrode DE may be disposed on the substrate SUB.

A second insulating layer ILD2 made of an insulating material may be disposed on the source electrode SE and the drain electrode DE, and a planarization layer PAC may be disposed on the second insulating layer ILD2. The planarization layer PAC may be made of an organic insulating material, for example, may be made of an organic material capable of planarizing an upper surface, such as polyimide. A first electrode E1 and a bank BNK may be disposed on the planarization layer PAC.

The first electrode E1 may be an anode, and may be electrically connected to the drain electrode DE through a contact hole formed in the second insulating layer ILD2 and the planarization layer PAC. Although not shown, a reflective film may be further disposed under the first electrode E1 .

The bank BNK may be disposed to cover a portion of both sides of the first electrode E1 , and an organic light emitting layer EML may be disposed to define a light emitting region capable of emitting light.

An organic light emitting layer EML may be disposed on the first electrode E1 partially exposed by the bank BNK.

The organic emission layer EML may include a hole injection layer, a hole transport layer, an emission layer, an electron transport layer, and an electron injection layer.

A second electrode E2 may be disposed on the organic light emitting layer EML and the bank BNK.

The second electrode E2 may be a cathode, and the second electrode E2 may be made of a transparent conductive material. The transparent conductive material may include, for example, Tin Oxide (TO), Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Indium Zinc Tin Oxide; ITZO) and the like, but is not limited thereto. The second electrode E2 may constitute the organic light emitting diode OLED together with the first electrode E1 and the organic light emitting layer EML.

An encapsulation layer EN may be disposed on the organic light emitting device OLED to protect the organic light emitting device OLED and prevent foreign substances that may be generated outside or during the process from being input to the organic light emitting device OLED. The encapsulation layer EN may have a structure in which a plurality of inorganic layers and a plurality of organic layers are alternately disposed, but is not limited thereto.

Although an embodiment of the present invention has been described by taking a pixel including an organic light emitting diode (OLED) as an embodiment, the present invention is not limited thereto, and may include a liquid crystal element.

Referring back to FIG. 2 , a concave portion concave toward the first display area AA1 may be disposed on a different side of the second display area AA2 among the display areas AA in which the plurality of pixels are disposed. . The concave portion is a notch area NTA, and may be a non-display area NA in which pixels are not disposed.

According to the first embodiment of the present invention, the link wiring area LA, the compensation area CA, the common electrode area CEA, and the antistatic area are sequentially arranged from the bottom in the notch area NTA on the first display area AA1. A circuit area ESA is disposed. Also, according to the first embodiment of the present invention, the link wiring area LA, the common electrode area CEA, and the antistatic circuit area ESA are sequentially arranged from the bottom in the non-display area NA on the left and right sides of the notch area NTA. characterized by being However, the present invention is not limited thereto, and any one of the link wiring area LA, the common electrode area CEA, and the antistatic circuit area ESA may be deleted or disposed in a different order.

The link wiring area LA is an area in which the data line DL and the high potential voltage supply line VDDL of the display area AA extend to the non-display area NA, and the compensation area CA is for RC load compensation. This is the area where the pattern is placed. The common electrode area CEA is an area in which a common electrode is disposed, and the antistatic circuit area ESA is an area in which an antistatic circuit is disposed.

The gate lines GL disposed in the second display area AA2 have a shorter length than the gate lines GL disposed in the first display area AA1 due to the notch area NTA. Also, the data lines DL disposed under the notch area NTA have a shorter length than the data lines DL disposed on the left and right sides of the notch area NTA due to the notch area NTA. Accordingly, a difference in RC load occurs between the first display area AA1 and the second display area AA2 . However, in general, the data signal output from the data driver, that is, the data voltage, is equally applied to the first display area AA1 and the second display area AA2 . Accordingly, there is a problem in that the luminance of the first display area AA1 and the luminance of the second display area AA2 are different in a display device including a generally irregular side. For example, since the luminance of the second display area AA2 is lower than that of the first display area AA1 , it may be recognized as a spot.

That is, in the display device having the notch area NTA, the RC loads of the gate line GL and the data line DL of the second display area AA2 to the left and right of the notch area NTA are lower than the notch area NTA. There is a problem in that the RC loads of the gate line GL and the data line DL of the first display area AA1 are different from each other.

Accordingly, in the display device according to an embodiment of the present invention, the compensation area CA having the RC load compensation pattern is disposed in the notch area NTA. The compensation area CA may be disposed between the link wiring area LA and the common electrode area CEA, but is not limited thereto, and the link wiring area LA, the common electrode area CEA, and the antistatic circuit area ( ESA).

Here, referring to FIG. 3 , the RC load compensation pattern includes the compensation gate line GL-C connected to the gate line GL of the second display area AA2 and the first under the notch area NTA. It may include a data line DL-C for compensation and a high potential voltage supply line VDDL-C for compensation respectively connected to the data line DL and the high potential voltage supply line VDDL of the display area AA1. have. However, the present invention is not limited thereto, and the high potential voltage supply line VDDL-C for compensation may be omitted depending on the pixel design.

The compensation gate line GL-C electrically connects the gate line GL of the 2-1 th display area and the gate line GL of the 2-2 th display area, which are disposed to be separated due to the notch area NTA. can In this case, the compensation gate line GL-C is made of the same material as the gate line GL of the first and second display areas AA1 and AA2 and is disposed on the same layer on which the gate line GL is disposed. can However, the present invention is not limited thereto.

The gate line GL extending to the notch area NTA may be disposed along the shape of the notch area NTA. Accordingly, the gate line GL extending to the notch region NTA may be disposed in a stepped shape in the region C, which is a curved region according to the shape of the concave portion.

The data line DL-C for compensation and the high potential voltage supply line VDDL-C for compensation are the data line DL and the high potential voltage supply line of the first display area AA1 under the notch area NTA, respectively. (VDDL) can be connected. The compensation data line DL-C and the compensation high potential voltage supply line VDDL-C are made of the same material as the data line DL of the first and second display areas AA1 and AA2, and the data line It may be disposed on the same layer on which (DL) is disposed. However, the present invention is not limited thereto.

The compensation gate line GL-C may be disposed to overlap the compensation data line DL-C and the compensation high potential voltage supply line VDDL-C.

That is, the compensation gate line GL-C may form a capacitor together with the compensation data line DL-C and the compensation high potential voltage supply line VDDL-C disposed on the first insulating layer.

At this time, the compensation data line DL-C and the compensation high potential voltage supply line VDDL-C of the present invention are arranged in a zigzag shape to increase the overlapping area with the compensation gate line GL-C. characterized. That is, for example, the compensation data line DL-C and the compensation high potential voltage supply line DL-C extending from the data line DL and the high potential voltage supply line VDDL of the first display area AA1, respectively. After meeting the compensation gate line GL-C, VDDL-C is bent once and extends parallel to the arrangement direction of the compensation gate line GL-C, so that the area overlaps with the compensation gate line GL-C can increase Thereafter, it may be bent once again to extend toward the neighboring compensation gate line GL-C, and may be bent in another direction to extend in parallel with the arrangement direction of the neighboring compensation gate line GL-C. Thereafter, it may be bent once again and extended toward another neighboring gate line GL-C for compensation.

At this time, each of the compensation data line DL-C and the compensation high potential voltage supply line VDDL-C extending parallel to the arrangement direction of the neighboring compensation gate line GL-C is a previous compensation gate line. The compensation data line DL-C and the compensation high potential voltage supply line VDDL-C extended in parallel to the arrangement direction of the GL-C extend in opposite directions to have a zigzag shape as a whole. have. However, the present invention is not limited thereto.

As described above, according to the present invention, the same RC load, that is, the same resistance and capacitance, is provided between the second display area AA2 on the left and right of the notch area NTA and the first display area AA1 under the second display area AA2. It is characterized in that the RC load compensation pattern is compensated and designed in the notch area NTA. That is, the compensation gate line GL-C and the compensation data line are calculated so that the same capacitance is formed in the notch area NTA by calculating the capacitance or the overlapping area between the gate line GL and the data line DL in the unit pixel. (DL-C) can be designed.

For example, the overlapping area of the compensation gate line GL-C and the compensation data line DL-C is approximately 99.8% of the overlapping area of the gate line GL and the data line DL in a unit pixel. design, but is not limited thereto.

In addition, the compensation gate line GL-C of the present invention has a step-like step compensation structure in a portion overlapping with the compensation data line DL-C and the compensation high potential voltage supply line VDDL-C. characterized in that Accordingly, it is possible to prevent loss of the compensation data line DL-C and the compensation high potential voltage supply line VDDL-C.

That is, for example, the first insulating layer is stacked on the compensation gate line GL-C, and the compensation data line DL-C and the compensation high potential voltage supply line VDDL-C are stacked thereon. do. In this case, the compensation data line DL-C and the compensation high potential voltage supply line VDDL-C, which are later deposited, are stacked with a step difference depending on the presence or absence of the compensation gate line GL-C. That is, when the compensation data line DL-C and the compensation high potential voltage supply line VDDL-C are stacked across the compensation gate line GL-C, the compensation gate line GL-C There is a step difference due to the difference in thickness between the part with and without. If the step path is short, there is a possibility that the data line DL-C for compensation and the high potential voltage supply line VDDL-C for compensation may be disconnected during wet etching for patterning.

Referring to FIG. 5 , for example, the compensation data line DL-C is deposited on the compensation gate line GL-C' across the compensation gate line GL-C'. In this case, since there is no step compensation structure, the step difference path EA' is relatively short, and there is a possibility that the compensation data line DL-C may be disconnected during deposition.

On the other hand, referring to FIG. 6 , for example, the compensation gate line GL-C of the present invention has a step compensation structure in the form of steps on both sides overlapping the compensation data line DL-C. do it with Accordingly, since the step path EA becomes relatively long compared to the case where there is no step compensation structure, disconnection of the compensation data line DL-C' can be prevented during deposition.

The step compensation structure may include a groove (H).

The groove H may have a width of, for example, about 3 μm or more, but is not limited thereto.

The compensation data line DL-C and the compensation high potential voltage supply line VDDL-C may be disposed to pass through a portion of the groove H.

The step compensation structure may have a shape symmetrical to both sides of the compensation gate line GL-C. That is, according to the present invention, a mirror-type step difference compensation is provided on upper and lower sides of the compensation data line DL-C and the compensation gate line GL-C overlapping the compensation high potential voltage supply line VDDL-C. It is characterized by having a structure. Accordingly, even if the alignment of the compensation gate line GL-C, the compensation data line DL-C, and the compensation high potential voltage supply line VDDL-C is misaligned, the RC load may be maintained the same.

Referring to FIG. 7A , for example, even if the alignment of the compensation data line DL-C′ stacked on the compensation gate line GL-C is partially shifted in the left and right directions, the compensation data line DL -C') and the overlapping area may be compensated and maintained the same as the mirror-shaped step compensation structure is formed on upper and lower side surfaces of the compensation gate line GL-C. That is, for example, when the alignment of the compensation data line DL-C' stacked on the compensation gate line GL-C is partially shifted in the left direction, the compensation data line DL-C' The overlapping area of the upper side of the compensation gate line GL-C overlapping with the compensation gate line GL-C increases, but the overlapping area of the lower side of the compensation gate line GL-C overlapping with the compensation data line DL-C' This is reduced so that the overall overlapping area can remain the same.

Also, referring to FIG. 7B , even if the alignment of the compensation data line DL-C″ stacked on the compensation gate line GL-C is partially shifted in the vertical direction, the compensation data line DL-C As a mirror-shaped step difference compensation structure is formed on upper and lower side surfaces of the compensation gate line GL-C overlapping the '), the overlapping area may be compensated and maintained the same. That is, for example, when the alignment of the compensation data line DL-C″ stacked on the compensation gate line GL-C is shifted upward, the compensation data line DL-C″ and The overlapping area of the upper side of the overlapping compensation gate line GL-C is reduced, but the overlapping area of the lower side of the compensation gate line GL-C overlapping with the compensation data line DL-C" is decreased. increased so that the overall overlapping area can be maintained the same.

8 is a table showing a change in a gate load according to a position of a gate line.

9 is a graph showing the result of FIG. 8 .

8 and 9 illustrate, for example, a gate load for the gate line GL sequentially arranged from the upper end of the second display area AA2 to the first display area AA1 in the display device of FIG. 2 . is showing

In this case, points 1, 2, 3, 4, 5, 6, 7, and 8 are 1, 11, 21, 31, 41 sequentially arranged from the upper end of the second display area AA2 to the first display area AA1. , 51 , 61-64 , and 65 th gate lines GL. Point 8 corresponds to the 65th gate line GL disposed in the first display area AA1 which is the reference area.

The RC delay τ of the first display area AA1 may be calculated and this may be set as a reference value.

9 shows the percentage of resistance (R), capacitance (C), and RC delay (τ) with respect to a reference value according to the position of the gate line.

8 and 9, for the 1, 11, 21, 31, 41, 51, and 61-64th gate lines GL, the resistance R is 4.19, 4.16, 4.14, 4.12, 4.09, 4.07 and It can be seen that 4.05, 4.05, 4.00, and 4.00 (Ω). This corresponds to the range of 104% to 99.4% with respect to the reference value of 4.02 (Ω), and it can be seen that the required specification (94-110%) is satisfied.

For the 1, 11, 21, 31, 41, 51, and 61-64th gate lines (GL), the capacitance (C) is 278.33, 278.07, 277.80, 277.54, 277.28, 277.02, and 276.78, 276.68, 276.71, 277.12 (pF) respectively. ) can be seen. This corresponds to a range of about 100% to 97.4% with respect to the reference value of 284.00 (pF), and it can be seen that the required specifications are satisfied.

For the 1, 11, 21, 31, 41, 51, and 61-64th gate lines GL, the RC delay τ is 1.17, 1.16, 1.15, 1.14, 1.14, 1.13 and 1.12, 1.12, 1.11, 1.11 ( μs) can be seen. This corresponds to the range of about 102% to 96.7% with respect to the reference value of 1.14 (μs), and it can be seen that the required specification is satisfied.

In addition, for the 1st, 11th, 21st, 31st, 41st, 51st, and 61st-64th gate lines GL, the variation ΔVcom of the common voltage is -0.53, -0.56, -0.60, -0.63, and -0.66, respectively. , -0.70 and -0.73, -0.74, -0.75, -0.72 (mV).

10 is a table showing variations in data load according to positions of data lines.

11 is a graph showing the result of FIG. 10 .

10 and 11 show, for example, data lines DL sequentially arranged from the second display area AA2 to the left of the notch area NTA in the display device of FIG. 2 to the notch area NTA. The data load is shown. In this case, points 1, 2, 3, 4, and 5 are 4680, 4701, 4702, 4703, and 4799-th data lines sequentially arranged from the second display area AA2 to the left of the notch area NTA to the notch area NTA. It corresponds to (DL). Point 1 corresponds to the 4680th data line DL disposed in the second display area AA2 to the left of the notch area NTA, which is the reference area.

And, FIG. 11 shows percentages of resistance (R), capacitance (C), and RC delay (τ) with respect to a reference value according to the location of the data line.

10 and 11 , it can be seen that the resistors R are 5.88, 5.77, 5.77, and 5.77 (Ω) for the 4701, 4702, 4703, and 4799-th data lines DL, respectively. This corresponds to the range of 100% to 98.2% with respect to the reference value of 5.88(Ω), and it can be seen that the required specification (94-108%) is satisfied.

It can be seen that the capacitances C for the 4701, 4702, 4703, and 4799th data lines DL are 56.70, 56.75, 56.76, and 56.74 (pF), respectively. This corresponds to about 99.5% with respect to the reference value of 57.09 (pF), and it can be seen that the required specification is satisfied.

It can be seen that the RC delays τ for the 4701, 4702, 4703, and 4799th data lines DL are 0.333, 0.328, 0.328, and 0.327 (μs), respectively. This corresponds to about 98% to 97.7% of the reference value of 0.335 (μs), and it can be seen that the required specifications are satisfied.

In addition, it can be seen that the amount of change (ΔVcom) of the common voltage for the 4701, 4702, 4703, and 4799th data lines DL is 0.018, 0.016, 0.015, and 0.016 (mV), respectively.

An exemplary embodiment of the present invention can be described as follows.

A display device according to an embodiment of the present invention includes a display area having an irregular side and a non-display area including a notch area defined by a shape of the irregular side of the display area to surround the display area. a plurality of gate lines disposed in a substrate, a first display area under the notch area, and a second display area on left and right sides of the notch area of the display area; A compensation gate line connecting a plurality of separately disposed gate lines and a compensation gate line disposed to overlap the compensation gate line in the notch region and extending from a data line disposed in a first display region under the notch region It may contain data lines.

According to another feature of the present invention, the notch region includes a link wiring region, a compensation region, a common electrode region, and an antistatic circuit region, and the compensation gate line and the compensation data line are disposed in the compensation region. can

According to another feature of the present invention, the compensation region may be disposed between the link wiring region and the common electrode region.

According to another feature of the present invention, the non-display area to the left and right of the notch area may include a link wiring area, a common electrode area, and an antistatic circuit area.

According to another feature of the present invention, the compensation gate line may be made of the same material as the gate lines of the first and second display regions, and may be disposed on the same layer on which the gate lines are disposed.

According to another feature of the present invention, the gate line extending to the notch region may be disposed in a step shape along the shape of the notch region.

According to another feature of the present invention, the compensation data line may be made of the same material as the data lines of the first and second display areas, and may be disposed on the same layer on which the data lines are disposed.

According to another feature of the present invention, the compensation data lines may be arranged in a zigzag shape.

According to another feature of the present invention, the compensation data line is disposed perpendicular to the arrangement direction of the compensation gate line between the compensation gate lines, and the compensation gate line is disposed on the compensation gate line. It may be arranged parallel to the arrangement direction.

According to another feature of the present invention, the compensation gate line may be arranged in a zigzag shape.

In the display device according to another embodiment of the present invention, the compensation gate line may have a step compensation structure in the form of a step on both upper and lower sides overlapping the compensation data line.

According to another feature of the present invention, the step compensation structure may include a groove.

According to another feature of the present invention, the compensation data line may be disposed to pass through a portion of the groove.

According to another feature of the present invention, the step compensation structure may have a shape symmetrical to both sides of the compensation gate line.

According to another feature of the present invention, the compensation data lines may overlap with the step difference compensation structure arranged in a shape symmetrical to each other in the same area.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made within the scope without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100: display device
110: substrate
111: first gate driver
112: second gate driver
120: data driving unit
AA: display area
AA1: first display area
AA2: second display area
AA21: 2-1 display area
AA22: 2-2 display area
DL-C: data line for compensation
GL-C: gate line for compensation
NTA: notch area
NA: non-display area
VDDL-C: High-potential voltage supply line for compensation

Claims (15)

a substrate comprising: a substrate including a non-display area disposed to surround the display area including a display area having an irregular edge and a notch area defined by a shape of the irregular edge of the display area;
a plurality of gate lines disposed in a first display area under the notch area and a second display area on left and right sides of the notch area in the display area;
a compensation gate line disposed in the notch region and configured to connect a plurality of gate lines separately disposed in the second display region to the left and right of the notch region; and
and a compensation data line disposed in the notch area to overlap the compensation gate line and extending from a data line disposed in a first display area under the notch area. The method of claim 1,
The notch region includes a link wiring region, a compensation region, a common electrode region, and an antistatic circuit region,
The compensation gate line and the compensation data line are disposed in the compensation area. 3. The method of claim 2,
The compensation region is disposed between the link wiring region and the common electrode region. The method of claim 1,
The non-display area to the left and right of the notch area includes a link wiring area, a common electrode area, and an antistatic circuit area. The method of claim 1,
The compensation gate line is made of the same material as the gate lines of the first and second display regions, and is disposed on the same layer on which the gate line is disposed. The method of claim 1,
The gate line extending to the notch region is disposed in a step shape along a shape of the notch region. The method of claim 1,
The compensation data line is made of the same material as the data lines of the first and second display areas, and is disposed on the same layer on which the data lines are disposed. The method of claim 1,
The compensation data line is arranged in a zigzag shape. 9. The method of claim 8,
The compensation data line is
between the compensation gate lines and disposed perpendicular to the arrangement direction of the compensation gate lines,
The display device is disposed on the compensation gate line in parallel with an arrangement direction of the compensation gate line. The method of claim 1,
The compensation gate line is disposed in a zigzag shape. The method of claim 1,
The display device of claim 1, wherein the compensation gate line has a step difference compensation structure in upper and lower sides overlapping the compensation data line. 12. The method of claim 11,
The step compensation structure includes a groove. 13. The method of claim 12,
The compensation data line is disposed to pass through a portion of the groove. 12. The method of claim 11,
The step compensation structure has a shape that is symmetrical to each other with respect to both sides of the compensation gate line. 12. The method of claim 11,
and the compensation data lines overlap the step difference compensation structure arranged in a symmetrical form by the same area.

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