KR20220093599A - Display apparatus - Google Patents

Abstract

A display apparatus according to an exemplary embodiment of the present invention includes: a substrate on which a plurality of sub-pixels are defined; a plurality of light emitting elements disposed in the plurality of sub-pixels, sharing a common organic layer and a cathode, and each of which has a separate light emitting layer; a bank disposed below the cathode between each of the plurality of light emitting elements; and a low-resistance layer disposed between the bank and the cathode between the plurality of light emitting elements and having a lower resistance than the light emitting layer. Therefore, the low-resistance layer creates a path different from the path of a lateral current flowing between the adjacent different light emitting layers to suppress unintended light emission of the light emitting elements due to the leakage current and minimize degradation in display quality.

Description

display device {DISPLAY APPARATUS}

The present invention relates to a display device, and more particularly, to a display device capable of improving color mixing of light emitted from a plurality of light emitting devices.

Currently, as we enter the information age, the field of display devices that visually display electrical information signals is rapidly developing, and research to develop performance such as thinness, weight reduction, and low power consumption for various display devices is continuing.

Among these various display devices, an organic display device is a self-emission type display device, and unlike a liquid crystal display device, it does not require a separate light source, and thus can be manufactured in a lightweight and thin form. In addition, the organic display device is not only advantageous in terms of power consumption due to low voltage driving, but also has excellent color realization, response speed, viewing angle, and contrast ratio (CR), and thus is being studied as a next-generation display.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display device capable of minimizing leakage current when the display device is driven.

Another object of the present invention is to provide a display device in which emission of light due to leakage current from some light emitting devices among a plurality of light emitting devices having a common organic layer is minimized.

Another problem to be solved by the present invention is to provide a display device capable of improving image display quality in low grayscale.

The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

A display device according to an embodiment of the present invention includes a plurality of light emitting devices disposed on a substrate on which a plurality of sub-pixels are defined, a plurality of sub-pixels, sharing a common organic layer and a cathode, and each having separate light-emitting layers; and a bank disposed under the cathode between each of the light emitting devices, and a low-resistance layer disposed between the bank and the cathode between the plurality of light emitting devices, the low-resistance layer having a lower resistance than that of the light emitting layer. Accordingly, the low-resistance layer generates a path different from that of a leakage current flowing between adjacent light emitting layers, thereby suppressing unintentional light emission of the light emitting device due to leakage current, thereby minimizing display quality degradation. .

Details of other embodiments are included in the detailed description and drawings.

The present invention can improve current leakage through a common organic layer of a plurality of light emitting devices.

According to the present invention, color reproducibility can be improved by minimizing unintentional light emission from a light emitting device when driving a display device.

According to the present invention, it is possible to improve display quality by minimizing the recognition of spots or color abnormalities when displaying a low grayscale image.

The effect according to the present invention is not limited by the contents exemplified above, and more various effects are included in the present invention.

1 is a schematic configuration diagram of a display device according to an exemplary embodiment of the present invention.
2 is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment.
3 is an enlarged plan view of a display device according to an exemplary embodiment.
4 is a cross-sectional view taken along line IIIb-IIIb' of FIG. 3 .
5A is a schematic cross-sectional view of a first light emitting part of a third sub-pixel of a display device according to an exemplary embodiment.
5B is a schematic cross-sectional view illustrating a low-resistance layer of a display device according to an exemplary embodiment.
6 is an equivalent circuit diagram illustrating an effect of a display device according to an exemplary embodiment.
7A is a schematic cross-sectional view of a first light emitting part and a second light emitting part of a third sub-pixel of a display device according to another exemplary embodiment of the present invention.
7B is a schematic cross-sectional view of a low-resistance layer of a display device according to another exemplary embodiment.
8 is a schematic cross-sectional view of a low-resistance layer of a display device according to another exemplary embodiment.
9 is a cross-sectional view of a display device according to another exemplary embodiment.
10 is an enlarged plan view of a display device according to another exemplary embodiment.
11 is an enlarged plan view of a display device according to another exemplary embodiment.

Advantages and features of the present invention, and a method of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different shapes, only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention pertains It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative and the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. When 'includes', 'have', 'consists of', etc. mentioned in the present invention are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is construed as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

Reference to a device or layer “on” another device or layer includes any intervening layer or other device directly on or in the middle of the other device or layer.

Also, although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

Like reference numerals refer to like elements throughout.

The area and thickness of each component shown in the drawings are illustrated for convenience of description, and the present invention is not necessarily limited to the area and thickness of the illustrated component.

Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be independently implemented with respect to each other or implemented together in a related relationship. may be

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic configuration diagram of a display device according to an exemplary embodiment of the present invention. In FIG. 1 , only the display panel PN, the gate driver GD, the data driver DD, and the timing controller TC are illustrated among various components of the display device 100 for convenience of explanation.

Referring to FIG. 1 , the display device 100 includes a display panel PN including a plurality of sub-pixels SP, a gate driver GD and a data driver DD supplying various signals to the display panel PN. , and a timing controller TC controlling the gate driver GD and the data driver DD.

The gate driver GD supplies the plurality of scan signals to the plurality of scan lines SL according to the plurality of gate control signals GCS provided from the timing controller TC. The plurality of scan signals may include a first scan signal SCAN1 and a second scan signal SCAN2. In FIG. 1 , one gate driver GD is illustrated as being spaced apart from one side of the display panel PN, but the gate driver GD may be disposed in a GIP (Gate In Panel) method. The number and arrangement of GD) are not limited thereto.

The data driver DD converts the image data RGB input from the timing controller TC into a data signal using a reference gamma voltage according to a plurality of data control signals DCS provided from the timing controller TC. In addition, the data driver DD may supply the converted data signal to the plurality of data lines DL.

The timing controller TC aligns the image data RGB input from the outside and supplies it to the data driver DD. The timing controller TC generates a gate control signal GCS and a data control signal DCS using an externally input synchronization signal SYNC, for example, a dot clock signal, a data enable signal, and a horizontal/vertical synchronization signal. can do. In addition, the timing controller TC supplies the generated gate control signal GCS and the data control signal DCS to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD. can be controlled

The display panel PN is configured to display an image to a user and includes a plurality of sub-pixels SP. In the display panel PN, the plurality of scan lines SL and the plurality of data lines DL cross each other, and each of the plurality of sub-pixels SP is connected to the scan line SL and the data line DL. In addition, although not shown in the drawings, each of the plurality of sub-pixels SP may be connected to a high potential power wiring, a low potential power wiring, an initialization signal wiring, a light emission control signal wiring, and the like.

The plurality of sub-pixels SP is a minimum unit constituting a screen, and each of the plurality of sub-pixels SP includes a light emitting device and a pixel circuit for driving the plurality of sub-pixels. The plurality of light emitting devices may be defined differently depending on the type of the display panel PN. For example, when the display panel PN is an organic light emitting display panel, the light emitting device 120 includes an anode ANO and an organic layer. It may be an organic light emitting device including 121 and a cathode CAT. In addition, a quantum dot light-emitting diode (QLED) including a quantum dot (QD) may be further used as the light emitting device. Hereinafter, it is assumed that the light emitting device is an organic light emitting device, but the type of the light emitting device is not limited thereto.

The pixel circuit is a circuit for controlling the driving of the light emitting element. The pixel circuit may include, for example, a plurality of transistors and capacitors, but is not limited thereto.

Hereinafter, the pixel circuit of the sub-pixel SP will be described in more detail with reference to FIG. 2 .

2 is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment.

Referring to FIG. 2 , the pixel circuit of the plurality of sub-pixels SP includes first to sixth transistors T1 , T2 , T3 , T4 , T5 , and T6 and a capacitor Cst.

The first transistor T1 may be connected to the second scan line and be controlled by the second scan signal SCAN2 supplied through the second scan line. In addition, the first transistor T1 may be electrically connected between the data line supplying the data signal Vdata and the capacitor Cst. When the second scan signal SCAN2 of the turn-on level is applied through the second scan line, the first transistor T1 transfers the data signal Vdata from the data line to the capacitor Cst. The first transistor T1 may be referred to as a switching transistor that controls the timing at which the data signal Vdata is applied to the capacitor Cst.

The second transistor T2 may be electrically connected between the high potential power line to which the high potential power signal EVDD is supplied and the fifth transistor T5 . In addition, the gate electrode of the second transistor T2 may be electrically connected to the capacitor Cst. The second transistor T2 may be referred to as a driving transistor that controls the luminance of the light emitting device 120 by controlling a current flowing to the light emitting device 120 according to a voltage applied to the gate electrode.

The third transistor T3 may be controlled by the first scan signal SCAN1 supplied through the first scan line. In addition, the third transistor T3 may be electrically connected between the gate electrode and the drain electrode of the second transistor T2 or between the gate electrode and the source electrode according to the type of the third transistor T3 .

Meanwhile, the second transistor T2 serving as the driving transistor should control the current flowing to the light emitting device 120 according to the data signal Vdata applied to the sub-pixel SP, but the second transistor T2 disposed in each sub-pixel SP A luminance deviation of the light emitting device 120 disposed in each of the sub-pixels SP may occur due to a threshold voltage deviation of the transistor T2 .

In this case, the threshold voltage of the second transistor T2 may be compensated by disposing the third transistor T3 , and the third transistor T3 may be referred to as a compensation transistor. For example, when the first scan signal SCAN1 for turning on the third transistor T3 is applied, the voltage obtained by subtracting the threshold voltage of the second transistor T2 from the high potential power signal EVDD is the first 2 is applied to the gate electrode of the transistor T2. Then, the data signal Vdata is applied to the capacitor Cst while the high potential power signal EVDD with the reduced threshold voltage is applied to the gate electrode of the second transistor T2. The threshold voltage can be compensated.

Meanwhile, although the third transistor T3 is illustrated as receiving different scan signals SCAN1 and SCAN2 from scan lines different from the first transistor T1, the third transistor T3 and the first transistor T1 are It may be connected to the same scan line to receive the same scan signals SCAN1 and SCAN2, but is not limited thereto.

The fourth transistor T4 may be electrically connected to the initialization signal line to which the capacitor Cst and the initialization signal Vini are supplied. In addition, the fourth transistor T4 may be controlled by the emission control signal EM supplied through the emission control signal line. The fourth transistor T4 initializes the voltage of the capacitor Cst when the light emission control signal EM of the turn-on level is applied through the light emission control signal line or the data signal Vdata applied to the capacitor Cst. By gradually discharging, a current according to the data signal Vdata may flow through the light emitting device 120 .

The fifth transistor T5 is electrically connected between the second transistor T2 and the light emitting device 120 and may be controlled by the light emission control signal EM supplied through the light emission control signal line. The fifth transistor T5 is turned in a state in which the data signal Vdata is applied to the capacitor Cst and the high potential power signal EVDD in which the threshold voltage is compensated is applied to the gate electrode of the second transistor T2. When the light emission control signal EM of the -on level is applied, it is turned on to allow a current to flow through the light emitting device 120 .

The sixth transistor T6 is electrically connected between the initialization signal line to which the initialization signal Vini is supplied and the anode ANO of the light emitting device, and is electrically connected to the first scan signal SCAN1 supplied through the first scan line. can be controlled. When the first scan signal SCAN1 of the turn-on level is applied through the first scan line, the sixth transistor T6 is the anode ANO of the light emitting device or the second transistor T2 as an initialization signal Vini. A node between the fifth transistors T5 may be initialized.

The capacitor Cst may be a storage capacitor Cst that stores a voltage applied to the gate electrode of the second transistor T2 serving as a driving transistor. Here, the capacitor Cst is electrically connected between the gate electrode of the second transistor T2 and the anode ANO of the light emitting device 120 . Accordingly, the capacitor Cst may store a difference between the voltage of the gate electrode of the second transistor T2 and the voltage supplied to the anode ANO of the light emitting device 120 .

In this specification, it has been described that the pixel circuit of the plurality of sub-pixels SP includes the first to sixth transistors T1, T2, T3, T4, T5, and T6 and the capacitor Cst. The number of capacitors may be changed.

Hereinafter, the sub-pixel SP of the display device 100 according to an exemplary embodiment will be described in more detail with reference to FIGS. 3 and 4 .

3 is an enlarged plan view of a display device according to an exemplary embodiment. 4 is a cross-sectional view taken along line IIIb-IIIb' of FIG. 3 .

3 and 4 , the display device 100 according to an embodiment of the present invention includes a substrate 110 , a buffer layer 111 , a gate insulating layer 112 , an interlayer insulating layer 113 , and a passivation layer ( 114), the planarization layer 115, the bank 116, the high potential power supply wiring PL, the plurality of scan wirings SL, the data wiring DL, the initialization signal wiring IL, the light emission control signal wiring EL. , a fifth transistor T5 , a light emitting device, a spacer 130 , and a plurality of first low-resistance layers LRL1 . In FIG. 3 , only the anode (ANO) of the light emitting device 120 is illustrated for convenience of explanation. In FIG. 4 , only the fifth transistor T5 among the plurality of transistors T1 , T2 , T3 , T4 , T5 , and T6 and the capacitor Cst of the pixel circuit is illustrated for convenience of description.

Referring to FIG. 3 , the plurality of sub-pixels SP is an individual unit emitting light, and a light emitting device is disposed in each of the plurality of sub-pixels SP. The plurality of sub-pixels SP includes a first sub-pixel SP1 , a second sub-pixel SP2 , and a third sub-pixel SP3 that emit light of different colors. For example, the first sub-pixel SP1 may be a blue sub-pixel, the second sub-pixel SP2 may be a green sub-pixel, and the third sub-pixel SP3 may be a red sub-pixel.

The plurality of first sub-pixels SP1 may be arranged in a plurality of columns. That is, the plurality of first sub-pixels SP1 may be arranged in the same column. In addition, the plurality of second sub-pixels SP2 and the plurality of third sub-pixels SP3 may be disposed between each of the plurality of columns in which the plurality of first sub-pixels SP1 are disposed. For example, the plurality of first sub-pixels SP1 may be disposed in one column, and the second sub-pixel SP2 and the third sub-pixel SP3 may be disposed together in an adjacent column. In addition, the plurality of second sub-pixels SP2 and the plurality of third sub-pixels SP3 may be alternately disposed in the same column. However, in the present specification, the plurality of sub-pixels SP has been described as including the first sub-pixel SP1 , the second sub-pixel SP2 , and the third sub-pixel SP3 , but the plurality of sub-pixels SP The arrangement, number, and color combination of the elements may be variously changed depending on the design, but is not limited thereto.

A high potential power wiring PL extending in a column direction is disposed between the plurality of sub-pixels SP. The plurality of high potential power lines PL are lines that transmit the high potential power signal EVDD to each of the plurality of sub-pixels SP. Each of the plurality of high potential power lines PL may be disposed between the first sub-pixel SP1 and the second sub-pixel SP2 and between the first sub-pixel SP1 and the third sub-pixel SP3 .

A plurality of data lines DL extending in the same column direction as the plurality of high potential power lines PL are disposed. The plurality of data lines DL are lines that transmit the data signal Vdata to each of the plurality of sub-pixels SP. Each of the plurality of data lines DL may be disposed between the second sub-pixel SP2 and the high-potential power line PL and between the third sub-pixel SP3 and the high-potential power line PL. However, the plurality of data lines DL may be disposed between the plurality of high potential power lines PL and the first sub-pixel SP1, but is not limited thereto.

A plurality of scan lines SL extending in the row direction are disposed. The plurality of scan lines SL are lines that transmit scan signals SCAN1 and SCAN2 to each of the plurality of sub-pixels SP. The plurality of scan lines SL include a first scan line SL1 and a second scan line SL2 . The first scan line SL1 is disposed to extend in the row direction between the second sub-pixel SP2 and the third sub-pixel SP3 , and the second scan line SL2 crosses the third sub-pixel SP3 . It may be arranged to extend in the row direction.

A plurality of initialization signal lines IL extending in the row direction in the same manner as the plurality of scan lines SL are disposed between the plurality of sub-pixels SP. The plurality of initialization signal lines IL are wirings that transmit the initialization signal Vini to each of the plurality of sub-pixels SP. Each of the plurality of initialization signal lines IL may be disposed between the second sub-pixel SP2 and the third sub-pixel SP3 . The plurality of initialization signal lines IL may be disposed between the first scan line SL1 and the second scan line SL2 .

A plurality of light emission control signal lines EL extending in the row direction in the same manner as the plurality of scan lines SL are disposed. The plurality of light emission control signal lines EL are lines that transmit the light emission control signal EM to each of the plurality of sub-pixels SP. The plurality of light emission control signal lines EL may be disposed adjacent to the plurality of second scan lines SL2 . The plurality of light emission control signal lines EL may be disposed to cross the third sub-pixel SP3 and extend in a row direction. A second scan line SL2 may be disposed between the plurality of light emission control signal lines EL and the plurality of initialization signal lines IL.

Meanwhile, the plurality of wirings may be classified into a DC wiring transmitting a DC signal and an AC wiring transmitting an AC signal. Among the plurality of wirings, the high potential power supply line PL and the initialization signal line IL transmitting the high potential power signal EVDD or the initialization signal Vini, which are DC signals, may be included in the DC wiring. Also, among the plurality of wires, the scan wires SL and DL that transmit the scan signals SCAN1 and SCAN2 and the data signal Vdata that are AC signals may be included in the AC wire.

A plurality of spacers 130 are disposed between the plurality of sub-pixels SP. When the light emitting device 120 is formed in the plurality of sub-pixels SP, a fine metal mask (FMM), which is a deposition mask, may be used. In this case, a plurality of spacers 130 may be disposed to prevent damage that may be caused by contact with the deposition mask and to maintain a constant distance between the deposition mask and the substrate 110 .

A plurality of first low-resistance layers LRL1 may be disposed between the plurality of sub-pixels SP. For example, the first low-resistance layer LRL1 may be disposed between the first sub-pixel SP1 and the third sub-pixel SP3 . Also, the first low-resistance layer LRL1 may be additionally disposed between the first sub-pixel SP1 and the second sub-pixel SP2 . This is to minimize low grayscale emission of the second sub-pixel SP2 or the third sub-pixel SP3 due to a leakage current generated from the first sub-pixel SP1 having the largest turn-on voltage.

The plurality of first low-resistance layers LRL1 may have a lower resistance than that of the first emission layer EML1 disposed in the third sub-pixel SP3 . This is because the first low-resistance layer LRL1 has a bandgap energy smaller than the bandgap energy of the first light emitting layer EML1 disposed on the third sub-pixel SP3, so that the leakage current from the first sub-pixel SP1 is reduced. This is because it is easier to flow to the cathode CAT through the first low-resistance layer LRL1 than to flow to the second sub-pixel SP2 or the third sub-pixel SP3 . A detailed description of the first low-resistance layer LRL1 will be described later.

Referring to FIG. 4 , a substrate 110 is a support member for supporting other components of the display device 100 , and may be made of an insulating material. For example, the substrate 110 may be made of glass or resin. In addition, the substrate 110 may include a polymer or plastic such as polyimide (PI), or may be made of a material having flexibility.

A buffer layer 111 is disposed on the substrate 110 . The buffer layer 111 may reduce penetration of moisture or impurities through the substrate 110 . The buffer layer 111 may be formed of, for example, a single layer or a multilayer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. However, the buffer layer 111 may be omitted depending on the type of the substrate 110 or the type of the transistor, but is not limited thereto.

A fifth transistor T5 is disposed on the buffer layer 111 . The fifth transistor T5 includes an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

The active layer ACT may be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto. For example, when the active layer ACT is formed of an oxide semiconductor, the active layer ACT includes a channel region, a source region, and a drain region, and the source region and the drain region may be a conductive region, but is limited thereto. doesn't happen

A gate insulating layer 112 is disposed on the active layer ACT. The gate insulating layer 112 is an insulating layer for insulating the active layer ACT and the gate electrode GE, and may be composed of a single layer or a multilayer of silicon oxide (SiOx) or silicon nitride (SiNx), but is limited thereto. doesn't happen

A gate electrode GE is disposed on the gate insulating layer 112 . The gate electrode GE may be formed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present invention is not limited thereto.

An interlayer insulating layer 113 is disposed on the gate electrode GE. A contact hole for connecting the source electrode SE and the drain electrode DE to the active layer ACT is formed in the interlayer insulating layer 113 . The interlayer insulating layer 113 may be formed of a single layer or a multilayer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

A source electrode SE and a drain electrode DE are disposed on the interlayer insulating layer 113 . The source electrode SE and the drain electrode DE disposed to be spaced apart from each other may be electrically connected to the active layer ACT. The source electrode SE and the drain electrode DE may be formed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or the like. It may be composed of an alloy for, but is not limited thereto.

A high potential power line PL and a data line DL are disposed on the interlayer insulating layer 113 . The high potential power line PL and the data line DL are disposed on the same layer as the source electrode SE and the drain electrode DE and may be made of the same conductive material, but are not limited thereto. For example, the high potential power line PL and the data line DL may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), It may be composed of chromium (Cr) or an alloy thereof, but is not limited thereto.

A passivation layer 114 is disposed on the high potential power line PL, the data line DL, the source electrode SE, and the drain electrode DE. The passivation layer 114 is an insulating layer for protecting the structure under the passivation layer 114 . For example, the passivation layer 114 may be formed of a single layer or a multilayer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. Also, the passivation layer 114 may be omitted according to embodiments.

A planarization layer 115 is disposed on the passivation layer 114 . The planarization layer 115 is an insulating layer that planarizes an upper portion of the substrate 110 . The planarization layer 115 may be made of an organic material, for example, may be formed of a single layer or a multilayer of polyimide or photo acryl, but is not limited thereto.

A plurality of light emitting devices 120 are disposed in each of the plurality of sub-pixels SP on the planarization layer 115 . The light emitting device 120 includes an anode ANO, an organic layer 121 and a cathode CAT.

An anode ANO is disposed on the planarization layer 115 . The anode ANO may be electrically connected to a transistor of the pixel circuit, for example, the second transistor T2 and the fifth transistor T5 to receive a driving current. Since the anode ANO supplies holes to the organic layer 121 , it may be made of a conductive material having a high work function. The anode ANO may be formed of, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

Meanwhile, the display device 100 may be implemented in a top emission method or a bottom emission method. In the case of the top emission method, a metal material having excellent reflection efficiency is provided under the anode ANO so that light emitted from the organic layer 121 is reflected by the anode ANO and is directed upward, that is, toward the cathode CAT side. , for example, a reflective layer made of a material such as aluminum (Al) or silver (Ag) may be added. Conversely, when the display device 100 is a bottom emission type, the anode ANO may be formed of only a transparent conductive material. Hereinafter, it is assumed that the display device 100 according to an embodiment of the present invention is a top emission type.

A bank 116 is disposed on the anode ANO and the planarization layer 115 . The bank 116 is an insulating layer disposed between the plurality of sub-pixels SP to separate the plurality of sub-pixels SP. The bank 116 includes an opening exposing a portion of the anode ANO. The bank 116 may be formed of an organic insulating material disposed to cover an edge or an edge portion of the anode ANO. The bank 116 may be made of, for example, polyimide, acryl, or benzocyclobutene (BCB)-based resin, but is not limited thereto.

A spacer 130 is disposed on the bank 116 . The spacer 130 is disposed on the bank 116 to maintain a predetermined distance from the deposition mask when the light emitting device 120 is formed. Due to the spacer 130 , the deposition mask, the bank 116 and the anode ANO under the spacer 130 may maintain a predetermined distance from the deposition mask, and damage due to contact may be prevented. In this case, the plurality of spacers 130 may be formed in a shape that becomes narrower toward an upper portion, for example, a tapered shape, so as to minimize an area in contact with the deposition mask.

An organic layer 121 is disposed on the anode ANO, the bank 116 , and the spacer 130 . The organic layer 121 includes a first emission layer EML1 and common organic layers HIL, HTL1, and ETL1. The first light emitting layer EML1 is an organic layer for emitting light of a specific color, and is a first light emitting layer EML1 different from each other in the first sub-pixel SP1 , the second sub-pixel SP2 , and the third sub-pixel SP3 . ) may be disposed, or the same first emission layer EML1 may be disposed on all of the plurality of sub-pixels SP. For example, when different first emission layers EML1 are disposed in each of the plurality of sub-pixels SP, the first emission layer EML1 disposed in the first sub-pixel SP1 is a blue emission layer, and the second sub-pixel SP1 is a blue emission layer. The first emission layer EML1 disposed in the pixel SP2 may be a green emission layer, and the first emission layer EM1 disposed in the third sub-pixel SP3 may be a red emission layer. In addition, the first emission layer EML1 of the plurality of sub-pixels SP may be connected to each other to form a single layer over the plurality of sub-pixels SP, for example, the entirety of the plurality of sub-pixels SP. A first light emitting layer EML1 is disposed on the emitting layer, and light from the first light emitting layer EML1 may be converted into light of various colors through a separate light conversion layer, a color filter, and the like.

The common organic layers HIL, HTL1, and ETL1 are layers disposed to improve light emission efficiency of the first light emitting layer EML1. The common organic layers HIL, HTL1, and ETL1 are formed as a single layer over the plurality of sub-pixels SP, so that the plurality of light emitting devices 120 may share each other. That is, the common organic layers HIL, HTL1, and ETL1 of each of the plurality of sub-pixels SP may be connected to each other and formed integrally. The common organic layers HIL, HTL1, and ETL1 may include, but are not limited to, a first hole injection layer HIL, a first hole transport layer HTL1, a first electron transport layer ETL1, and the like.

A cathode CAT is disposed on the organic layer 121 . Since the cathode CAT supplies electrons to the organic layer 121 , it may be formed of a conductive material having a low work function. The cathode CAT may be formed as one layer across the plurality of sub-pixels SP. That is, the cathodes CAT of each of the plurality of sub-pixels SP may be integrally formed in a shared manner by being connected to each other. The cathode (CAT) is formed of, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a metal alloy such as MgAg or a ytterbium (Yb) alloy. and may further include a metal doped layer, but is not limited thereto. Meanwhile, although not shown in the drawings, the cathode CAT may be electrically connected to the low potential power wiring to receive the low potential power signal EVSS.

A plurality of first low-resistance layers LRL1 are disposed in the bank 116 . The plurality of first low-resistance layers LRL1 may be disposed on the bank 116 to be spaced apart from the first emission layer EML1 of the organic layer 121 by a predetermined interval. That is, referring to FIG. 4 , an end of the first emission layer EML1 may be disposed on the bank, and the first low-resistance layer LRL1 is disposed between the sub-pixels SP adjacent to each other. ) may be disposed to be spaced apart from the first emission layer EML1. Accordingly, both the first emission layer EML1 and the first low-resistance layer LRL1 may be formed on the same plane, that is, on the first hole transport layer HTL1 .

Hereinafter, for a more detailed description of the first low-resistance layer LRL1, FIGS. 5A and 5B are referred to together.

5A is a schematic cross-sectional view of a first light emitting part of a third sub-pixel of a display device according to an exemplary embodiment. 5B is a schematic cross-sectional view illustrating a first low-resistance layer LRL1 of a display device according to an exemplary embodiment. In FIG. 5B , only the layers between the bank 116 and the cathode CAT disposed between the sub-pixels SP adjacent to each other are illustrated for convenience of illustration.

Referring to FIG. 5A , the first light emitting part E1 includes common organic layers HIL, HTL1, and ETL1 and a first light emitting layer EML1 having a dopant-host structure. Specifically, the first light emitting part E1 may have a structure in which a first hole injection layer HIL, a first hole transport layer HTL1, a first emission layer EML1, and a first electron transport layer ETL1 are stacked in this order. have. However, the present invention is not limited thereto, and other organic layers may be further included or omitted according to the structure or design of the light emitting device 120 . Here, the first light emitting layer EML1 uses energy transfer from a high excitation energy host to a low excitation energy dopant, and various colors of light may be emitted according to the dopant type.

Referring to FIG. 5B , the common organic layers HIL, HTL1, ETL1 and the first hole transport layer HTL1 and the first electron transport layer between the bank 116 and the cathode CAT between the sub-pixels SP adjacent to each other A first low-resistance layer LRL1 is disposed between ETL1).

The first low-resistance layer LRL1 is made of a material having a lower resistance than the host included in the first emission layer EML1 . That is, the first low-resistance layer LRL1 may have a bandgap energy smaller than the bandgap energy of the first emission layer EML1 of the third sub-pixel SP3 . For example, the bandgap energy of the first emission layer EML1 of the third sub-pixel SP3 may be about 2.89 eV, and the bandgap energy of the first low-resistance layer LRL1 may be about 2.61 eV. It is not limited. In this case, the first low-resistance layer LRL1 is a material having a lower bandgap energy than a generally used red light emitting layer, and may be CBP, TCTA, TAZ, TPBi, Balq, Bebp2, etc., but is not limited thereto.

Hereinafter, in order to explain the effect and principle of the display device according to an embodiment of the present invention, reference is also made to FIG. 6 .

6 is an equivalent circuit diagram illustrating an effect of a display device according to an exemplary embodiment. In FIG. 6 , the fifth transistor T5 of the first sub-pixel SP1 and the third sub-pixel SP3 adjacent to each other, the equivalent resistances R _120-1 and R _120-3 of the light emitting device, and the first sub-pixel Using the equivalent resistance R _L of the common organic layer HIL, HTL1, and ETL1 between SP1 and the third sub-pixel SP3 and the equivalent resistance R _LRL1 of the first low-resistance layer LRL1 An equivalent circuit diagram is shown. 6 illustrates a case in which the fifth transistor T5 of the first sub-pixel SP1 is turned on while the fifth transistor T5 of the third sub-pixel SP3 is turned off. .

Referring to FIG. 6 , ideally, since the fifth transistor T5 of the third sub-pixel SP3 having a low turn-on voltage is turned off, the equivalent resistance of the light emitting device of the third sub-pixel SP3 includes a current should not flow. However, leakage current from the first sub-pixel SP1 to the third sub-pixel SP3 through the common organic layers HIL, HTL1, and ETL1 positioned between the first sub-pixel SP1 and the third sub-pixel SP3 can flow However, in the display device 100 according to the exemplary embodiment of the present invention, the resistance R LRL1 of the first low-resistance layer _LRL1 is the resistance R _120-3 of the light emitting device of the third sub-pixel SP3 . smaller than Accordingly, flowing from the first sub-pixel SP1 to the third sub-pixel SP3 through the common organic layers HIL, HTL1 , and ETL1 positioned between the first sub-pixel SP1 and the third sub-pixel SP3 The leakage current may flow to the cathode CAT through the first low-resistance layer LRL1 having a relatively low resistance. Accordingly, in the display device 100 according to the exemplary embodiment of the present invention, the leakage current may be reduced by the first low-resistance layer LRL1 disposed between the adjacent light emitting devices 120 .

The common organic layers HIL, HTL1, and ETL1 of the plurality of light emitting devices 120 are formed as a single layer over the plurality of sub-pixels SP. In this case, since the light emitting devices of the plurality of sub pixels SP are formed in a structure that shares the common organic layers HIL, HTL1, and ETL1, when the light emitting device 120 of a specific sub pixel SP emits light, neighboring sub pixels A phenomenon in which current flows through the light emitting device 120 of the pixel SP, that is, a current leakage phenomenon may occur. The current leakage phenomenon may cause the light emitting device 120 of another sub-pixel SP to emit light, which may cause color mixing between the plurality of sub-pixels SP and increase power consumption. In addition, color abnormality and unevenness may be visually recognized due to leakage current, and thus display quality may be deteriorated. For example, when only the first sub-pixel SP1 among the plurality of sub-pixels SP emits light, a portion of the current supplied to drive the light-emitting device 120 of the first sub-pixel SP1 is transferred to the common organic layer ( It may leak to the adjacent second sub-pixel SP2 and the third sub-pixel SP3 through HIL, HTL1, and ETL1.

In addition, the first emission layer EML1 arranged separately for each of the plurality of sub-pixels SP has turn-on voltages different from each other. For example, the turn-on voltage for driving the first sub-pixel SP1 on which the blue emission layer is disposed is the largest, and the turn-on voltage for driving the third sub-pixel SP3 on which the red emission layer is disposed is the highest. can be small In addition, since the barrier through which current can flow is lower in the second sub-pixel SP2 or the third sub-pixel SP3 having a smaller turn-on voltage than the first sub-pixel SP1 having the largest turn-on voltage, the common organic layer The current leaked through (HIL, HTL1, ETL1) is easily transferred from the first sub-pixel SP1 having a large turn-on voltage to the second sub-pixel SP2 and the third sub-pixel SP3 having a low turn-on voltage. flow, and when the first sub-pixel SP1 is driven, the second sub-pixel SP2 and the third sub-pixel SP3 having a small turn-on voltage may emit light together.

In particular, during low grayscale driving, the luminance of light emitted from the driven sub-pixel SP is low, so that the light emitted from the neighboring sub-pixel SP can be more easily recognized. That is, when the low gray level is driven, color abnormalities and unevenness due to leakage current may be more easily recognized, and thus display quality may be seriously deteriorated. In addition, when displaying low grayscale white light, the first sub-pixel SP1 having the lowest turn-on voltage through the common organic layers HIL, HTL1, and ETL1 emits light first, so that the light is not pure white. A redish phenomenon in which white with red light is displayed may occur.

Accordingly, in the display device 100 according to an embodiment of the present invention, between the first sub-pixel SP1 and the third sub-pixel SP3 and between the first sub-pixel SP1 and the second sub-pixel SP2 Leakage current through the common organic layers HIL, HTL1, and ETL1 of the light emitting device 120 may be minimized by disposing the first low-resistance layer LRL1 spaced apart from the first light emitting layer EML1 by a predetermined interval. In detail, the resistance of the first low-resistance layer LRL1 may be less than the resistance of the first emission layer EML1 of the third sub-pixel SP3 having the smallest turn-on voltage. That is, the first low-resistance layer LRL1 has a bandgap energy smaller than the bandgap energy of the first light emitting layer EML1 disposed on the third sub-pixel SP3, so that the leakage current from the first sub-pixel SP1 It may be easier to flow to the cathode CAT through the first low-resistance layer LRL1 than to flow into the second sub-pixel SP2 or the third sub-pixel SP3 . Accordingly, leakage current from the first sub-pixel SP1 may be blocked by the first low-resistance layer LRL1 from flowing to the second sub-pixel SP2 or the third sub-pixel SP3 . Accordingly, in the display device 100 according to the exemplary embodiment of the present invention, a plurality of first low-resistance layers ( LRL1), the leakage current from the first sub-pixel SP1 having the largest turn-on voltage flowing to the second sub-pixel SP2 and the third sub-pixel SP3 is reduced, It is possible to minimize deterioration of display quality due to color abnormality or the like.

7A is a cross-sectional view between a cathode and an anode of a third sub-pixel of a display device according to another exemplary embodiment of the present invention. 7B is a cross-sectional view between a cathode and a bank in a region in which a low-resistance layer is disposed between adjacent sub-pixels of a display device according to another exemplary embodiment of the present invention. 7B illustrates only the layers between the bank 116 and the cathode CAT disposed between the sub-pixels SP adjacent to each other for convenience of illustration. The display device of FIGS. 7A and 7B is different from the display device 100 of FIGS. 1 to 6 only in the organic layer 221 and the low-resistance layer LRL, and other configurations are substantially the same. is omitted.

Referring to FIG. 7A , in the display device according to another exemplary embodiment, the organic layer 221 includes a first emission layer EML1, a second emission layer EML2, and common organic layers HIL, HTL1, ETL1, CGL, HTL2, ETL2. ) is included. The first emission layer EML1 and the second emission layer EML2 are organic layers 221 for emitting light of a specific color, and include the first sub-pixel SP1 , the second sub-pixel SP2 , and the third sub-pixel SP3 . ), different first light emitting layers EML1 and second light emitting layers EML2 may be disposed respectively. For example, the first emission layer EML1 and the second emission layer EML2 disposed in the first sub-pixel SP1 are blue emission layers, and the first emission layer EML1 and the second emission layer EML1 disposed in the second sub-pixel SP2 are The second emission layer EML2 may be a green emission layer, and the first emission layer EML1 and the second emission layer EML2 disposed in the third sub-pixel SP3 may be a red emission layer.

The common organic layers HIL, HTL1, ETL1, CGL, HTL2, and ETL2 are layers disposed to improve the luminous efficiency of the first light emitting layer EML1 and the second light emitting layer EML2. The common organic layers HIL, HTL1, ETL1, CGL, HTL2, and ETL2 may be formed as one layer over the plurality of sub-pixels SP, and may be shared by the plurality of light emitting devices 120 . That is, the common organic layers HIL, HTL1, ETL1, CGL, HTL2, and ETL2 of each of the plurality of sub-pixels SP may be connected to each other and formed integrally. The common organic layers HIL, HTL1, ETL1, CGL, HTL2, and ETL2 include a first hole injection layer HIL, a first hole transport layer HTL1, a first electron transport layer ETL1, a charge generation layer CGL, and a second It may include a hole transport layer (HTL2) and a second electron injection layer (ETL2), but is not limited thereto.

The charge generation layer (CGL) may be disposed between the plurality of emission layers EML1 and EML2 to smoothly supply electrons or holes to each of the plurality of emission layers EML1 and EML2 . For example, the charge generation layer CGL may be disposed between two blue light emitting layers, between two green light emitting layers, and between two red light emitting layers, but is not limited thereto.

Referring to FIG. 7A , the first light emitting part E1 and the second light emitting part E2 may be divided by the charge generating layer CGL as a boundary. The first light emitting part E1 includes the common organic layers HIL, HTL1, and ETL1 and the first light emitting layer EML1 having a dopant-host structure, and the second light emitting part E2 includes the common organic layers HTL2 and ETL2 and a dopant. - Consists of a second light emitting layer EML2 having a host structure. Specifically, the first light emitting part E1 may have a structure in which a first hole injection layer HIL, a first hole transport layer HTL1, a first emission layer EML1, and a first electron transport layer ETL1 are stacked in this order. have. In addition, the second light emitting part E2 may have a structure in which a second hole transport layer HTL2 , a second emission layer EML2 , and a second electron transport layer ETL2 are stacked. However, the present invention is not limited thereto, and other organic layers may be further included or omitted according to the structure or design of the light emitting device 120 .

Referring to FIG. 7B , common organic layers HIL, HTL1, ETL1, CGL, HTL2, ETL2, and a first hole transport layer HTL1 between the bank 116 and the cathode CAT between the sub-pixels SP adjacent to each other. A first low-resistance layer LRL1 between the and the first electron transport layer ETL1 and a second low-resistance layer LRL2 between the second hole transport layer HTL2 and the second electron transport layer ETL2 are disposed.

The first low-resistance layer LRL1 is made of a material having a lower resistance than the host included in the first emission layer EML1 . That is, the first low-resistance layer LRL1 may have a bandgap energy smaller than the bandgap energy of the first emission layer EML1 of the third sub-pixel SP3 . In addition, the second low-resistance layer LRL2 is made of a material having a lower resistance than the host included in the second emission layer EML2 . That is, the second low-resistance layer LRL2 may have a bandgap energy smaller than the bandgap energy of the second emission layer EML2 of the third sub-pixel SP3 .

Hereinafter, the results of confirming the effect of the display device according to another embodiment of the present invention through an experiment are summarized in [Table 1].

With or without low-resistance layer Current (mA/cm ² ) Leakage current ramp rate Radish (comparative example) 4.61*10 ^-3 - U (Example) 1.82*10 ^-3 60% reduction

The embodiment is a display device according to another embodiment of the present invention illustrated in FIGS. 7A and 7B , and the comparative example has a structure in which the low-resistance layer LRL is omitted from the display device according to another embodiment of the present invention. In the experiment, the leakage current flowing through the third sub-pixel SP3 was measured while the first sub-pixel SP1 was turned on and the third sub-pixel SP3 was turned off in Comparative Examples and Examples.

It was confirmed that the leakage current of the example including the first low-resistance layer LRL1 and the second low-resistance layer LRL2 was reduced by about 60% based on the leakage current of the comparative example. This is because leakage current from the first sub-pixel SP1 to the third sub-pixel SP3 does not flow to the third sub-pixel SP3, and the low-resistance between the first sub-pixel SP1 and the third sub-pixel SP3 is It means flowing through the layer (LRL) to the cathode (CAT).

Accordingly, in the display device according to another exemplary embodiment of the present invention, a low-low-rate pixel is disposed between the first sub-pixel SP1 and the third sub-pixel SP3 and between the first sub-pixel SP1 and the second sub-pixel SP2. A resistive layer LRL is disposed. Accordingly, the leakage current from the first sub-pixel SP1 having the largest turn-on voltage flowing to the second sub-pixel SP2 and the third sub-pixel SP3 is reduced, and color mixture, unevenness, color abnormality, etc. are reduced. It is possible to minimize deterioration of display quality due to this.

8 is a cross-sectional view between a cathode and a bank in which a first low-resistance layer is disposed between adjacent sub-pixels of a display device according to another exemplary embodiment of the present invention. In FIG. 8 , only the layers between the bank 116 and the cathode CAT disposed between the sub-pixels SP adjacent to each other are illustrated for convenience of illustration. Compared to the display device of FIGS. 7A to 7B , the display device of FIG. 8 differs only in the layers between the bank 116 and the cathode CAT disposed between the sub-pixels SP adjacent to each other. Since they are substantially the same, redundant descriptions are omitted.

Referring to FIG. 8 , in the display device according to another exemplary embodiment of the present invention, the common organic layers HIL, HTL1, ETL1 and the second layer are disposed between the bank 116 and the cathode CAT between the sub-pixels SP adjacent to each other. A first low-resistance layer LRL1 is disposed between the first hole transport layer HTL1 and the first electron transport layer ETL1 .

The first low-resistance layer LRL1 is made of a material having a lower resistance than the host included in the first emission layer EML1 . That is, the first low-resistance layer LRL1 may have a bandgap energy smaller than the bandgap energy of the first emission layer EML1 of the third sub-pixel SP3 . For example, the bandgap energy of the first emission layer EML1 of the third sub-pixel SP3 may be about 2.89 eV, and the bandgap energy of the first low-resistance layer LRL1 may be about 2.61 eV. It is not limited.

In some embodiments, the common organic layers HIL, HTL2, ETL2 and the second hole transport layer HTL2 and the second electron transport layer ETL2 between the bank 116 and the cathode CAT between the sub-pixels SP adjacent to each other. ), a second low-resistance layer LRL2 may be disposed. In this case, the second low-resistance layer LRL2 may be formed of a material having a lower resistance than that of the host included in the second emission layer EML2 .

In the display device according to another embodiment of the present invention, two light emitting units are disposed in each of the first sub-pixel SP1 , the second sub-pixel SP2 , and the third sub-pixel SP3 , while the sub-pixels adjacent to each other Between the bank 116 and the cathode CAT between the common organic layers HIL, HTL1, ETL1 and the first low-resistance layer between the first hole transport layer HTL1 and the first electron transport layer ETL1 between SP LRL1) is placed. The resistance of the first low-resistance layer LRL1 between the sub-pixels SP adjacent to each other may be less than the resistance of the first light emitting layer EML1 and the second light emitting layer EML2 in the two light emitting units. Accordingly, the leakage current from the first sub-pixel SP1 having the largest turn-on voltage flowing to the second sub-pixel SP2 and the third sub-pixel SP3 is reduced, and color mixture, unevenness, color abnormality, etc. are reduced. It is possible to minimize deterioration of display quality due to this.

9 is a cross-sectional view of a display device according to another exemplary embodiment. The display device 400 of FIG. 9 has only the first low-resistance layer LRL1 different from that of the display device 100 of FIGS. 1 to 5B , and other configurations are substantially the same, so a redundant description will be omitted. .

Referring to FIG. 9 , in the display device 400 according to another exemplary embodiment, the first low-resistance layer LRL1 may be disposed to overlap the end of the first emission layer EML1 of the adjacent sub-pixel SP. can In detail, ends of the first emission layer EML1 of the first sub-pixel SP1 and the third sub-pixel SP3 may be disposed on the bank 116 , and the first low-resistance layer LRL1 may be connected to each other. It may be disposed between the first and third sub-pixels SP1 and SP3 adjacent to each other so as to contact or overlap an end of the first emission layer EML1 between the first emission layers EML1 .

In the display device 400 according to another embodiment of the present invention, the second sub-pixel SP1 and the third sub-pixel SP3 and between the first sub-pixel SP1 and the second sub-pixel SP2 are disposed. A leakage current leaked through the common organic layers HIL, HTL1, and ETL1 of the light emitting device 120 may be minimized by disposing the first low-resistance layer LRL1 overlapping the end of the first emission layer EML1 . Accordingly, deterioration of display quality due to color mixing, unevenness, or color abnormality can be minimized. In addition, the first low-resistance layer LRL1 is disposed to overlap the end of the first emission layer EML1 to minimize the space between the sub-pixels SP, thereby minimizing leakage current and a display device suitable for high resolution. (400) can be provided.

10 is an enlarged plan view of a display device according to another exemplary embodiment.

The display device 500 of FIG. 10 is different from the display device 100 of FIGS. 1 to 5B only in the first low-resistance layer LRL1 , and other configurations are substantially the same. Therefore, a redundant description will be omitted. . In FIG. 10 , only the anode (ANO) of the light emitting device 120 is illustrated for convenience of explanation.

Referring to FIG. 10 , a plurality of first low-resistance layers LRL1 may be disposed between the plurality of sub-pixels SP. For example, the first low-resistance layer LRL1 may be formed between the first sub-pixel SP1 and the third sub-pixel SP3 , between the first sub-pixel SP1 and the second sub-pixel SP2 , and the second It may be disposed between the sub-pixel SP2 and the third sub-pixel SP3 . Accordingly, the first low-resistance layer LRL1 may be disposed to surround each of the second sub-pixel SP2 and the third sub-pixel SP3 . In this case, the first low-resistance layer RLR1 may not be disposed between each of the plurality of first sub-pixels SP3 disposed in the same column. Since the turn-on voltage of each of the plurality of first sub-pixels SP1 arranged in the same column is substantially the same, when one first sub-pixel SP1 is driven, the adjacent first sub-pixel SP1 emits light due to leakage current A problem is unlikely to occur, and rather, the second sub-pixel SP2 or the third sub-pixel SP3 having a relatively low turn-on voltage emits light or the second sub-pixel SP1 emits light due to the leakage current in the first sub-pixel SP1 . Due to the leakage current in the pixel SP2 , the third sub-pixel SP3 having a relatively low turn-on voltage may emit light. Accordingly, the first low-resistance layer LRL1 may be disposed between the plurality of sub-pixels SP having different turn-on voltages, and may not be disposed between the sub-pixels SP having substantially the same turn-on voltages. It may not be.

The plurality of first low-resistance layers LRL1 may have a lower resistance than that of the first emission layer EML1 disposed in the third sub-pixel SP3 . This is because the first low-resistance layer LRL1 has a bandgap energy smaller than the bandgap energy of the first light emitting layer EML1 disposed on the third sub-pixel SP3, so that the leakage current from the first sub-pixel SP1 is reduced. This is because it is easier to flow to the cathode CAT through the first low-resistance layer LRL1 than to flow to the second sub-pixel SP2 or the second sub-pixel SP3 .

In the display device 500 according to another embodiment of the present invention, a plurality of first low-resistance layers LRL1 are disposed between different adjacent sub-pixels SP, and specifically, a first low-resistance layer having the smallest turn-on voltage. A first low-resistance layer LRL1 is disposed to surround the third sub-pixel SP3 . Accordingly, the flow of leakage current from the first sub-pixel SP1 and the second sub-pixel SP2 having relatively large turn-on voltages to the third sub-pixel SP3 having the smallest turn-on voltage is suppressed, thereby mixing colors However, it is possible to minimize deterioration of display quality due to stains, color abnormalities, etc.

11 is an enlarged plan view of a display device according to another exemplary embodiment. The display device 600 of FIG. 11 is different from the display device 500 of FIG. 10 except that only the plurality of sub-pixels SP, the plurality of wirings, and the plurality of first low-resistance layers LRL1 are different from those of the display device 500 of FIG. 10 . are substantially the same, and thus a redundant description thereof will be omitted.

Referring to FIG. 11 , the plurality of sub-pixels SP includes a first sub-pixel SP1 , a second sub-pixel SP2 , and a third sub-pixel SP3 .

The plurality of first sub-pixels SP1 and the plurality of third sub-pixels SP3 may be alternately disposed in the same column or in the same row. For example, the first sub-pixel SP1 and the third sub-pixel SP3 are alternately arranged in the same column, and the first sub-pixel SP1 and the third sub-pixel SP3 are alternately arranged in the same row can be

The plurality of second sub-pixels SP2 are disposed in different columns and different rows from the plurality of first sub-pixels SP1 and the plurality of third sub-pixels SP3 . For example, a plurality of second sub-pixels SP2 are arranged in one row, and a plurality of first sub-pixels SP1 and a plurality of third sub-pixels SP3 are alternately arranged in a row adjacent to one row. can be placed as A plurality of second sub-pixels SP2 may be disposed in one column, and a plurality of first sub-pixels SP1 and a plurality of third sub-pixels SP3 may be alternately disposed in a column adjacent to one column. The plurality of first sub-pixels SP1 and the second sub-pixels SP2 may face each other in a diagonal direction, and the plurality of third sub-pixels SP3 and the second sub-pixels SP2 may also face each other in a diagonal direction. Accordingly, the plurality of sub-pixels SP may be arranged in a grid shape.

However, in FIG. 11 , the plurality of first sub-pixels SP1 and the plurality of third sub-pixels SP3 are disposed in the same column and in the same row, and the plurality of second sub-pixels SP2 includes the plurality of first sub-pixels. Although it is illustrated that the plurality of sub-pixels SP are disposed in different columns and different rows from those of SP1 and the plurality of third sub-pixels SP3, the arrangement of the plurality of sub-pixels SP is not limited thereto.

A plurality of high potential power lines PL extending in a column direction are disposed between each of the plurality of sub-pixels SP. The high potential power line PL may be disposed between a column in which the plurality of second sub-pixels SP2 are disposed and a column in which the plurality of first sub-pixels SP1 and a plurality of third sub-pixels SP3 are disposed. . For example, the high potential power wiring PL may be disposed on both sides of the plurality of second sub-pixels SP2 , and on both sides of the plurality of first sub-pixels SP1 and the plurality of third sub-pixels SP3 . .

A plurality of data lines DL extending in a column direction are disposed between each of the plurality of high potential power lines PL. That is, the plurality of high potential power lines PL and the plurality of data lines DL may be alternately disposed. Some of the plurality of data lines DL are disposed to overlap the plurality of second sub-pixels SP2 disposed in the same column, and other portions of the plurality of data lines DL are disposed to overlap with the plurality of first sub-pixels disposed in the same column. It may be disposed to overlap SP1 and the plurality of third sub-pixels SP3 .

A plurality of initialization signal lines IL extending in the row direction are disposed between each of the plurality of sub-pixels SP. The initialization signal line IL may be disposed between a row in which the plurality of second sub-pixels SP2 are disposed and a row in which the plurality of first sub-pixels SP1 and a plurality of third sub-pixels SP3 are disposed. . For example, the initialization signal line IL may be disposed on both sides of the plurality of second sub-pixels SP2 and on both sides of the plurality of first sub-pixels SP1 and the plurality of third sub-pixels SP3 .

A plurality of scan lines SL and a plurality of light emission control signal lines EL extending in the row direction are disposed between the plurality of initialization signal lines IL, respectively. For example, the first scan line SL1 of the plurality of scan lines SL is disposed to overlap the plurality of second sub-pixels SP2 , and the second scan line SL2 of the plurality of scan lines SL is disposed to overlap the plurality of second sub-pixels SP2 . may be disposed to overlap the plurality of first sub-pixels SP1 and the plurality of third sub-pixels SP3 . In addition, each of the plurality of emission control signal lines EL may be disposed adjacent to the first scan line SL1 to overlap each of the second sub-pixels SP2 . However, in FIG. 11 , some of the plurality of wires are disposed between the plurality of sub-pixels SP and others overlap with the plurality of sub-pixels SP, but the arrangement of the plurality of wires is not limited thereto. .

Referring to FIG. 11 , the first low-resistance layer LRL1 is disposed in a closed curve shape surrounding the plurality of sub-pixels SP. For example, the plurality of first low-resistance layers LRL1 may have a closed curve shape to correspond to the planar shape of each of the first sub-pixels SP1 . However, in FIG. 11 , the first sub-pixel SP1 has the highest turn-on voltage, and thus the second sub-pixel SP2 or the third sub-pixel SP3 is caused by leakage current generated from the first sub-pixel SP1. Since unintentional light emission is highly likely, the plurality of first low-resistance layers LRL1 are illustrated as being disposed to surround each of the plurality of first sub-pixels SP1 , but the plurality of first low-resistance layers The LRL1 may be disposed to surround the third sub-pixel SP3 having the lowest turn-on voltage instead of the first sub-pixel SP1 , or may be disposed to surround all of the plurality of sub-pixels SP.

The plurality of first low-resistance layers LRL1 may have a lower resistance than that of the first emission layer disposed in the third sub-pixel SP3 . This is because the first low-resistance layer LRL1 has a bandgap energy smaller than the bandgap energy of the first emission layer disposed in the third sub-pixel SP3, so that the leakage current from the first sub-pixel SP1 is reduced in the second sub-pixel SP3. This is because it is easier to flow to the cathode CAT through the first low-resistance layer LRL1 than to flow to the pixel SP2 or the second sub-pixel SP3 .

In the display device 600 according to another embodiment of the present invention, a plurality of first low-resistance layers LRL1 are disposed to surround each of the plurality of first sub-pixels SP1 . Accordingly, when the display device 600 is driven, it is possible to minimize leakage current from being transmitted to the sub-pixel SP unintentionally. For example, the leakage current path is formed from the first sub-pixel SP1 having a high turn-on voltage to the second sub-pixel SP2 or the third sub-pixel SP3 having a low turn-on voltage, and the resistance of the emission layer When the first low-resistance layer LRL1 having a lower resistance is disposed to surround the plurality of sub-pixels SP, a path of a leakage current may be blocked by the first low-resistance layer LRL1 . Accordingly, in the display device 600 according to another embodiment of the present invention, leakage current from the first sub-pixel SP1 having the largest turn-on voltage occurs in the second sub-pixel SP2 and the third sub-pixel SP3. ), and it is possible to minimize deterioration of display quality due to color mixing, unevenness, or color abnormality.

Display devices according to embodiments of the present invention may be described as follows.

A display device according to an exemplary embodiment includes a plurality of light emitting devices disposed on a substrate on which a plurality of sub-pixels are defined, a plurality of sub-pixels, sharing a common organic layer and a cathode, and each having separate light-emitting layers, and a plurality of light-emitting devices and a bank disposed below the cathode between each of the devices and a low-resistance layer disposed between the bank and the cathode between the plurality of light emitting devices, the low-resistance layer having a lower resistance than that of the light emitting layer.

According to another feature of the present invention, each of the plurality of light emitting devices includes a first light emitting part, the common organic layer includes a first hole injection layer, a first hole transport layer and a first electron transport layer, and the first light emitting part includes a first hole It has a structure in which an injection layer, a first hole transport layer, a light emitting layer, and a first electron transport layer are stacked in this order, and the low-resistance layer may be disposed between the first hole transport layer and the first electron transport layer between the plurality of light emitting devices.

According to another feature of the present invention, each of the plurality of light emitting devices includes a first light emitting part and a second light emitting part on the first light emitting part, and the common organic layer includes a first hole injection layer, a first hole transport layer, and a first electron transport layer. , a charge generating layer, a second hole transport layer, and a second electron transport layer, wherein the light emitting layer includes a first light emitting layer and a second light emitting layer that emit light of the same color, and the first light emitting unit includes a first hole injection layer, a second The hole transport layer, the first light emitting layer and the first electron transport layer have a stacked structure in this order, the second light emitting unit has a second hole transport layer, the second light emitting layer and the second electron transport layer have a stacked structure in this order, and the charge generating layer includes The first low-resistance layer and the second hole transport layer are disposed between the first light emitting part and the second light emitting part, and the low-resistance layer is disposed between the first hole transport layer and the first electron transport layer between the plurality of light emitting devices. and a second low-resistance layer disposed between the two electron transport layers.

According to another feature of the present invention, the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel that emit light of different colors, the first sub-pixel, the second sub-pixel, and A turn-on voltage may decrease in the order of the third sub-pixels, and the low-resistance layer may be disposed between the first sub-pixel and the third sub-pixel.

According to another feature of the present invention, the first sub-pixel is a blue sub-pixel,

The second sub-pixel may be a green sub-pixel, and the third sub-pixel may be a red sub-pixel.

According to another feature of the present invention, the low-resistance layer may be disposed to surround the first sub-pixel.

According to another feature of the present invention, the low-resistance layer may be further disposed between the first sub-pixel and the second sub-pixel.

According to another feature of the present invention, the low-resistance layer may have a lower resistance than the light emitting layer disposed in the first sub-pixel.

According to another feature of the present invention, the low-resistance layer may have a bandgap energy smaller than a bandgap energy of the light emitting layer disposed in the first sub-pixel.

According to another feature of the present invention, the low-resistance layer may be made of a material having a lower resistance than the host included in the emission layer disposed in the first sub-pixel.

According to another feature of the present invention, the low-resistance layer may be disposed between the emission layers of the sub-pixels adjacent to each other.

According to another feature of the present invention, the low-resistance layer may be disposed to overlap the ends of the emission layers of the sub-pixels adjacent to each other.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made within the scope without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100, 400, 500, 600: display device
110: substrate
111: buffer layer
112: gate insulating layer
113: interlayer insulating layer
114: passivation layer
115: planarization layer
116: bank
120, 620: light emitting device
ANO: anode
121, 221, 621: organic layer
HIL: hole injection layer
HTL1: first hole transport layer
HTL2: second hole transport layer
ETL1: first electron transport layer
ETL2: second electron transport layer
CGL: charge generation layer
LRL: low-resistance layer
LRL1: first low-resistance layer
LRL2: second low-resistance layer
EML1: first light emitting layer
EML2: second light emitting layer
CAT: cathode
130, 630: spacer
PN: display panel
GD: gate driver
DD: data driver
TC: Timing Controller
SP: sub pixel
SP1: first sub-pixel
SP2: second sub-pixel
SP3: third sub-pixel
SL: scan wiring
SL1: first scan wiring
SL2: second scan wiring
DL: data wiring
PL: high potential power wiring
EL: Light emission control signal wiring
IL: Initialization signal wiring
DPL: Dummy Wiring
Cst: capacitor
T1: first transistor
T2: second transistor
T3: third transistor
T4: fourth transistor
T5: fifth transistor
T6: sixth transistor
ACT: active layer
GE: gate electrode
DE: drain electrode
SE: source electrode
CE: connecting electrode
RGB: image data
GCS: gate control signal
DCS: data control signal
SYNC: Sync signal
EVDD: high potential power signal
EVSS: low potential power signal
SCAN1: first scan signal
SCAN2: second scan signal
Vdata: data signal
EM: light emission control signal
Vini: initialization signal
R _LRL1 : Resistance of the first low-resistance layer
R _120-1 : resistance of the light emitting device of the first sub-pixel
R _120-3 : resistance of the light emitting element of the third sub-pixel
R _L : resistance of the common organic layer connected between the first sub-pixel and the third sub-pixel
E1: first light emitting part
E2: second light emitting part

Claims (12)

a substrate on which a plurality of sub-pixels are defined;
a plurality of light emitting devices disposed in the plurality of sub-pixels, sharing a common organic layer and a cathode, and each having separate light emitting layers;
a bank disposed below the cathode between each of the plurality of light emitting devices; and
and a low-resistance layer disposed between the bank and the cathode between the plurality of light emitting elements and having a lower resistance than that of the light emitting layer. According to claim 1,
Each of the plurality of light emitting devices includes a first light emitting unit,
The common organic layer includes a first hole injection layer, a first hole transport layer, and a first electron transport layer,
The first light emitting part has a structure in which the first hole injection layer, the first hole transport layer, the light emitting layer, and the first electron transport layer are stacked in this order,
and the low-resistance layer is disposed between the first hole transport layer and the first electron transport layer between the plurality of light emitting devices. According to claim 1,
Each of the plurality of light emitting devices includes a first light emitting unit and a second light emitting unit on the first light emitting unit,
The common organic layer includes a first hole injection layer, a first hole transport layer, a first electron transport layer, a charge generation layer, a second hole transport layer, and a second electron transport layer,
The light emitting layer includes a first light emitting layer and a second light emitting layer emitting light of the same color,
The first light emitting part has a structure in which the first hole injection layer, the first hole transport layer, the first light emitting layer and the first electron transport layer are stacked in this order,
The second light emitting unit has a structure in which the second hole transport layer, the second light emitting layer, and the second electron transport layer are stacked in this order,
The charge generation layer is located between the first light emitting part and the second light emitting part,
wherein the low-resistance layer is disposed between the first low-resistance layer and the second hole transport layer and the second electron transport layer disposed between the first hole transport layer and the first electron transport layer between the plurality of light emitting devices A display device comprising a second low-resistance layer. According to claim 1,
The plurality of sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel that emit light of different colors;
a turn-on voltage decreases in the order of the first sub-pixel, the second sub-pixel, and the third sub-pixel;
and the low-resistance layer is disposed between the first sub-pixel and the third sub-pixel. 5. The method of claim 4,
the first sub-pixel is a blue sub-pixel;
the second sub-pixel is a green sub-pixel;
and the third sub-pixel is a red sub-pixel. 5. The method of claim 4,
The low-resistance layer is disposed to surround the first sub-pixel. 7. The method of claim 6,
and the low-resistance layer is further disposed between the first sub-pixel and the second sub-pixel. 5. The method of claim 4,
and the low-resistance layer has a lower resistance than a light emitting layer disposed in the third sub-pixel. 5. The method of claim 4,
The low-resistance layer has a bandgap energy smaller than a bandgap energy of the light emitting layer disposed in the third sub-pixel. 5. The method of claim 4,
The low-resistance layer is made of a material having a lower resistance than a host included in the emission layer disposed in the third sub-pixel. According to claim 1,
and the low-resistance layer is disposed between light emitting layers of sub-pixels adjacent to each other. According to claim 1,
The low-resistance layer is disposed to overlap with ends of the emission layers of the sub-pixels adjacent to each other.

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