KR20220089996A - Gate driver and display device including the same - Google Patents

Abstract

The gate driver according to an embodiment of the present invention includes a plurality of stage groups each including a plurality of stages, a lowermost stage of an Nth stage group among a plurality of stage groups, and a start connected to the uppermost stage of an N+1th stage a control circuit, and an enable line connected to the start control circuit, wherein the start control circuit stores the Q node voltage of the lowest stage of the Nth stage group. Therefore, by arranging a start control circuit that stores the Q node voltage of the previous stage during the touch sensing period and outputs a start signal to a stage group to be driven in the next display period, it is possible to reduce the number of start wires, and a plurality of stage groups The timing of each operation can be easily controlled.

Description

A gate driver and a display device including the same

The present invention relates to a gate driver and a display device including the same, and more particularly, to a display device in which the gate driver is simplified.

Display devices used in computer monitors, TVs, and mobile phones include organic light emitting displays (OLEDs) that emit light by themselves, and liquid crystal displays (LCDs) that require a separate light source. have.

Display devices are being applied to personal portable devices as well as computer monitors and TVs, and research on a display device having a reduced volume and weight while having a large display area is in progress.

Meanwhile, among display devices, there is a touch screen-integrated display device including a touch unit capable of recognizing a user's touch. The touch screen-integrated display device can directly input information using a finger or a pen, and is widely applied to portable terminals, navigation devices, and home appliances.

SUMMARY OF THE INVENTION An object of the present invention is to provide a gate driver in which a display section and a touch sensing section are performed together in one frame in order to improve touch sensitivity, and a display device including the same.

Another object of the present invention is to provide a gate driver capable of easily operating a gate driving circuit temporarily stopped during a touch sensing period when a display period starts, and a display device including the same.

Another object of the present invention is to provide a gate driver in which a wiring to which a start signal for operating the gate driver is applied is unified, and a display device including the same.

Another object of the present invention is to provide a gate driver capable of individually controlling starting points of a plurality of stage groups each including a plurality of stages, and a display device including the same.

The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

In order to solve the above problems, the gate driver according to an embodiment of the present invention includes a plurality of stage groups each including a plurality of stages, a lowermost stage of an Nth stage group among the plurality of stage groups, and an Nth + a start control circuit connected to the uppermost stage of the first stage, and an enable line connected to the start control circuit, wherein the start control circuit stores the Q node voltage of the lowermost stage of the Nth stage group. Therefore, by arranging a start control circuit that stores the Q node voltage of the previous stage during the touch sensing period and outputs a start signal to a stage group to be driven in the next display period, it is possible to reduce the number of start wires, and a plurality of stage groups The timing of each operation can be easily controlled.

In order to solve the above problems, a display device according to an embodiment of the present invention includes a display panel including a plurality of sub-pixels, and a gate driver supplying a scan signal to each of the plurality of sub-pixels, the gate The driving unit includes a plurality of stage groups each including a plurality of stages, a start control circuit connected to a lowermost stage of an Nth stage group and an uppermost stage of an N+1th stage group among the plurality of stage groups, and a start control circuit; It includes a connected enable line, and the start control circuit may store the Q node voltage of the lowest stage of the Nth stage group and apply the start signal to the highest stage of the N+1th stage group. Accordingly, the driving timing of the plurality of stage groups can be controlled by one start wire and a plurality of start control circuits, so that the size of the non-display area can be reduced.

Details of other embodiments are included in the detailed description and drawings.

The present invention can improve the touch sensing sensitivity of the touch unit by repeatedly performing the display period and the touch sensing period in one frame.

The present invention can simplify the start wiring to which the start signal for driving the gate driver in the display section is applied.

According to the present invention, a plurality of stage groups of the gate driver may be operated at different timings.

According to the present invention, by disposing a start control circuit for individually controlling a plurality of stage groups, the number of wires for driving the gate driver can be reduced and the bezel size can be minimized.

The effect according to the present invention is not limited by the contents exemplified above, and more various effects are included in the present invention.

1 is a schematic configuration diagram of a display device according to an exemplary embodiment of the present invention.
2 is a diagram for explaining a method of driving a display device according to an exemplary embodiment.
3 and 4 are schematic configuration diagrams of a gate driver of a display device according to an exemplary embodiment.
5 is a circuit diagram of a stage of a gate driver of a display device according to an exemplary embodiment.
6 is a waveform diagram illustrating signals input/output to a stage of a gate driver of a display device according to an exemplary embodiment.
7 is a circuit diagram of a start control circuit of a gate driver of a display device according to an exemplary embodiment.
8 and 9 are waveform diagrams illustrating signals input and output to a start control circuit of a gate driver of a display device according to an exemplary embodiment.
10 is a circuit diagram of a start control circuit of a display device according to another exemplary embodiment.
11 is a circuit diagram of a start control circuit of a display device according to another exemplary embodiment.
12 is a waveform diagram illustrating signals input/output to a start control circuit of a display device according to another exemplary embodiment.

Advantages and features of the present invention, and a method of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different shapes, only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention pertains It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative and the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. When 'includes', 'have', 'consists of', etc. mentioned in the present invention are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, cases including the plural are included unless otherwise explicitly stated.

In interpreting the components, it is construed as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

Reference to a device or layer “on” another device or layer includes any intervening layer or other device directly on or in the middle of the other device or layer.

Also, although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

Like reference numerals refer to like elements throughout.

The area and thickness of each component shown in the drawings are illustrated for convenience of description, and the present invention is not necessarily limited to the area and thickness of the illustrated component.

Each feature of the various embodiments of the present invention can be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be independently implemented with respect to each other or implemented together in a related relationship. may be

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic configuration diagram of a display device according to an exemplary embodiment of the present invention. 1 illustrates only the display panel PN, the gate driver GD, the data driver DD, the touch driver TD, and the timing controller TC among various components of the display device 100 for convenience of explanation. .

Referring to FIG. 1 , the display device 100 includes a display panel PN including a plurality of sub-pixels SP, a gate driver GD and a data driver DD supplying various signals to the display panel PN. , a timing controller TC for controlling the gate driver GD and the data driver DD, and a touch driver TD for sensing a touch input.

The gate driver GD supplies the plurality of scan signals SCAN to the plurality of scan lines SL according to the plurality of gate control signals GCS provided from the timing controller TC. Although one gate driver GD is illustrated as being spaced apart from one side of the display panel PN in FIG. 1 , the number and arrangement of the gate drivers GD is not limited thereto.

The data driver DD converts the image data RGB input from the timing controller TC into a data signal using a reference gamma voltage according to a plurality of data control signals DCS provided from the timing controller TC. In addition, the data driver DD may supply the converted data signal to the plurality of data lines DL.

The timing controller TC aligns the image data RGB input from the outside and supplies it to the data driver DD. The timing controller TC generates a gate control signal GCS and a data control signal DCS using an externally input synchronization signal SYNC, for example, a dot clock signal, a data enable signal, and a horizontal/vertical synchronization signal. can create In addition, the timing controller TC supplies the generated gate control signal GCS and the data control signal DCS to each of the gate driver GD and the data driver DD to control the gate driver GD and the data driver DD. can be controlled

The touch driver TD drives the touch unit based on a touch enable signal input from the timing controller TC or an external component. The touch driving unit TD may sense a touch input by supplying a touch driving signal to the plurality of touch electrodes of the touch unit through the touch sensing wiring TL.

Although not shown in the drawings, the touch unit is configured to include a plurality of touch electrodes for detecting a touch input. The touch unit may be disposed to overlap the display panel PN, and may detect a touch input input on the display panel PN. The plurality of touch electrodes may be connected to the touch sensing line TL and the touch driver TD to sense a touch input. At this time, depending on the arrangement method of the touch electrodes, an add-on type in which a separate touch unit is manufactured and attached to the display panel PN, and an on-cell type in which the touch unit is directly formed on the display panel PN (on-cell type) cell type), and an in-cell type in which a touch unit is built into the display panel PN.

The display panel PN is configured to display an image to a user and includes a plurality of sub-pixels SP. In the display panel PN, the plurality of scan lines SL and the plurality of data lines DL cross each other, and each of the plurality of sub-pixels SP is connected to the scan line SL and the data line DL. In addition, although not shown in the drawings, each of the plurality of sub-pixels SP may be connected to a high potential power line, a low potential power line, an initialization signal line, a light emission control signal line, and the like.

The plurality of sub-pixels SP is a minimum unit constituting a screen, and each of the plurality of sub-pixels SP includes a light emitting device and a pixel circuit for driving the plurality of sub-pixels. The plurality of light emitting devices may be defined differently depending on the type of the display panel PN. For example, when the display panel PN is an organic light emitting display panel, the light emitting device may be an organic light emitting device including an anode, an organic layer, and a cathode. In addition, a quantum dot light-emitting diode (QLED) including a quantum dot (QD) may be further used as the light emitting device.

Hereinafter, a method of driving the display device 100 according to an exemplary embodiment of the present invention will be described with reference to FIG. 2 .

2 is a diagram for explaining a method of driving a display device according to an exemplary embodiment.

First, referring to FIG. 2 , in the display device 100 according to an embodiment of the present invention, one frame period is time-divided into a plurality of display periods DT and a plurality of touch sensing periods TT, and the display period DT ), the scan signal SCAN and the data voltage Vdata may be output to the plurality of sub-pixels SP to input the image data RGB to the display panel PN.

For example, one frame period may include a plurality of display periods DT for inputting image data RGB to the plurality of sub-pixels SP and a plurality of touch sensing periods TT for driving the touch unit. In addition, the plurality of display periods DT and the plurality of touch sensing periods TT may be alternately repeated within one frame period.

A driving method in which the display period DT and the touch sensing period TT are alternately repeated during one frame period is called an Intra-Frame Pause (IFP) method. In the IFP method, by arranging the touch sensing period TT in one frame period, the touch sensing time may be secured and the touch sensitivity may be improved. That is, the touch performance of the display device 100 may be improved through the IFP method.

The plurality of display periods DT are periods in which the image data RGB is input to the plurality of sub-pixels SP, and the gate driver GD sequentially outputs the scan signal SCAN to the display panel PN, , the data driver DD may supply the data voltage Vdata to the display panel PN in synchronization with the scan signal SCAN.

The plurality of touch sensing sections TT are sections in which the touch unit including the plurality of touch electrodes is driven. The gate driver GD stops outputting the scan signal SCAN, and the touch driver TD drives a touch by the touch unit. A touch input may be sensed by supplying a signal.

However, the number and length of the plurality of display sections DT and the plurality of touch sensing sections TT illustrated in FIG. 2 are exemplary and are not limited thereto.

Hereinafter, a method of driving the display device 100 and the gate driver GD according to an embodiment of the present invention will be described in more detail with reference to FIGS. 3 and 4 .

3 and 4 are schematic configuration diagrams of a gate driver of a display device according to an exemplary embodiment. 3 is a diagram illustrating a plurality of stage groups STG and a plurality of start control circuits STC of the display device 100 according to an exemplary embodiment. 4 is a diagram illustrating a plurality of stages ST and a start control circuit STC of a plurality of stage groups STG of the display device 100 according to an exemplary embodiment. In FIG. 4 , only some stages ST of the first stage group STG1 and the second stage group STG2 among the plurality of stage groups STG are illustrated for convenience of description.

Referring to FIG. 3 , the gate driver GD may include a plurality of stage groups STG for driving the IFP. Each of the plurality of stage groups STG may output a scan signal SCAN corresponding to each of the plurality of display periods DT. For example, as shown in FIG. 2 , when there are four display sections DT, the gate driver GD includes the first stage group STG1, the second stage group STG2, and the third stage group DT. STG3) and a fourth stage group STG4.

In addition, the first stage group STG1 may be driven during the first display period DT1 among the plurality of display periods DT and the second stage group STG2 may be driven during the second display period DT2, , the third stage group STG3 may be driven during the third display period DT3 , and the fourth stage group STG4 may be driven during the fourth display period DT4 . The number of the plurality of stage groups STG may correspond to the number of the plurality of display periods DT during one frame time.

A plurality of touch sensing sections TT in which the touch driver TD is driven are configured between each of the plurality of display sections DT. For example, the plurality of touch sensing periods TT include a first touch sensing period TT1 , a second touch sensing period TT2 , a third touch sensing period TT3 , and a fourth touch sensing period TT4 . can do. The first touch sensing period TT1 is a period in which the touch driver TD operates after the driving of the first stage group STG1 is completed, and the second touch sensing period TT2 is the driving period of the second stage group STG2 After this is completed, the touch driver TD operates, and the third touch sensing period TT3 is a period in which the touch driver TD operates after the driving of the third stage group STG3 is completed, and the fourth touch sensing The period TT4 may be a period in which the touch driver TD operates after driving of the fourth stage group STG4 is completed.

3 and 4 together, each of the plurality of stage groups STG includes a plurality of stages ST. The plurality of stages ST may be dependently connected to sequentially output the scan signal SCAN. For example, the plurality of stages ST includes a plurality of first stages ST1 forming the first stage group STG1 , a plurality of second stages ST2 forming the second stage group STG2 , and a third stage forming the second stage group STG2 . It may include a plurality of third stages constituting the group STG3 and a plurality of fourth stages constituting the fourth stage group STG4 .

The plurality of stages ST receive the output of the previous stage ST, charge the Q node Q, and output the scan signal SCAN to the scan wiring SL corresponding to each of the plurality of stages ST. can For example, each of the plurality of first stages ST1 constituting the first stage group STG1 receives the scan signal SCAN output from the first stage ST1 of the previous stage and charges the Q node Q, , the scan signal SCAN may be sequentially output. In this case, the uppermost first stage ST1a among the plurality of first stages ST1 does not have the previous first stage ST1 , and thus receives the first start signal from the first start wiring VSTa to perform a first scan A signal SCAN(1) may be output.

Meanwhile, since each of the plurality of stage groups STG is independently driven to correspond to the plurality of display periods DT, the lowermost stage ST of each of the plurality of stage groups STG is the uppermost stage of the next stage group STG. (ST) may not be connected. For example, when the lowermost first stage ST1b of the first stage group STG1 and the uppermost second stage ST2a of the second stage group STG2 are dependently connected, the output from the lowermost first stage ST1b The n-th scan signal SCAN(n) from the uppermost second stage ST2a of the second stage group STG2 is generated during the touch sensing period TT by the n-th scan signal SCAN(n-1). can be output to Therefore, in order to individually drive the first stage group STG1 and the second stage group STG2 , the output of the first stage ST1b at the lowermost stage of the first stage group STG1 is the uppermost stage of the second stage group STG2. It may not be directly transmitted to the second stage ST2a.

Therefore, the driving timing of some stage groups STG in which the uppermost stage ST is not connected to the first start wiring VSTa may be controlled by the start control circuit STC. For example, in the first stage group STG1, the uppermost first stage ST1a is connected to the first start wiring VSTa, and the first scan is performed according to a first start signal applied to the first start wiring VSTa. A signal SCAN(1) may be output. For example, each of the second stage group STG2 , the third stage group STG3 , and the fourth stage group STG4 in which the uppermost stage ST is not connected to the first start wiring VSTa has different start control It may be connected to the circuit STC, and may receive the second start signal from the start control circuit STC and output the scan signal SCAN.

The start control circuit STC is disposed between each of the plurality of stage groups STG, and applies the second start signal to the next stage group STG in the new display period DT after the touch sensing period TT. to be. Specifically, the start control circuit STC stores the voltage of the Q node Q from the lowest stage ST of one stage group STG, and then moves the second stage group STG to the highest stage ST. It is a circuit that applies a start signal. The start control circuit STC is connected between the lowermost stage ST of the Nth stage group STG and the uppermost stage ST of the N+1th stage group STG, and is the lowermost end of the Nth stage group STG. The voltage of the Q node Q of the stage ST may be stored, and the second start signal may be applied to the uppermost stage ST of the (N+1)th stage group STG. For example, the start control circuit STC may be connected to the lowermost first stage ST1b of the first stage group STG1 and the uppermost second stage ST2a of the second stage group STG2, and the first stage The second start signal may be applied from the lowest first stage ST1b of the group STG1 to the uppermost stage ST of the second stage group STG2 using the Q node Q voltage.

The start control circuit STC is connected to the enable line EN and the reset line RS. The start control circuit STC may receive the enable signal from the enable line EN and output the second start signal. The start control circuit STC may receive a reset signal from the reset line RS to reset a first node and a second node, which will be described later. A more detailed description of the enable line EN and the reset line RS will be described later with reference to FIGS. 7 and 8 .

Hereinafter, the plurality of stages ST will be described in detail with reference to FIGS. 5 to 6 .

5 is a circuit diagram of a stage of a gate driver of a display device according to an exemplary embodiment. 6 is a waveform diagram illustrating signals input/output to a stage of a gate driver of a display device according to an exemplary embodiment. FIG. 5 is a circuit diagram of the uppermost first stage ST1a of the first stage group STG1 and the uppermost second stage ST2a of the second stage group STG2 among the plurality of stage groups STG. 6 is a waveform diagram of signals input and output to the uppermost first stage ST1a of the first stage group STG1 among the plurality of stage groups STG.

Referring to FIG. 5 , the uppermost first stage ST1a of the first stage group STG1 includes a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , It includes a fifth transistor T5 , a sixth transistor T6 , a seventh transistor T7 , a bridge voltage transistor Tbv , a first capacitor CQ, and a second capacitor CB. Hereinafter, it is assumed that both the first transistors T1 to T7 and the bridge voltage transistor Tbv are P-type transistors, but the present invention is not limited thereto.

The first transistor T1 has a gate electrode connected to one of the plurality of clock lines. For example, the gate electrode of the first transistor T1 may be connected to the first clock line CLK1 . And the first electrode of the first transistor T1 is connected to the first start wiring (VSTa). The second electrode of the first transistor T1 may be connected to the node A. The A node (A) may be a node that maintains substantially the same voltage state as the Q node (Q). In this case, when the first transistor T1 is a P-type, the first electrode may be a source electrode and the second electrode may be a drain electrode, but is not limited thereto.

The gate electrode of the second transistor T2 is connected to another clock line among the plurality of clock lines. For example, the gate electrode of the second transistor T2 may be connected to the second clock line CLK2 . And, the first electrode of the second transistor T2 is connected to the node A, and the second electrode is connected to the third transistor T3.

The third transistor T3 has a gate electrode connected to the QB node QB. The third transistor T3 has a first electrode connected to the gate high wiring VGH and a second electrode connected to the second electrode of the second transistor T2 .

The fourth transistor T4 has a gate electrode connected to the node A and a first electrode connected to the second clock line CLK2 . The second electrode of the fourth transistor T4 is connected to the QB node QB.

The fifth transistor T5 has a gate electrode connected to the first clock line CLK1 . A first electrode of the fifth transistor T5 is connected to the gate row line VGL, and a second electrode of the fifth transistor T5 is connected to the QB node QB.

The gate electrode of the sixth transistor T6 is connected to the Q node Q, the first electrode is connected to the second clock line CLK2, and the second electrode is connected to the output terminal.

The seventh transistor T7 has a gate electrode connected to the QB node QB and a first electrode connected to the gate high line VGH. And the second electrode of the seventh transistor T7 is connected to the output terminal.

The bridge voltage transistor Tbv may have a gate electrode connected to the gate row line VGL to always maintain a turned-on state. Since the bridge voltage transistor Tbv is a P-type, it may be connected to the gate row wiring VGL through which a low-level signal is transmitted and turned on. In the bridge voltage transistor Tbv, the first electrode is connected to the A node (A) and the second electrode is connected to the Q node (Q), so that the voltages of the A node (A) and the Q node (Q) are substantially the same can be kept Also, the bridge voltage transistor Tbv may prevent static electricity from the A node A from being transferred to the Q node Q.

The Q node Q may charge the gate electrode of the sixth transistor T6 , and the QB node QB may discharge the gate electrode of the seventh transistor T7 .

The first capacitor CQ is connected between the Q node Q and the output terminal. The first capacitor CQ may store the voltage of the Q node Q. The second capacitor CB is connected between the QB node QB and the gate high wiring VGH. The second capacitor CB may store the voltage of the QB node QB.

Compared to the uppermost first stage ST1a of the first stage group STG1, the uppermost second stage ST2a of the second stage group STG2 has the first electrode of the first transistor T1 connected to the second start wiring ( It is substantially the same except that it is connected to VSTb). In the uppermost second stage ST2a of the second stage group STG2, the first electrode of the first transistor T1 is connected to the second start wiring VSTb to which the second start signal is transmitted from the start control circuit STC. can

Meanwhile, in FIG. 5 , the uppermost first stage ST1a of the first stage group STG1 and the uppermost second stage ST2a of the second stage group STG2 are connected to the first clock wire CLK1 and the second clock wire ( Although illustrated as being connected to CLK2), the clock wirings connected to each of the uppermost stages ST are exemplary and are not limited thereto.

Referring to FIG. 6 , a low-level signal is applied to the first start line VSTa and the first clock line CLK1 connected to the uppermost first stage ST1a. In this case, a low-level signal is applied to the first clock line CLK1 so that the first transistor T1 and the fifth transistor T5 of the uppermost first stage ST1a of the first stage group STG1 are turned- can be on In addition, the first start signal may be transmitted to the Q node Q through the turned-on first transistor T1 . Accordingly, by applying a low-level signal to the first clock line CLK1 and the first start line VSTa, the voltage of the Q node Q can be set to be the same as the first start signal, and the uppermost first stage ( The output of ST1a) can be controlled.

Subsequently, a low-level signal is applied to the second clock line CLK2 . When a high level signal is applied to the first clock line CLK1 and a low level signal is applied to the second clock line CLK2, the Q node Q is floated and the second clock line ( A signal from CLK2 may be transferred to the second electrode of the sixth transistor T6 through the sixth transistor T6 in a turned-on state. Accordingly, the voltage of the Q node Q may change to a lower voltage than the low-level first start signal due to a bootstrap phenomenon of the first capacitor CQ. The bootstrap phenomenon is a method of increasing the output of the drain electrode by lowering the voltage of the gate electrode of the transistor. Accordingly, as the voltage at the Q node Q is lowered, the sixth transistor T6 may maintain a turned-on state and stably output the first scan signal SCAN.

Accordingly, the uppermost first stage ST1a of the first stage group STG1 has a clock signal applied to the gate electrode of the first transistor T1 and a first start signal applied to the first electrode of the first transistor T1 . When is at the same low level, the Q node Q may be charged to output the first scan signal SCAN.

In addition, the uppermost second stage ST2a of the second stage group STG2 may also output the scan signal SCAN in the same principle as the uppermost first stage ST1a of the first stage group STG1 . For example, when a second start signal is input from the start control circuit STC to the uppermost second stage ST2a of the second stage group STG2 and a low-level signal is applied from the first clock line CLK1 , , the first transistor T1 and the fifth transistor T5 may be turned on. In addition, the second start signal may be transmitted to the Q node Q through the turned-on first transistor T1 , and the scan signal SCAN may be output through the voltage charged in the Q node Q. have.

Hereinafter, the start control circuit STC for outputting the second start signal will be described in more detail with reference to FIGS. 7 to 9 .

7 is a circuit diagram of a start control circuit of a gate driver of a display device according to an exemplary embodiment. 8 and 9 are waveform diagrams illustrating signals input and output to a start control circuit of a gate driver of a display device according to an exemplary embodiment. Specifically, FIG. 7 is a circuit diagram of the start control circuit STC connected between the lowest first stage ST1b of the first stage group STG1 and the uppermost second stage ST2a of the second stage group STG2. 8 is a waveform diagram illustrating signals input and output to the start control circuit STC when the scan signal SCAN is output from the first stage ST1b at the lowermost stage of the first stage group STG1. 9 is a waveform diagram illustrating signals input and output to the start control circuit STC when the scan signal SCAN is not output from the first stage ST1b at the lowermost stage of the first stage group STG1.

Referring to FIG. 7 , the start control circuit STC includes a first control transistor M1 , a second control transistor M2 , a third control transistor M3 , and a fourth control transistor M4 . Hereinafter, for convenience of explanation, it is assumed that the first control transistor M1, the second control transistor M2, the third control transistor M3, and the fourth control transistor M4 are P-type. , but not limited thereto.

In the first control transistor M1 , the gate electrode and the first electrode are connected to the Q node Q of the lowest stage ST of the N-th stage group STG, and the second electrode is connected to the first node N1 . do. For example, the first control transistor M1 may be connected to the Q node Q of the lowest first stage ST1b of the first stage group STG1, and the first control transistor M1 is turned on according to the Q node Q voltage. The first control transistor M1 may transfer the voltage of the Q node Q to the first node N1 .

The gate electrode of the second control transistor M2 is connected to the first node N1 . The first electrode of the second control transistor M2 is connected to the enable line EN. A second electrode of the second control transistor M2 is connected to a second node N2 that is an output terminal of the start control circuit STC. When the second control transistor M2 is turned on, the enable signal may be transmitted from the enable line EN to the second node N2 , and the enable signal transmitted to the second node N2 may be It may be output to the second start wiring VSTb connected to the node N2. That is, the enable signal may function as a second start signal for controlling the driving of the uppermost second stage ST2a of the second stage group STG2.

The third control transistor M3 has a gate electrode connected to the reset line RS. A first electrode of the third control transistor M3 is connected to the gate high wiring VGH, and a second electrode of the third control transistor M3 is connected to the first node N1 . When the third control transistor M3 is turned on by the reset signal from the reset line RS, the first node N1 may be initialized with the gate high signal of the gate high line VGH.

The fourth control transistor M4 has a gate electrode connected to the reset line RS. A first electrode of the fourth control transistor M4 is connected to the gate high wiring VGH, and a second electrode of the fourth control transistor M4 is connected to the second node N2 . When the fourth control transistor M4 is turned on by a reset signal from the reset line RS, the second node N2 may be initialized with a gate high signal.

Referring also to FIG. 8 , a low-level signal may be charged to the Q node Q of the first stage ST1b at the lowest end of the first stage group STG1 at time a. In addition, as the low-level signal is charged in the Q node Q, the n-1 th scan signal SCAN may be output from the first stage ST1b at the lowermost stage of the first stage group STG1.

In addition, the Q node Q of the lowermost first stage ST1b of the first stage group STG1 is electrically connected to the first control transistor M1 of the start control circuit STC, and the voltage of the Q node Q It may be transmitted to the first control transistor M1 of the start control circuit STC.

In this case, the voltage of the Q node Q may be at a high level again from a point b when the output of the scan signal SCAN of the lowest first stage ST1b is finished. Meanwhile, in FIG. 8 , it is illustrated that the voltage of the Q node Q is at the same low level from time a to time b for convenience of explanation, but the voltage waveform of the Q node Q is configured as shown in FIG. 6 . may, but is not limited thereto.

At a point in time a, the first control transistor M1 may be turned on by applying the voltage of the low-level Q node Q to the gate electrode, and may apply the low-level Q node Q voltage to the first node N1. can transmit

In addition, the second control transistor M2 may be turned on by the low-level Q node Q voltage stored in the first node N1 . The second control transistor M2 continues by the voltage of the Q node Q of the first node N1 until the touch sensing period TT is terminated even after the point b when the voltage of the Q node Q becomes high level. It can remain turned on.

Meanwhile, when the low-level Q node Q is transferred to the first control transistor M1 , a low-level to high-level reset signal may be applied to the reset wiring RS. Accordingly, the third control transistor M3 and the fourth control transistor M4 connected to the first node N1 are turned off, so that the gate high signal is not transmitted to the first node N1 and the second node N2. It may not be possible, and only the Q node Q voltage may be stored in the first node N1 .

Subsequently, a low-level enable signal may be applied to the enable line EN to restart the display period DT at time c. The low-level enable signal may be transferred to the second node N2 through the second control transistor M2 that maintains a turned-on state by the voltage of the Q node Q of the first node N1 . Accordingly, the low-level enable signal transmitted to the second node N2 may function as a second start signal, and is transmitted to the uppermost second stage ST2a of the second stage group STG2 and the uppermost second stage The operation of (ST2a) can be controlled.

Subsequently, a second start signal is output to the second uppermost stage ST2a at a time point c, and the second uppermost stage ST2a at a time point d receives the second start signal and outputs an Nth scan signal SCAN(n). can do.

Next, a low-level reset signal is applied to the reset line RS at a time point e after the N-th scan signal SCAN(n) is output. When a low-level reset signal is applied to the reset line RS, the third control transistor M3 and the fourth control transistor M4 may be turned on. In addition, the turned-on third control transistor M3 may transmit a gate high signal to the first node N1 , and the turned-on fourth control transistor M4 may transmit a gate high signal to the second node N2 . have. Accordingly, the voltages of the first node N1 and the second node N2 may be initialized to a gate high signal.

Referring to FIG. 9 , the plurality of start control circuits STC disposed between each of the plurality of stage groups STG are connected to the same enable line EN and the reset line RS, but a low-level Q node The second start signal may be generated only when the (Q) voltage is applied to the first control transistor M1 .

If the low level signal is not charged to the Q node Q in the lowest stage ST connected to the start control circuit STC and the scan signal SCAN is not output, the first control transistor M1 Only a high level voltage can be transmitted. Accordingly, the P-type first control transistor M1 may continuously maintain a turned-off state, and a low-level signal may not be transmitted to the first node N1 . Also, even when a low-level enable signal is applied to the enable line EN, if the low-level Q node Q voltage is not transmitted to the first node N1, the second control transistor M2 is turned on. and the low level enable signal cannot be transmitted to the second node N2 and the second start line VSTb. Accordingly, only the start control circuit STC connected to the lowest stage ST that has output the scan signal SCAN among the plurality of start control circuits STC may output the second start signal in the next display period DT.

In the display device 100 according to an embodiment of the present invention, the start control circuit STC is disposed between each of the plurality of stage groups STG to independently control the operation timing of the plurality of stage groups STG. can Each of the plurality of stage groups STG may be driven to correspond to each of the plurality of display periods DT, and driving may be temporarily stopped during the touch sensing period TT. At this time, due to the characteristics of the stage ST operating by receiving the output of the previous stage ST, the gate driver GD, which has been stopped in the touch sensing period TT, is separately driven in the display period DT. A start signal of may be required. However, when a plurality of start wirings corresponding to each of the plurality of stage groups STG are provided, the number of wirings increases to increase the bezel size, which may lead to an increase in manufacturing cost. Accordingly, the voltage of the Q node Q from the lowest stage ST is temporarily stored between each of the plurality of stage groups STG, and then returned to the highest stage ST of the next stage group STG in the display period DT. By arranging the start control circuit STC for outputting the second start signal, the number of start wirings can be reduced. For example, the start control circuit STC disposed between the first stage group STG1 and the second stage group STG2 applies the voltage of the Q node Q of the lowest first stage ST1b to the first node N1 . . 2 It can be applied with the start wiring (VSTb). Accordingly, the uppermost second stage ST2a may receive the enable signal as the second start signal to start the operation. Accordingly, in the display device 100 according to an embodiment of the present invention, the Q node Q voltage of the previous stage ST is stored during the touch sensing period TT, and based on the stored Q node Q voltage, By disposing a start control circuit STC that outputs a new second start signal in the next display period DT, the number of wires may be reduced, and a bezel size may be reduced.

10 is a circuit diagram of a start control circuit of a display device according to another exemplary embodiment. Compared to the display device 100 of FIGS. 1 to 9 , in the display device 1000 of FIG. 10 , the start control circuit STC further includes a first control capacitor C1 and a second control capacitor C2 . Except for, other configurations are substantially the same, and thus a redundant description will be omitted.

Referring to FIG. 10 , the first control capacitor C1 is connected between the first node N1 and the gate high wiring VGH. The first control capacitor C1 may stably maintain the voltage of the first node N1 . The first control capacitor C1 may stably maintain the voltage of the Q node Q stored in the first node N1 during the touch sensing period TT.

If there is no first control capacitor C1, as the touch sensing period TT increases, it is difficult for the voltage of the first node N1 to be maintained at a low-level Q node Q voltage, even in the second start signal. Because of the influence, it may be difficult to normally output the scan signal SCAN in the next display period DT. Accordingly, the voltage of the first node N1 may be stably maintained by connecting the first control capacitor C1 to the first node N1 .

The second control capacitor C2 is connected between the gate high wiring VGH and the second electrode of the fourth control transistor M4 . That is, the second control capacitor C2 may be connected between the gate high wiring VGH and the second node N2 . The second control capacitor C2 may stably maintain the voltage of the second node N2 . The second control capacitor C2 may minimize a change in the voltage of the second node N2 under the influence of external noise or the like.

In the display device 1000 according to another embodiment of the present invention, a first control capacitor C1 and a second control capacitor C2 are added to the start control circuit STC to form a first node ( The voltages of N1) and the second node N2 may be stably maintained. As the touch sensing period TT increases, it may be difficult to constantly maintain the voltages of the first node N1 and the second node N2 of the start control circuit STC. For example, in the start control circuit STC, the voltages of the first node N1 and the second node N2 may be changed under the influence of a signal or the like from an adjacent wiring. If the voltages of the first node N1 and the second node N2 are changed, it may be difficult for the start control circuit STC to output a normal second start signal, and the scan signal SCAN is also normally output. It can be difficult. Accordingly, by connecting the first control capacitor C1 to the first node N1 and the second control capacitor C2 to the second node N2, even if the touch sensing period TT is extended, the first It is possible to minimize variations in voltages of the node N1 and the second node N2 . Accordingly, in the display device 1000 according to another exemplary embodiment of the present invention, the first control capacitor C1 and the second control capacitor C2 are connected to the first node N1 to Q during the touch sensing period TT. The node Q voltage may be stably maintained and a normal second start signal may be output.

11 is a circuit diagram of a start control circuit of a display device according to another exemplary embodiment. 12 is a waveform diagram illustrating signals input/output to a start control circuit of a display device according to another exemplary embodiment. Compared to the display device 100 of FIGS. 1 to 9 , the display device 1100 of FIGS. 11 and 12 only further includes a first control capacitor C1 and an enable bar wire ENB, and has a different configuration. Since they are substantially the same, redundant descriptions are omitted.

Referring to FIG. 11 , the start control circuit STC is connected to the enable bar wiring ENB. Specifically, the gate electrode of the fourth control transistor M4 may be connected to the enable bar wiring ENB. The signal applied to the enable bar line ENB may have a waveform opposite to that of the signal applied to the enable line EN. For example, while a high level enable signal is applied to the enable line EN, a low level enable bar signal may be applied to the enable bar line ENB. For example, a high level enable bar signal may be applied to the enable bar line ENB while a low level enable signal is applied to the enable line EN.

Referring to FIG. 12 together, a low-level enable signal may be applied to the enable line EN at a time point c, and a second start signal may be output from the start control circuit STC.

Subsequently, after the second start signal is output, a low-level reset signal is applied to the reset line RS at time e to turn on the third control transistor M3 and the enable bar line ENB The low level enable bar signal may be applied to turn on the fourth control transistor M4 . When the enable bar signal of a low level is applied to the enable bar wiring ENB, the gate high signal may be transmitted to the second node N2 by the turned-on fourth control transistor M4 . In addition, when a low-level reset signal is applied to the reset wiring RS, a gate-high signal may be transmitted to the first node N1 by the turned-on third control transistor M3 .

In the display device 1100 according to another embodiment of the present invention, the enable line EN and the enable bar respectively connect the second control transistor M2 and the fourth control transistor M4 connected to the second node N2. By connecting to the wiring ENB, the second node N2 may be prevented from being in a floating state, and the second node N2 may be maintained in a stable state. Specifically, when the low-level Q node Q voltage is stored in the first node N1 and the second control transistor M2 is turned on, the enable line EN through the second control transistor M2 is may be output to the second node N2 and the second start wiring VSTb. In addition, the enable signal for outputting the second start signal may become a high level again, and a reset signal for resetting the first node N1 may be applied. If a time difference occurs between the enable signal and the reset signal when the gate electrode of the fourth control transistor M4 is connected to the reset line RS, the second node N2 to which a separate control capacitor is not connected is floated so that the voltage can be varied. Accordingly, the fourth control transistor M4 supplying the gate high signal to the second node N2 is connected to the enable bar wiring ENB to which a signal having a waveform opposite to that of the enable wiring EN is supplied to the second node A section in which (N2) is plotted can be minimized. Accordingly, in the display device 1100 according to another embodiment of the present invention, the second control transistor M2 connected to the second node N2 is connected to the enable line EN, and the second node N2 is The connected fourth control transistor M4 is connected to the enable bar wiring ENB to prevent the second node N2 from which the second start signal is output from floating, and is connected to the second node N2 The control capacitor used can be simplified.

A gate driver and a display device including the gate driver according to embodiments of the present invention may be described as follows.

The gate driver according to an embodiment of the present invention includes a plurality of stage groups each including a plurality of stages, a lowermost stage of an Nth stage group among a plurality of stage groups, and a start connected to the uppermost stage of an N+1th stage a control circuit, and an enable line connected to the start control circuit, wherein the start control circuit stores the Q node voltage of the lowest stage of the Nth stage group.

According to another feature of the present invention, when the enable signal is applied to the enable wiring, the start control circuit may apply the start signal to the uppermost stage of the N+1th stage.

According to another feature of the present invention, the start control circuit includes a first control transistor having a gate electrode and a first electrode connected to a Q node of the lowest stage of the N-th stage group, and a second electrode connected to the first node, and A gate electrode may be connected to the first node, the second control transistor may include a second control transistor connected to an enable line, and a second electrode of the second control transistor may be connected to a second node from which a start signal is output.

According to another feature of the present invention, it further includes a reset wire and a gate high wire connected to the start control circuit, wherein the start control circuit has a third electrode connected to a first node and a gate electrode connected to the reset wire. It may further include a control transistor and a fourth control transistor having a second electrode connected to the second node, wherein the first electrode of the third control transistor and the first electrode of the fourth control transistor are connected to the gate high wiring.

According to another feature of the present invention, the gate electrode of the fourth control transistor may be connected to the reset wiring.

According to another feature of the present invention, the start control circuit may further include a first control capacitor connected between the gate high line and the first node, and a second control capacitor connected between the gate high line and the second node. .

According to still another feature of the present invention, it may further include an enable bar line connected to the gate electrode of the fourth control transistor, and the enable line and the signal applied to the enable bar line may have opposite waveforms.

According to another feature of the present invention, the start control circuit may further include a first control capacitor connected between the gate high wiring and the first node.

A display device according to an embodiment of the present invention includes a display panel including a plurality of sub-pixels, and a gate driver supplying a scan signal to each of the plurality of sub-pixels, wherein the gate driver includes a plurality of stages, respectively. a plurality of stage groups including, a start control circuit connected to a lowermost stage of an Nth stage group and an uppermost stage of an N+1th stage group among the plurality of stage groups, and an enable line connected to the start control circuit, The control circuit may store the Q node voltage of the lowest stage of the Nth stage group and apply the start signal to the highest stage of the N+1th stage group.

According to another feature of the present invention, the start control circuit includes a first control transistor that transfers a Q node voltage to a first node, and a gate electrode connected to the first node, and a second output line and a start signal. It includes a second control transistor connecting the nodes, and when a scan signal is output from the lowest stage of the Nth stage group, the second control transistor may be turned on.

According to another feature of the present invention, the start control circuit may further include a third control transistor connected between the first node and the gate high wiring, and a fourth control transistor connected between the second node and the gate high wiring. .

According to still another feature of the present invention, it further includes a reset wire connected to the gate electrode of the third control transistor and the gate electrode of the fourth control transistor, wherein when a reset signal is applied to the reset wire, the first node and the second node are It may be connected to the gate high wiring.

According to another feature of the present invention, the start control circuit may further include a first control capacitor connected between the first node and the gate high wiring, and a second control capacitor connected between the second node and the gate high wiring. .

According to still another feature of the present invention, it further includes a reset wire connected to the gate electrode of the third control transistor, and an enable bar wire connected to the gate electrode of the fourth control transistor, wherein when a reset signal is applied to the reset wire, the The first node may be connected to the gate high wiring, and when the enable bar signal is applied to the enable bar wiring, the second node may be connected to the gate high wiring.

Although embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made within the scope without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100, 1000, 1100: display device
PN: display panel
GD: gate driver
DD: data driver
TD: touch drive
TC: Timing Controller
SP: sub pixel
STG: stage group
STG1: first stage group
STG2: 2nd stage group
STG3: 3rd stage group
STG4: 4th stage group
ST: stage
ST1: first stage
ST1a: top first stage
ST1b: lowest first stage
ST2: second stage
ST2a: the top second stage
STC: start control circuit
RGB: image data
SYNC: Sync signal
GCS: gate control signal
DCS: data control signal
SCAN: scan signal
Vdata: data voltage
DT: display section
DT1: first display period
DT2: second display period
DT3: third display section
DT4: 4th display section
TT: touch sensing section
TT1: first touch sensing section
TT2: second touch sensing section
TT3: third touch sensing section
TT4: fourth touch sensing section
T1: first transistor
T2: second transistor
T3: third transistor
T4: fourth transistor
T5: fifth transistor
T6: sixth transistor
T7: 7th transistor
Tbv : Bridge Voltage Transistor
CQ: first capacitor
CB: second capacitor
Q: Q node
QB: QB Node
A: node A
M1: first control transistor
M2: second control transistor
M3: third control transistor
M4: fourth control transistor
N1: first node
N2: second node
C1: first control capacitor
C2: second control capacitor
SL: scan wiring
DL: data wiring
TL: Touch sensing wiring
VSTa: first start wiring
VSTb: second start wiring
RS: reset wiring
EN: enable wiring
ENB: enable bar wiring
VGL: gate row wiring
VGH: gate high wiring
CLK1: first clock wiring
CLK2: second clock wiring

Claims (14)

a plurality of stage groups each including a plurality of stages;
a start control circuit connected to a lowermost stage of an Nth stage group and an uppermost stage of an N+1th stage among the plurality of stage groups; and
and an enable wire connected to the start control circuit,
The start control circuit stores the Q node voltage of the lowest stage of the Nth stage group, the gate driver. According to claim 1,
The start control circuit may be configured to apply a start signal to an uppermost stage of the N+1th stage when an enable signal is applied to the enable line. 3. The method of claim 2,
The start control circuit,
a first control transistor having a gate electrode and a first electrode connected to a Q node of the lowest stage of the N-th stage group, and a second electrode connected to a first node; and
a second control transistor having a gate electrode connected to the first node and a first electrode connected to the enable line;
and a second electrode of the second control transistor is connected to a second node from which the start signal is output. 4. The method of claim 3,
Further comprising a reset wiring and a gate high wiring connected to the start control circuit,
The start control circuit,
a third control transistor having a second electrode connected to the first node and a gate electrode connected to the reset line; and
Further comprising a fourth control transistor connected to the second electrode to the second node,
The first electrode of the third control transistor and the first electrode of the fourth control transistor are connected to the gate high line. 5. The method of claim 4,
and a gate electrode of the fourth control transistor is connected to the reset line. 6. The method of claim 5,
The start control circuit,
a first control capacitor connected between the gate high line and the first node; and
and a second control capacitor connected between the gate high line and the second node. 5. The method of claim 4,
and an enable bar wiring connected to the gate electrode of the fourth control transistor,
The signal applied to the enable line and the enable bar line has opposite waveforms. 8. The method of claim 7,
The start control circuit may further include a first control capacitor connected between the gate high line and the first node. a display panel including a plurality of sub-pixels; and
a gate driver supplying a scan signal to each of the plurality of sub-pixels;
The gate driver,
a plurality of stage groups each including a plurality of stages;
a start control circuit connected to a lowermost stage of an Nth stage group and an uppermost stage of an N+1th stage group among the plurality of stage groups; and
and an enable wire connected to the start control circuit,
The start control circuit stores a Q node voltage of a lowest stage of the Nth stage group and applies a start signal to an uppermost stage of the N+1th stage group. 10. The method of claim 9,
The start control circuit,
a first control transistor transferring the Q node voltage to a first node; and
a second control transistor having a gate electrode connected to the first node and connecting the enable line and a second node outputting the start signal;
The second control transistor is turned on when the scan signal is output from the lowest stage of the Nth stage group. 11. The method of claim 10,
The start control circuit,
a third control transistor connected between the first node and a gate high line; and
and a fourth control transistor coupled between the second node and the gate high line. 12. The method of claim 11,
a reset wiring connected to the gate electrode of the third control transistor and the gate electrode of the fourth control transistor;
When a reset signal is applied to the reset line, the first node and the second node are connected to the gate high line. 13. The method of claim 12,
The start control circuit,
a first control capacitor connected between the first node and the gate high line; and
and a second control capacitor connected between the second node and the gate high line. 12. The method of claim 11,
a reset line connected to the gate electrode of the third control transistor; and
and an enable bar wiring connected to the gate electrode of the fourth control transistor,
When a reset signal is applied to the reset line, the first node is connected to the gate high line;
When an enable bar signal is applied to the enable bar line, the second node is connected to the gate high line.

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