KR20220088279A - Transistor for implementing photo-responsive neuronal device - Google Patents

Abstract

A transistor for implementing a light-responsive neuron device is disclosed. According to an embodiment, a transistor may include: a semiconductor substrate including a hole barrier region or an electron barrier region; a floating body layer extending in a horizontal direction on the hole barrier region or the electron barrier region; a source region and a drain region formed at both ends of the floating body layer; a gate insulating layer formed on the floating body layer; and a gate region formed on the gate insulating layer.

Description

Transistor for implementing light-responsive neuron devices

The following embodiments relate to a transistor implementing a neuron device responding to light, and a neuromorphic-based artificial visual perception system including the neuron device.

As an alternative to overcome the limitations of the existing Von Neumann method, which consumes a lot of energy in artificial intelligence operations, a neuromorphic computing system is receiving a lot of attention. Neuromorphic computing is a technology that implements artificial intelligence operations by imitation of the human brain in hardware. The human brain performs very complex functions, but the brain consumes only 20 W of energy. Neuromorphic computing can imitate the structure of the human brain itself and perform artificial intelligence operations such as association, reasoning, and recognition that are superior to conventional computing with ultra-low power.

Such neuromorphic computing is widely used in artificial visual perception systems to mimic biological visual perception systems to enable efficient pattern recognition, object detection, and real-time image processing. In a biological visual perception system, when a photoreceptor present in the retina receives external light, ganglion cells of the retina may be activated. Accordingly, the ganglion cell may generate an electrical spike signal that varies depending on the intensity of light, and transmit this signal to the visual cortex. Therefore, based on the signal transmitted to the visual cortex, optical image processing is started in the neural network to recognize the object. To mimic such biological visual perception systems using hardware, we need components that act as retinal neurons, such as photoreceptors and ganglion cells. However, the existing passive photodetector cannot be applied because it does not have such a function.

Instead, a system is used that combines an image sensor that detects an optical signal, a circuit that converts the optical signal into an electrical signal, and an artificial neural network that processes the transmitted signal. However, this method not only has high hardware cost, but also becomes a bottleneck in the process of converting an optical signal to an electrical signal, which may result in signal delay and additional power consumption.

Accordingly, there is a need to propose a technique for overcoming the limitations of existing techniques using an image sensor, an optical signal conversion circuit, and a processing artificial neural network.

One embodiment is to propose an artificial visual perception system including a transistor implementing a neuron device that responds to light by changing a spiking characteristic when light is incident, and the neuron device.

Accordingly, one embodiment is to propose an artificial visual perception system including a transistor and the neuron device having both a function of detecting light and a function of expressing a spike in a single device.

However, the technical problems to be solved by the exemplary embodiments are not limited to the above problems, and may be variously expanded without departing from the technical spirit and scope of the described examples.

According to an embodiment, a transistor for implementing a neuron device responding to light includes: a semiconductor substrate including a hole barrier region or an electron barrier region; a floating body layer extending in a horizontal direction on the hole barrier region or the electron barrier region; a source region and a drain region formed at both ends of the floating body layer; a gate insulating layer formed on the floating body layer; and a gate region formed on the gate insulating layer.

According to one side, the floating body layer may be characterized in that both holes generated by impact ionization and holes generated by photons incident to the floating body layer are accumulated.

According to the other side, the source region and the drain region output a spike-shaped voltage signal through an integration phenomenon and a firing phenomenon in response to a current signal being applied to the source region and the drain region. and lowering the firing threshold voltage in response to the incident of the photons to increase the spiking frequency.

According to another side, the semiconductor substrate, silicon (Si), silicon germanium (SiGe), tensile silicon (Strained Si), tensile silicon germanium (Strained SiGe), insulating layer buried silicon (Silicon-On-Insulator, SOI) , it may be characterized in that it is formed of at least one of silicon carbide (SiC) or a group 3-5 compound semiconductor.

According to another aspect, the hole barrier region or the electron barrier region may include a buried oxide, a buried n-well, a buried p-well, and a buried oxide. It may be characterized in that it is formed of at least one of buried SiC (SiC) or buried SiGe (SiGe).

According to another side, the floating body layer has any one of a planar type, a fin type, a nanowire type, and a nanosheet type, among which silicon (Si), silicon germanium ( SiGe) or group 3-5 compound semiconductor may be formed of at least one.

According to another aspect, the semiconductor substrate may be operable as a back gate.

According to another aspect, the source region and the drain region may be formed of at least one of p-type silicon, n-type silicon, and metal silicide.

According to another aspect, the source region and the drain region formed of the p-type silicon or the n-type silicon are diffusion, solid-phase diffusion, epitaxial growth, selective It may be characterized in that it is formed by at least one of epitaxial growth, ion implantation, and subsequent heat treatment.

According to another side, the metal silicide, erbium (Er), ytterbium (Yb), samarium (Sm), yttrium (Y), gadorium (Gd), terbium (Tb), cerium (Ce), platinum ( the source region including at least one of Pt), lead (Pb), iridium (Ir), nickel (Ni), titanium (Ti), tungsten (W), and cobalt (Co), and formed of the metal silicide; The drain region may be characterized by using dopant segregation for improved bonding.

According to another side, the gate insulating film is an oxide film (Silicon oxide), a nitride film (Silicon nitride), an oxynitride film (Silicon oxynitride), aluminum oxide (Aluminum oxide), hafnium oxide (Hafnium oxide), hafnium oxynitride (Hafnium Oxynitride) ), zinc oxide, zirconium oxide, polymer dielectric, or hafnium zirconium oxide (HZO).

According to another side, the gate insulating layer is, poly-silicon, amorphous silicon, metal oxide, silicon nitride, silicon oxynitride, silicon nano It may be characterized in that it comprises a charge storage layer formed of at least one of a crystalline material (Silicon nano-crystal) and metal oxide nanocrystals.

According to another aspect, the gate region may include n-type polysilicon, p-type polysilicon, titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al), molybdenum (Mo), magnesium (Mg), and chromium (Cr). ), palladium (Pd), platinum (Pt), nickel (Ni), titanium (Ti), gold (Au), tantalum (Ta), tungsten (W), silver (Ag), or at least one of tin (Sn) It may be characterized in that it is formed.

According to another aspect, the gate region is a transparent metal material including at least one of zinc oxide (ZnO), tin oxide (SnO), and indium tin oxide (TIO) in order to increase photon transmittance to the floating body layer. It may be characterized in that it is formed with

According to an embodiment, a transistor for implementing a neuron device responding to light includes: a semiconductor substrate; a source region and a drain region formed on the semiconductor substrate while being spaced apart from each other in a vertical direction; a floating body layer extending in the vertical direction between the source region and the drain region; a gate region having a gate-all-around structure surrounding the entire side surface of the floating body layer; and a gate insulating layer formed between the floating body layer and the gate region.

According to one side, the floating body layer may be characterized in that both holes generated by impact ionization and holes generated by photons incident to the floating body layer are accumulated.

According to the other side, the source region and the drain region output a spike-shaped voltage signal through an integration phenomenon and a firing phenomenon in response to a current signal being applied to the source region and the drain region. and lowering the firing threshold voltage in response to the incident of the photons to increase the spiking frequency.

According to an embodiment, the neuromorphic-based artificial visual perception system is implemented with at least one transistor including a semiconductor substrate, a source region and a drain region, a floating body layer, a gate region, and a gate insulating film. The floating body layer including one neuron device and included in the at least one transistor accumulates both holes generated by impact ionization and holes generated by photons incident to the floating body layer. characterized in that, in the source region and the drain region included in the at least one transistor, an integration phenomenon and a firing phenomenon in response to a current signal being applied to the source region and the drain region It may be characterized by outputting a voltage signal in the form of a spike through , and increasing a spiking frequency by lowering a firing threshold voltage in response to an incident of a photon.

According to one side, the neuromorphic-based artificial visual perception system, at least one synaptic element, at least one resistor, at least one capacitor, or at least one additional transistor at least one can be characterized in that it further comprises .

According to an embodiment, a transistor for implementing a neuron device responding to light includes: a semiconductor substrate including a hole barrier region or an electron barrier region; a floating body layer extending in a horizontal direction on the hole barrier region or the electron barrier region and accumulating all holes generated by incident photons; a source region and a drain region formed at both ends of the floating body layer; a gate insulating layer formed on the floating body layer; and a gate region formed on the gate insulating layer.

Embodiments may propose an artificial visual perception system including a transistor implementing a neuron device that responds to light by changing a spiking characteristic when light is incident, and the neuron device.

Accordingly, one embodiment may propose an artificial visual perception system including a transistor having both a function of detecting light and a function of expressing a spike in a single device and the neuron device.

Accordingly, some embodiments do not require additional components, unlike the existing technology using an image sensor, an optical signal conversion circuit, and a processing artificial neural network, thereby consuming a small hardware cost to achieve low cost and high integration, and It is possible to achieve the effect of removing bottlenecks such as signal delay and additional power consumption generated in the process of converting to a signal.

The exemplary embodiments are not limited to the above effects, and may be variously expanded without departing from the spirit and scope of the described examples.

1 is a view for explaining a biological visual perception system including retinal neurons.
2A is a perspective view illustrating a transistor implementing a neuron device responding to light according to an exemplary embodiment.
FIG. 2B is a side cross-sectional view illustrating a cross-section AA′ of the transistor illustrated in FIG. 2A .
3A is a perspective view illustrating a transistor implementing a neuron device responding to light according to another exemplary embodiment.
FIG. 3B is a side cross-sectional view illustrating a cross-section AA′ of the transistor illustrated in FIG. 3A .
4 is a view for explaining an operation principle of a neuron device that responds to light.
5A to 5B are graphs illustrating electrical measurement results according to light intensity actually measured from the transistors illustrated in FIGS. 3A to 3B .
6A to 6C are graphs illustrating electrical measurement results according to wavelengths of light actually measured from the transistors illustrated in FIGS. 3A to 3B.
7A to 7C are graphs illustrating electrical measurement results according to gate voltages of the transistors illustrated in FIGS. 3A to 3B .
8A to 8B are graphs illustrating simulation results of pattern recognition using the transistors illustrated in FIGS. 3A to 3B .

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or limited by the examples. Also, like reference numerals in each figure denote like members.

In addition, the terms (Terminology) used in this specification are terms used to properly express a preferred embodiment of the present invention, which may vary depending on the intention of a user or operator or customs in the field to which the present invention belongs. Accordingly, definitions of these terms should be made based on the content throughout this specification.

Hereinafter, a neuron device responding to light according to an embodiment to be described is based on a transistor. In this case, the transistor implementing the neuron device may have a horizontal transistor structure or a vertical transistor structure.

To summarize terms before describing the embodiment in detail, in general, a floating body or floating body layer is a 4-electrode (gate, source, drain, body)-based channel, unlike a channel of a 3-electrode (gate, source, drain, body). It means a channel of a transistor composed of electrodes (gate, source, drain). Typically, it can be widely used in devices on an insulating layer buried silicon (Silicon-On-Insulator, SOI) substrate. In this case, the gate existing over the channel may control the channel potential of the upper part or part of the channel exposed through the very thin gate insulating layer. However, since the lower part of the channel is adjacent to the buried oxide, it is difficult to control the potential under the channel because of the very thick buried oxide film even when a voltage is applied through the back-gate, which is an SOI substrate. Therefore, the SOI device cannot effectively control the potential under the channel, resulting in an undesirable floating body effect.

In a broader concept, a separate voltage is applied to the body even in an isolated channel of a GAA transistor in which a channel such as a nanowire or a nanosheet is surrounded by a gate-all-around (GAA). Since it cannot be applied, it can be a floating body. However, in this case, the effect of the floating body can be mitigated because the channel potential is well controlled by the gate because of the gate covering the entire surface of the channel and the very thin gate insulating film.

Unlike the horizontal transistor, the vertical transistor is formed on a bulk silicon (Bulk-Si) substrate, so it seems at first glance that there will be no floating body, but in reality, this is not the case. For example, in the case of a p-type body, the n+ source region and n+ drain region arranged in a vertical direction, and in the case of an n-type body, the channel is isolated by the vertically arranged p+ source region and p+ drain region and the floating body A structure may be formed. Here, the superscript '+' means that the doping concentration is very high, about 1020 cm ^-3 . Similarly, the channel may be electrically isolated from the bulk silicon substrate by buried SiC (Buried SiC) or buried SiGe (Buried SiGe) under the vertical protrusion to form a floating body. Therefore, hereinafter, both the horizontal transistor and the vertical transistor may be expressed as having a floating body.

1 is a diagram for explaining a biological visual perception system including retinal neurons.

1 , the human retina is composed of various neurons such as photoreceptors, bipolar cells, ganglion cells, horizontal cells, and amacrine cells. can be configured. The photoreceptor receives the light signal, converts it into an electrical signal, and transmits the signal to the ganglion cell through the bipolar cell. Horizontal cells control the reactivity of photoreceptors to regulate adaptation to the external environment, while amacrine cells improve sensory perception by creating contrast differences through lateral inhibition of ganglion cells. The visual cortex, which receives the spike signal from the ganglion cell, can recognize the object through signal processing in the neural network.

Such a biological visual perception system may be imitated as a transistor-based artificial visual perception system that implements a neuron device responding to light, which will be described later. A detailed description thereof will be provided below.

FIG. 2A is a perspective view illustrating a transistor implementing a neuron device responding to light according to an exemplary embodiment, and FIG. 2B is a side cross-sectional view illustrating a cross-section A-A′ of the transistor shown in FIG. 2A.

2A to 2B , the horizontal transistor 200 according to an exemplary embodiment is a device that implements a neuron device responding to light. Hereinafter, the horizontal transistor 200 may mean a neuron device. Also, hereinafter, the horizontal transistor 200 may be referred to as a transistor 200 for convenience.

The transistor 200 may include a semiconductor substrate 210 , a floating body layer 220 , a source region 230 and a drain region 240 , a gate insulating layer 250 , and a gate region 260 . have.

The semiconductor substrate 210 is silicon (Si), silicon germanium (SiGe), tensile silicon (Strained Si), tensile silicon germanium (Strained SiGe), insulating layer buried silicon (Silicon-On-Insulator, SOI), silicon carbide ( SiC) or at least one of a group 3-5 compound semiconductor.

The semiconductor substrate 210 may operate as a back gate to which a voltage bias is applied, and may be configured to include a hole barrier region (or electron barrier region) 211 .

Here, the hole barrier region (or electron barrier region) 211 is a buried oxide, a buried n-well in the case of a p-type body, and an n-type body. In this case, it may be formed of at least one of a buried p-well, a buried SiC (Buried SiC), or a buried SiGe (Buried SiGe).

The floating body layer 220 may be formed on the hole barrier region (or electron barrier region) 211 using at least one of silicon (Si), silicon germanium (SiGe), or a group III-V compound semiconductor.

In particular, the floating body layer 220 accumulates both holes generated by impact ionization and holes generated by photons included in light incident to the floating body layer 220, thereby forming the transistor 200 . It is possible to enable the spiking operation of neurons in

At this time, the floating body layer 220 may have any one structure of a planar type, a fin type, a nanowire type, or a nanosheet type, and the transistor 200 is a horizontal type transistor. It may be formed to extend in the horizontal direction in consideration. However, the present invention is not limited thereto, and the floating body layer 220 may be formed to extend in a vertical direction. A detailed description thereof will be described with reference to FIGS. 3A to 3B.

The source region 230 and the drain region 240 may be formed at both ends of the floating body layer 220 using at least one of p-type silicon, n-type silicon, and metal silicide.

For example, the source region 230 and the drain region 240 may be formed of p-type silicon or n-type silicon. In this case, the source region 230 and the drain region 240 are formed of the floating body layer 220 . It can have a type opposite to the ion type. As a more specific example, when the floating body layer 220 is p-type, the source region 230 and the drain region 240 may be n-type, and when the floating body layer 220 is n-type, the source region 230 and the drain. Region 240 may be p-type.

In addition, when the source region 230 and the drain region 240 are formed of p-type silicon or n-type silicon, the source region 230 and the drain region 240 perform diffusion and solid-phase diffusion. ), epitaxial growth, selective epitaxial growth, ion implantation, or subsequent heat treatment.

For another example, the source region 230 and the drain region 240 may include erbium (Er), ytterbium (Yb), samarium (Sm), yttrium (Y), gadorium (Gd), terbium (Tb), and cerium. (Ce), platinum (Pt), lead (Pb), iridium (Ir), nickel (Ni), titanium (Ti), tungsten (W), to be formed of a metal silicide containing at least one of cobalt (Co) In this case, the source region 230 and the drain region 240 formed of metal silicide may use dopant segregation for improved bonding, and the transistor 200 is a dopant segregation Schottky barrier transistor. can be

The source region 230 and the drain region 240 , in response to a current signal being applied to the source region 230 and the drain region 240 , an integration phenomenon and ignition in the floating body layer 220 . Through the (Firing) phenomenon, it is possible to output a voltage signal in the form of a spike.

In particular, the source region 230 and the drain region 240 lower the firing threshold voltage in the floating body layer 220 in response to the incident of photons into the floating body layer 220 to increase the spiking frequency. can increase A detailed description thereof will be described with reference to FIG. 4 below.

The gate insulating layer 250 is a component that insulates the floating body layer 220 and the gate region 260 , and includes a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer on the floating body layer 220 . oxynitride, aluminum oxide, hafnium oxide, hafnium oxynitride, zinc oxide, zirconium oxide, polymer dielectric or hafnium zirconium oxide HZO) may be formed of at least one of.

In addition, the gate insulating layer 250 is made of poly-silicon, amorphous silicon, metal oxide, silicon nitride, silicon oxynitride, or a silicon nanocrystal material ( Silicon nano-crystal) or a charge storage layer formed of at least one of metal oxide nanocrystals may be included.

The gate region 260 is formed on the gate insulating layer 250 on n-type polysilicon, p-type polysilicon, titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al), molybdenum (Mo), magnesium (Mg), Among chromium (Cr), palladium (Pd), platinum (Pt), nickel (Ni), titanium (Ti), gold (Au), tantalum (Ta), tungsten (W), silver (Ag) or tin (Sn) At least one may be formed.

On the other hand, the gate region 260 is made of a transparent metal material including at least one of zinc oxide (ZnO), tin oxide (SnO), and indium tin oxide (TIO) in order to increase photon transmittance to the floating body layer 220 . can also be formed.

Also, the gate region 260 may have at least one structure selected from a double-gate, a tri-gate, an omega-gate, and a multiple-gate structure.

The gate region 260 and the gate insulating layer 250 may not be required when the doping concentration of the floating body layer 220 is a predetermined value (eg, 5*10 ¹⁷ cm ^-3 ) or more. In this case, the transistor 200 may have a structure of a two-terminal npn gateless transistor or a pnp gateless transistor.

FIG. 3A is a perspective view illustrating a transistor implementing a neuron device responding to light according to another exemplary embodiment, and FIG. 3B is a side cross-sectional view illustrating a cross-section A-A′ of the transistor shown in FIG. 3A.

Referring to FIGS. 3A to 3B , a vertical transistor 300 according to another exemplary embodiment is a device that implements a light-responsive neuron device. Hereinafter, the vertical transistor 300 may mean a neuron device. Also, hereinafter, the vertical transistor 300 may be referred to as a transistor 300 for convenience.

The transistor 300 may include a semiconductor substrate 310 , a source region 320 and a drain region 330 , a floating body layer 340 , a gate region 350 , and a gate insulating layer 360 . have.

The semiconductor substrate 310 is, silicon (Si), silicon germanium (SiGe), tensile silicon (Strained Si), tensile silicon germanium (Strained SiGe), insulating layer buried silicon (Silicon-On-Insulator, SOI), silicon carbide ( SiC) or at least one of a group 3-5 compound semiconductor.

The semiconductor substrate 310 may operate as a back gate to which a voltage bias is applied, and may be configured not to include a hole barrier region (or an electron barrier region).

This is because the gate region 350, which will be described later, has a gate-all-around (GAA) structure surrounding the entire side surface of the floating body layer 340 , so that bombardment ionization or photons in the floating body layer 340 . This is because the holes created by the can be trapped without a hole barrier.

The source region 320 and the drain region 330 may be formed of at least one of p-type silicon, n-type silicon, and metal silicide on the semiconductor substrate 310 while being vertically spaced apart from each other.

For example, the source region 320 and the drain region 330 may be formed of p-type silicon or n-type silicon. In this case, the source region 320 and the drain region 330 are formed of the floating body layer 340 . It can have a type opposite to the ion type. As a more specific example, when the floating body layer 340 is p-type, the source region 320 and the drain region 330 may be n-type, and when the floating body layer 340 is n-type, the source region 320 and the drain region. Region 330 may be p-type.

In addition, when the source region 320 and the drain region 330 are formed of p-type silicon or n-type silicon, the source region 320 and the drain region 330 are formed by diffusion and solid-phase diffusion. ), epitaxial growth, selective epitaxial growth, ion implantation, or subsequent heat treatment.

For another example, the source region 320 and the drain region 330 may include erbium (Er), ytterbium (Yb), samarium (Sm), yttrium (Y), gadorium (Gd), terbium (Tb), and cerium. (Ce), platinum (Pt), lead (Pb), iridium (Ir), nickel (Ni), titanium (Ti), tungsten (W), to be formed of a metal silicide containing at least one of cobalt (Co) In this case, the source region 320 and the drain region 330 formed of metal silicide may use dopant segregation for improved bonding, and the transistor 300 is a dopant segregation Schottky barrier transistor. can be

The source region 320 and the drain region 330 , in response to a current signal being applied to the source region 320 and the drain region 330 , an integration phenomenon and ignition in the floating body layer 340 . Through the (Firing) phenomenon, it is possible to output a voltage signal in the form of a spike.

In particular, the source region 320 and the drain region 330 lower the firing threshold voltage in the floating body layer 340 in response to photons being incident on the floating body layer 340 to increase the spiking frequency. can increase A detailed description thereof will be described with reference to FIG. 4 below.

The floating body layer 340 may be formed to extend between the source region 320 and the drain region 330 using at least one of silicon (Si), silicon germanium (SiGe), or a group III-V compound semiconductor.

In particular, the floating body layer 340 accumulates both holes generated by impact ionization and holes generated by photons included in light incident to the floating body layer 340, thereby forming the transistor 300 . It is possible to enable the spiking operation of neurons in

At this time, the floating body layer 340 may have any one of a planar type, a fin type, a nanowire type, or a nanosheet type, and the transistor 300 is a vertical type transistor. It may be formed to extend in the vertical direction in consideration.

The gate region 350 includes n-type polysilicon, p-type polysilicon, titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al), Molybdenum (Mo), magnesium (Mg), chromium (Cr), palladium (Pd), platinum (Pt), nickel (Ni), titanium (Ti), gold (Au), tantalum (Ta), tungsten (W), It may be formed of at least one of silver (Ag) or tin (Sn).

On the other hand, the gate region 350 is made of a transparent metal material including at least one of zinc oxide (ZnO), tin oxide (SnO), and indium tin oxide (TIO) in order to increase photon transmittance to the floating body layer 340 . can also be formed.

Also, the gate region 350 may have at least one structure selected from a double-gate, a tri-gate, an omega-gate, and a multiple-gate structure.

The gate insulating layer 360 is a component that insulates the floating body layer 340 and the gate region 350 , and includes a silicon oxide layer and a silicon nitride layer between the floating body layer 340 and the gate region 350 . ), silicon oxynitride, aluminum oxide, hafnium oxide, hafnium oxynitride, zinc oxide, zirconium oxide, polymer dielectric ) or hafnium zirconium oxide (HZO) may be formed of at least one of.

In addition, the gate insulating layer 360 is made of poly-silicon, amorphous silicon, metal oxide, silicon nitride, silicon oxynitride, or a silicon nanocrystal material ( Silicon nano-crystal) or a charge storage layer formed of at least one of metal oxide nanocrystals may be included.

The gate region 350 and the gate insulating layer 360 may not be required when the doping concentration of the floating body layer 340 is equal to or greater than a predetermined value (eg, 5*10 ¹⁷ cm ^-3 ). In this case, the transistor 200 may have a structure of a two-terminal npn gateless transistor or a pnp gateless transistor.

The horizontal transistor 200 and the vertical transistor 300 described above are included in the neuromorphic-based artificial visual perception system, so that the artificial visual perception system can imitate a biological visual perception system. In this case, the artificial visual perception system is not limited to including at least one or more of the aforementioned horizontal transistor 200 or vertical transistor 300, but at least one synaptic element, at least one resistor, at least one capacitor or At least one of at least one additional transistor (a different transistor distinct from the horizontal transistor 200 or the vertical transistor 300) may be further included.

4 is a view for explaining an operation principle of a neuron device that responds to light.

Referring to FIG. 4, when a current signal is applied to a source region or a drain region in a transistor implementing the light-responsive neuron device described with reference to FIGS. 2A to 2B or 3A to 3B, charge is accumulated. ) may occur. Thereafter, when the accumulated charge exceeds a predetermined value (a value based on a firing threshold voltage (V _{T, firing} )), a firing phenomenon in which the accumulated charge escapes may occur. Due to the repetition of the integration phenomenon and the ignition phenomenon, the transistor outputs a voltage signal in the form of a spike.

Here, the principle that the accumulated electric charge is discharged in an instant is based on a single transistor latch phenomenon. More specifically, it is a phenomenon in which holes generated according to impact ionization generated by a high voltage in the source region and the drain region are accumulated over a certain level and a large current flows rapidly.

At this time, when additional holes are generated by photons in addition to impact ionization, a firing threshold voltage (VT _{, firing} ) is decreased, so that spiking may be active as the spiking frequency is increased.

Thus, the property of a biological retinal neuron in which the spiking frequency is increased in response to a photon, which is light, can be mimicked through the transistor.

5A to 5B are graphs illustrating electrical measurement results according to light intensity actually measured from the transistors illustrated in FIGS. 3A to 3B . Hereinafter, an electrical measurement result of the vertical transistor will be described, but the electrical measurement result of the horizontal transistor may also appear the same.

Referring to FIG. 5A , it can be seen that when a constant current signal is input to the transistor, a voltage in the form of a spike is output. At this time, when light is irradiated, it can be seen that the ignition threshold voltage is decreased and the spiking is active. The reason is that additional holes are created in the floating body layer by the photons, which can cause ignition at a lower voltage.

Referring to FIG. 5B , it can be seen that the spiking frequency increases as the intensity of light increases.

The experiment of FIGS. 5A to 5B was directly measured in a vertical transistor (neuron device) having a vertical nanowire diameter of 700 nm, and a gate voltage of -1V and a drain constant current of 100 nA were applied to enable the neuron operation. In addition, LED white light was used as a light source.

6A to 6C are graphs illustrating electrical measurement results according to wavelengths of light actually measured from the transistors illustrated in FIGS. 3A to 3B. Hereinafter, an electrical measurement result of the vertical transistor will be described, but the electrical measurement result of the horizontal transistor may also appear the same.

Referring to FIG. 6A , when red light (R) having a wavelength of 638 nm is irradiated to the transistor, it can be seen that the spiking is active while the ignition threshold voltage is decreased. On the other hand, referring to FIG. 6B , it can be seen that there is no change in the ignition threshold voltage and the spiking frequency when infrared (IR) having a wavelength of 1550 nm is irradiated.

The reason is that, in the case of infrared rays, since the energy is smaller than the energy band gap (1.12 eV) of silicon, holes cannot be formed.

Meanwhile, referring to FIG. 6C , it can be seen that the change in the spiking frequency is the least in blue light among red light (R), green light (G), and blue light (B). The reason is that as the wavelength decreases, energy loss increases and the penetration depth decreases.

The experiments of FIGS. 6A to 6C were also directly measured in a vertical transistor (neuron device) having a vertical nanowire diameter of 700 nm, and a gate voltage of -1V and a drain constant current of 100 nA were applied to enable the neuron operation. In addition, as a light source, a laser and a diode for irradiating light in a specific wavelength band were used.

7A to 7C are graphs illustrating electrical measurement results according to gate voltages of the transistors illustrated in FIGS. 3A to 3B . Hereinafter, an electrical measurement result of the vertical transistor will be described, but the electrical measurement result of the horizontal transistor may also appear the same.

The responsiveness of biological retinal neurons to light is influenced by the external environment. For example, when the eye is continuously exposed to a bright environment, the reactivity decreases, and when the eye is continuously exposed to a dark environment, the reactivity increases. Since these characteristics help retinal neurons to adapt to the changing external environment, a neuron device implemented as a transistor also needs a function to control the reactivity of the neuron device. This can be implemented through adjustment of the gate voltage.

As shown in FIG. 7A, when the gate voltage is -1V, the ignition threshold voltage and the spiking frequency change significantly as light is irradiated, but it can be seen that there is little change when the gate voltage is -2V as shown in FIG. 7B. Accordingly, as shown in FIG. 7C , it can be seen that the change in the spiking frequency increases as the gate voltage increases.

The reason is that when the gate voltage is low, the difference in energy barrier between the source region or the drain region and the floating body layer is large, and even if additional holes are created by photons, the effect is small.

The experiment of FIGS. 7A to 7C was also directly measured in a vertical transistor (neuron device) having a vertical nanowire diameter of 700 nm, and a drain constant current of 100 nA was applied to enable the neuron operation. In addition, LED white light was used as a light source.

8A to 8B are graphs illustrating simulation results of pattern recognition using the transistors illustrated in FIGS. 3A to 3B . Hereinafter, a simulation result using a vertical transistor will be described, but a simulation result using a horizontal transistor may also appear the same.

Referring to FIG. 8A , a neural network for identifying an 'X' pattern and an 'O' pattern in an image pattern composed of 3*3 black and white pixels was constructed. The neural network consists of 9 input layers (1 to 9) and 9*2 output layers (A, B). Each pixel represents one input neuron, with white pixels representing lighted pixels and black pixels representing unlit pixels. The SPICE circuit simulation was used to model the spiking characteristics of the neuron element that did not receive light and the spiking characteristic of the neuron element that received 1.2 mW white light. Since the synapse can be simulated as an effective resistance, it is expressed as a two-terminal resistance.

Referring to Figure 8b, when comparing the sum of the currents output from the synapses connected to each output layer, when the 'X' pattern is input, the spiking frequency of the current output from the synapses connected to the output layer A is more When a large, 'O' pattern is input, it can be seen that the spiking frequency of the current output from the synapses connected to the output layer B is larger. Therefore, image pattern recognition can be performed using the proposed light-responsive neuron element, and since an artificial visual perception system can be configured without an image sensor and a conversion circuit, an artificial visual perception system can be configured with low hardware cost. In addition, bottlenecks such as signal delay and additional power consumption occurring in the process of converting an optical signal into an electrical signal can be eliminated. Accordingly, the neuron device implemented by the described transistor can configure a highly integrated artificial visual perception system at low cost and enable mass production.

As described above, although the embodiments have been described with reference to the limited embodiments and drawings, various modifications and variations are possible from the above description by those skilled in the art. For example, the described techniques are performed in an order different from the described method, and/or the described components of the system, structure, apparatus, circuit, etc. are combined or combined in a different form than the described method, or other components Or substituted or substituted by equivalents may achieve an appropriate result.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (20)

In a transistor for implementing a neuron device that responds to light,
a semiconductor substrate including a hole barrier region or an electron barrier region;
a floating body layer extending in a horizontal direction on the hole barrier region or the electron barrier region;
a source region and a drain region formed at both ends of the floating body layer;
a gate insulating layer formed on the floating body layer; and
a gate region formed on the gate insulating layer
A transistor comprising a. According to claim 1,
The floating body layer,
A transistor characterized in that it accumulates both holes generated by impact ionization and holes generated by photons incident to the floating body layer. 3. The method of claim 2,
The source region and the drain region are
In response to a current signal being applied to the source region and the drain region, a voltage signal in the form of a spike is output through an integration phenomenon and a firing phenomenon, and a firing threshold voltage (Firing) is output in response to an incident photon. Transistor, characterized in that by lowering the threshold voltage) to increase the spiking frequency. According to claim 1,
The semiconductor substrate,
Silicon (Si), Silicon Germanium (SiGe), Tensile Silicon (Strained Si), Tensile Silicon Germanium (Strained SiGe), Silicon-On-Insulator (SOI), Silicon Carbide (SiC) or Group 3-5 A transistor formed of at least one of compound semiconductors. According to claim 1,
The hole barrier region or the electron barrier region,
At least any of buried oxide, buried n-well, buried p-well, buried SiC (Buried SiC), or buried SiGe (Buried SiGe) Transistor, characterized in that formed as one. According to claim 1,
The floating body layer,
At least any one of silicon (Si), silicon germanium (SiGe), or a group III-V compound semiconductor among those having any one of a planar type, a fin type, a nanowire type, and a nanosheet type Transistor, characterized in that formed as one. According to claim 1,
The semiconductor substrate,
Transistor, characterized in that it can operate as a back gate (Back gate). According to claim 1,
The source region and the drain region are
Transistor, characterized in that it is formed of at least one of p-type silicon, n-type silicon, and metal silicide. 9. The method of claim 8,
The source region and the drain region formed of the p-type silicon or the n-type silicon,
Diffusion, solid-phase diffusion, epitaxial growth, selective epitaxial growth, ion implantation, or subsequent heat treatment. Characteristics of a transistor. 9. The method of claim 8,
The metal silicide is
Erbium (Er), Ytterbium (Yb), Samarium (Sm), Yttrium (Y), Gadolium (Gd), Terbium (Tb), Cerium (Ce), Platinum (Pt), Lead (Pb), Iridium (Ir) ), including at least one of nickel (Ni), titanium (Ti), tungsten (W), and cobalt (Co),
The source region and the drain region formed of the metal silicide,
A transistor characterized in that it utilizes dopant segregation for improved junctions. According to claim 1,
The gate insulating film is
Silicon oxide, nitride, silicon oxynitride, aluminum oxide, hafnium oxide, hafnium oxynitride, zinc oxide, zirconium oxide (Zirconium oxide), a polymer insulating film (Polymer dielectric), or a transistor, characterized in that formed of at least one of hafnium zirconium oxide (HZO). According to claim 1,
The gate insulating film is
Poly-silicon, amorphous silicon, metal oxide, silicon nitride, silicon oxynitride, silicon nano-crystal or metal oxide A transistor comprising a charge storage layer formed of at least one of nanocrystals. According to claim 1,
The gate region is
n-type polysilicon, p-type polysilicon, titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al), molybdenum (Mo), magnesium (Mg), chromium (Cr), palladium (Pd), platinum (Pt) , nickel (Ni), titanium (Ti), gold (Au), tantalum (Ta), tungsten (W), a transistor, characterized in that formed of at least one of silver (Ag) or tin (Sn). According to claim 1,
The gate region is
and a transparent metal material including at least one of zinc oxide (ZnO), tin oxide (SnO), and indium tin oxide (TIO) in order to increase photon transmittance to the floating body layer. In a transistor for implementing a neuron device that responds to light,
semiconductor substrate;
a source region and a drain region formed on the semiconductor substrate while being spaced apart from each other in a vertical direction;
a floating body layer extending in the vertical direction between the source region and the drain region;
a gate region having a gate-all-around structure surrounding the entire side surface of the floating body layer; and
a gate insulating layer formed between the floating body layer and the gate region
A transistor comprising a. 16. The method of claim 15,
The floating body layer,
A transistor characterized in that it accumulates both holes generated by impact ionization and holes generated by photons incident to the floating body layer. 17. The method of claim 16,
The source region and the drain region are
In response to a current signal being applied to the source region and the drain region, a voltage signal in the form of a spike is output through an integration phenomenon and a firing phenomenon, and a firing threshold voltage (Firing) is output in response to an incident photon. Transistor, characterized in that by lowering the threshold voltage) to increase the spiking frequency. In the neuromorphic-based artificial visual perception system,
at least one neuron device responsive to light, implemented by at least one transistor including a semiconductor substrate, a source region and a drain region, a floating body layer, a gate region, and a gate insulating film
including,
The floating body layer included in the at least one transistor comprises:
It is characterized in that both holes generated by impact ionization and holes generated by photons incident to the floating body layer are accumulated,
The source region and the drain region included in the at least one transistor,
In response to a current signal being applied to the source region and the drain region, a voltage signal in the form of a spike is output through an integration phenomenon and a firing phenomenon, and a firing threshold voltage (Firing) is output in response to an incident photon. A neuromorphic-based artificial visual perception system, characterized in that by lowering the threshold voltage) to increase the spiking frequency. 19. The method of claim 18,
The neuromorphic-based artificial visual perception system,
Neuromorphic-based artificial visual perception system, characterized in that it further comprises at least one of at least one synaptic element, at least one resistor, at least one capacitor, or at least one additional transistor. In a transistor for implementing a neuron device that responds to light,
a semiconductor substrate including a hole barrier region or an electron barrier region;
a floating body layer extending in a horizontal direction on the hole barrier region or the electron barrier region and accumulating all holes generated by incident photons;
a source region and a drain region formed at both ends of the floating body layer;
a gate insulating layer formed on the floating body layer; and
a gate region formed on the gate insulating layer
A transistor comprising a.

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