KR20220081919A - Semiconductor package - Google Patents

Abstract

The technical idea of the present invention is a package substrate including a conductive layer; a semiconductor chip on the package substrate; a sealing layer provided on the package substrate to cover the semiconductor chip and including a first through hole; a vertical connection conductor including a portion buried in the first through hole of the sealing layer and a portion protruding from an upper surface of the sealing layer, and electrically connected to the conductive layer of the package substrate; a conductive layer extending along a sidewall of the sealing layer defining a first through hole of the sealing layer and disposed between the vertically connecting conductor and the sealing layer and between the vertical connecting conductor and the conductive layer of the package substrate connection pattern; a cover insulating layer provided on the sealing layer and in contact with the vertical connecting conductor; and a redistribution structure provided on the cover insulating layer and including a conductive wiring structure electrically connected to the vertical connection conductor.

Description

Semiconductor package {SEMICONDUCTOR PACKAGE}

The technical idea of the present invention relates to a semiconductor package.

Electronic devices are becoming smaller and lighter in accordance with the rapid development of the electronic industry and user demands. Accordingly, semiconductor packages are required to have small size and high-density input/output terminals. Recently, research and development on a semiconductor package having a fan-out structure in which an input/output terminal is formed outside a region in which a semiconductor chip is disposed and an input/output terminal and a semiconductor chip are connected through rewiring has been continuously conducted.

An object to be solved by the technical spirit of the present invention is to provide a semiconductor package and a method for manufacturing the same.

In order to solve the above problems, the technical idea of the present invention is a package substrate including a conductive layer; a semiconductor chip on the package substrate; a sealing layer provided on the package substrate to cover the semiconductor chip and including first and second through holes; a vertical connection conductor including a portion buried in the first through hole of the sealing layer and a portion protruding from an upper surface of the sealing layer, and electrically connected to the conductive layer of the package substrate; a first portion extending along a sidewall of the sealing layer defining the first through hole of the sealing layer, a second portion connected to the chip pad of the semiconductor chip through the second through hole of the sealing layer, and the a third portion extending along the top surface of the sealing layer, the first portion disposed between the vertically connecting conductor and the sealing layer and between the vertically connecting conductor and the conductive layer of the package substrate; conductive connection pattern; a cover insulating layer provided on the sealing layer and in contact with the vertical connecting conductor; and a redistribution structure provided on the cover insulating layer and including a conductive wiring structure electrically connected to the vertical connection conductor.

In exemplary embodiments, the vertical connection conductor includes a recess, and a buried insulating layer is provided in the recess of the vertical connection conductor and is in contact with the conductive wiring structure of the redistribution structure; The buried insulating layer and the cover insulating layer may include the same material.

In example embodiments, a surface of the cover insulating layer in contact with the redistribution structure, a surface of the vertical connection conductor in contact with the redistribution structure, and a surface of the buried insulating layer in contact with the redistribution structure are on the same plane as each other.

In exemplary embodiments, the upper surface of the vertically connecting conductor is characterized in that the overall flat plane.

In order to solve the above problems, the technical idea of the present invention is a package substrate including a conductive layer; a semiconductor chip on the package substrate; a via frame provided on the package substrate and including a frame body having a cavity in which the semiconductor chip is accommodated and a vertical connecting conductor passing through the frame body; a sealing layer filling the cavity of the frame body; a redistribution structure provided on the sealing layer and including a conductive wiring structure electrically connected to the vertical connection conductor and a chip pad of the semiconductor chip; and a conductive connection pillar disposed on the chip pad of the semiconductor chip and configured to electrically connect between the chip pad of the semiconductor chip and the conductive wiring structure of the redistribution structure; is, a lower part having a horizontal width gradually increasing in a direction away from the package substrate; and an upper portion whose horizontal width gradually increases in a direction away from the package substrate, wherein an upper surface of the conductive connection pillar, an upper surface of the sealing layer, and an upper surface of the via frame are on the same plane. .

In order to solve the above problems, the technical idea of the present invention is a package substrate including a conductive layer; a semiconductor chip on the package substrate; a conductive connection pillar disposed on a chip pad of the semiconductor chip; a sealing layer provided on the package substrate to cover the semiconductor chip; a vertical connection conductor passing through the sealing layer and connected to the conductive layer of the package substrate; a redistribution structure provided on the sealing layer and including a conductive wiring structure electrically connected to the vertical connection conductor and the conductive connection pillar; and a conductive adhesive layer provided between the vertically connecting conductor and the conductive layer of the package substrate, wherein an upper surface of the sealing layer, an upper surface of the vertical connecting conductor, and an upper surface of the conductive connecting pillar are on the same plane to provide a semiconductor package.

In order to solve the above problems, the technical idea of the present invention is to mount a semiconductor chip on a package substrate including a conductive layer; a sealing layer covering the semiconductor chip and the package substrate, the sealing layer including a first through hole exposing at least a portion of the conductive layer of the package substrate and a second through hole exposing at least a portion of the chip pad of the semiconductor chip; forming; a first portion extending along a sidewall of the sealing layer defining the first through hole of the sealing layer, a second portion connected to the chip pad of the semiconductor chip through the second through hole of the sealing layer, and the forming a conductive connection pattern including a third portion extending along an upper surface of the sealing layer; a portion buried in the first through hole of the sealing layer and a portion protruding from an upper surface of the sealing layer, and electrically connected to the conductive layer of the package substrate and the chip pad of the semiconductor chip through the conductive connection pattern forming a vertical connecting conductor; forming, on the sealing layer, a cover insulating layer covering the sealing layer and in contact with the vertical connecting conductor; and forming, on the cover insulating layer, a redistribution structure including a conductive wiring structure electrically connected to the vertical connection conductor.

In example embodiments, the forming of the cover insulating layer may include: forming a preliminary insulating layer covering the sealing layer and the vertical connection conductor; and a polishing step of removing a portion of the preliminary insulating layer so that the vertical connection conductor is exposed, wherein the preliminary insulating layer remaining after the polishing step fills the concave portions of the cover insulating layer and the vertical connection conductor It is characterized in that a buried insulating layer is formed.

In exemplary embodiments, the surface of the cover insulating layer, the surface of the vertically connecting conductor, and the surface of the buried insulating layer are on the same plane as each other.

1 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention.
2A to 2G are cross-sectional views illustrating a method of manufacturing the semiconductor package of FIG. 1 .
3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor package according to exemplary embodiments of the present invention.
4A to 4E are cross-sectional views illustrating a method of manufacturing the via frame illustrated in FIG. 2A .
5 is a cross-sectional view illustrating a semiconductor package according to exemplary embodiments of the present invention.
6A to 6G are cross-sectional views illustrating a method of manufacturing the semiconductor package of FIG. 5 .
7A to 7C are cross-sectional views illustrating a method of manufacturing a semiconductor package according to exemplary embodiments of the present invention.
8 is a cross-sectional view illustrating a semiconductor package according to exemplary embodiments of the present invention.
9 is an enlarged view showing an enlarged area indicated by "AA" of FIG.
10A to 10H are cross-sectional views illustrating a method of manufacturing the semiconductor package of FIG. 8 .
11A and 11B are cross-sectional views illustrating a method of manufacturing a semiconductor package according to exemplary embodiments of the present invention.

Hereinafter, preferred embodiments of the present invention concept will be described in detail with reference to the accompanying drawings. However, the embodiments of the inventive concept may be modified in various other forms, and the scope of the inventive concept should not be construed as being limited by the embodiments described below. The embodiments of the inventive concept are preferably interpreted as being provided in order to more completely explain the inventive concept to those of ordinary skill in the art. The same symbols refer to the same elements from time to time. Furthermore, various elements and regions in the drawings are schematically drawn. Accordingly, the inventive concept is not limited by the relative size or spacing drawn in the accompanying drawings.

Terms such as first, second, etc. may be used to describe various elements, but the elements are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the inventive concept, a first component may be referred to as a second component, and conversely, the second component may be referred to as a first component.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the inventive concept. The singular expression includes the plural expression unless the context clearly dictates otherwise. In the present application, expressions such as "comprises" or "have" are intended to designate that a feature, number, step, operation, component, part, or combination thereof described in the specification is present, but one or more other features or It should be understood that the existence or addition of numbers, operations, components, parts or combinations thereof is not precluded in advance.

Unless defined otherwise, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept belongs, including technical and scientific terms. In addition, commonly used terms as defined in the dictionary should be construed as having a meaning consistent with their meaning in the context of the relevant technology, and unless explicitly defined herein, in an overly formal sense. It will be understood that they shall not be construed.

1 is a cross-sectional view showing a semiconductor package 100 according to exemplary embodiments of the present invention.

Referring to FIG. 1 , a semiconductor package 100 may include a package substrate 110 , a semiconductor chip 120 , a via frame 130 , a sealing layer 151 , and a redistribution structure 140 . The semiconductor package 100 may be, for example, a semiconductor package having a fan-out structure.

The package substrate 110 may be a mounting substrate on which the semiconductor chip 120 is mounted. The package substrate 110 includes a redistribution board formed through a redistribution process, a printed circuit board (PCB), a metal core PCB (MCPCB), a metal PCB (MPCB), and a flexible PCB (FPCB). It may correspond to either one. Hereinafter, the package substrate 110 will be described as a redistribution substrate.

In example embodiments, the package substrate 110 may include a plurality of first wiring insulating layers 111 and a first conductive wiring structure 113 .

The plurality of first wiring insulating layers 111 may be stacked on each other in a vertical direction (eg, a Z direction). For example, the plurality of first wiring insulating layers 111 may be formed of an insulating polymer, epoxy, or a combination thereof.

The first conductive wiring structure 113 includes first conductive layers 1131 extending along any one of the top and bottom surfaces of each of the plurality of first wiring insulating layers 111 , and a plurality of first wiring insulating layers. It may include first conductive via patterns 1133 extending in a vertical direction (eg, a Z direction) through at least one layer of 111 . The first conductive layers 1131 may be disposed at different vertical levels to form a multilayer structure. Each of the first conductive layers 1131 may include a line pattern extending in the form of a line on one of the upper and lower surfaces of each of the plurality of first wiring insulating layers 111 . The first conductive via patterns 1133 may electrically connect between the first conductive layers 1131 disposed at different vertical levels. For example, first conductive layers 1131 are disposed on a lower surface of each of the plurality of first wiring insulating layers 111 , and first conductive layers 1131 are disposed between the first conductive layers 1131 disposed at different vertical levels. They may be electrically connected by via patterns 1133 . The first conductive layer 1131 extending along the lower surface of the lowermost first wiring insulating layer 111 among the plurality of first wiring insulating layers 111 is exposed to the outside and constitutes a pad for connection with an external device. can do.

The first conductive wiring structure 113 may include tungsten (W), copper (Cu), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), ruthenium (Ru), palladium (Pd), It may be made of platinum (Pt), cobalt (Co), nickel (Ni), or a combination thereof. The material of the second conductive wiring structure 143 of the redistribution structure 140 to be described later may also be substantially the same as or similar to the material of the first conductive wiring structure 113 .

The semiconductor chip 120 may be disposed on the package substrate 110 . The semiconductor chip 120 may include upper and lower surfaces opposite to each other. A chip pad 121 may be provided on an upper surface of the semiconductor chip 120 , and a lower surface of the semiconductor chip 120 may face the package substrate 110 . The semiconductor chip 120 may be attached to the package substrate 110 substrate by an adhesive film 153 provided between the lower surface of the semiconductor chip 120 and the package substrate 110 . The adhesive film 153 may include, for example, a die attach film.

In example embodiments, the semiconductor chip 120 may be a memory chip. The memory chip is, for example, a volatile memory chip such as dynamic random access memory (DRAM) or static random access memory (SRAM), phase-change random access memory (PRAM), magnetic random access memory (MRAM), FeRAM (FeRAM) It may be a non-volatile memory chip such as ferroelectric random access memory (RRAM) or resistive random access memory (RRAM).

In example embodiments, the semiconductor chip 120 may be a logic chip. For example, the semiconductor chip 120 may be a central processor unit (CPU), a micro processor unit (MPU), a graphic processor unit (GPU), or an application processor (AP).

1 illustrates that one semiconductor chip 120 is disposed on the package substrate 110 , a plurality of semiconductor chips 120 may be disposed on the package substrate 110 . For example, a plurality of semiconductor chips 120 spaced apart in a horizontal direction may be disposed on the package substrate 110 . The two or more semiconductor chips 120 included in the semiconductor package 100 may be semiconductor chips of the same type or different types of semiconductor chips. In example embodiments, the semiconductor package 100 may be a system in package in which different types of semiconductor chips and various electronic components are electrically connected to each other to operate as one system.

The via frame 130 may be disposed on the package substrate 110 . The via frame 130 may be spaced apart from the sidewall of the semiconductor chip 120 so that a space is formed between the via frame 130 and the semiconductor chip 120 . The via frame 130 may include a frame body 131 and a vertical connection conductor 133 .

The frame body 131 may include an insulating material. For example, the frame body 131 may include ceramic, plastic, polymer, glass, or the like. For example, the frame body 131 may include an epoxy molding compound (EMC).

The vertical connection conductor 133 may pass through the frame body 131 . A lower surface of the vertical connection conductor 133 is connected to the first conductive wiring structure 113 of the package substrate 110 , and an upper surface of the vertical connection conductor 133 is a second conductive wiring structure of the redistribution structure 140 . (143) can be connected. The vertical connection conductor 133 may electrically connect between the first conductive wiring structure 113 of the package substrate 110 and the second conductive wiring structure 143 of the redistribution structure 140 . For example, the vertical connection conductor 133 may include copper (Cu), aluminum (Al), solder, tin (Sn), zinc (Zn), lead (Pb), silver (Ag), gold (Au), and palladium. (Pd) and/or doped polysilicon.

In exemplary embodiments, the horizontal width of the vertically connecting conductor 133 may be maximum at an intermediate portion between the bottom and the top of the vertical connecting conductor 133 . For example, the lower portion 1331 of the vertical connection conductor 133 has a shape in which the horizontal width gradually increases as it moves away from the package substrate 110 , and the upper portion 1333 of the vertical connection conductor 133 is formed on the package substrate. The horizontal width gradually decreases as the distance from 110 is increased, and at the boundary where the lower portion 1331 of the vertical connection conductor 133 and the upper portion 1333 of the vertical connection conductor 133 come into contact with each other, the vertical connection conductor ( 133) may have a maximum horizontal width. In example embodiments, when viewed from the cross-section of the semiconductor package 100 , the cross-section of the vertically connecting conductor 133 may be hexagonal.

In example embodiments, the via frame 130 may include a cavity 135 accommodating the semiconductor chip 120 , and the via frame 130 has a ring shape surrounding the semiconductor chip 120 in a plan view. can have The cavity 135 of the via frame 130 may be defined by a sidewall of the frame body 131 facing the sidewall of the semiconductor chip 120 . The cavity 135 may penetrate the frame body 131 in a vertical direction (eg, a Z direction).

The sealing layer 151 is disposed on the package substrate 110 and may contact the semiconductor chip 120 and the via frame 130 . The sealing layer 151 may be formed to fill the cavity 135 of the via frame 130 to fill a gap between the sidewall of the semiconductor chip 120 and the via frame 130 . Also, the sealing layer 151 may cover sidewalls and an upper surface of the semiconductor chip 120 . In example embodiments, the upper surface 1511 of the sealing layer 151 may be on the same plane as the upper surface 130U of the via frame 130 . In example embodiments, the sealing layer 151 may be formed of EMC. In other exemplary embodiments, the sealing layer 151 may include a photosensitive material such as polyimide (PI) or polybenzoxazole (PBO).

The redistribution structure 140 may be disposed on the via frame 130 and the sealing layer 151 . The redistribution structure 140 may include a plurality of second wiring insulating layers 141 and a second conductive wiring structure 143 .

The plurality of second wiring insulating layers 141 are provided on the upper surface 1511 of the sealing layer 151 and may be stacked on each other in a vertical direction (eg, Z direction). The plurality of second wiring insulating layers 141 may be formed of an insulating polymer, epoxy, or a combination thereof.

The second conductive wiring structure 143 includes a second conductive layer 1431 extending along one of the upper and lower surfaces of each of the plurality of second wiring insulating layers 141 , and a plurality of second wiring insulating layers ( A second conductive via pattern 1433 extending in a vertical direction (eg, a Z-direction) through at least one layer of 141 may be included. The second conductive layers 1431 may be disposed at different vertical levels to form a multilayer structure. Each of the second conductive layers 1431 may include a line pattern extending in the form of a line on one of the top and bottom surfaces of each of the plurality of second wiring insulating layers 141 . The second conductive via patterns 1433 may electrically connect between the second conductive layers 1431 disposed at different vertical levels. For example, second conductive layers 1431 are disposed on an upper surface of each of the plurality of second wiring insulating layers 141 , and second conductive layers 1431 are disposed between the second conductive layers 1431 disposed at different vertical levels. They may be electrically connected by via patterns 1433 . The second conductive layer 1431 extending along the upper surface of the uppermost second wiring insulating layer 141 among the plurality of second wiring insulating layers 141 may constitute a bump pad to which the connection bump 190 is attached. . For example, the connecting bump 190 may be formed from a solder ball or a solder bump.

The second conductive wiring structure 143 is electrically connected to the vertical connection conductor 133 of the via frame 130 , and is electrically connected to the chip pad 121 of the semiconductor chip 120 through the conductive connection pillar 155 . can be connected The second conductive wiring structure 143 is formed between the chip pad 121 of the semiconductor chip 120 and the vertical connection conductor 133 of the via frame 130 , the chip pad 121 of the semiconductor chip 120 and the connection bump It may be configured to electrically connect between the 190 and the vertical connection conductor 133 of the via frame 130 and the connection bump 190 .

In example embodiments, a conductive connection pillar 155 may be disposed on the chip pad 121 of the semiconductor chip 120 . The second conductive wiring structure 143 may be electrically connected to the chip pad 121 of the semiconductor chip 120 through the conductive connection pillar 155 . The conductive connection pillar 155 may have a pillar shape extending in a vertical direction from the chip pad 121 of the semiconductor chip 120 , and a sidewall of the conductive connection pillar 155 may be covered with the sealing layer 151 . In example embodiments, the upper surface of the conductive connecting pillar 155 and the upper surface 1511 of the sealing layer 151 are planarized surfaces, and the upper surface of the conductive connecting pillar 155 and the upper surface 1511 of the sealing layer 151 are planarized. ) may be on the same plane. The conductive connection pillar 155 may include, for example, copper (Cu), aluminum (Al), solder, or the like.

2A to 2G are cross-sectional views illustrating a method of manufacturing the semiconductor package 100 of FIG. 1 .

Referring to FIG. 2A , a via frame 130 including a frame body 131 and a vertical connection conductor 133 is prepared. The via frame 130 has a flat plate shape or a panel shape, and may include an upper surface 130U and a lower surface 130L opposite to each other.

Referring to FIG. 2B , the package substrate 110 is formed on the lower surface 130L of the via frame 130 . For example, a redistribution process may be performed on the lower surface 130L of the via frame 130 to form the package substrate 110 . For example, in order to form the package substrate 110 , an insulating layer forming step of forming a first wiring insulating layer 111 including a via hole on the lower surface 130L of the via frame 130 , the first wiring The metal wiring process of forming the first conductive via pattern 1133 filling the via hole of the insulating layer 111 and the first conductive layer 1131 extending along the lower surface of the first wiring insulating layer 111 is repeated several times. can do.

Referring to FIG. 2C , a cavity 135 is formed in the frame body 131 by removing a portion of the frame body 131 . The cavity 135 is formed to pass through the frame body 131 , and a portion of the upper surface of the package substrate 110 may be exposed through the frame body 131 .

Referring to FIG. 2D , the semiconductor chip 120 is mounted on the package substrate 110 exposed through the cavity 135 of the frame body 131 . The semiconductor chip 120 may be fixed on the package substrate 110 by an adhesive film 153 . After the semiconductor chip 120 is disposed on the package substrate 110 , a conductive connection pillar 155 may be formed on the chip pad 121 of the semiconductor chip 120 .

Referring to FIG. 2E , a preliminary sealing layer 151p covering the semiconductor chip 120 and the via frame 130 is formed. The preliminary sealing layer 151p may be filled in the cavity 135 of the frame body 131 to cover the sidewall of the semiconductor chip 120 . Also, the preliminary encapsulation layer 151p may cover the upper surface of the semiconductor chip 120 and the conductive connection pillar 155 .

Referring to FIGS. 2E and 2F , a polishing process of removing a portion of the preliminary sealing layer 151p is performed so that the conductive connecting pillars 155 and the vertical connecting conductors 133 are exposed to the outside. Another portion of the preliminary sealing layer 151p remaining after the polishing process may form the sealing layer 151 . Through the polishing process, a portion of the conductive connecting pillar 155 and/or a portion of the via frame 130 may be removed together with a portion of the preliminary sealing layer 151p. The polishing process may include a planarization process such as chemical mechanical polishing. The polished top surface 1511 of the sealing layer 151 , the polished top surface of the conductive connecting pillar 155 , and the polished top surface 130U of the via frame 130 may be on the same plane.

Referring to FIG. 2G , the redistribution structure 140 is formed on the upper surface 1511 of the sealing layer 151 and the upper surface 130U of the via frame 130 . For example, a redistribution process may be performed on the upper surface 1511 of the sealing layer 151 and the upper surface 130U of the via frame 130 to form the redistribution structure 140 . For example, to form the redistribution structure 140 , the second wiring insulating layer 141 including a via hole on the upper surface 1511 of the sealing layer 151 and the upper surface 130U of the via frame 130 . an insulating layer forming step of forming ) may be repeated several times. After the redistribution structure 140 is formed, a connection bump 190 is formed on the redistribution structure 140 . For example, the connection bump 190 may be formed through a solder ball attach process and a reflow process.

Thereafter, a sawing process is performed for the structure of FIG. 2G. That is, the structure manufactured at the panel level may be cut along the scribe lane, and the structure manufactured at the panel level may be separated into individual units of the semiconductor packages 100 illustrated in FIG. 1 .

3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor package according to exemplary embodiments of the present invention. Hereinafter, differences from the semiconductor package described with reference to FIGS. 1 and 2A to 2G and a manufacturing method thereof will be mainly described.

Referring to FIG. 3A , the package substrate 110 is formed on the carrier substrate CA. The package substrate 110 includes a plurality of first wiring insulating layers 111 , and a first conductive wiring structure 113 including first conductive layers 1131 and first conductive via patterns 1133 . can do. The package substrate 110 may be formed through a redistribution process similar to that described above with reference to FIG. 2B .

Referring to FIG. 3B , after the package substrate 110 is formed, the via frame 130 in the form of a flat plate or a panel is disposed on the package substrate 110 . In some example embodiments, between the via frame 130 and the package substrate 110 , a physical connection between the via frame 130 and the package substrate 110 and a vertical connection conductor 133 of the via frame 130 are provided. An anisotropic conductive film or an anisotropic conductive paste for electrical connection between the first conductive wiring structure 113 of the package substrate 110 may be disposed.

Referring to FIG. 3C , a cavity 135 is formed in the frame body 131 by removing a portion of the frame body 131 . The cavity 135 is formed to pass through the frame body 131 , and the package substrate 110 may be exposed through the cavity 135 of the frame body 131 .

After the cavity 135 is formed in the frame body 131 , similarly to that described with reference to FIGS. 2D to 2G , the semiconductor chip 120 is mounted, the sealing layer 151 is formed, and the redistribution structure 140 is formed. , attaching the connection bump 190 , and sawing are sequentially performed, and then the carrier substrate CA may be removed to form a semiconductor package.

4A to 4E are cross-sectional views illustrating a method of manufacturing the via frame 130 illustrated in FIG. 2A . Hereinafter, a method of manufacturing the via frame 130 will be described with reference to FIGS. 4A to 4E together with FIG. 1 .

Referring to FIG. 4A , a conductive layer 310 is prepared. The conductive layer 310 may have a flat plate shape or a panel shape, and may include an upper surface 310U and a lower surface 310L opposite to each other. The conductive layer 310 may include a lower conductive layer 311 and an upper conductive layer 313 that are divided based on an imaginary center line or a central plane. For example, the conductive layer 310 may be copper or an alloy including copper.

4A and 4B , a patterning process may be performed on the lower conductive layer 311 . As a result of the patterning process on the lower conductive layer 311 , a lower portion 1331 of the vertically connecting conductor 133 of FIG. 1 may be formed. In example embodiments, the patterning process for the lower conductive layer 311 may include a wet etching process. Through a wet etching process performed from the lower surface 310L of the conductive layer 310 , the lower portion 1331 of the vertically connected conductor 133 is formed to have an inclined sidewall, and The lower portion 1331 may be formed to have a shape in which the horizontal width gradually increases upward.

4B and 4C , after forming the lower portion 1331 of the vertical connection conductor 133 , the sidewall of the lower portion 1331 of the vertical connection conductor 133 is formed on the lower side of the upper conductive layer 313 . A lower insulating body 1311 to cover is formed. For example, in order to form the lower insulating body 1311 , an insulating material covering the lower portion 1331 of the vertical connection conductor 133 is formed below the upper conductive layer 313 , and the vertical connection conductor 133 is formed. ) may be polished to expose the lower portion 1331 of the insulating material. For example, the lower insulating body 1311 may be formed of EMC.

4C and 4D , a patterning process may be performed on the upper conductive layer 313 . As a result of the patterning process on the upper conductive layer 313 , an upper portion 1333 of the vertically connecting conductor 133 of FIG. 1 may be formed. In example embodiments, the patterning process for the upper conductive layer 313 may include a wet etching process. Through a wet etching process performed from the upper side of the upper conductive layer 313 , the upper portion 1333 of the vertically connecting conductor 133 is formed to have an inclined sidewall, and the upper portion of the vertical connecting conductor 133 ( 1333) may be formed to have a shape in which the horizontal width gradually widens downward. The lower portion 1331 and the upper portion 1333 of the vertical connection conductor 133 may be interconnected to form the vertical connection conductor 133 .

Referring to FIG. 4E , after forming the upper portion 1333 of the vertical connecting conductor 133 , the upper insulating body covering the sidewall of the upper portion 1333 of the vertical connecting conductor 133 on the lower insulating body 1311 . (1313) is formed. For example, to form the upper insulating body 1313, an insulating material covering the upper portion 1333 of the vertical connecting conductor 133 is formed on the lower insulating body 1311, and the vertical connecting conductor 133 is formed. The insulating material may be polished to expose the upper portion 1333 of the . For example, the upper insulating body 1313 may be formed of the same material as the lower insulating body 1311 , for example, EMC. The upper insulating body 1313 and the lower insulating body 1311 may form the frame body 131 .

5 is a cross-sectional view illustrating a semiconductor package 101 according to exemplary embodiments of the present invention. Hereinafter, the semiconductor package 101 shown in FIG. 5 will be described with a focus on differences from the semiconductor package 100 described with reference to FIG. 1 .

Referring to FIG. 5 , the semiconductor package 101 may include a package substrate 210 , a semiconductor chip 120 , a sealing layer 251 , a vertical connection conductor 230 , and a redistribution structure 140 . . The semiconductor package 101 may be, for example, a semiconductor package having a fan-out structure.

The package substrate 210 may be a printed circuit board. The package substrate 210 includes, for example, a substrate insulating layer 211 including at least one material selected from phenol resin, epoxy resin, and polyimide, and an upper conductive layer 213 on the upper surface of the substrate insulating layer 211 . ) and a lower conductive layer 215 on a lower surface of the substrate insulating layer 211 . The upper conductive layer 213 and the lower conductive layer 215 may be electrically connected through an internal wiring of the package substrate 210 . The lower conductive layer 215 may constitute a pad for connection with an external device. In FIG. 5 , the package substrate 210 is exemplified as a printed circuit board, but it may have a structure corresponding to a redistribution substrate like the package substrate 210 of FIG. 1 .

The semiconductor chip 120 may be disposed on the package substrate 210 . The semiconductor chip 120 may include upper and lower surfaces opposite to each other. A chip pad 121 may be provided on an upper surface of the semiconductor chip 120 , and a lower surface of the semiconductor chip 120 may face the package substrate 210 . The semiconductor chip 120 may be attached to the package substrate 210 substrate by an adhesive film 153 provided between the lower surface of the semiconductor chip 120 and the package substrate 210 .

The sealing layer 251 is disposed on the package substrate 210 and may cover the semiconductor chip 120 . The encapsulation layer 251 may cover the top surface of the package substrate 210 , and may cover the top surface and sidewalls of the semiconductor chip 120 . Also, the sealing layer 251 may cover a sidewall of the conductive connection pillar 155 attached on the chip pad 121 of the semiconductor chip 120 . In example embodiments, the top surface 2519 of the sealing layer 251 may be on the same plane as the top surface of the conductive connection pillar 155 . In example embodiments, the sealing layer 251 may be formed of EMC. In other exemplary embodiments, the sealing layer 251 may be formed of a photosensitive material such as polyimide.

The vertical connection conductor 230 has a columnar shape extending in a vertical direction (eg, Z-direction), and may penetrate the sealing layer 251 in a vertical direction (eg, Z-direction). The lower surface of the vertical connection conductor 230 is connected to the upper conductive layer 213 of the package substrate 210 , and the upper surface of the vertical connection conductor 230 is the second conductive wiring structure 143 of the redistribution structure 140 . ) can be connected to In example embodiments, the upper surface of the vertically connecting conductor 230 may be coplanar with the upper surface 2519 of the sealing layer 251 . The vertical connection conductor 230 may electrically connect the upper conductive layer 213 of the package substrate 210 and the second conductive wiring structure 143 of the redistribution structure 140 . For example, the vertical connection conductor 230 may include copper (Cu), aluminum (Al), solder, tin (Sn), zinc (Zn), lead (Pb), silver (Ag), gold (Au), and palladium. (Pd) and/or doped polysilicon.

The redistribution structure 140 may be disposed on the sealing layer 251 . The redistribution structure 140 includes a plurality of second interconnection insulating layers 141 and a second conductive layer (eg, Z-direction) stacked on the upper surface 2519 of the sealing layer 251 in a vertical direction. 1431 ) and a second conductive wiring structure 143 including a second conductive via pattern 1433 . The second conductive wiring structure 143 may be electrically connected to the vertical connection conductor 230 and electrically connected to the chip pad 121 of the semiconductor chip 120 through the conductive connection pillar 155 . The second conductive wiring structure 143 is formed between the chip pad 121 of the semiconductor chip 120 and the vertical connection conductor 230 , between the chip pad 121 of the semiconductor chip 120 and the connection bump 190 , and It may be configured to electrically connect between the vertical connection conductor 230 and the connection bump 190 .

6A to 6G are cross-sectional views illustrating a method of manufacturing the semiconductor package 101 of FIG. 5 .

Referring to FIG. 6A , a package substrate 210 is prepared. The package substrate 210 may be a printed circuit board. After preparing the package substrate 210 , a photosensitive material layer 610 is formed on the package substrate 210 . The photosensitive material layer 610 may include an opening 611 exposing the upper conductive layer 213 of the package substrate 210 . For example, in order to form the photosensitive material layer 610, a photosensitive film is applied on the package substrate 210, and a patterning process is performed on the photosensitive film to expose the upper conductive layer 213. The steps of forming 611 may be performed sequentially.

Referring to FIG. 6B , a vertical connecting conductor 230 that at least partially fills the opening 611 of the photosensitive material layer 610 is formed. In example embodiments, the vertically connecting conductor 230 may be formed by a plating method. In other exemplary embodiments, the vertically connecting conductor 230 may be formed through a printing method or a nano-paste process using a conductive material such as copper (Cu).

6B and 6C , after the vertically connecting conductor 230 is formed, the photosensitive material layer 610 is removed. The photosensitive material layer 610 may be removed through a stripping process.

Referring to FIG. 6D , the semiconductor chip 120 is mounted on the package substrate 210 . The semiconductor chip 120 may be fixed on the package substrate 210 through the adhesive film 153 . After the semiconductor chip 120 is disposed on the package substrate 210 , a conductive connection pillar 155 may be formed on the chip pad 121 of the semiconductor chip 120 .

Referring to FIG. 6E , a preliminary sealing layer 251p covering the semiconductor chip 120 and the vertical connection conductor 230 is formed.

6E and 6F , a polishing process of removing a portion of the preliminary sealing layer 251p is performed so that the conductive connection pillars 155 and the vertical connection conductors 230 are exposed to the outside. Another portion of the preliminary sealing layer 251p remaining after the polishing process may form the sealing layer 251 . Through the polishing process, a portion of the conductive connection pillar 155 and/or a portion of the vertical connection conductor 230 may be removed together with a portion of the preliminary sealing layer 251p. The polishing process may include a planarization process such as chemical mechanical polishing. The polished top surface 2519 of the sealing layer 251 , the polished top surface of the conductive connection pillar 155 , and the polished top surface of the vertical connection conductor 230 may be coplanar with each other.

Referring to FIG. 6G , a redistribution process is performed on the sealing layer 251 to form the redistribution structure 140 . After the redistribution structure 140 is formed, a connection bump 190 may be formed on the redistribution structure 140 . Thereafter, a sawing process is performed on the structure of FIG. 6G. That is, the structure manufactured at the panel level may be cut along the scribe lane, and the structure manufactured at the panel level may be separated into individual units of the semiconductor packages 101 illustrated in FIG. 5 .

7A to 7C are cross-sectional views illustrating a method of manufacturing a semiconductor package according to exemplary embodiments of the present invention. The semiconductor package described with reference to FIGS. 7A to 7C , see FIG. 5 , except that it further includes a conductive adhesive layer 261 interposed between the vertical connection conductor 230 and the upper conductive layer 213 . It may be substantially the same as or similar to the semiconductor package 101 described above. Hereinafter, differences from the semiconductor package 101 described with reference to FIGS. 5 and 6A to 6G and a manufacturing method thereof will be mainly described.

Referring to FIG. 7A , a conductive adhesive layer 261 is formed on the upper conductive layer 213 of the package substrate 210 . The conductive adhesive layer 261 may include, for example, solder.

Referring to FIG. 7B , a vertical connection conductor 230 is disposed on the conductive adhesive layer 261 . For example, the vertically connecting conductor 230 may be attached on the conductive adhesive layer 261 using a stencil mask 620 having alignment holes.

Referring to FIG. 7C , a curing process using a laser beam 630 may be performed to fix the vertically connecting conductor 230 on the upper conductive layer 213 . As the conductive adhesive layer 261 is cured through the curing process, the vertically connecting conductor 230 may be more firmly fixed on the upper conductive layer 213 .

Thereafter, similarly to that described with reference to FIGS. 6D to 6G , the semiconductor chip 120 mounting, the sealing layer 251 formation, the redistribution structure 140 formation, the connection bump 190 attachment, and sawing steps are sequentially performed. carried out, a semiconductor package can be manufactured.

8 is a cross-sectional view illustrating a semiconductor package 102 according to exemplary embodiments of the present invention. 9 is an enlarged view showing an enlarged area indicated by "AA" of FIG. Hereinafter, the semiconductor package 102 shown in FIGS. 8 and 9 will be described with a focus on differences from the semiconductor package 101 described with reference to FIG. 5 .

8 and 9 , the semiconductor package 102 includes a package substrate 210 , a semiconductor chip 120 , a sealing layer 251 , a conductive connection pattern 270 , a vertical connection conductor 280 , and a cover insulation. layer 290 , and redistribution structure 140 . The semiconductor package 102 may be, for example, a semiconductor package having a fan-out structure.

The sealing layer 251 may cover the semiconductor chip 120 disposed on the package substrate 210 . The encapsulation layer 251 may cover the top surface of the package substrate 210 , and may cover the top surface and sidewalls of the semiconductor chip 120 . The sealing layer 251 includes a first through hole 2511 positioned to overlap the upper conductive layer 213 of the package substrate 210 in a vertical direction (eg, a Z direction), and a chip of the semiconductor chip 120 . A second through-hole 2512 positioned to overlap the pad 121 in a vertical direction (eg, a Z-direction) may be included.

The conductive connection pattern 270 conformally extends along the surface of the sealing layer 251 , and may be respectively connected to the upper conductive layer 213 of the package substrate 210 and the chip pad 121 of the semiconductor chip 120 . have. In example embodiments, the conductive connection pattern 270 is provided in the first through-hole 2511 of the sealing layer 251 to be connected to the upper conductive layer 213 , the first portion 271 and the sealing layer 251 . The second portion 273 provided in the first through-hole 2511 of the semiconductor chip 120 and connected to the chip pad 121, and the first portion extending along the upper surface 2519 of the sealing layer 251 ( A third portion 275 electrically connecting between the 271 and the second portion 273 may be included.

The first portion 271 of the conductive connection pattern 270 may conformally extend along a surface defining the first through hole 2511 of the sealing layer 251 . The first portion 271 of the conductive connection pattern 270 extends from the top to the bottom of the sidewall of the sealing layer 251 defining the first through hole 2511 of the sealing layer 251 , and the upper conductive layer 213 . ) may extend along the surface of

The second portion 273 of the conductive connection pattern 270 may conformally extend along a surface defining the second through hole 2512 of the sealing layer 251 . The second portion 273 of the conductive connection pattern 270 extends from the top to the bottom of the sidewall of the sealing layer 251 defining the second through hole 2512 of the sealing layer 251 , and the semiconductor chip 120 . may extend along the surface of the chip pad 121 of the In other exemplary embodiments, the second portion 273 of the conductive connection pattern 270 may be replaced with the conductive connection pillar 155 of FIG. 5 .

The vertical connection conductor 280 is disposed on the conductive connection pattern 270 , and is disposed in the first through hole 2511 of the sealing layer 251 to fill the first through hole 2511 of the sealing layer 251 . can The sidewall of the vertical connection conductor 280 may be spaced apart from the sealing layer 251 with the conductive connection pattern 270 interposed therebetween, and the lower surface of the vertical connection conductor 280 has the conductive connection pattern 270 interposed therebetween. and may be spaced apart from the upper conductive layer 213 of the package substrate 210 . In the first through hole 2511 of the sealing layer 251 , the vertical connection conductor 280 may be surrounded by the first portion 271 of the conductive connection pattern 270 . That is, the first portion 271 of the conductive connection pattern 270 may surround the vertical connection conductor 280 in a plan view. The vertical connection conductor 280 may be electrically connected to the upper conductive layer 213 of the package substrate 210 and the chip pad 121 of the semiconductor chip 120 through the conductive connection pattern 270 .

The vertical connection conductor 280 may include a portion buried in the first through hole 2511 of the sealing layer 251 and a protrusion 281 protruding upward from the upper surface 2519 of the sealing layer 251 . have. For example, the height at which the vertical connection conductor 280 protrudes from the upper surface 2519 of the sealing layer 251 may be between approximately 5 micrometers and 50 micrometers.

The cover insulating layer 290 may be disposed on the sealing layer 251 to cover the upper surface 2519 of the sealing layer 251 and the conductive connection pattern 270 . In addition, the cover insulating layer 290 may cover the sidewall of the vertical connection conductor 280 , but may not cover the upper surface 283 of the vertical connection conductor 280 . In example embodiments, the upper surface 291 of the cover insulating layer 290 may be on the same plane as the upper surface 283 of the vertical connection conductor 280 . In example embodiments, the cover insulating layer 290 may be formed of EMC. In other exemplary embodiments, the cover insulating layer 290 may be formed of a photosensitive material such as polyimide (PI) or polybenzoxazole (PBO).

In exemplary embodiments, the vertically connecting conductor 280 may include a recess 285 provided in its top surface 283 . A buried insulating layer 295 may be filled in the recess 285 of the vertical connection conductor 280 . The buried insulating layer 295 may be spaced apart from the cover insulating layer 290 with the vertical connecting conductor 280 interposed therebetween. In example embodiments, the upper surface of the buried insulating layer 295 in contact with the lower surface of the redistribution structure 140 and the surface (ie, the surface of the vertical connection conductor 280 in contact with the lower surface of the redistribution structure 140 ) The upper surface 291 of the cover insulating layer 290 in contact with the lower surface of the redistribution structure 140 and the upper surface 291 of the upper surface 283 of the vertical connection conductor 280 except for the concave portion 295 are coplanar with each other. may be on the In example embodiments, the buried insulating layer 295 may have the same material and/or material combination as the cover insulating layer 290 .

The redistribution structure 140 may be disposed on the cover insulating layer 290 . The redistribution structure 140 includes a plurality of second wiring insulating layers 141 and a second conductive layer stacked on the upper surface 291 of the cover insulating layer 290 in a vertical direction (eg, Z direction). A second conductive wiring structure 143 including a 1431 and a second conductive via pattern 1433 may be included. A lower surface of the second conductive via pattern 1433 in the lowermost second wiring insulating layer 141 may contact the vertical connection conductor 280 and the buried insulating layer 295 . The second conductive wiring structure 143 includes the chip pad 121 of the semiconductor chip 120 and the upper conductive layer 213 of the package substrate 210 through the vertical connection conductor 280 and the conductive connection pattern 270 . ) can be electrically connected to.

10A to 10H are cross-sectional views illustrating a method of manufacturing the semiconductor package 102 of FIG. 8 .

Referring to FIG. 10A , a package substrate 210 is prepared. The package substrate 210 may be a printed circuit board. After preparing the package substrate 210 , the semiconductor chip 120 is mounted on the package substrate 210 . The semiconductor chip 120 may be fixed on the package substrate 210 by an adhesive film 153 .

Referring to FIG. 10B , a sealing layer 251 covering the semiconductor chip 120 is formed on the package substrate 210 . The sealing layer 251 at least partially exposes the first through hole 2511 configured to at least partially expose the upper conductive layer 213 of the package substrate 210 and the chip pad 121 of the semiconductor chip 120 . It may include a second through-hole 2512 configured to allow the For example, in order to form the sealing layer 251, a photosensitive material film made of a photosensitive material such as polyimide is formed on the package substrate 210, and a patterning process is performed on the photosensitive material film to form the photosensitive material. The steps of forming the first through-hole 2511 and the second through-hole 2512 in the film may be sequentially performed.

Referring to FIG. 10C , a conductive connection pattern 270 conformally extending along the surface of the sealing layer 251 is formed. The conductive connection pattern 270 may be formed through a redistribution process. For example, the conductive connection pattern 270 may include a seed metal layer and a core metal layer formed through a plating process using the seed metal layer as a seed and stacked on the seed metal layer. The seed metal layer may include titanium (Ti), copper (Cu), chromium (Cr), tungsten (W), nickel (Ni), aluminum (Al), palladium (Pd), gold (Au), or a combination thereof. can The core metal layer may include copper (Cu) or an alloy of copper (Cu).

Referring to FIG. 10D , a mask layer 640 is formed on the sealing layer 251 . The mask layer 640 may include a mask opening 641 positioned to overlap the first through hole 2511 . The mask opening 641 of the mask layer 640 may define a region in which the vertical connection conductor 280 to be formed in a subsequent step is to be formed.

After the mask layer 640 is formed, the vertically connecting conductor 280 is formed. The vertical connection conductor 280 may be formed to fill the first through hole 2511 exposed through the mask opening 641 of the mask layer 640 and partially fill the mask opening 641 . The vertical connection conductor 280 may be formed through, for example, a plating process. For example, the vertical connection conductor 280 may include copper (Cu) or an alloy of copper (Cu).

In example embodiments, the horizontal width of the mask opening 641 of the mask layer 640 may determine the horizontal width of the protrusion ( 281 of FIG. 9 ) of the vertically connecting conductor 280 . In example embodiments, a horizontal width of the mask opening 641 of the mask layer 640 may be greater than a horizontal width of the first through hole 2511 of the sealing layer 251 . In this case, the protrusion 281 of the vertical connection conductor 280 may be formed to have a greater horizontal width than the horizontal width of the first through hole 2511 of the sealing layer 251 .

10D and 10E , after the vertically connecting conductor 280 is formed, the mask layer 640 is removed. The mask layer 640 may be removed through, for example, a strip process.

Referring to FIG. 10F , a preliminary cover insulating layer 290p covering the conductive connection pattern 270 and the vertical connection conductor 280 is formed on the sealing layer 251 .

10F and 10G , a polishing process of removing a portion of the preliminary cover insulating layer 290p is performed so that the vertical connection conductor 280 is exposed to the outside. The other portion of the preliminary cover insulating layer 290p remaining after the polishing process may form the cover insulating layer 290 and the buried insulating layer 295 . Through the polishing process, a portion of the vertical connection conductor 280 may be removed together with a portion of the preliminary cover insulating layer 290p. The polishing process may include a planarization process such as chemical mechanical polishing. The polished top surface of the cover insulating layer 290 , the polished surface of the vertically connecting conductor 280 , and the polished top surface of the buried insulating layer 295 may be coplanar with each other.

Referring to FIG. 10H , a redistribution process is performed on the cover insulating layer 290 to form the redistribution structure 140 . After the redistribution structure 140 is formed, a connection bump 190 may be formed on the redistribution structure 140 . Thereafter, a sawing process is performed for the structure of FIG. 10H. That is, the structure manufactured at the panel level may be cut along the scribe lane, and the structure manufactured at the panel level may be separated into individual units of semiconductor packages 102 illustrated in FIG. 8 .

11A and 11B are cross-sectional views illustrating a method of manufacturing a semiconductor package according to exemplary embodiments of the present invention. The semiconductor package described with reference to FIGS. 11A and 11B is shown in FIG. 8 except that the buried insulating layer 295 filling the recessed portion 285 of the vertically connecting conductor 280 of FIG. 8 is omitted. may be substantially the same as or similar to the semiconductor package 102 described above. Hereinafter, differences from the semiconductor package 102 and a manufacturing method thereof described with reference to FIGS. 8, 9, and 10A to 10H will be mainly described.

Referring to FIG. 11A , a structure corresponding to the structure of FIG. 10F is prepared, and a polishing process of removing a portion of the preliminary cover insulating layer 290p is performed. The polishing process may be performed so that the concave portion ( 285 of FIG. 9 ) of the vertical connection conductor 280 can be removed. Since the concave portion 285 of the vertical connection conductor 280 is removed, the upper surface 283 of the vertical connection conductor 280 may be an overall flat plane.

Referring to FIG. 11B , a redistribution process is performed on the cover insulating layer 290 to form the redistribution structure 140 . A lower surface of the second conductive via pattern 1433 in the lowermost second wiring insulating layer 141 may continuously contact an upper surface of the vertical connection conductor 280 . After the redistribution structure 140 is formed, the attaching and sawing steps of the connection bump 190 are sequentially performed, so that a semiconductor package may be manufactured.

Exemplary embodiments have been disclosed in the drawings and specification as described above. Although the embodiments have been described using specific terms in the present specification, these are used only for the purpose of explaining the technical spirit of the present disclosure, and not used to limit the meaning or the scope of the present disclosure described in the claims. Therefore, it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the true technical protection scope of the present disclosure should be defined by the technical spirit of the appended claims.

100: semiconductor package 110: package substrate
120: semiconductor chip 130: via frame
131: frame body 133: vertical connection conductor
140: redistribution structure

Claims (9)

a package substrate including a conductive layer;
a semiconductor chip on the package substrate;
a sealing layer provided on the package substrate to cover the semiconductor chip and including first and second through holes;
a vertical connection conductor including a portion buried in the first through hole of the sealing layer and a portion protruding from an upper surface of the sealing layer, and electrically connected to the conductive layer of the package substrate;
a first portion extending along a sidewall of the sealing layer defining the first through hole of the sealing layer, a second portion connected to the chip pad of the semiconductor chip through the second through hole of the sealing layer, and the a third portion extending along the top surface of the sealing layer, the first portion disposed between the vertically connecting conductor and the sealing layer and between the vertically connecting conductor and the conductive layer of the package substrate; conductive connection pattern;
a cover insulating layer provided on the sealing layer and in contact with the vertical connecting conductor; and
a redistribution structure provided on the cover insulating layer and including a conductive wiring structure electrically connected to the vertical connection conductor;
A semiconductor package comprising a. The method of claim 1,
the vertical connecting conductor comprises a recess,
a buried insulating layer provided in the recess of the vertical connection conductor and in contact with the conductive wiring structure of the redistribution structure;
The semiconductor package according to claim 1, wherein the buried insulating layer and the cover insulating layer include the same material. 3. The method of claim 2,
The surface of the cover insulating layer in contact with the redistribution structure, the surface of the vertical connection conductor in contact with the redistribution structure, and the surface of the buried insulating layer in contact with the redistribution structure are on the same plane. A semiconductor package, characterized in that. The method of claim 1,
The semiconductor package, characterized in that the upper surface of the vertically connecting conductor is a flat surface as a whole. a package substrate including a conductive layer;
a semiconductor chip on the package substrate;
a via frame provided on the package substrate and including a frame body having a cavity in which the semiconductor chip is accommodated and a vertical connecting conductor passing through the frame body;
a sealing layer filling the cavity of the frame body;
a redistribution structure provided on the sealing layer and including a conductive wiring structure electrically connected to the vertical connection conductor and a chip pad of the semiconductor chip; and
a conductive connection pillar disposed on the chip pad of the semiconductor chip and configured to electrically connect between the chip pad of the semiconductor chip and the conductive wiring structure of the redistribution structure;
including,
The vertical connection conductor,
a lower portion whose horizontal width gradually increases in a direction away from the package substrate; and
an upper portion whose horizontal width gradually increases in a direction away from the package substrate;
including,
A top surface of the conductive connecting pillar, a top surface of the sealing layer, and a top surface of the via frame are on the same plane. a package substrate including a conductive layer;
a semiconductor chip on the package substrate;
a conductive connection pillar disposed on a chip pad of the semiconductor chip;
a sealing layer provided on the package substrate to cover the semiconductor chip;
a vertical connection conductor passing through the sealing layer and connected to the conductive layer of the package substrate;
a redistribution structure provided on the sealing layer and including a conductive wiring structure electrically connected to the vertical connection conductor and the conductive connection pillar; and
a conductive adhesive layer provided between the vertical connection conductor and the conductive layer of the package substrate;
including,
and the upper surface of the sealing layer, the upper surface of the vertical connecting conductor, and the upper surface of the conductive connecting pillar are coplanar with each other. mounting a semiconductor chip on a package substrate including a conductive layer;
a sealing layer covering the semiconductor chip and the package substrate, the sealing layer including a first through hole exposing at least a portion of the conductive layer of the package substrate and a second through hole exposing at least a portion of the chip pad of the semiconductor chip; forming;
a first portion extending along a sidewall of the sealing layer defining the first through hole of the sealing layer, a second portion connected to the chip pad of the semiconductor chip through the second through hole of the sealing layer, and the forming a conductive connection pattern including a third portion extending along an upper surface of the sealing layer;
a portion buried in the first through hole of the sealing layer and a portion protruding from the upper surface of the sealing layer, and is electrically connected to the conductive layer of the package substrate and the chip pad of the semiconductor chip through the conductive connection pattern forming a vertical connecting conductor;
forming, on the sealing layer, a cover insulating layer covering the sealing layer and in contact with the vertical connecting conductor; and
forming a redistribution structure including a conductive wiring structure electrically connected to the vertical connection conductor on the cover insulating layer;
A method of manufacturing a semiconductor package comprising a. 8. The method of claim 7,
The step of forming the cover insulating layer,
forming a preliminary insulating layer covering the sealing layer and the vertical connecting conductor; and
a polishing step of removing a portion of the preliminary insulating layer so that the vertical connection conductor is exposed;
including,
The method of claim 1 , wherein the preliminary insulating layer remaining after the polishing step forms a buried insulating layer filling the recesses of the cover insulating layer and the vertically connecting conductor. 9. The method of claim 8,
A method for manufacturing a semiconductor package, wherein a surface of the cover insulating layer, a surface of the vertical connection conductor, and a surface of the buried insulating layer are on the same plane.

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