KR20220081831A - Printed circuit board - Google Patents

Abstract

The present disclosure includes a base substrate; a circuit layer disposed on the base substrate and including a connection pad; a solder resist layer disposed on the base substrate and having an opening exposing the connection pad; a first seed layer disposed on the exposed connection pad and the solder resist layer; a first metal post layer disposed on the first seed layer to fill the opening; a second seed layer disposed on an upper surface of the first metal post layer; and a second metal post layer disposed on the second seed layer.

Description

Printed Circuit Board {PRINTED CIRCUIT BOARD}

The present disclosure relates to a printed circuit board.

In order to respond to the recent trend of weight reduction and miniaturization of mobile devices, the need to implement lightweight, thin, and compact also increases in printed circuit boards mounted thereon.

On the other hand, for the realization of micro circuits in printed circuit boards, BGA package products are made of metal.

A fine pitch is implemented using the post structure. At this time, the height of the metal post is high and the plating area is small, so that the height deviation may increase. In order to reduce this deviation, a demand for patterning a microcircuit has emerged, and a dummy pattern is placed in the PNL dummy area to distribute the current density.

However, when the PNL dummy area is narrow, there is a limit to inserting the dummy pattern. Accordingly, since the dummy pattern cannot be freely designated or arbitrarily changed, a metal post circuit process method capable of freely changing the design of the dummy pattern is required.

One of several objects of the present disclosure is to provide a printed circuit board including a micro circuit and/or a micro via.

Another object of the present disclosure is to provide a printed circuit board into which a dummy pattern can be freely inserted.

Another object of the present disclosure is to provide a printed circuit board that forms a dummy pattern on the DFR.

A printed circuit board according to an example proposed by the present disclosure includes: a base substrate; a circuit layer disposed on the base substrate and including a connection pad; a solder resist layer disposed on the base substrate and having an opening exposing the connection pad; a first seed layer disposed on the exposed connection pad and the solder resist layer; a first metal post layer disposed on the first seed layer to fill the opening; a second seed layer disposed on an upper surface of the first metal post layer; and a second metal post layer disposed on the second seed layer, wherein the first and second seed layers each include copper.

As one effect among various effects of the present disclosure, it is possible to provide a printed circuit board including a micro circuit and/or a micro via.

As another effect among various effects of the present disclosure, it is possible to provide a printed circuit board into which a dummy pattern can be freely inserted.

As another effect among various effects of the present disclosure, it is possible to provide a printed circuit board for forming a dummy pattern on the DFR.

1 is a diagram schematically showing an example of an electronic device system.
2 is a diagram schematically illustrating an example of an electronic device.
3A to 3D are diagrams schematically illustrating an example of a printed circuit board according to the present disclosure.
4 to 15 are views schematically illustrating a manufacturing process of a printed circuit board according to the present disclosure.

Hereinafter, the present disclosure will be described with reference to the accompanying drawings. The shapes and sizes of elements in the drawings may be exaggerated or reduced for clearer description.

In addition, in adding reference numbers to the components of the accompanying drawings, only the same components are to have the same numbers as possible even though they are indicated on different drawings.

In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

Electronics

1 is a block diagram schematically showing an example of an electronic device system.

Referring to the drawings, the electronic device 1000 accommodates the main board 1010 . A chip-related component 1020 , a network-related component 1030 , and other components 1040 are physically and/or electrically connected to the main board 1010 . These are also combined with other electronic components to be described later to form various signal lines 1090 .

The chip-related component 1020 includes a memory chip such as a volatile memory (eg, DRAM), a non-volatile memory (eg, ROM), and a flash memory; application processor chips such as a central processor (eg, CPU), a graphics processor (eg, GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller; Logic chips such as analog-to-digital converters and ASICs (application-specific ICs) are included, but are not limited thereto, and of course, other types of chip-related electronic components may be included. Also, it goes without saying that these electronic components 1020 may be combined with each other. The chip-related component 1020 may be in the form of a package including the above-described chip or electronic component.

The network-related components 1030 include Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM. , GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G and any other wireless and wired protocols designated thereafter, including, but not limited to, many other wireless or wired protocols. Any of the standards or protocols may be included. Also, it goes without saying that the network-related component 1030 may be combined with the chip-related electronic component 1020 .

The other components 1040 include a high frequency inductor, a ferrite inductor, a power inductor, ferrite beads, low temperature co-firing ceramics (LTCC), an electro magnetic interference (EMI) filter, a multi-layer ceramic condenser (MLCC), and the like. . However, the present invention is not limited thereto, and in addition to this, a passive element in the form of a chip component used for various other purposes may be included. Also, it goes without saying that the other component 1040 may be combined with the chip-related electronic component 1020 and/or the network-related electronic component 1030 .

Depending on the type of the electronic device 1000 , the electronic device 1000 may include other electronic components that may or may not be physically and/or electrically connected to the main board 1010 . Examples of other electronic components include a camera module 1050 , an antenna module 1060 , a display 1070 , and a battery 1080 . However, the present invention is not limited thereto, and an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (eg, a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), etc. may be In addition to this, it goes without saying that other electronic components used for various purposes may be included depending on the type of the electronic device 1000 .

The electronic device 1000 includes a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, and a computer ( computer), monitor, tablet, laptop, netbook, television, video game, smart watch, automotive, and the like. However, the present invention is not limited thereto, and may be any other electronic device that processes data in addition to these.

2 is a perspective view schematically illustrating an example of an electronic device.

Referring to the drawings, the electronic device may be, for example, a smartphone 1100 . A main board 1110 is accommodated inside the smartphone 1100 , and various electronic components 1120 are physically and/or electrically connected to the main board 1110 . In addition, other electronic components that may or may not be physically and/or electrically connected to the main board 1110 such as the camera module 1130 and/or the speaker 1140 are accommodated therein. A part of the electronic component 1120 may be the aforementioned chip-related component, for example, the antenna module 1121, but is not limited thereto. The antenna module 1121 may be a form in which electronic components are surface mounted on a printed circuit board, but is not limited thereto. On the other hand, the electronic device is not necessarily limited to the smart phone 1100, and of course, it may be another electronic device as described above.

Printed circuit board structure and manufacturing method

3A to 3D are diagrams schematically illustrating an example of a printed circuit board according to the present disclosure.

Referring to the drawings, printed circuit boards 10A, 10B, 10C, and 10D include a base substrate 100 , a circuit layer 200 , a solder resist layer 230 , a first seed layer 300 , and a first metal post layer. 400 , a second seed layer 500 disposed on the first metal post layer 400 , and a second metal post layer 600 disposed on the second seed layer 500 .

The circuit layer 200 is disposed on the base substrate 100 , and includes a connection pad 210 , and an opening 220 exposing the connection pad 210 is formed in the solder resist layer 230 .

The first seed layer 300 is disposed on the exposed connection pad 210 and the solder resist layer 230 , and the first metal post layer 400 filling the opening 220 on the first seed layer 300 . ) is placed.

The first metal post layer 400 includes a first region 420 filling the opening 220 , and is disposed on an upper surface of the first region 420 to protrude from the solder resist layer 230 , and the first region 420 . ) may have a second region 430 having a larger diameter than that of .

The base substrate 100 may include a copper clad laminate (CCL). Types of copper clad laminates include glass/epoxy copper clad laminates, heat-resistant resin copper clad laminates, paper/phenolic copper clad laminates, high frequency copper clad laminates, flexible copper clad laminates, and composite copper clad laminates, depending on their use. The base substrate 100 according to the present disclosure may include a glass/epoxy copper clad laminate as a double-sided package substrate and a multi-layer package substrate.

The circuit layer 200 may be disposed on the base substrate 100 . The circuit layer 200 is a component for transmitting an electrical signal, and may include a circuit paddle, a via, and a connection pad. The circuit layer 200 may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Conductive materials such as these may be used.

A solder resist layer 230 may be disposed on the circuit layer 200 to prevent damage to the circuit layer 200 by soldering using solder or the like. An opening 220 may be formed in the solder resist layer 230 to expose the connection pad 210 of the circuit layer 200 to the outside.

The first seed layer 300 may be disposed on the solder resist layer 230 . The first seed layer 300 may be disposed not only on the solder resist layer 230 , but also on the inner wall of the opening 220 . The first seed layer 300 may be formed by an electroless plating method or the like, and may be formed of an electrically conductive material.

The first metal post layer 400 may be disposed on the first seed layer 300 . The first metal post layer 400 may fill the opening 220 formed on the upper portion of the connection pad 210 to transmit an electrical signal to the circuit layer 200 . As a material of the first metal post layer 400 , copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) , or a conductive material such as an alloy thereof may be used.

A second seed layer 500 may be disposed on the first metal post layer 400 . The second seed layer 500 may be formed to cover the entire upper surface of the first metal post layer 400 . The second seed layer 500 may be formed by an electroless plating method or the like, and may be formed of an electrically conductive material.

A second metal post layer 600 may be disposed on the second seed layer 500 . A diameter of the second metal post layer 600 may be larger or smaller than a diameter of at least some of the diameters of the first metal post layer 400 , and the first metal post layer 400 and the second metal post layer 600 . ) may have the same diameter. As a material of the second metal post layer 600 , copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) , or a conductive material such as an alloy thereof may be used.

The first seed layer 300 and the second seed layer 500 may be formed on the lower surface of the first metal post layer 400 and the second metal post layer 600 , respectively, to have a step difference such as a step shape. have.

A non-insulating material may be used for the circuit layer 200 , the first metal post layer 400 , and the second metal post layer 600 , and may include different metals or may include the same metal.

A non-insulating material may also be used for the first seed layer 300 and the second seed layer 500 , and the first seed layer 300 includes a solder resist layer 230 and an upper portion of the connection pad 210 , and a first metal post. It may be formed between the lower portions of the layers 400 . The second seed layer 500 may be formed between the upper portion of the first metal post layer 400 and the lower portion of the second metal post layer 600 .

In addition, the first seed layer 300 and the second seed layer may be formed by an electroless plating method or the like, and may each include copper (Cu).

Referring to FIG. 3A , the first metal post layer 400 and the second metal post layer 600 may have the same diameter.

Referring to FIG. 3B , a diameter of at least a portion of the first metal post layer 400 may be greater than a diameter of the second metal post layer 600 . In this case, the second seed layer 500 may be formed only on the lower surface of the second metal post layer 600 .

Referring to FIG. 3C , a diameter of at least a portion of the first metal post layer 400 may be smaller than a diameter of the second metal post layer 600 . In this case, the second seed layer 500 may be formed on the entire lower surface of the second metal post layer 600 .

Referring to FIG. 3D , the first seed layer 300 may be disposed to extend to the side surface 410 of one region protruding from the solder resist layer 230 of the first metal post layer 400 . That is, the first metal post layer 400 may be completely embedded in the first seed layer 300 and the second seed layer 500 .

The metal posts may be disposed on the printed circuit board to form a dummy pattern inside the PNL dummy. If the height of the metal post is high, only one side is plated, and if the plating area is small, the height deviation of the plurality of metal posts becomes large. In order to realize a light, thin and compact printed circuit board, it is necessary to reduce the height deviation of the metal post.

The first metal post layer 400 may form a dummy pattern in order to reduce the height deviation of the metal posts as described above. In this case, the dummy pattern may be formed on the solder resist layer 230 .

Also, according to the present disclosure, the second metal post layer 600 may form a dummy pattern. In this case, the dummy pattern may be formed on the second seed layer 500 instead of the solder resist layer 230 .

Also, according to the present disclosure, a dummy pattern can be freely designed inside the PNL by forming a dummy pattern on the second seed layer 500 .

4 to 12 are views schematically illustrating a method of manufacturing a printed circuit board according to the present disclosure.

Referring to FIG. 4 , the base substrate 100 on which the circuit layer 200 is formed may be provided.

The base substrate 100 may include a copper clad laminate (CCL). Types of copper clad laminates include glass/epoxy copper clad laminates, heat-resistant resin copper clad laminates, paper/phenolic copper clad laminates, high frequency copper clad laminates, flexible copper clad laminates, and composite copper clad laminates, depending on their use. The base substrate 100 according to the present disclosure may include a glass/epoxy copper clad laminate as a double-sided package substrate and a multi-layer package substrate.

The circuit layer 200 may be disposed on the base substrate 100 . The circuit layer 200 is a component for transmitting electrical signals, and may include a circuit paddle, a wiring layer, a via, and a connection pad. The circuit layer 200 may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Conductive materials such as these may be used. According to the present disclosure, the circuit layer 200 may be a circuit layer formed in the outermost layer.

Also, the circuit layer 200 may be formed as a single layer, but is not limited thereto. That is, a multi-layered circuit layer may be formed on the base substrate 100 .

In addition, a single-layer or multi-layer circuit layer may be disposed on both surfaces of the base substrate 100 as well as on one surface.

In addition, the circuit layer may include a plurality of wires for transmitting electrical signals, and the thicknesses of the wires may be different from each other or may include wires having the same thickness.

Referring to FIG. 5 , a solder resist layer 230 may be disposed on the base substrate 100 . When the circuit layer 200 is the outermost layer, a solder resist layer 230 may be disposed on the circuit layer 200 to prevent damage to the circuit layer 200 by soldering using solder, etc. The resist layer 230 may form an opening 220 such that the connection pad 210 of the circuit layer 200 is exposed to the outside.

Referring to FIG. 6 , the first seed layer 300 may be disposed on the solder resist layer 230 and the connection pad 210 . In this case, the first seed layer 200 may also be disposed on the inner wall of the opening 220 so as to be disposed on the exposed connection pad 210 . The first seed layer 300 may be formed by an electroless plating method or the like, and may be formed of an electrically conductive material.

Referring to FIG. 7 , a first plating resist layer 310 may be disposed on the first seed layer 300 . The first plating resist layer 310 may be disposed to expose the opening 220 .

Also, according to the present disclosure, after the first plating resist layer 310 is disposed, a seed layer may be additionally disposed thereon. In this case, the additionally disposed seed layer may include the same material as that of the first seed layer 300 , and cover the upper surface of the first plating resist layer 310 and a portion of the solder resist layer 230 and the opening 220 . It may be disposed on the seed layer 300 .

Referring to FIG. 8 , the first metal post layer 400 may be disposed on the first seed layer. The first metal post layer 400 may fill the opening 220 formed on the upper portion of the connection pad 210 to transmit an electrical signal to the circuit layer 200 .

As a material of the first metal post layer 400 , copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) , or a conductive material such as an alloy thereof may be used.

The first metal post layer 400 includes a first region 420 filling the opening 220 , and is disposed on an upper surface of the first region 420 to protrude from the solder resist layer 230 , and the first region 420 . ) may have a second region 430 having a larger diameter than that of .

Also, according to the present disclosure, the first metal post layer 400 may be in contact with a seed layer additionally disposed to cover the first plating resist layer 310 . In this case, the first seed layer may be disposed to extend to the side surface 410 of one region protruding from the solder resist layer 230 of the first metal post layer 400 . Except for the top surface of the first metal post layer 400 , it may be surrounded by a seed layer.

Referring to FIG. 9 , a second seed layer 500 may be disposed on the first plating resist 310 and the first metal post layer 400 . The second seed layer 500 may be formed to cover the entire upper surface of the first metal post layer 400 . The second seed layer 500 may be formed by an electroless plating method or the like, and may be formed of an electrically conductive material.

Also, according to the present disclosure, the first metal post layer 400 may be surrounded by the first seed layer 300 extending on the lower surface and side surfaces, and the upper surface may be surrounded by the second seed layer 500 . In this case, the first metal post layer 400 may be disposed in a form embedded in the first seed layer 300 and the second seed layer 500 .

Referring to FIG. 10 , a second plating resist layer 510 may be disposed on the second seed layer 500 . A diameter of the second plating resist layer 510 may be equal to or smaller than a diameter of the first plating resist layer 310 . In addition, the diameter of the second plating resist layer 510 may be larger than the diameter of the first plating resist layer 310 .

The second plating resist layer 510 may include a material different from that of the first plating resist layer 310 , or may include the same material.

Referring to FIG. 11 , the second metal post layer 600 may be disposed on the second seed layer 500 . The second metal post layer 400 may transmit an electrical signal to the circuit layer 200 and the first metal post layer 400 .

A diameter of the second metal post layer 600 may be larger or smaller than a diameter of at least some of the diameters of the first metal post layer 400 , and the first metal post layer 400 and the second metal post layer 600 . ) may have the same diameter.

When the diameter of the second plating resist layer 510 is the same as that of the first plating resist layer 310 , the diameters of the second plating resist layer 510 and the first plating resist layer 310 may be the same.

When the diameter of the second plating resist layer 510 is smaller than the diameter of the first plating resist layer 310 , the diameter of the second metal post layer 600 may be larger than the diameter of the first metal post layer 400 . .

When the diameter of the second plating resist layer 510 is greater than the diameter of the first plating resist layer 310 , the diameter of the second metal post layer 600 may be smaller than the diameter of the first metal post layer 400 .

As a material of the second metal post layer 600 , copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) , or a conductive material such as an alloy thereof may be used.

In addition, the second metal post layer 600 may include a metal material different from that of the first metal post layer 400 , or may include the same metal material.

The first seed layer 300 and the second seed layer 500 may be formed on the lower surface of the first metal post layer 400 and the second metal post layer 600 , respectively, to have a step difference such as a step shape. have.

A non-insulating material may be used for the circuit layer 200 , the first metal post layer 400 , and the second metal post layer 600 , and may include different metals or may include the same metal.

A non-insulating material may also be used for the first seed layer 300 and the second seed layer 500 , and the first seed layer 300 includes a solder resist layer 230 and an upper portion of the connection pad 210 , and a first metal post. It may be formed between the lower portions of the layers 400 . The second seed layer 500 may be formed between the upper portion of the first metal post layer 400 and the lower portion of the second metal post layer 600 .

In addition, the first seed layer 300 and the second seed layer 500 may include different materials or may include the same material. The first seed layer 300 and the second seed layer 500 may be formed by an electroless plating method or the like, and may each include copper (Cu).

The first seed layer 300 and the second seed layer 500 may be respectively formed by an electro copper plating method or a chemical copper plating method, or may be formed by a sputtering deposition method or the like.

Also, the first metal post layer 400 and the second metal post layer 600 may be formed by an electrolytic plating method.

Referring to FIG. 12 , the second plating resist layer 510 may be removed. In this case, a side surface of the second metal post layer 600 may be exposed. The second plating resist layer 510 may be removed by a method of removing a conventional plating resist.

A portion of the second seed layer 500 may be exposed by removing the second plating resist layer 510 .

Also, according to the present disclosure, a process of planarizing the second metal post layer 600 may be included. By grinding the exposed upper portion of the second metal post layer 600 , the second metal post layer 600 having the same height may be formed.

A planarization process may be performed on the second metal post layer 600 after the second plating resist layer 510 is removed, and then the second seed layer 500 is removed or the first plating resist layer 310 is removed. ) can be carried out in the step where it is removed.

When the second metal post layer 600 and the first metal post layer 400 are planarized together in the step of removing the first plating resist layer 310 , the first metal post layer 400 and the second metal post layer 400 are The metal post layer 600 may have the same diameter.

Referring to FIG. 13 , a portion of the exposed second seed layer 500 may be removed. The second seed layer 500 may be removed by etching or the like. The second seed layer 500 may be removed except for a portion in contact with the lower surface of the second metal post layer 600 .

Referring to FIG. 14 , the first plating resist layer 310 may be removed. In this case, a portion of the side surface of the first metal post layer 600 may be exposed. The first plating resist layer 310 may be removed by a method of removing a conventional plating resist.

A portion of the first seed layer 300 may be exposed by removing the first plating resist layer 310 .

The first plating resist layer 310 and the second plating resist layer 510 may be removed in the same manner.

Referring to FIG. 15 , a portion of the exposed first seed layer 300 may be removed. The first seed layer 300 may be removed by etching or the like. The first seed layer 300 may be removed except for a portion in contact with the lower surface of the first metal post layer 400 . When a portion of the first seed layer 300 is removed, a portion of the solder resist layer 230 may be exposed.

As the first plating resist layer 310 and the second plating resist layer 510 are removed, the first metal post layer 400 and the second metal post layer 600 may be formed in a step shape, and have a plurality of diameters. It is possible to form a printed circuit board including a metal post.

In addition, by depositing the second metal post layer 600 additionally on the first metal post layer 400 instead of the solder resist layer 230 , a metal dummy pattern can be formed regardless of the distance between the strip dummy. And it is possible to reduce the deviation between the plurality of metal posts.

Descriptions of other components are substantially the same as those described above, and detailed descriptions thereof will be omitted.

The expression of being disposed on any component in the present specification is not intended to establish a direction. Accordingly, the expression disposed on a certain component may mean disposed on an upper side of a certain component or may mean disposed on a lower side of a certain component.

In this specification, terms such as upper surface, lower surface, upper side, lower side, uppermost side, and lowermost side are directions set based on the drawings for convenience of description. Accordingly, the upper surface, the lower surface, the upper side, the lower side, the uppermost side, the lowest side, etc. may be described with different terms according to the setting direction.

The meaning of being connected in the present specification is a concept including not only directly connected, but also indirectly connected. In addition, the meaning of being electrically connected is a concept including both the case of being physically connected and the case of not being connected.

In the present specification, expressions such as first, second, etc. are used to distinguish one component from another, and do not limit the order and/or importance of the corresponding components. According to the description, the first component may be referred to as a second component, and similarly, the second component may be referred to as a first component.

The expression “an example” used in this specification does not mean the same embodiment, and is used to emphasize and explain different unique features. However, the examples presented above are not excluded from being implemented in combination with features of other examples. For example, even if a matter described in one specific example is not described in another example, it may be understood as a description related to another example unless a description contradicts or contradicts the matter in another example.

The terminology used herein is used to describe an example, and is not intended to limit the present disclosure. In this case, the singular expression includes the plural expression unless the context clearly indicates otherwise.

The printed circuit board and the printed circuit board manufacturing method according to the present specification are not limited thereto, and those of ordinary skill in the art can view the present invention within the scope not departing from the spirit and scope of the present invention described in the claims below. Various modifications and variations of the invention are possible.

10: printed circuit board
100: base substrate
200: circuit layer 210: connection pad
220: opening 230: solder resist layer
300: first seed layer
310: first plating resist layer
400: first metal post layer
410: side portion of the first metal post layer
420 and 430: first and second regions of the first metal post layer
500: second seed layer
510: second plating resist layer
600: second metal post layer
1000: electronic device 1010: main board
1020: chip related parts 1030: network related parts
1040: other parts 1050: camera module
1060: antenna module 1070: display
1080: battery 1090: signal line
1100: smartphone 1110: smartphone internal main board
1120: internal electronic parts of the smartphone
1121: smartphone internal antenna module
1130: smartphone internal camera module
1140: Smartphone internal speaker

Claims (7)

base substrate;
a circuit layer disposed on the base substrate and including a connection pad;
a solder resist layer disposed on the base substrate and having an opening exposing the connection pad;
a first seed layer disposed on the exposed connection pad and the solder resist layer;
a first metal post layer disposed on the first seed layer to fill the opening;
a second seed layer disposed on an upper surface of the first metal post layer; and
a second metal post layer disposed on the second seed layer;
The first and second seed layers each include copper.
According to claim 1,
The first metal post layer,
A printed circuit board having a plurality of diameters.
According to claim 1,
The first seed layer is disposed to extend to a side surface of a region protruding from the solder resist layer among the first metal post layers.
According to claim 1,
and the first metal post layer and the second metal post layer have the same diameter.
According to claim 1,
The first metal post layer, at least a portion of the diameter is different from that of the second metal post layer, the printed circuit board.
According to claim 1,
The first metal post layer, at least a part of the diameter of the printed circuit board is smaller than the diameter of the second metal post layer.
3. The method of claim 2,
The first metal post layer,
a first region filling the opening;
The printed circuit board, which is disposed in the first region and protrudes from the solder resist layer, and has a second region having a larger diameter than the first region.

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