KR20220070043A - Communication method and communication device - Google Patents

Abstract

A communication method according to an aspect of the present disclosure provides an arrangement of traversing blocks within a codeword generated based on a pseudo traversing low-density parity check code including a repeat-accumulated pseudo traversing low-density parity check code. Executes traversing block permutation to change , and maps each bit of the codeword subjected to traversal block permutation to constellation points of non-uniform constellations. Accordingly, the reception performance is improved.

Description

COMMUNICATION METHOD AND COMMUNICATION DEVICE

The disclosures of the specification, claims, drawings and abstracts contained in European Patent Application 14169535.3 filed on May 22, 2014 are all incorporated herein by reference.

The present disclosure relates to the field of digital communication. More specifically, bit-interleaved coding modulation (bit-) using a quasi-cyclic low-density parity-check code (QC LDPC code) and quadrature amplitude modulation (QAM). It relates to a bit interleaver and a bit deinterleaver in an interleaved coding and modulation: BICM system.

Recently, a bit interleaver has been used between an encoder that encodes information bits and outputs codeword bits, and a constellation mapper that maps codeword bits to a constellation and outputs a modulation symbol. Many arranged transmitters have been proposed (see, for example, Patent Document 1).

Specification of European Patent Application Publication No. 2552043

DVB-S2 standard: ETSI EN 302 307, V1.2.1 (August 2009)

A communication method according to an aspect of the present disclosure is a data communication method for performing data communication in a digital communication system using a pseudo cyclic low-density parity check code including a repeat-accumulated pseudo cyclic low-density parity check code, wherein the pseudo cyclic parity check code is used. A traversal block permutation is performed on a codeword generated based on the check code, and the codeword is composed of a column of N traversal blocks, each of the N traversal blocks consists of Q bits, and N and Q is a positive integer, respectively, and the traversing block permutation is a ratio between an interleaving step, which is a rearrangement of traversing blocks within the codeword, and each bit of the codeword on which the traversing block permutation is performed. and a constellation mapping step of mapping to a constellation point of a uniform constellation, wherein the traversing block permutation and the non-uniform constellation correspond to the coding rate of the pseudo traversing low-density parity check code used to generate the codeword. selected based on

1 is a block diagram illustrating an example of a configuration of a transmitter including a general bit-interleaved coding and modulation (BICM).
FIG. 2 is a block diagram showing an example of the configuration of the BICM encoder of FIG. 1 .
3 is a diagram showing an example of a parity check matrix of a pseudo traversing low-density parity check code of M=6, N=18, and Q=8.
4 is a diagram illustrating an example of a table defining a repeat-accumulated pseudo traversing low-density parity check code.
FIG. 5 is a diagram showing an information part of a parity check matrix with respect to the first bit in each traversal block of the information part for the repeat-accumulated pseudo circulating low-density parity check code of FIG. 4 .
FIG. 6 is a diagram illustrating a complete parity check matrix including an input for all information bits and step-shaped parity parts with respect to the parity check matrix of FIG. 5 .
FIG. 7 is a diagram illustrating a matrix indicating a pseudo-traversal structure of the parity check matrix of FIG. 6 .
8A is a diagram illustrating a 4-QAM constellation.
8B is a diagram illustrating a 16-QAM constellation.
8C is a diagram illustrating a 64-QAM constellation.
9A is a block diagram showing the configuration of a 4-QAM mapper.
9B is a block diagram illustrating the configuration of a 16-QAM mapper.
9C is a block diagram illustrating the configuration of a 64-QAM mapper.
10 is a schematic diagram for explaining different robust levels in an 8-PAM symbol using gray coding.
11 is a diagram illustrating an example of a 4096-QAM constellation based on 1D-64 NU-PAM designed for a specific SNR.
12A is a diagram for explaining an example of the BICM encoder of FIG. 2 based on DVB-NGH.
12B is a diagram for explaining an example of the BICM encoder of FIG. 2 based on DVB-NGH.
12C is a diagram for explaining an example of the BICM encoder of FIG. 2 based on DVB-NGH.
13A is a diagram for explaining an example of the BICM encoder of FIG. 2 based on ATSC3.0.
13B is a diagram for explaining an example of the BICM encoder of FIG. 2 based on ATSC3.0.
13C is a diagram for explaining an example of the BICM encoder of FIG. 2 based on ATSC3.0.
14 is a block diagram showing a configuration example of a bit interleaver according to the disclosed embodiment.

<Confirmations made by the inventors to the present disclosure>

1 is a block diagram illustrating a configuration example of a transmitter including general bit-interleaved coding and modulation (BICM).

The transmitter 100 shown in FIG. 1 includes an input processing unit 110 , a BICM encoder 120 , an OFDM modulator 130 , an up converter 140 , a radio frequency (RF) amplifier 150 , and an antenna 160 . to provide

The input processing unit 110 transforms the input bit stream into blocks of a predetermined length called base band frames. The BICM encoder 120 converts the baseband frame into a data stream composed of a plurality of complex values. OFDM modulator 130 uses, for example, orthogonal frequency-division multiplexing (OFDM) modulation, and typically performs time interleaving and frequency interleaving to improve diversity. The up-converter 140 converts a digital baseband signal into an analog radio frequency (RF) signal. The RF amplifier 150 amplifies the power of the analog RF signal and outputs it to the antenna 160 .

FIG. 2 is a block diagram showing a configuration example of the BICM encoder 120 of FIG. 1 .

The BICM encoder 120 shown in FIG. 2 is equipped with the low-density parity-check (LDPC) encoder 121, the bit interleaver 122, and the QAM mapper 124.

The LDPC encoder 121 encodes an input block, that is, a baseband frame, and outputs the LDPC codeword to the bit interleaver 122 . The bit interleaver 122 rearranges the bits of each LDPC codeword before being mapped to the complex cell by the QAM mapper 124 . The QAM mapper 124 maps bits of each LDPC codeword after the bits are rearranged to complex cells using quadrature amplitude modulation (QAM).

Hereinafter, each component of the BICM encoder 120 of FIG. 2 will be described in more detail.

First, the LDPC encoder 121 will be described.

The LDPC encoder 121 encodes a baseband frame using a specific LDPC code. In particular, the present disclosure is designed for LDPC block codes having a step-like parity structure as employed in the DVB-S2, DVB-T2, and DVB-C2 standards, and transformations of Raptor-like and LDPC codes. . A more detailed description is given below.

The LDPC block code is a linear error correction code completely defined by a parity-check matrix (PCM). This PCM is a binary sub-matrix indicating the connection of codeword bits (also called bit nodes or variable nodes) to parity check (also called check nodes). Columns and rows of the PCM correspond to variable nodes and check nodes, respectively. The connection of the variable node to the check node is indicated by a "1" entry in the PCM matrix.

The quasi-cyclic low-density parity-check (QC LDPC) code has a structure particularly suitable for hardware implementation. In fact, today, many, if not all, standards use QC LDPC codes. The PCM of this QC LDPC code has a special structure having a traversal matrix (also called traversal). A traversal matrix is a square matrix in which each row is traversed by shifting one previous row by one matrix element, and may have one or more folded diagonals.

The size of each traversal matrix is Q×Q (Q rows and Q columns), where Q is called a cyclic factor of the QC LDPC code. With this pseudo-traversal structure, it becomes possible to process Q test nodes in parallel. For this reason, the pseudo-traversal structure is clearly advantageous for efficient hardware implementation.

The PCM of the QC LDPC code is a matrix of Q×M rows and Q×N columns, and the codeword consists of N blocks each of Q bits. In addition, M is the number of blocks in a parity part. In addition, a block of Q bits is called a pseudo traversal block, or simply a traversal block, and is abbreviated as QB throughout this document.

3 is a diagram illustrating an example of PCM of a QC LDPC code of M=6, N=18, and Q=8. PCM contains a traversal matrix with a diagonal of 1 or 2. This QC　LDPC code encodes a block of 8x12=96 bits into a codeword of 8x18=144 bits, so that the coding rate is 2/3. In addition, in Figs. 3 and 5 to 7 , a black rectangle is a matrix element with a value of “1”, and a white rectangle is a matrix element with a value of “0”.

The QC LDPC code shown in Fig. 3 by PCM belongs to a special family of QC LDPC codes called repeat-accumulate quasi-cyclic low-density parity-check (RA QC LDPC) codes. . The RA QC LDPC code is known to be easy to encode, and is employed in many standards such as the second generation DVB standards (DVB-S2, DVB-T2, DVB-C2).

Next, DVB described in section 5.3.2 and Appendix B, C of Non-Patent Document 1 of the DVB-S2 standard (DVB-S2 standard: ETSI EN 302 307: V1.2.1 (August 2009)) The definition of the RA QC LDPC code used in the standard family of -S2, DVB-T2, and DVB-C2 will be described. For this family of specifications, the traversal factor Q is 360.

Each LDPC code is completely defined by a table including the index of each check node to which the first bit is connected with respect to the first bit of each circulating block in the information part. Also, the index of the check node starts from 0. These indices are called "addresses of the parity bit accumulators" in the DVB-S2 standard. FIG. 4 shows a table for an LDPC code showing an example in FIG. 3 .

FIG. 5 : is a figure which shows the information part of PCM with respect to the first bit in each circulating block of an information part with respect to the RA QC LDPC code of FIG.

The complete PCM includes an input for all information bits and a step-shaped parity part, and is shown in FIG. 6 .

For each bit other than the first bit of each traversal block in the information part, the index of each check node to which the bit is connected is calculated using the following number 1.

[Number 1]

However, q is a bit index (0, ..., Q-1) in one traversal block. i _q is the index of the check node for bit q. i ₀ is one of the check nodes to which the first bit of the traversal block in the table of Fig. 4 is connected. M is the number of circulating blocks in the parity part, and is 6 in the example of FIG. 6, Q is the number of bits of one circulating block, and 8 in the example of FIG. QxM is the number of parity bits, and in the example of Fig. 6, 8x6 = 48. % is a modulo operator. Incidentally, for example, for a traversal block QB of "1", calculation using the above number 1 is performed for each of i _{0 =} 13, 24, 27, 31, and 47 in the case of Fig. 4 .

In order to show the pseudo-traversal structure of the PCM of FIG. 6, the permutation indicated by the following Equation 2 is applied to the rows of the PCM of FIG. 6, and by applying this permutation, the matrix is shown in FIG.

[Number 2]

However, i and j are indexes starting from zero. i is the index of the check node before rearrangement, and j is the index of the check node after rearrangement. M is the number of circulating blocks in the parity part, and is 6 in the example of FIG. 6, Q is the number of bits of one circulating block, and 8 in the example of FIG. % is a modulo operator, and floor(x) is a function that outputs the largest integer less than or equal to x.

Since permutation using the number 2 is not applied to bits, the definition of the sign does not change. However, the parity part of PCM obtained as a result of permutation using this number 2 is not pseudo-circulated. In order to pseudo-circulate the parity part, a special permutation represented by the following number 3 must be applied only to the parity bit.

[Number 3]

However, i and j are indexes starting from zero, i is the index of the parity bit before rearrangement, and j is the index of the parity bit after rearrangement. M is the number of circulating blocks in the parity part, and is 6 in the example of FIG. 7, Q is the number of bits of one circulating block, and 8 in the example of FIG. % is a modulo operator, and floor(x) is a function that outputs the largest integer less than or equal to x.

Permutation using the number 3 applied only to this parity bit changes the definition of the code.

In addition, permutation using the number 3 applied only to parity bits is referred to as parity permutation or parity interleaving throughout this document. However, parity permutation or parity interleaving is considered to be a part of the LDPC encoding process hereinafter.

The ATSC3.0 standard, which is a next-generation standard for terrestrial reception of digital video services, is currently under development and has a coding rate of 1/15, 2/15, ... , 13/15, 16200 code bits and 64800 code bits will be defined as the codeword length.

Next, the QAM mapper 124 will be described.

The QAM mapper 124 independently modulates the real component and the imaginary component by using pulse-amplitude modulation (PAM), respectively, so that the bit of the codeword is converted to one point among a plurality of points in the QAM constellation. map to Each point in the QAM constellation corresponds to one combination of bits each. 8A to 8C are diagrams illustrating three types of QAM constellations, 4-QAM constellation, 16-QAM constellation, and 64-QAM constellation according to the present disclosure.

Here, the PAM of the same type is used for the real component and the imaginary component. In the 4-QAM constellation, the 16-QAM constellation, and the 64-QAM constellation, 2-PAM, 4-PAM, and 8-PAM are used for the real component and the imaginary component, respectively.

This disclosure also assumes that gray coding is used for PAM mapping, as shown in FIGS. 8A to 8C .

9A, 9B, and 9C are blocks showing the configuration of a QAM mapper corresponding to the constellation of FIGS. 8A, 8B, and 8C, respectively. The 4-QAM mapper 124A of FIG. 9A consists of two independent 2-PAM mappers 124A-1 and 124A-2, each encoding one bit. The 16-QAM mapper 124B of FIG. 9B consists of two independent 4-PAM mappers 124B-1 and 124B-2, each encoding 2 bits. The 64-QAM mapper 124C of FIG. 9C consists of two independent 8-PAM mappers 124C-1 and 124C-2, each encoding 3 bits.

The coded bits in the PAM symbol have different robust levels, in other words, reliability when the received PAM symbol is demapped at the receiver. This is a well-known fact, and FIG. 10 shows a schematic diagram for explaining different robust levels in an 8-PAM symbol using Gray coding.

The different robust levels are due to the fact that the distance between the bit-valued portion and the bit-valued portion is different between the three bits b ₁ , b ₂ , and b ₃ . The reliability of a bit is proportional to the average distance between the portion in which the value of the bit is 0 and the portion in which the bit is 1. In the example shown in Fig. 10, the reliability of the bit b1 is the lowest, the reliability _of the bit b2 is the _second lowest, _and the reliability of the bit b3 is the highest.

In order to increase the bit rate, that is, the capacity of the BICM, non-uniform constellation was first introduced in the DVB-NGH standard. This augmentation is achieved by changing the spacing between the points of the PAM constellation, so-called 1D-NU-PAMs are obtained. Then, a square non-uniform constellation is obtained from the 1D-NU-PAMs.

In ATSC3.0, this idea is further improved by introducing two-dimensional non-uniform constellations, so-called 2D-NUCs. 2D-NUCs are accompanied by an increase in the complexity of demapping at the receiver because the I (in-phase) component and the Q (quadrature) component of the received complex cell depend on each other. The higher complexity of demapping is considered to be that the order of constellation is allowed up to 1024 in ATSC3.0. In addition, it is determined that only constellations based on PAM for 4096-QAM constellations are permitted. An example of a 4096-QAM constellation based on 1D-64 NU-PAM is shown in FIG. 11 .

The number of bits of the QAM symbol is denoted by B. Since the QAM constellation is square, B is even. In addition, since the square QAM symbol consists of two PAM symbols of the same type, bits encoded in the QAM symbol can be grouped into pairs having the same robust level. A set of bits encoded as a QAM symbol is called a constellation word.

Next, the bit interleaver 122 will be described.

Typically, bits of an LDPC codeword have different importance levels, and bits of a constellation have different robustness levels. If the bits of the LDPC codeword are mapped to the bits of the QAM constellation directly, that is, without interleaving, optimal performance cannot be obtained. In order to prevent this performance degradation, it is necessary to interleave the bits of the codeword before mapping them to the constellation.

For this reason, the bit interleaver 122 is provided between the LDPC encoder 121 and the QAM mapper 124, as shown in FIG. By carefully designing the bit interleaver 122, it is possible to obtain an optimal relationship between the bits of the LDPC codeword and the bits encoded by the constellation, leading to improvement in performance. Typically, performance evaluation criteria is a bit error rate (BER) or frame error rate (FER) as a function of a signal-to-noise ratio (SNR).

The difference in the importance of bits in the LDPC codeword is due to the fact that, first, the number of parity checks (check nodes) is not the same for all bits. As the number of parity check (check nodes) connected to the codeword bit (variable node) increases, the bit becomes more important in the iterative LDPC decoding process.

In addition, the difference in the importance of the bits of the LDPC codeword is due to, secondly, that the variable nodes have different connectivity with respect to the cycle in the Turner graph representation of the LDPC code. Therefore, even if the number of parity checks (check nodes) connected to the codeword bits of the LDPC code is the same, the importance of bits may differ.

These views are well known in the art. As a rule, as the number of check nodes connected to a variable node increases, the importance of the variable node increases.

In particular, in the case of the QC LDPC code, all bits included in the Q bit traversal block have the same number of parity checks (check nodes) connected to the bits, and the connectivity to the cycle in the Turner graph representation is the same, of the same importance.

Next, a method of mapping the bits of the QC LDPC codeword to the constellation word will be described. This mapping is done by the bit interleaver 122 of FIG. In addition, this mapping method is disclosed in patent document 1 (EP11006087.8), and is fully integrated here. Although Patent Document 1 (EP11006087.8) relates to an arbitrary number T of the number of transmission antennas, a case related to the present disclosure, that is, a case where the number of transmission antennas T is 1, will be described below.

According to Patent Document 1 (EP11006087.8), the bits of the QC LDPC codeword are,

(i) Each constellation word is made of bits of B/2 traversal blocks of QC LDPC codeword,

(ii) Each pair of bits of the constellation word, encoded with the same QAM symbol and having the same robust level, is mapped to the constellation word so as to be made of the bits of the same traversal block.

In particular, Q×B/2 bits of B/2 traversal blocks are mapped to Q/2 spatial multiple blocks. In this case, the B/2 traversal blocks are called sections.

12A to 12C are diagrams for explaining an example of the BICM encoder 120 of FIG. 2 .

12A shows the arrangement for 24 traversing blocks in 4 sections. In the example of Fig. 12A, the number of traversal blocks per section is B/2=12/2=6.

Fig. 12b shows the steps from the bit interleaver 122 to the QAM mapper 124 (including a pair of PAM mappers 124-1 and 124-2) of the BICM encoder 120 of Fig. 2 based on DVB-NGH. It is a diagram showing an example of the structure of a path.

The LDPC codeword generated by the LDPC encoder 121 of FIG. 2 is supplied to the bit interleaver 122 of FIG. 12B. The bit interleaver 122 is 6 traversal blocks per section. Further, for each section in Fig. 12A, processing is performed by the bit interleaver 122 and the QAM mapper 124 (including a pair of PAM mappers 124-1 and 124-2) in Fig. 12B. The bit interleaver 122 changes the arrangement order of the supplied bits, and arranges the rearranged bits therefrom in the real part and the imaginary part of the corresponding constellation word. A pair of PAM mappers 124-1 and 124-2 uses a 64-PAM constellation to convert bits (b _{1, Re} , b _{2, Re} , ..., b _{6, Re} ) to real numbers of complex symbols s1. To the component Re, the bits b _{1 , lm} , b _{2 , lm} , ..., b _{6 , lm} ) are mapped to the imaginary component lm of the complex symbol s1 .

FIG. 12C is a diagram for explaining bit rearrangement executed by the bit interleaver 122 of FIG. 12B. As shown in Fig. 12C, the bit interleaver 122 writes all bits of one section of a codeword in a matrix row-by-row, and writes the written bits in a column direction from the matrix. -by-column) Execute processing equivalent to reading. Also, this matrix is B/2 rows and Q columns.

13A to 13C are diagrams for explaining another example of the BICM encoder 120 of FIG. 2 . 13A to 13C are similar to FIGS. 12A to 12C except that they respectively show an arrangement based on ATSC3.0.

Figure 13a shows the arrangement for 24 traversing blocks in two sections. In the example of FIG. 13A, unlike the case of FIG. 12A, the number of traversing blocks per section is the number of bits B of the QAM symbol, and is 12 in the example of FIG. 13A.

13B is a diagram showing an example of the structure of a path from the bit interleaver 122 to the QAM mapper 124 of the BICM encoder 120 of FIG. 2 based on ATSC3.0.

The LDPC codeword generated by the LDPC encoder 121 of FIG. 2 is supplied to the bit interleaver 122 of FIG. 13B. The bit interleaver 122 is 12 traversal blocks per section. Further, for each section in Fig. 13A, processing is performed by the bit interleaver 122 and the QAM mapper 124 in Fig. 13B. The bit interleaver 122 changes the arrangement order of the supplied bits. The QAM mapper 124 uses the 4096-QAM constellation to map bits ( b ₀ , b ₁ , ..., b ₁₁ ) to complex symbols s1 .

FIG. 13C is a diagram for explaining bit rearrangement executed by the bit interleaver 122 of FIG. 13B. As shown in Fig. 13C, the bit interleaver 122 writes all bits of one section of a codeword in a matrix row-by-row, and writes the written bits in a column direction from the matrix. -by-column) Execute processing equivalent to reading. Also, this matrix has B rows and Q columns.

<Embodiment>

As described above, it is possible that traversal blocks having different LDPC codes have different importance because the importance of a bit depends on the number of check nodes to which the bit is connected. Accordingly, by including the importance of the traversal block and the robustness of bits of the constellation word to which the traversal block is mapped, there is a possibility that the transmission performance can be improved. In particular, the bit of the traversal block with the highest importance is mapped to the bit of the constellation word with the strongest robustness. Conversely, the bit of the traversal block with the lowest importance is mapped to the bit of the constellation word with the weakest robustness.

14 is a block diagram illustrating a configuration example of a bit interleaver according to an embodiment of the present disclosure. In the example of Fig. 14, the LDPC codeword consists of N = 12 traversal blocks QB1, QB2, ..., QB12 each of which Q = 8 bits.

In the bit interleaver, in a first stage, traversing block permutation ( QB permutation: QB permutation) is executed. The processing of this first stage is performed by the traversing block permutation unit 210 .

In the second stage, in order to change the arrangement order of bits in the traversal block, intra-QB permutation (Intra-QB permutation) is performed on the traversal block. The processing of this second stage is executed by the permutation units 220-1 to 220-12 in the traversal block. In addition, the second stage does not need to exist.

In the third stage, after the first stage and the second stage are executed, the bits of each traversal block of the codeword are mapped to the constellation word. This third stage can be implemented by dividing the codeword into a plurality of sections and mapping each section to a constellation word (section permutation). For example, this is realized by arranging an interleaver (section interleaver) having a function equivalent to that of the bit interleaver 122 described with reference to Figs. 13A to 13C at the rear end of the permutation unit in the traversal block.

The inventor realized that communication performance for a given LDPC code is improved by optimizing the traversing block permutation, that is, by selecting a traversing block permutation that combines traversing blocks of different reliability with constellation bits of different reliability. .

However, the mapping of traversal blocks to constellation word bits is not straightforward. Finding an optimized traversal block permutation is a very time consuming task, as no analytic solutions are currently known. The method used to find the optimal traversing block permutation disclosed in the present disclosure consists of the following steps, and is applied to each of different constellations and different coding rates.

In the preliminary step, a very large number (1e4 ... 1e5) of traversing block permutations are randomly generated without restrictions. For these traversal block permutations, the Monte-Carlo simulation is performed blindly to obtain a threshold signal-to-noise ratio (SNR) at a predetermined target value of the block error rate (BLER). It is implemented using mapping and iterative demapping. The traversal block permutation with the lowest threshold SNR, ie, the best performance, is maintained.

The inventors have realized that optimization of traversal block permutation for blind demapping does not yield optimal performance for iterative demapping, and vice versa. Finding a traversing block permutation that yields good performance for both blind and iterative demapping remains a daunting task.

Therefore, we present a traversal block permutation with good performance for both blind demapping and iterative demapping.

In a preliminary step, ranges of SNRs for various traversal block permutations are obtained. Then, a threshold SNR is set to select only traversal block permutations that obtain good performance for blind demapping. Good performance means low SNR. The threshold SNR should not be set too low. This is because, if the threshold SNR is set too low, many traversal block permutations that achieve very good performance for iterative demapping are excluded. On the other hand, when traversing block permutation strictly optimized for blind demapping is used for iterative demapping, performance deteriorates. Proper selection of the initial threshold SNR is a matter of experience.

In the first selection step, a large number of traversing block permutations are randomly generated without restrictions. For each traversal block permutation, a BLER curve for blind demapping is obtained, for example using Monte-Carlo simulations. Only traversal block permutations in which the SNR at the target value of BLER is lower than the predetermined threshold SNR are maintained. For the maintained traversal block permutation, a BLER curve for iterative demapping is obtained, and the best traversal block permutation is maintained.

In the second selection step, an intermediate number of traversing block permutations obtained from the traversing block permutations selected in the first selection step are randomly generated under constraints. Then, the selection criteria of the first selection step are applied. The constrained traversing block permutation is obtained by applying a random permutation to a traversing block of one randomly selected section. By applying this constraint, it is ensured that the performance variation is small and concentrates around the good performing traversal block permutations already selected in the first selection step. In this way, better performing traversal block permutations can be found more effectively than using blind-unconstrained search.

In the third selection step, a medium number of traversing block permutations obtained from the traversing block permutations selected in the second selection step are randomly generated under constraints. Then, the selection criteria of the first selection step are applied. The constrained traversal block permutation is obtained by applying random permutation to bits having the same robust level. Therefore, the change in performance is very small and affects iterative demapping rather than blind demapping. Thus, performance with respect to iterative demapping is optimized without sacrificing performance with respect to blind demapping.

The inventor performed optimization of traversal block permutation for each of the coding rates of 6/15, 7/15, and 8/15. In addition, the inventor determined the optimal nonuniformity constellation used together with the coding rates 6/15, 7/15, and 8/15 simultaneously with the optimization of a traversal block permutation. Hereinafter, the optimized QB permutation and non-uniform constellation for each of the coding rates 6/15, 7/15, and 8/15 are shown.

Tables 1 and 2 are tables showing non-uniform 64-PAM constellations constituting traversing block permutation and non-uniform 4096-QAM constellation when the coding rate is 6/15 according to the present disclosure, respectively. .

However, in Table 1 and Tables 3 and 5 to be described later, the index of the traversal block starts from 0 and is up to 179. "j-th block of Group-wise Interleaver Output" indicates the index of the traversal block in the codeword after the traversal block is rearranged. In addition, "π(j)-thblock of Group-wise Interleaver Input" indicates the index of the traversal block in the codeword before the traversal block is rearranged. In addition, in Table 2 and Tables 3 and 5 to be described later, the address label x starts from 0 to 63. In "Address Label x (integer, MSB first)", the address label of the most significant bit (MSB) of the bit is "0", and the address label of the next bit of the most significant bit is "1". "PAM spots p(x)" indicates the real value of the PAM symbol corresponding to the address label.

[Table 1]

[Table 2]

Tables 3 and 4 are tables showing non-uniform 64-PAM constellations constituting traversing block permutation and non-uniform 4096-QAM constellation when the encoding rate is 7/15, respectively, according to the present disclosure. .

[Table 3]

[Table 4]

Tables 5 and 6 are tables showing non-uniform 64-PAM constellations constituting traversing block permutation and non-uniform 4096-QAM constellation when the encoding rate is 8/15, respectively, according to the present disclosure. .

[Table 5]

[Table 6]

In addition, according to the coding rate of the code used by the LDPC encoder 121, the traversing block permutation unit 210 of FIG. 14 shows Tables 1 and 3 according to the coding rates 6/15, 7/15, and 8/15. , and rearrangement of traversing blocks in the codeword based on traversal block permutation in Table 5.

Next, the operation of the QAM mapper of the present embodiment will be described.

The mapping to the complex cell s(Re, Im) by the QAM mapper 124 is performed by calculating the following number 4. However, the non-uniform PAM coordinates p(x) are obtained from Table 2 in the case of the coding rate of 6/15, from Table 4 in the case of the coding rate of 7/15, and from Table 6 in the case of the coding rate of 8/15.

[Number 4]

However, the address label x' of the real part p(x') is an interleaver (section interleaver) (section The number of per traversal blocks is calculated from number 5 using even-numbered bits b ₀ , b ₂ , b ₄ , b ₆ , b ₈ , and b ₁₀ output from B).

[Number 5]

In addition, the address label x" of the imaginary part p(x") is derived from number 6 using odd-numbered bits b ₁ , b ₃ , b ₅ , b ₇ , b ₉ , b ₁₁ output from the section interleaver. Calculated.

[Number 6]

The above-described traversing block permutations (eg, Tables 1, 3, and 5) and non-uniform QAM constellations (eg, Tables 2, 4, and 6) are performed on the transmitter side in the digital communication system and It relates to both sides of the receiver. Each of the above-mentioned traversing block permutations uniquely defines an opposite traversing block permutation, one of the above-mentioned traversing block permutations is used for bit interleaving at the transmitter side, and the reverse traversing block permutation is the bit at the receiver side. used for deinterleaving. In addition, based on the above definition of the non-uniform QAM constellation (two-dimensional non-uniform constellation), mapping the bits of the constellation word, that is, the codeword, to the complex cell used for transmission is and demapping of the received complex cell is done at the receiver on the other side of the communication channel.

The aforementioned traversing block permutation and the aforementioned non-uniform 4096-QAM constellation are optimized for special LDPC codes having coding rates of 6/15, 7/15, and 8/15, respectively.

Tables 7-1 and 7-2 show the definition of the LDPC code having a code length of 64800 code bits at this coding rate of 6/15. In fact, the definition of the LDPC code is completed by continuing the first row of Table 7-2 after the last row of Table 7-1.

[Table 7-1]

[Table 7-2]

Tables 8-1 and 8-2 show the definition of an LDPC code having a code length of 64800 code bits at this coding rate of 7/15. In fact, the definition of the LDPC code is completed by continuing the first row of Table 8-2 after the last row of Table 8-1.

[Table 8-1]

[Table 8-2]

Tables 9-1 and 9-2 show the definition of an LDPC code having a code length of 64800 code bits at this coding rate of 8/15. In fact, the definition of the LDPC code is completed by continuing the first row of Table 9-2 after the last row of Table 9-1.

[Table 9-1]

[Table 9-2]

Hereinafter, the parity bit arithmetic processing performed by the LDPC encoder 121 is demonstrated.

LDPC codes with coding rates of 6/15 and 7/15 are defined based on the following algorithm.

The LDPC code encodes an information block s=(s ₀ , s ₁ , ..., s _K-1 ), and accordingly, a codeword ∧=(λ ₀ , λ ₁ , ...) of code length N=K+M ₁ +M ₂ . , λ _N-1 )=(λ ₀ , λ ₁ , …, λ _k-1 , p ₀ , p ₁ , …, p _M1+M2-1 ).

However, in the case of a coding rate of 6/15, M ₁ =1080, M ₂ =37800, Q ₁ =3, Q ₂ =105. In addition, in the case of a coding rate of 7/15, M1 ₌ 1080, M2=33480, _Q1 = ₃ , _Q2 =93.

The LDPC encoder 121 calculates the parity bit as follows.

(1) Number 7 is initialized.

[Number 7]

(2) For λ _m (however, m=0, 1, ..., 359), λ _m is accumulated in the parity bit address using the number 8.

[Number 8]

However, x represents the address of the parity bit accumulator corresponding to the first bit λ ₀ . Also, mod denotes a modulo operator (the same hereinafter).

(3) With respect to the 360th information bit λ _L , the address of the parity bit accumulator is given in the second line of the definition based on Tables 7-1 and 7-2 in the case of a coding rate of 6/15, and a coding rate of 7 In the case of /15, it is given in the 2nd line of the definition based on Table 8-1 and Table 8-2. In the same way, the address of the parity bit accumulator for the following λ _m (however, m=L+1, L+2, ..., L+359) is obtained using the number 9.

[Number 9]

However, x represents the address of λ _L , and is a value in the second line of the definition based on Tables 7-1 and 7-2 in the case of a coding rate of 6/15, and Table 8-1 and in the case of a coding rate of 7/15 It is the value of the 2nd line of the definition based on Table 8-2.

(4) In the same way, for each group of 360 new information bits, a new row of definitions based on Table 7-1 and Table 7-2 in the case of the coding rate of 6/15 is added to Table 8 in the case of the coding rate of 7/15. A new row of definitions based on -1 and Table 8-2 is used to find the address of the parity bit accumulator.

(5) After the codeword bits from λ ₀ to λ _K-1 are processed, the operation shown in the number 10 is performed in order starting with i=1.

[Number 10]

(6) Parity bits from _λK to _λK+M1-1 are obtained using the interleaving operation of L=360 shown in Equation 11.

[Wed 11]

(7) For each group of new L=360 codeword bits from _λK to _λK+M1-1 , the address of the parity bit accumulator is A new row of definitions is calculated from the number 12 using a new row of definitions based on Tables 8-1 and 8-2 in the case of a code rate of 7/15.

[Number 12]

However, x represents an address corresponding to the leading sign bit of each group of codeword bits, and in the case of a coding rate of 6/15, the row corresponding to each group of definitions based on Tables 7-1 and 7-2 is It is a value, and in the case of a coding rate of 7/15, it is a value of a row corresponding to each group of definitions based on Tables 8-1 and 8-2.

(8) After the codeword bits from _λK to _λK+M1-1 are processed, parity bits from λK+ _M1 to _λK+M1+M2-1 are obtained using the interleaving operation of L=360 shown in Equation 13.

[Number 13]

(9) Bit λ _i (i=0, 1, ..., N-1) of the codeword is continuously sent to the traversal block permutation unit 210 of the bit interleaver.

An LDPC code with a coding rate of 8/15 is defined by the following algorithm.

(1) The bits of the LDPC codeword are c ₀ , c ₁ , … , c _N-1 , and the first K bits are represented by the number 14 in the same way as the information bits.

[Number 14]

Then, the parity bit p _k = c _{k + K} is calculated by the LDPC encoder 121 as follows.

(2) Number 15 is initialized.

[Number 15]

However, N=64800, K=N×encoding rate.

(3) When k is 0 or more and less than K, let i be the largest integer not greater than the value obtained by dividing k by 360, and let l = k mod 360. For all j, i _k is accumulated as p _{q(i, j, k)} as shown in number 16.

[Number 16]

However, w(i) is the number of elements in the i-th row in the index list based on the definitions based on Tables 9-1 and 9-2.

(4) Process of number 17 is performed for all k of 0<k<N-K.

[Wed 17]

(5) In the above steps, all codeword bits c ₀ , c ₁ , ... , c _N-1 is obtained. The parity interleaver shown in Equation 18 is applied to the last N-K codeword bits.

[Wed 18]

The role of the parity interleaver is to convert the step-like structure of the parity part of the LDPC parity check matrix into a pseudo-traversal structure similar to the information part of the matrix. Parity Interleaved codeword bits c ₀ , c ₁ , … , c _N-1 are sent to the traversal block permutation unit 210 of the bit interleaver.

The parameter q(i, j, 0) represents the j-th entry in the i-th row in the index list based on the definitions based on Tables 9-1 and 9-2, and satisfies the relationship of number 19.

[Wed 19]

The total accumulation is realized by addition with respect to GF(2). In the case of a coding rate of 8/15, R is 84.

<Supplementary (Part 1)>

The present disclosure is not limited to the contents described in the above embodiments, and can be implemented in any form for achieving the purpose of the present disclosure and the purpose related thereto or incidental thereto, for example, it may be understood as follows.

(1) The present disclosure is described by referring to special embodiments described in the accompanying drawings, in particular, by giving examples as values of key parameters N, M, and Q. However, the present disclosure is not limited by any particular combination of these parameters. In fact, the present disclosure applies to any practically relevant combination of values (defining integers) for their parameters, as described in the DVB-T2 standard, or as defined by a similar standard. It is possible.

(2) The present disclosure is not limited to a specific form in order to implement the disclosed method or device in both software and hardware.

In particular, the present disclosure may be embodied in the form of a computer-readable medium embodying computer-executable instructions adapted to cause a computer, microprocessor, microcontroller, etc. to execute all steps of the method according to the disclosed embodiment. .

In addition, the present disclosure may be implemented in the form of an ASIC (Application-Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array).

(3) The present disclosure relates to a digital communication system based on a QC LDPC code and a higher-order constellation. The present disclosure provides a special permutation for rearranging bits of an LDPC code and a special non-uniform constellation for transmitting an interleaved codeword. The permutation and the non-uniform constellation are optimized in cooperation with each other at a coding rate of 6/15, 7/15, or 8/15.

<Supplementary (Part 2)>

A communication method according to the present disclosure, etc. will be summarized.

(1) A first communication method is a data communication method for performing data communication in a digital communication system using a pseudo cyclic low-density parity check code including a repeat-accumulated pseudo cyclic low-density parity check code. A traversal block permutation is performed on a codeword generated based on a check code, the codeword consists of a sequence of N traversal blocks, each of the N traversal blocks consists of Q bits, and N and Q are each It is a positive integer, and the traversing block permutation includes an interleaving step, which is a rearrangement of traversing blocks within the codeword, and a constellation of a non-uniform constellation for each bit of the traversal block permutation-executed codeword. and a constellation mapping step of mapping to points, wherein the traversing block permutation and the non-uniform constellation are selected based on a coding rate of the pseudo traversing low-density parity check code used to generate a codeword.

(2) In the second communication method, in the first communication method,

Non-uniformity 4096 where the coding rate of the pseudo traversing low-density parity check code is 6/15, and the non-uniform constellation is a non-uniform 64-PAM constellation in which real coordinates and imaginary coordinates are respectively given according to Table 2 above. -QAM constellation.

(3) In the third communication method, in the first or second communication method, the coding rate of the pseudo traversing low-density parity check code is 6/15, and the traversing block permutation is defined according to Table 1 above. do.

(4) In a fourth communication method, in the first communication method, a coding rate of the pseudo traversing low-density parity check code is 7/15, and the non-uniform constellation includes the real coordinates and the imaginary coordinates, respectively. A non-uniform 4096-QAM constellation, which is a non-uniform 64-PAM constellation given according to Table 4 of

(5) In the fifth communication method, in the first or fourth communication method, the coding rate of the pseudo traversing low-density parity check code is 7/15, and the traversing block permutation is defined according to Table 3 above. do.

(6) In a sixth communication method, in the first communication method, a coding rate of the pseudo traversing low-density parity check code is 8/15, and the non-uniform constellation includes the real coordinates and the imaginary coordinates, respectively. A non-uniform 4096-QAM constellation, which is a non-uniform 64-PAM constellation given according to Table 6 of

(7) In the seventh communication method, in the first or sixth communication method, the coding rate of the pseudo traversing low-density parity check code is 8/15, and the traversing block permutation is defined according to Table 5 above. do.

(8) In the eighth communication method, in any one of the first to seventh communication methods, the N is 180 and the Q is 360.

(9) In a ninth communication method, in any one of the first to eighth communication methods, the pseudo-circulating parity check code used for generating the codeword includes a plurality of predetermined pseudo-circulating parity check codes having different coding rates from each other. It is selected from among parity check codes.

(10) The first communication device is a communication device in a digital communication system that performs any one of the first to ninth communication methods.

(11) A tenth communication method is a data communication method for performing data communication in a digital communication system using a pseudo cyclic low-density parity check including a repeat-accumulated pseudo traversing low-density parity check code, the pseudo cyclic low-density parity check For each of the complex cells obtained by performing traversing block permutation on a codeword generated based on the code, and constellation mapping of bits of the codeword subjected to traversal block permutation to a non-uniform constellation, the Demapping based on the non-uniform constellation is performed, and the processing opposite to that of the traversal block permutation is performed on the result of the demapping.

(12) The second communication device is a communication device in a digital communication system that performs the tenth communication method.

(Industrial Applicability)

The present disclosure can be used for a BICM system using QC　LDPC code and QAM.

100: transmitter 110: input processing unit
120: BICM encoder 130: OFDM modulator
140: upconverter 150: RF amplifier
121: LDPC encoder 122: bit interleaver
124: QAM mapper 210: traversal block permutation unit
220-1 to 220-12: permutation unit in traversal block

Claims (8)

As a transmission method:
performing traversal block permutation on a codeword generated based on a pseudo traversing low-density parity check code including a repeat-accumulated pseudo traversing low-density parity check code, wherein the codeword includes N traversing blocks, and the N each of the traversal blocks includes Q bits, each of N and Q is a positive integer, and the traversing block permutation is a permutation of the traversing block within the codeword;
mapping each bit of the codeword subjected to the traversal block permutation to any one of constellation points of a non-uniform constellation; and
transmitting the mapped codeword;
The traversing block permutation is optimized for a coding rate of the pseudo traversing low-density parity check code used to generate a codeword and the non-uniform constellation;
If the non-uniform constellation is a non-uniform 4096-QAM constellation composed of two non-uniform 64-PAM constellations having address labels from 0 to 63, the PAM symbol consists of two non-uniform 64-PAM constellations. - have the same real value corresponding to the same address label in each of the PAM constellations,
and the traversing block permutation is defined according to Table 1 when the coding rate of the pseudo traversing low-density parity check code is 7/15.
[Table 1]

The method according to claim 1,
The N is 180, the Q is 360, the transmission method. The method according to claim 1,
and the pseudo iteration low density parity check code used for generating the codeword is selected from a plurality of predetermined pseudo iteration low density parity check codes having different coding rates from each other. A transmitting device comprising:
In operation, an interleaving circuit that performs traversing block permutation on a codeword generated based on a pseudo-traversing low-density parity check code including a repeat-accumulated pseudo-traversing low-density parity check code, wherein the codeword includes N traversal blocks and, each of the N traversing blocks includes Q bits, each of N and Q is a positive integer, and the traversing block permutation is a permutation of a traversing block within the codeword;
a constellation mapping circuit that, in operation, maps each bit of the traversal block permutated codeword to any one of constellation points of a non-uniform constellation; and
and a transmitting circuit that, in operation, transmits the mapped codeword;
The traversing block permutation is optimized for a coding rate of the pseudo traversing low-density parity check code used to generate a codeword and the non-uniform constellation;
If the non-uniform constellation is a non-uniform 4096-QAM constellation composed of two non-uniform 64-PAM constellations having address labels from 0 to 63, the PAM symbol consists of two non-uniform 64-PAM constellations. - have the same real value corresponding to the same address label in each of the PAM constellations,
and the traversing block permutation is defined according to Table 2 when the coding rate of the pseudo traversing low-density parity check code is 7/15.
[Table 2]

As a receiving method:
A traversing block permutation is performed on a codeword generated based on a pseudo traversing low-density parity check code including a repeat-accumulated pseudo traversing low-density parity check code, and each bit of the traversing block permutation is performed. receiving a codeword mapped by non-uniform constellation mapping mapping to any one of the constellation points of the uniform constellation, the codeword including N traversal blocks, and each contains Q bits, each of N and Q are positive integers, and the traversing block permutation is the permutation of the traversing block within the codeword;
non-uniform constellation demapping of each bit of the mapped codeword based on a constellation point of the non-uniform constellation; and
performing a traversal block permutation opposite to the traversal block permutation on the result of the non-uniform constellation demapping;
The reverse traversing block permutation is optimized for a coding rate and non-uniform constellation demapping of the pseudo traversing low-density parity check code used to generate the codeword;
If the non-uniform constellation is a non-uniform 4096-QAM constellation composed of two non-uniform 64-PAM constellations having address labels from 0 to 63, the PAM symbol consists of two non-uniform 64-PAM constellations. - have the same real value corresponding to the same address label in each of the PAM constellations,
and when the coding rate of the pseudo traversing low-density parity check code is 7/15, the reverse traversing block permutation is defined according to Table 3.
[Table 3]

6. The method of claim 5,
The N is 180, the Q is 360, the receiving method. 6. The method of claim 5,
The receiving method, wherein the pseudo-circulating low-density parity check code used for generating the codeword is selected from a plurality of predetermined pseudo-circulating low-density parity check codes having different coding rates from each other. A receiving device, comprising:
In operation, traversing block permutation is performed on a codeword generated based on a pseudo traversing low density parity check code including a repeat accumulated pseudo traversing low density parity check code, and each of the traversing block permutations is performed. A receiving circuit for receiving a codeword mapped by non-uniform constellation mapping that maps bits to any one of the constellation points of the non-uniform constellation, wherein the code word includes N traversal blocks, the N each of the traversal blocks includes Q bits, N and Q are each positive integers, and the traversing block permutation is a permutation of the traversing block within the codeword;
a constellation demapping circuit that, in operation, demaps each bit of the mapped codeword to a non-uniform constellation based on a constellation point of the non-uniform constellation; and
a deinterleaving circuit that, in operation, performs a traversing block permutation opposite to the traversing block permutation on a result of the demapping circuit;
The reverse traversing block permutation is optimized for a coding rate and non-uniform constellation demapping of the pseudo traversing low-density parity check code used to generate the codeword;
If the non-uniform constellation is a non-uniform 4096-QAM constellation composed of two non-uniform 64-PAM constellations having address labels from 0 to 63, the PAM symbol consists of two non-uniform 64-PAM constellations. - have the same real value corresponding to the same address label in each of the PAM constellations,
The receiving apparatus, wherein when the coding rate of the pseudo traversing low-density parity check code is 7/15, the reverse traversing block permutation is defined according to Table 4.
[Table 4]

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