KR20220068364A - Pixel sensing apparatus and panel driving apparatus - Google Patents

Abstract

An embodiment of the present invention provides a pixel sensing circuit which sequentially samples and holds the characteristic voltages of a plurality of pixels with one holding circuit, and scales the held characteristic voltages by using one scaling circuit, and provides a pixel sensing apparatus which has a small size while sensing characteristics of a pixel accurately and quickly through the pixel sensing circuit.

Description

Pixel sensing device and panel driver {PIXEL SENSING APPARATUS AND PANEL DRIVING APPARATUS}

This embodiment relates to a technology for driving a display device.

The display device includes a source driver for driving pixels disposed on the panel.

The source driver determines the data voltage according to the image data, and controls the brightness of each pixel by supplying the data voltage to the pixels.

Meanwhile, even when the same data voltage is supplied, the brightness of each pixel may vary according to characteristics of the pixels. For example, a pixel includes a driving transistor, and if the threshold voltage of the driving transistor changes, the brightness of the pixel changes even if the same data voltage is supplied. If the source driver does not consider the characteristic change of these pixels, the pixels may be driven with an undesired brightness, and a problem of deterioration of image quality may occur.

Specifically, the characteristics of the pixels change according to time or the surrounding environment. At this time, if the source driver supplies the data voltage without considering the changed characteristics of the pixels, a problem of image quality deterioration - for example, a problem such as screen stains - occurs.

In order to improve the problem of image quality degradation, the display device may include a pixel sensing device for sensing characteristics of pixels.

The pixel sensing device may receive an analog signal for each pixel through a sensing line connected to each pixel. Then, the pixel sensing device converts the analog signal into pixel sensing data and transmits it to the timing controller, and the timing controller grasps the characteristics of each pixel through the pixel sensing data. In addition, the timing controller compensates for the image data by reflecting the characteristics of each pixel, thereby improving the problem of image quality deterioration due to pixel deviation.

Meanwhile, the pixel sensing device may include a plurality of channel circuits to measure many pixels disposed on the panel (eg, many pixels of several thousand or more). In addition, each channel circuit may include a circuit for sampling and holding the characteristic voltage of the pixel and a scaling circuit for adjusting the level of the measured characteristic voltage to be suitable for the input range of the analog-to-digital converter. However, since each channel circuit includes a sampling circuit and a scaling circuit, there is a problem in that the size of the pixel sensing device increases. In particular, as the number of pixels disposed in the display device increases with higher resolution of the display device, the problem of increasing the size of the pixel sensing device is further highlighted.

Against this background, an object of the present embodiment is to provide a technique for reducing the size of a pixel sensing device.

In order to achieve the above object, in one aspect, in the present embodiment, in an apparatus for sensing characteristics of pixels disposed on a display panel, a sample and hold method for sequentially sampling and holding characteristic voltages of the pixels according to a sampling signal hold circuit; a scaling circuit for scaling and outputting the level of the characteristic voltage using a switched capacitor amplifier; and an analog-to-digital converter for converting a voltage corresponding to the output of the scaling circuit into digital data.

The sample and hold circuit may hold the characteristic voltage through a first capacitor, and the switched capacitor amplifier may include an amplifier and a second capacitor disposed between one input terminal and an output terminal of the amplifier.

The first capacitor may be connected to the one input terminal of the amplifier, and the level of the characteristic voltage may be scaled according to a ratio of the capacitance of the first capacitor to the capacitance of the second capacitor.

The time constant for the voltage of the second capacitor may be determined as a ratio of the capacitance of the first capacitor to the gain of the amplifier.

The scaling circuit may include a switch for controlling a connection to the sample and hold circuit, and an on-resistance of the switch may be greater than a reciprocal of the gain of the amplifier.

A clock composed of a first time period and a second time period is supplied to the analog-to-digital converter, the sample and hold circuit samples the characteristic voltage in the first time period, and the analog-to-digital converter generates the digital data; , the scaling circuit may scale the level of the characteristic voltage in the second time period.

The switched capacitor amplifier may further include a reset switch connected in parallel to the second capacitor.

In another aspect, in the present embodiment, in the device for sensing the characteristics of pixels disposed on a display panel, the characteristic voltages of the pixels are sequentially applied for each first time period of a clock including a first time period and a second time period a sample and hold circuit for sampling and holding; a scaling circuit for scaling and outputting the level of the characteristic voltage in the second time period; and an analog-to-digital converter for converting a voltage corresponding to the output of the scaling circuit into digital data in the first time period.

The sample and hold circuit may hold the characteristic voltage through a first capacitor, and the scaling circuit may include a second capacitor and a switch controlling a connection between the second capacitor and the first capacitor.

The sample and hold circuit holds the characteristic voltage through a first capacitor and includes a plurality of connection circuits, each connection circuit connecting a point of the pixel and the first capacitor using at least one switch can do it

In another aspect, the present embodiment provides an apparatus for driving a panel in which a plurality of pixels are disposed and a plurality of data lines connected to the pixels and a plurality of sensing lines are disposed. a data driving circuit for supplying the data line; a data processing circuit for compensating the image data using pixel sensing data corresponding to the characteristics of the pixel; and a sample and hold circuit for sequentially sampling and holding characteristic voltages of pixels according to a sampling signal, a scaling circuit for scaling and outputting the level of the characteristic voltage, and converting a voltage corresponding to the output of the scaling circuit into digital data. Provided is a panel driving device including an analog-to-digital converter and a pixel sensing circuit configured to generate the pixel sensing data according to the digital data.

The plurality of pixels includes a first group of pixels and a second group of pixels, the pixel sensing circuit sequentially samples and holds the characteristic voltages of the first group of pixels, and the second group of pixels It is possible to simultaneously sample and hold the characteristic voltage of each of them.

The scaling circuit may scale and output the level of the characteristic voltage using a switched capacitor amplifier.

An ADC (Analog-Digital-Converter) clock composed of a first time period and a second time period is supplied to the analog-to-digital converter, and in the first time period, the sample and hold circuit samples the characteristic voltage and A converter may generate the digital data, and the scaling circuit may scale the level of the characteristic voltage in the second time period.

A clock may be embedded in the image data, and the ADC clock may be generated in synchronization with a clock embedded in the image data.

As described above, according to the present embodiment, it is possible to implement a pixel sensing device having a small size while sensing characteristics of a pixel accurately and quickly.

1 is a block diagram of a display device according to an exemplary embodiment.
FIG. 2 is a diagram illustrating the structure of each pixel of FIG. 1 and signals input/output from the data driving circuit and the pixel sensing circuit to the pixel.
3 is a block diagram of a general pixel sensing circuit.
4 is a block diagram of a pixel sensing circuit according to an exemplary embodiment.
5 is a first exemplary configuration diagram of a pixel sensing circuit according to an embodiment.
6 is a timing diagram of a pixel sensing circuit according to an exemplary embodiment.
7 is a second exemplary configuration diagram of a pixel sensing circuit according to an embodiment.

1 is a block diagram of a display device according to an exemplary embodiment.

Referring to FIG. 1 , the display device 100 may include a panel 110 and panel driving devices 120 , 130 , 140 , and 150 for driving the panel 110 .

A plurality of data lines DL, a plurality of gate lines GL, and a plurality of sensing lines SL may be disposed on the panel 110 , and a plurality of pixels P may be disposed.

The devices 120 , 130 , 140 , and 150 for driving at least one component included in the panel 110 may be referred to as a panel driving device. For example, the data driving circuit 120 , the pixel sensing circuit 130 , the gate driving circuit 140 , and the data processing circuit 150 may be referred to as a panel driving device.

Each of the circuits 120 , 130 , 140 , and 150 described above may be called a panel driving device, and all or a plurality of circuits may be called a panel driving device.

In the panel driving device, the gate driving circuit 140 may supply a scan signal of a turn-on voltage or a turn-off voltage to the gate line GL. When the scan signal of the turn-on voltage is supplied to the pixel P, the pixel P is connected to the data line DL. When the scan signal of the turn-off voltage is supplied to the pixel P, the pixel P and the data line ( DL) is disconnected.

In the panel driving device, the data driving circuit 120 supplies a data voltage to the data line DL. The data voltage supplied to the data line DL is transferred to the pixel P connected to the data line DL according to the scan signal.

In the panel driving device, the pixel sensing circuit 130 receives an analog signal (eg, voltage, current, etc.) formed in each pixel P. The pixel sensing circuit 130 may be connected to each pixel P according to a scan signal, or may be connected to each pixel P according to a separate sensing signal. In this case, a separate sensing signal may be generated by the gate driving circuit 140 .

In the panel driving device, the data processing circuit 150 may supply various control signals to the gate driving circuit 140 and the data driving circuit 120 . The data processing circuit 150 may generate a gate control signal GCS for starting a scan according to timing implemented in each frame and transmit it to the gate driving circuit 140 . In addition, the data processing circuit 150 may output the image data RGB converted from externally input image data to the data signal format used by the data driving circuit 120 to the data driving circuit 120 . Also, the data processing circuit 150 may transmit a data control signal DCS for controlling the data driving circuit 120 to supply a data voltage to each pixel P according to each timing.

The data processing circuit 150 may compensate and transmit the image data RGB according to the characteristics of the pixel P. In this case, the data processing circuit 150 may receive the pixel sensing data S_DATA from the pixel sensing circuit 130 . The pixel sensing data S_DATA may include a measurement value for the characteristic of the pixel P.

Meanwhile, the data driving circuit 120 may be referred to as a source driver. Also, the gate driving circuit 140 may be referred to as a gate driver. Also, the data processing circuit 150 may be referred to as a timing controller. The data driving circuit 120 and the pixel sensing circuit 130 are included in one integrated circuit 125 and may be referred to as a source driver integrated circuit (IC). Also, the data driving circuit 120 , the pixel sensing circuit 130 , and the data processing circuit 150 are included in one integrated circuit and may be referred to as an integrated IC. Although the present embodiment is not limited to these names, descriptions of some commonly known components of a source driver, a gate driver, a timing controller, etc. will be omitted in the description of the embodiment below. Therefore, in understanding the embodiment, it should be considered that some of these components are omitted.

Meanwhile, the panel 110 may be an organic light emitting display panel. In this case, the pixels P disposed on the panel 110 may include an organic light emitting diode (OLED) and one or more transistors. The characteristics of the organic light emitting diode (OLED) and the transistor included in each pixel P may change according to time or a surrounding environment. The pixel sensing circuit 130 according to an exemplary embodiment may sense characteristics of these components included in each pixel P and transmit it to the data processing circuit 150 .

FIG. 2 is a diagram illustrating the structure of each pixel of FIG. 1 and signals input/output from the data driving circuit and the pixel sensing circuit to the pixel.

Referring to FIG. 2 , the pixel P may include an organic light emitting diode (OLED), a driving transistor (DRT), a switching transistor (SWT), a sensing transistor (SENT), and a storage capacitor (Cstg).

The organic light emitting diode (OLED) may include an anode electrode, an organic layer, and a cathode electrode. Under the control of the driving transistor DRT, the anode electrode is connected to the driving voltage EVDD and the cathode electrode is connected to the base voltage EVSS to emit light. More specifically, the organic light emitting diode (OLED) may emit light while the driving current is supplied from the driving voltage (EVDD) side while the driving transistor (DRT) is turned on, and the organic light emitting diode (OLED) is disposed between the anode electrode and the cathode electrode. A voltage according to the characteristic may be formed.

The driving transistor DRT may control the brightness of the organic light emitting diode OLED by controlling the driving current supplied to the organic light emitting diode OLED.

The first node N1 of the driving transistor DRT may be electrically connected to the anode electrode of the organic light emitting diode OLED, and may be a source node or a drain node. The second node N2 of the driving transistor DRT may be electrically connected to a source node or a drain node of the switching transistor SWT, and may be a gate node. The third node N3 of the driving transistor DRT may be electrically connected to the driving voltage line DVL supplying the driving voltage EVDD, and may be a drain node or a source node.

The switching transistor SWT may be electrically connected between the data line DL and the second node N2 of the driving transistor DRT, and may be turned on by receiving a scan signal through the gate lines GL1 and GL2 .

When the switching transistor SWT is turned on, the data voltage Vdata supplied from the data driving circuit 120 through the data line DL is transferred to the second node N2 of the driving transistor DRT.

The storage capacitor Cstg may be electrically connected between the first node N1 and the second node N2 of the driving transistor DRT.

The storage capacitor Cstg may be a parasitic capacitor existing between the first node N1 and the second node N2 of the driving transistor DRT, or may be an external capacitor intentionally designed outside the driving transistor DRT. can

The sensing transistor SENT connects the first node N1 of the driving transistor DRT and the sensing line SL, and the sensing line SL transmits the reference voltage Vref to the first node N1 and An analog signal (eg, voltage or current) formed at the first node N1 may be transmitted to the pixel sensing circuit 130 .

In addition, the pixel sensing circuit 130 measures the characteristics of the pixel P using the analog signal Vsense or Isense transmitted through the sensing line SL.

When the voltage of the first node N1 is measured, the threshold voltage, mobility, current characteristics, and the like of the driving transistor DRT can be grasped. In addition, when the voltage of the first node N1 is measured, the degree of deterioration of the organic light emitting diode OLED such as parasitic capacitance and current characteristics of the organic light emitting diode OLED can be grasped.

The pixel sensing circuit 130 may measure the voltage of the first node N1 and transmit the measured value to the data processing circuit (see 150 of FIG. 1 ). In addition, the data processing circuit (see 150 of FIG. 1 ) may analyze the voltage of the first node N1 to determine the characteristics of each pixel P.

3 is a block diagram of a general pixel sensing circuit.

Referring to FIG. 3 , the pixel sensing circuit 10 may include a plurality of channel circuits 11a to 11n , a multiplexer circuit 12 , and an analog-to-digital converter 13 .

In addition, each of the channel circuits 11a to 11n may include a sample and hold circuit and a scaling circuit. The sample and hold circuit may include one switch S1 and one capacitor C1, and the scaling circuit may include another switch S2 and another capacitor C2. When one switch S1 is closed, the characteristic voltage of the pixel P may be stored in one capacitor C1. And, when one switch S1 is opened and the other switch S2 is closed, one capacitor C1 and the other capacitor C2 share charge, and the voltage of one capacitor C1 may be adjusted. In the drawing, one resistor R1 may be a turn-on resistance of the other switch S2. The charge sharing between one capacitor C1 and the other capacitor C2 may be delayed by one resistor R1.

The pixel sensing circuit 10 samples the characteristic voltage for a plurality of pixels P using the plurality of channel circuits 11a to 11n and scales the level of the characteristic voltage, and then applies the scaled voltage to the multiplexer circuit 12 . It can be transmitted to the analog-to-digital converter 13 one by one through.

In addition, the analog-to-digital converter 13 may convert the transferred voltage into digital data P_DATA.

The pixel sensing circuit 10 has a problem in that it increases in size because each of the channel circuits 11a to 11n includes a sample and hold circuit and a scaling circuit. In particular, the number of pixels arranged in a display device is rapidly increasing according to the recent trend of large area and high resolution, and accordingly, the size of the general pixel sensing circuit 10 is further increased.

4 is a block diagram of a pixel sensing circuit according to an exemplary embodiment.

Referring to FIG. 4 , the pixel sensing circuit 130 may include sample and hold circuits 410 and 420 , a scaling circuit 430 , and an analog-to-digital converter 440 .

The sample and hold circuits 410 and 420 may sequentially sample and hold the characteristic voltages of the pixels P according to the sampling signal SAM. The characteristic voltage may be, for example, the anode voltage of the organic light emitting diode (refer to the OLED of FIG. 2) described with reference to FIG. 2 or the source voltage of the driving transistor (refer to the DRT of FIG. 2). Alternatively, the characteristic voltage may be an integral voltage of a current flowing through the driving transistor (see DRT in FIG. 2 ). To form such an integrated voltage, the sample and hold circuits 410 and 420 may further include an integrator.

The sample and hold circuits 410 and 420 may be divided into a sampling circuit 410 and a holding circuit 420 .

The sampling circuit 410 may select one pixel P among the plurality of pixels P and sample the characteristic voltage of the selected pixel P.

The sampling circuit 410 may include a plurality of connection circuits 411a to 411n. Each of the connection circuits 411a to 411n may be connected to one pixel P, and may transmit a characteristic voltage of the connected pixel P to the holding circuit 420 . Each of the connection circuits 411a to 411n may be sequentially connected to the pixel P according to the sampling signal SAM. For example, the first connection circuit 411a may be connected to the pixel P at the first sampling time, and the second connection circuit 411b may be connected to the pixel P at the second sampling time. In addition, the Nth connection circuit 411n may be connected to the pixel P at an Nth sampling time (N is a natural number equal to or greater than 2).

The sampling circuit 410 may be configured as a sampling switch (not shown). The sampling switch may control the connection between the pixel P and the holding circuit 420 . For example, when the sampling switch is closed, the voltage formed at one node of the pixel P is transferred to the holding circuit 420 . can

The sampling circuit 410 may include an analog front end (AFE) circuit for converting current into voltage. The analog front end circuit may be, for example, an integrator. The integrator may integrate the current flowing through the pixel P to generate an integrated voltage. In addition, the sampling circuit 410 may transmit the integral voltage to the holding circuit 420 according to the sampling signal.

The sampling circuit 410 may select a characteristic voltage of one pixel P at one sampling time and transmit it to the holding circuit 420 .

The holding circuit 420 may sample and hold the characteristic voltage transmitted from the sampling circuit 410 in the holding element. The holding element may be, for example, a capacitor. The holding circuit 420 may include a holding capacitor and hold the characteristic voltage of the pixel P in the holding capacitor.

The holding circuit 420 may match one holding capacitor with respect to the plurality of pixels P sequentially sampled. Characteristic voltages for one pixel P among the plurality of pixels P may be sequentially sampled and held by the holding capacitor according to the sampling signal.

The scaling circuit 430 may scale the level of the characteristic voltage held in the holding circuit 420 . The scaling circuit 430 may include a scaling capacitor, and the level of the characteristic voltage may be scaled using the capacitance relationship between the holding capacitor and the scaling capacitor included in the holding circuit 420 .

The scaling circuit 430 may scale the level of the characteristic voltage according to the scaling signal SCA. The scaling signal SCA may have a signal form inverted from the sampling signal SAM. For example, when the characteristic voltage of one pixel P among the plurality of pixels P is sampled by the holding circuit 420 by the sampling signal SAM, the scaling signal 430 performs a voltage scaling operation. may not Also, when the level of the characteristic voltage in the scaling circuit 430 is scaled according to the scaling signal SCA, the sample and hold circuits 410 and 420 may not sample the characteristic voltage of the pixel P.

The analog-to-digital converter 440 may convert the voltage scaled by the scaling circuit 430 into digital data P_DATA.

The analog-to-digital converter 440 may perform analog-to-digital conversion according to an analog-digital-converter (ADC) clock CLKA. The ADC clock may be composed of a first time period in which the signal has a high voltage level and a second time period in which the signal has a low voltage level. The analog-to-digital converter 440 performs analog-to-digital conversion in the first time period of the ADC clock. can do.

The ADC clock CLKA may be synchronized with a clock embedded in image data. A clock may be embedded in the image data (RGB of FIG. 1 ) described with reference to FIG. 1 . The data driving circuit ( 120 of FIG. 1 ) may receive image data (RGB of FIG. 1 ) and extract an embedded clock from the image data (RGB of FIG. 1 ). Further, the data driving circuit ( 120 of FIG. 1 ) may read a data packet of image data (RGB of FIG. 1 ) according to the extracted embedded clock.

The ADC clock CLKA may be synchronized with this embedded clock. The data driving circuit ( 120 in FIG. 1 ) or the pixel sensing circuit 130 may increase or decrease the frequency of the embedded clock by M times to generate the ADC clock CLKA.

The pixel sensing circuit 130 transmits the generated data to the data processing circuit (150 in FIG. 1). Since the clock at the time of transmission can also be synchronized with the ADC clock, the data processing circuit (150 in FIG. 1) It is possible to recognize the communication clock more accurately. For example, the data processing circuit ( 150 in FIG. 1 ) may generate and transmit an embedded clock using an internal clock. In addition, when the data processing circuit ( 150 of FIG. 1 ) receives data from the pixel sensing circuit 130 , the communication clock can be recognized more accurately by receiving data according to a clock synchronized with the embedded clock.

On the other hand, digital data (P_DATA) generated by the analog-to-digital converter 440 is merged to generate pixel sensing data, and then, by a control circuit (not shown) or a communication circuit (not shown), a data processing circuit (150 in FIG. 1 ) ) can be transmitted.

5 is a first exemplary configuration diagram of a pixel sensing circuit according to an embodiment, and FIG. 6 is a timing diagram of the pixel sensing circuit according to an embodiment.

Referring to FIG. 5 , the pixel sensing circuit 130a may include a sampling circuit 510 , a holding circuit 520 , a scaling circuit 530 , and an analog-to-digital converter 440 .

The sampling circuit 510 may include a plurality of sampling switches SSa, SSb to SSn.

Each of the sampling switches SSa and SSb to SSn may control the connection between the pixels Pa and Pb to Pn and the holding circuit 520 . The first sampling switch SSa controls the connection between the first pixel Pa and the holding circuit 520 , and the second sampling switch SSb controls the connection between the second pixel Pb and the holding circuit 520 . and the N-th sampling switch SSn may control the connection between the N-th pixel Pn and the holding circuit 520 .

The holding circuit 520 may include a holding capacitor CS as a holding element. One end of the holding capacitor CS may be connected to the sampling circuit 510 and the other end may be connected to the ground unit. When the holding capacitor CS is connected to the pixels Pa, Pb to Pn by the sampling circuit 510, characteristic voltages of the pixels Pa, Pb to Pn may be formed in the holding capacitor CS.

The scaling circuit 530 may include a scaling switch SC, a scaling capacitor CC, and the like. The scaling switch SC may control the connection of one side of the holding capacitor CS and one side of the scaling capacitor CC. In addition, one end of the scaling capacitor CC may be connected to the scaling switch SC, and the other end may be connected to the ground unit.

The resistance RC shown between one side of the scaling capacitor CC and the scaling switch CC in the drawing may be a turn-on resistance of the scaling switch CC.

When the scaling switch SC is turned on, charges sampled and held in the holding capacitor CS may be partially transferred to the scaling capacitor CC. By this movement, the voltage of the holding capacitor CS may be adjusted downward.

[Equation 1]

Vsca=Vsam f1(t) CS/(CS+CC)

f1(t)=(1-e^(-t/τ1))

τ1=RC·CC

The scaled voltage Vsca is generated by multiplying the sampled and held characteristic voltage Vsam by a constant scaling factor as shown in Equation (1). Here, the scaling factor may be determined as a value obtained by dividing the capacity of the holding capacitor CS by the sum of the capacity of the holding capacitor CS and the capacity of the scaling capacitor CC.

On the other hand, the first time function f1(t) may affect the scaled voltage Vsca, and the time constant τ1 of the first time function f1(t) is the turn-on resistance ( RC) and the capacity of the scaling capacitor (CC).

The analog-to-digital converter 440 may convert the voltage formed in the scaling capacitor CC into digital data P_DATA.

Referring to FIG. 6 , each component of the pixel sensing circuit 130a may operate according to signals synchronized with the ADC clock.

One cycle of the ADC clock CLKA may include a first time period T1 and a second time period T2. In addition, the sampling signals SAMa, SAMb to SAMn may be synchronized with the first time period T1 in a section having a high voltage level, and each of the sampling signals SAMa, SAMb to SAMn is connected to the ADC clock CLKA. Accordingly, a section having a high voltage level may be sequentially provided.

The scaling signal SCA may have an inverted signal waveform of the ADC clock CLKA. In a section in which the ADC clock CLKA has a high voltage level, the scaling signal SCA may have a low voltage level, and in a section in which the ADC clock CLKA has a low voltage level, the scaling signal SCA may have a high voltage level.

In the first time period T1 , the sample and hold circuits 510 and 520 may sample and hold the characteristic voltage of the pixel in the holding capacitor CS. In addition, in the first time period T1 , the analog-to-digital converter 440 may convert the voltage of the scaling capacitor CC into digital data P_DATA.

Further, in the second time period T2 , the scaling circuit 530 may scale the voltage of the holding capacitor CS and hold the scaled voltage in the scaling capacitor CC.

Each of the sampling switches SSa, SSb to SSn may be closed or opened according to the sampling signals SAMa, SAMb to SAMn, and the scaling switch SC may be closed or opened according to the scaling signal SCA.

7 is a second exemplary configuration diagram of a pixel sensing circuit according to an embodiment.

Referring to FIG. 7 , the pixel sensing circuit 130b may include a sampling circuit 510 , a holding circuit 520 , a scaling circuit 530 , and an analog-to-digital converter 440 .

The sampling circuit 510 may include a plurality of sampling switches SSa, SSb to SSn.

Each of the sampling switches SSa and SSb to SSn may control the connection between the pixels Pa and Pb to Pn and the holding circuit 520 . The first sampling switch SSa controls the connection between the first pixel Pa and the holding circuit 520 , and the second sampling switch SSb controls the connection between the second pixel Pb and the holding circuit 520 . and the N-th sampling switch SSn may control the connection between the N-th pixel Pn and the holding circuit 520 .

The holding circuit 520 may include a holding capacitor CS as a holding element. One end of the holding capacitor CS may be connected to the sampling circuit 510 and the other end may be connected to the ground unit. When the holding capacitor CS is connected to the pixels Pa, Pb to Pn by the sampling circuit 510, characteristic voltages of the pixels Pa, Pb to Pn may be formed in the holding capacitor CS.

The scaling circuit 730 may scale and output the level of the characteristic voltage using a switched capacitor amplifier.

The switched capacitor amplifier may include a scaling capacitor CC and an amplifier AMP. One end of the scaling capacitor CC may be connected to one input terminal of the amplifier AMP - for example, a negative input terminal - and the other end of the scaling capacitor CC may be connected to an output terminal of the amplifier AMP. A reset switch SR may be further disposed in parallel with the scaling capacitor CC, and a ground voltage may be supplied to another input terminal of the amplifier AMP (eg, a positive input terminal).

The scaling circuit 730 may further include a scaling switch SC, which may control a connection between one side of the holding capacitor CS and one input terminal of the amplifier AMP.

When the scaling switch SC is closed, all or part of the charge held in the holding capacitor CS moves to the scaling capacitor CC, and a scaled voltage is formed in the scaling capacitor CC according to the charge transfer. .

[Equation 2]

Vsca=Vsam f2(t) CS/CC

f2(t)=(1-e^(-t/τ2))

τ2=CS/Gm

The scaled voltage Vsca is generated by multiplying the sampled and held characteristic voltage Vsam by a constant scaling factor as shown in Equation (2). Here, the scaling factor can be determined by the ratio of the capacity of the holding capacitor (CS) to the capacity of the scaling capacitor (CC). It can be determined by dividing

The second time function f2(t) may affect the scaled voltage Vsca, and the time constant τ2 of the second time function f2(t) is the gain Gm of the amplifier AMP. It can be determined as a ratio of the capacity of the holding capacitor (CS). To summarize, the time constant τ2 can be determined as a value obtained by dividing the capacity of the holding capacitor (CS) by the gain (Gm) of the amplifier (AMP).

Meanwhile, the scaling switch SC may have a turn-on resistance, and this turn-on resistance may affect the time constant τ1 in the first example described with reference to FIG. 5 . However, in the switched capacitor amplifier structure, the time constant τ2 is mainly affected by the gain Gm of the amplifier AMP.

Here, when the time constant tau 1 and the time constant tau 2 are compared, the equation (3) is obtained.

[Equation 3]

τ1=RC·CC

τ2=CS/Gm

RC > (1/Gm)

Assuming that the difference between the capacity of the holding capacitor (CS) and the capacity of the scaling capacitor (CC) is not large, the difference between the two time constants is determined by the on-resistance (RC) of the scaling switch and the reciprocal of the gain of the amplifier (1/Gm) However, since the gain (Gm) of the amplifier may generally have a fairly large value, the reciprocal (1/Gm) of the gain of the amplifier may be smaller than the on-resistance (RC) of the scaling switch. According to this setting, the time constant τ2 may become smaller than the time constant τ1.

In a structure for sequentially sensing a plurality of pixels Pa, Pb to Pn, a switched capacitor amplifier method having a small time constant may be somewhat advantageous in terms of sensing speed.

Meanwhile, the voltage formed in the scaling capacitor CC through the above-described process may be converted into digital data P_DATA by the analog-to-digital converter 440 .

The timing of the signal applied to the pixel sensing circuit 130b of the second example may be the same as that shown in FIG. 6 .

Referring back to FIG. 6 , each component of the pixel sensing circuit 130b may operate according to signals synchronized with the ADC clock.

One cycle of the ADC clock CLKA may include a first time period T1 and a second time period T2. In addition, the sampling signals SAMa, SAMb to SAMn may be synchronized with the first time period T1 in a section having a high voltage level, and each of the sampling signals SAMa, SAMb to SAMn is connected to the ADC clock CLKA. Accordingly, a section having a high voltage level may be sequentially provided.

The scaling signal SCA may have an inverted signal waveform of the ADC clock CLKA. In a section in which the ADC clock CLKA has a high voltage level, the scaling signal SCA may have a low voltage level, and in a section in which the ADC clock CLKA has a low voltage level, the scaling signal SCA may have a high voltage level.

In the first time period T1 , the sample and hold circuits 510 and 520 may sample and hold the characteristic voltage of the pixel in the holding capacitor CS. In addition, in the first time period T1 , the analog-to-digital converter 440 may convert the voltage of the scaling capacitor CC into digital data P_DATA.

Further, in the second time period T2 , the scaling circuit 630 may scale the voltage of the holding capacitor CS and hold the scaled voltage in the scaling capacitor CC.

Each of the sampling switches SSa, SSb to SSn may be closed or opened according to the sampling signals SAMa, SAMb to SAMn, and the scaling switch SC may be closed or opened according to the scaling signal SCA.

The digital data P_DATA converted in this way are combined to form pixel sensing data, and the pixel sensing data is transmitted to a data processing circuit to be used for image data compensation.

Meanwhile, an example in which characteristic voltages of a plurality of pixels are sampled and held simultaneously in FIG. 3 has been described, and an example in which characteristic voltages of a plurality of pixels are sequentially sampled and held is described in FIGS. 4 to 7 . These examples are mixed and can be used

For example, the plurality of pixels are divided into a first group of pixels and a second group of pixels, and the pixel sensing circuit sequentially samples the characteristic voltages of the pixels of the first group as illustrated in FIGS. 4 to 7 . and holding, as in the example of FIG. 3 , the characteristic voltages of the pixels of the second group may be simultaneously sampled and held.

As described above, according to the present embodiment, it is possible to implement a pixel sensing device having a small size while sensing characteristics of a pixel accurately and quickly.

Claims (15)

An apparatus for sensing characteristics of pixels disposed on a display panel, comprising:
a sample and hold circuit for sequentially sampling and holding the characteristic voltages of the pixels according to a sampling signal;
a scaling circuit for scaling and outputting the level of the characteristic voltage using a switched capacitor amplifier; and
An analog-to-digital converter that converts a voltage corresponding to the output of the scaling circuit into digital data
A pixel sensing device comprising a. According to claim 1,
The sample and hold circuit is
holding the characteristic voltage through a first capacitor,
The switched capacitor amplifier,
A pixel sensing device comprising an amplifier and a second capacitor disposed between an input terminal and an output terminal of the amplifier. 3. The method of claim 2,
The first capacitor is connected to the one input terminal of the amplifier,
A pixel sensing device in which the level of the characteristic voltage is scaled according to a ratio of a capacitance of the first capacitor to a capacitance of the second capacitor. 3. The method of claim 2,
A time constant for the voltage of the second capacitor is determined by a ratio of a capacitance of the first capacitor to a gain of the amplifier. According to claim 1,
The scaling circuit is
a switch for controlling connection to the sample and hold circuit;
A pixel sensing device having an on-resistance of the switch greater than a reciprocal of the gain of the amplifier. According to claim 1,
A clock composed of a first time period and a second time period is supplied to the analog-to-digital converter,
In the first time period, the sample and hold circuit samples the characteristic voltage and the analog-to-digital converter generates the digital data;
A pixel sensing device in which the scaling circuit scales the level of the characteristic voltage in the second time period. 3. The method of claim 2,
The switched capacitor amplifier,
The pixel sensing device further comprising a reset switch connected in parallel with the second capacitor. An apparatus for sensing characteristics of pixels disposed on a display panel, comprising:
a sample and hold circuit for sequentially sampling and holding the characteristic voltages of the pixels for each first time period of a clock including a first time period and a second time period;
a scaling circuit for scaling and outputting the level of the characteristic voltage in the second time period; and
An analog-to-digital converter that converts a voltage corresponding to the output of the scaling circuit into digital data in the first time period
A pixel sensing device comprising a. 9. The method of claim 8,
The sample and hold circuit is
holding the characteristic voltage through a first capacitor,
The scaling circuit is
A pixel sensing device comprising a second capacitor and a switch for controlling a connection between the second capacitor and the first capacitor. 9. The method of claim 8,
The sample and hold circuit is
Holds the characteristic voltage through a first capacitor and includes a plurality of connection circuits,
Each connection circuit is
A pixel sensing device for connecting a point of the pixel to the first capacitor by using at least one switch. A device for driving a panel in which a plurality of pixels are disposed and a plurality of data lines and a plurality of sensing lines connected to the pixels are disposed, the apparatus comprising:
a data driving circuit that converts image data into data voltages and supplies them to the data lines;
a data processing circuit for compensating the image data using pixel sensing data corresponding to the characteristics of the pixel; and
A sample and hold circuit that sequentially samples and holds the characteristic voltage of pixels according to a sampling signal, a scaling circuit that scales and outputs the level of the characteristic voltage, and an analog that converts a voltage corresponding to the output of the scaling circuit into digital data A pixel sensing circuit including a digital converter and generating the pixel sensing data according to the digital data
A panel driving device comprising a. 12. The method of claim 11,
The plurality of pixels includes a first group of pixels and a second group of pixels,
The pixel sensing circuit is
A panel driving device for sequentially sampling and holding the characteristic voltage of the pixels of the first group, and simultaneously sampling and holding the characteristic voltage of the pixels of the second group. 12. The method of claim 11,
The scaling circuit is
A panel driving device for scaling and outputting the level of the characteristic voltage by using a switched capacitor amplifier. 12. The method of claim 11,
ADC (Analog-Digital-Converter) clock composed of a first time period and a second time period is supplied to the analog-to-digital converter,
In the first time period, the sample and hold circuit samples the characteristic voltage and the analog-to-digital converter generates the digital data;
In the second time period, the scaling circuit scales the level of the characteristic voltage. 15. The method of claim 14,
A clock is embedded in the image data,
The ADC clock is generated in synchronization with a clock embedded in the image data.

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