KR20220057400A - Multi-layer Circuit assembly for reducing parasitic inductance - Google Patents

Abstract

The present invention relates to a multilayer circuit structure, and more particularly, to a multilayer circuit structure for reducing parasitic inductance. The multilayer circuit structure according to an embodiment of the present invention includes: a first layer which is formed with a first conductor; and a second layer which is formed with a second conductor formed at a position corresponding to the first conductor. The direction of current flowing in the first conductor can be opposite to the direction of current flowing in the second conductor. The multilayer circuit structure according to the present invention can effectively reduce parasitic inductance by forming multiple electrical paths through which current flows in opposite directions.

Description

Multi-layer Circuit assembly for reducing parasitic inductance

The present invention relates to a multilayer circuit structure, and more particularly, to a multilayer circuit structure for reducing parasitic inductance.

A switch circuit used in a power electronic system requires a high breakdown voltage, normally off operation characteristics, low on resistance, high current characteristics, and high-speed switching. In particular, if a switch circuit capable of high-speed switching is used, the size of the inductor and capacitor of the power electronic system may be reduced. When a switch circuit is manufactured using an element having a normally on operation characteristic, a switch circuit having a high current characteristic can be manufactured due to a low manufacturing cost and a small size. Therefore, a switch circuit in which an element having a low breakdown voltage and normally-off operation characteristics and an element having a high breakdown voltage and normally-on operation characteristic are combined has been studied.

However, when a switch circuit is manufactured using a plurality of elements, parasitic inductance is generated by connecting the plurality of elements. Parasitic inductance is a major cause of hindering the operating speed of the switch circuit. A conventional stacked substrate structure may be configured such that a plurality of layers are stacked, and devices formed on each layer are electrically connected to form one loop. In this case, as at least one of the elements included in the loop is switched at high speed, a parasitic inductance may be induced in the surrounding conductive wire. The induced parasitic inductance has a negative effect on circuit operation, such as inhibiting the switching operation speed of the device. In particular, in order to use a WBG (Wide Band Gap) power semiconductor capable of fast switching, it is essential to reduce the parasitic inductance.

An object of the present invention is to provide a multilayer circuit structure capable of effectively reducing parasitic inductance.

A multilayer circuit structure according to an embodiment of the present invention includes: a first layer on which a first conductor is formed; and a second layer having a second conductor formed at a position corresponding to the first conductor, wherein a direction of a current flowing through the first conductor may be opposite to a direction of a current flowing through the second conductor.

According to an embodiment, a direction of a first main current of the first layer is opposite to a direction of a current flowing through the first conductor, and a direction of a second main current of the second layer is equal to a direction of a current flowing through the first conductor can be the same.

According to an embodiment, two vias are formed inside the first conductor, and two vias are formed outside adjacent to the second conductor, and the first conductor and the second conductor are electrically connected through the vias. can be connected

According to an embodiment, the second conductor may be formed in a convex shape, and vias may be formed on both sides of the convex protrusion portion of the second conductor.

In some embodiments, the first conductor may be formed in a convex shape, and vias may be formed at both ends of the convex non-protruding portion of the first conductor.

In some embodiments, convex shapes of the first conductor and the second conductor may be symmetrically disposed.

According to an embodiment, a third conductor is further formed in the first layer, and a fourth conductor is further formed in a position corresponding to the third conductor in the second layer, and the direction of the current flowing through the third conductor is The direction of the current flowing through the first conductor may be the same as the direction of the current flowing through the fourth conductor.

According to an embodiment, the first conductor and the third conductor are formed to be spaced apart, the directions of current flowing through the first conductor and the third conductor are the same, and flowing between the first conductor and the third conductor The direction of the current may be opposite to the direction of the current flowing through the first conductor.

According to an embodiment, the second conductor and the fourth conductor are formed to be spaced apart, the direction of current flowing through the second conductor and the fourth conductor is the same, and flowing between the second conductor and the fourth conductor The direction of the current may be opposite to the direction of the current flowing through the second conductor.

The multilayer circuit structure according to the present invention can effectively reduce parasitic inductance by forming a plurality of electrical paths through which current flows in opposite directions.

In particular, since the plurality of loops of the integrated circuit structure according to the present invention have different directions of current flowing in adjacent vertical, horizontal, and horizontal directions, parasitic inductance can be effectively reduced.

Effects that can be obtained in the embodiments according to the technical spirit of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned are common knowledge in the technical field to which the technical spirit of the present disclosure belongs from the description below. It will be clearly understood by those who have

In order to more fully understand the drawings recited in the Detailed Description, a brief description of each drawing is provided.
1 is a circuit diagram illustrating a multilayer circuit structure according to an embodiment of the present invention.
2 and 3 are views illustrating a case in which a convex conductor is formed in the multilayer circuit structure according to an embodiment of the present invention.
4 is a diagram illustrating current directions of loops formed in an integrated circuit structure according to an embodiment of the present invention.
5 is a diagram illustrating a PCB to which a multilayer circuit structure according to an embodiment of the present invention is applied.
6 and 7 are simulation results of a multilayer circuit structure according to an embodiment of the present invention.

Exemplary embodiments according to the technical spirit of the present invention are provided to more completely explain the technical spirit of the present invention to those of ordinary skill in the art, and the following embodiments are modified in various other forms may be, and the scope of the technical spirit of the present invention is not limited to the following embodiments. Rather, these embodiments are provided so as to more fully and complete the present disclosure, and to fully convey the technical spirit of the present invention to those skilled in the art.

Although the terms first, second, etc. are used herein to describe various members, regions, layers, regions, and/or components, these members, parts, regions, layers, regions, and/or components refer to these terms. It is self-evident that it should not be limited by These terms do not imply a specific order, upper and lower, or superiority, and are used only to distinguish one member, region, region, or component from another member, region, region, or component. Accordingly, the first member, region, region, or component to be described below may refer to the second member, region, region, or component without departing from the teachings of the present invention. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

Unless defined otherwise, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the concept of the present invention belongs, including technical terms and scientific terms. In addition, commonly used terms as defined in the dictionary should be construed as having a meaning consistent with their meaning in the context of the relevant technology, and unless explicitly defined herein, in an overly formal sense. shall not be interpreted.

As used herein, the term 'and/or' includes each and every combination of one or more of the recited elements.

Hereinafter, embodiments according to the technical spirit of the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram for explaining a multilayer circuit structure according to an embodiment of the present invention, and FIGS. 2 and 3 are a case in which an iron-shaped conductor is formed in the multilayer circuit structure according to an embodiment of the present invention. It is an exemplified drawing.

Referring to FIG. 1 , a stacked circuit structure 100 according to an embodiment of the present invention is a stacked PCB and may include a power source 110 , a first layer 101 , and a second layer 102 .

The power source 110 may be connected to the stacked circuit structure 100 to supply power to the stacked circuit structure 100 . For example, the power source 110 may supply current to an electrical path formed in the first layer 101 and the second layer 102 . That is, the current output from the power source 110 may be supplied to the second layer 102 through the first layer 101 . In this case, one or more conductors may be formed in the first layer 101 , and the directions of currents flowing through adjacent conductors may correspond to opposite directions. In addition, one or more conductors may be formed in the second layer 102 , and directions of currents flowing through adjacent conductors may correspond to opposite directions.

Hereinafter, the conductors formed in the first layer 101 and the second layer 102 and the current flow of each conductor will be described in detail with reference to FIG. 2 .

Referring to FIG. 2 , a first layer 101 in which two conductors, ie, a first conductor 210 and a second conductor 220 are spaced apart, is illustrated. Although the first layer 101 itself may be a conductor, it is not called a 'conductor' in order to distinguish it from the first conductor 210 and the second conductor 220 .

Two or more vias may be formed in the first layer 101 per one formed conductor. In the example of FIG. 2 , a first via 230 - 1 and a second via 230 - 2 are formed inside the first conductor 210 , and a third via 240 is formed on the outside adjacent to the first conductor 210 . -1) and the case in which the fourth via 240-2 is formed is exemplified. In addition, a case in which two vias are formed in the second conductor 220 and two on the adjacent outer side, a total of four vias are exemplified. That is, FIG. 2 exemplifies a case in which four vias are formed per one conductor.

If a separate conductor is not formed in the first layer 101, the direction of the current flowing through the first layer 101 (the direction of the red arrow in FIG. 2) (hereinafter referred to as the first main current direction) will all be the same. However, the first layer 101 includes the first conductor 210 and the second conductor 220 formed so that current flows in a direction opposite to the first main current direction ( a blue arrow direction in FIG. 2 ).

Also, referring to FIG. 2 , a case in which two conductors, ie, a third conductor 250 and a fourth conductor 260 are spaced apart from each other, is exemplified in the second layer 102 as in the first layer 101 . Although the second layer 102 itself may be a conductor, it is not referred to as a 'conductor' in order to distinguish it from the third conductor 250 and the fourth conductor 260 .

Two or more vias may be formed in the second layer 102 per one formed conductor. In the example of FIG. 2 , a fifth via 270-1 and a sixth via 270-2 are formed inside the third conductor 250, and a seventh via 280 adjacent to the third conductor 250 is formed outside. -1) and the case in which the eighth via 280 - 2 are formed are exemplified. Also, a case in which two vias are formed in the fourth conductor 260 and two on the adjacent outer side, a total of four vias are exemplified.

). 또한, 제1 도체(210) 내지 제4 도체(260) 각각의 내부에는 돌출되지 않은 부위의 양단 부분에 형성될 수 있다(

). 따라서, 개별 도체(210, 220, 250, 260)의 돌출 부위 외부 양 옆과 돌출되지 않은 부위의 양단 부분에는 4개의 비아가 형성될 수 있다(

).Meanwhile, the first conductor 210 to the fourth conductor 260 may be formed in an iron shape. In this case, two vias formed on the outside adjacent to each of the first conductors 210 to 260 may be formed on both sides of the convex-shaped protrusion (

). In addition, the first conductors 210 to the fourth conductors 260 may be formed at both ends of the non-protruding portion inside each (

). Accordingly, four vias may be formed on both sides of the outside of the protruding portion of the individual conductors 210 , 220 , 250 and 260 and at both ends of the non-protruding portion (

).

Also, conductors formed on the same layer 101 may be disposed in the same direction. That is, the direction of the protruding portion of the first conductor 210 may be the same as the direction of the protruding portion of the second conductor 220 . Also, the direction of the protruding portion of the third conductor 250 may be the same as the direction of the protruding portion of the fourth conductor 260 .

On the other hand, conductors formed in different layers 101 may be disposed in directions symmetrical to each other. That is, the direction of the protruding portion of the first conductor 210 and the direction of the protruding portion of the third conductor 250 may be opposite to each other, and the direction of the protruding portion of the second conductor 220 and the fourth conductor 260 may be opposite to each other. ) of the protruding portions may be opposite to each other. The first conductor 210 and the third conductor 250 (or the second conductor 220 and the fourth conductor 260) may be formed symmetrically. The vias formed inside and outside the convex shape of each conductor are symmetrically formed so that they can be easily connected to the vias of the corresponding other conductors.

Hereinafter, the flow of currents in the first layer 101 and the second layer 102 will be described.

If a separate conductor is not formed in the first layer 101, the direction of the current flowing through the first layer 101 (the direction of the red arrow in FIG. 2) (hereinafter referred to as the first main current direction) will all be the same. However, the first layer 101 includes the first conductor 210 and the second conductor 220 formed so that current flows in a direction opposite to the first main current direction ( a blue arrow direction in FIG. 2 ). In addition, since the first conductor 210 and the second conductor 220 are formed to be spaced apart, a current corresponding to the first main current direction may flow between the first conductor 210 and the second conductor 220 . .

In addition, if a separate conductor is not formed in the second layer 102 , the direction of the current flowing through the second layer 102 (the blue arrow direction in FIG. 2 ) (hereinafter, 'second main current direction') ') will all be the same. However, in the second layer 102, the third conductor 250 and the second layer 102 are formed so that current flows in a direction opposite to the direction of the second main current ( a red arrow in FIG. 2, which is the same as the direction of the first main current) . 4 conductors 260 are included. In addition, since the third conductor 250 and the fourth conductor 260 are formed to be spaced apart, a current corresponding to the second main current direction may flow between the third conductor 250 and the fourth conductor 260 . .

That is, some of the main current flowing through the first layer 101 is the fourth via 240 - 2 , the seventh via 280-1 , the third conductor 250 , and the eighth via 280 - 2 . ) and the third via 240 - 1 may sequentially flow in the first main current direction. That is, a portion of the main current flowing in the first layer 101 may return to the first layer 101 through the second layer 102 . Similarly, a portion of the main current flowing in the first layer 101 is transferred to the second layer ( After flowing from the fourth conductor 260 of 102 , it may return to the first layer 101 .

In addition, some of the main current flowing through the second layer 102 is the sixth via 270 - 2 , the first via 230 - 1 , the first conductor 210 , and the second via 230 - 2 ) and the fifth via 270-1, may flow in the second main current direction. That is, some of the main current flowing in the second layer 102 may return to the second layer 102 through the first layer 101 . Similarly, a portion of the main current flowing in the second layer 102 is transferred to the first layer ( After flowing from the second conductor 220 of 101 , it may come back to the second layer 102 .

FIG. 3 is a plan view illustrating current flows in the first layer 101 and the second layer 102 . Referring to FIG. 3 , the first main current direction of the first layer 101 is a bottom-up direction, and the second main current direction of the second layer 102 is opposite to the first main current direction from top to bottom. It may be in the direction it is facing.

In addition, a current flows in the same direction 310 as the second main current direction in the first conductor 210 formed in the first layer 101 , and the first conductor 250 is formed in the second layer 102 . It can be seen that the current flows in the same direction 330 as the main current direction.

4 is a diagram illustrating current directions of loops formed in an integrated circuit structure according to an embodiment of the present invention.

A perspective view of the first layer 101 and the second layer 102 is illustrated in FIG. 2 , a plan view of the first layer 101 and the second layer 102 is illustrated in FIG. 3 , and FIG. Cross-sections of the first layer 101 and the second layer 102 are illustrated. Referring to FIG. 4 , it can be seen that the direction 310 of the current flowing through the first conductor 210 is opposite to the directions 320 and 350 of other currents flowing adjacent to the first layer 101 . In addition, it can be seen that the direction 310 of the current flowing through the first conductor 210 is opposite to the direction 330 of the current flowing adjacent to the second layer 102 , that is, the current flowing through the third conductor 250 . . Similarly, it can be seen that the direction 330 of the current flowing through the second conductor 250 is opposite to the directions 340 and 360 of other currents flowing adjacent to the second layer 102 .

That is, the direction of current through any electrical path may be opposite to all directions of current flowing through other adjacent electrical paths 'up, down, left and right'.

Accordingly, even if the power semiconductor switch device (not shown) connected to the stacked circuit structure according to an embodiment of the present invention performs a high-speed switching operation, the parasitic inductance generated thereby may be effectively removed.

5 is a diagram illustrating a PCB to which a multilayer circuit structure according to an embodiment of the present invention is applied.

Referring to FIG. 5 , a PCB to which the first layer 101 and the second layer 102 are applied is illustrated. It can be seen that the conductors are formed at the upper end and lower end of the first layer 101 so that a current in a direction opposite to that of the first main current flows, respectively. In addition, it can be seen that the conductors are formed at the upper end and the lower end of the second layer 102 so that a current in the opposite direction to the second main current flows, respectively, and are formed so as to be symmetrical to the conductor forming direction of the first layer 102 . .

6 and 7 are simulation results of a multilayer circuit structure according to an embodiment of the present invention.

6 and 7 show the turn-off and turn-on of the double pulse test for the case where the multilayer circuit structure 100 according to the present invention is applied and when not, respectively. on) is a graph showing the waveform.

Referring to FIG. 6 , when the multilayer circuit structure 100 according to the present invention is applied, the voltage overshoot between the drain and the source across the switch is reduced from 275 [V] to 243 [V] compared to the case where it is not. , it can be seen that the undershoot of the current also decreased in size from -4.3 [A] to -3.0 [A].

Also referring to 7, when the switch is turned on, when the stacked circuit structure 100 according to the present invention is applied, the voltage undershoot between the drain and the source across the switch compared to the case where the stacked circuit structure 100 is applied. It can be seen that the magnitude decreases from -100 [V] to -69 [V], and the overshoot of the current also decreases in magnitude from 38.6 [A] to 38.4 [A].

As described above, in the multilayer circuit structure according to an embodiment of the present invention, loops having opposite directions of current are formed in the layers adjacent to the top, bottom, left, and right, respectively, to increase the cancellation of magnetic flux, and consequently, the parasitic inductance can be minimized. there is.

Above, the present invention has been described in detail with reference to a preferred embodiment, but the present invention is not limited to the above embodiment, and various modifications and changes by those skilled in the art within the technical spirit and scope of the present invention This is possible.

That is, in the above-described example, the case in which there are two layers (ie, the first layer 101 and the second layer 102) has been described as an example, but three or more layers may be formed. In this case, the first layer 101 and the second layer 102 may be alternately stacked. For example, when three layers are formed, the first layer 101 , the second layer 102 , and the first layer 101 may be sequentially stacked. As another example, when four layers are formed, the first layer 101 , the second layer 102 , the first layer 201 , and the second layer 102 may be sequentially stacked.

In addition, although the multilayer circuit structure according to the present invention has been described with the multilayer PCB as an example in FIG. 2 , the present invention may be applied to both a stacked bus bar and a multilayer circuit structure in which parasitic inductance is generated. Therefore, it is obvious that the scope of the present invention is not limited to the stacked type PCB.

200: laminated substrate assembly
201: first layer
202: second layer

Claims (9)

a first layer on which a first conductor is formed; and
a second layer having a second conductor formed at a position corresponding to the first conductor;
including,
A direction of a current flowing through the first conductor is opposite to a direction of a current flowing through the second conductor.
According to claim 1,
The direction of the first main current of the first layer is opposite to the direction of the current flowing through the first conductor,
and a second main current direction of the second layer is the same as a direction of a current flowing through the first conductor.
According to claim 1,
Two vias are formed inside the first conductor, and two vias are formed outside adjacent to the second conductor, and the first conductor and the second conductor are electrically connected through the vias. struct.
4. The method of claim 3,
The second conductor is formed in a convex shape, and vias are formed on both sides outside the convex protrusion portion of the second conductor.
5. The method of claim 4,
The first conductor is formed in a convex shape, and vias are formed at both ends inside the non-protruding portion of the convex shape of the first conductor.
6. The method of claim 5,
The convex (凸) shape of the first conductor and the second conductor are arranged symmetrically to each other, a multilayer circuit structure.
According to claim 1,
A third conductor is further formed on the first layer,
A fourth conductor is further formed in the second layer at a position corresponding to the third conductor,
The direction of the current flowing through the third conductor is the same as the direction of the current flowing through the first conductor and opposite to the direction of the current flowing through the fourth conductor.
8. The method of claim 7,
The first conductor and the third conductor are formed to be spaced apart, the direction of current flowing through the first conductor and the third conductor is the same, and the direction of the current flowing between the first conductor and the third conductor is the A stacked circuit structure opposite to the direction of the current flowing in the first conductor.
9. The method of claim 8,
The second conductor and the fourth conductor are formed to be spaced apart, the direction of the current flowing through the second conductor and the fourth conductor is the same, and the direction of the current flowing between the second conductor and the fourth conductor is the A stacked circuit structure opposite to the direction of the current flowing in the second conductor.

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