KR20220056388A - Smart reference board device equipped with improved test reliability - Google Patents

Abstract

The present invention relates to a smart information technology (IT) reference board with improved test reliability comprising: a mobile terminal including an application processor for performing an arithmetic operation for an operation such as running a test application and a touch panel for a user interface; a mobile memory connected to an interface of the application processor used as a main memory of the application processor; at least one peripheral device controlled by the application processor and connected to be detached from the interface of the application processor; and a test reliability circuit including a reference voltage transmission unit for outputting a reference voltage according to a change in a driving operation of an external driving voltage. Therefore, the present invention has an effect of providing a reference board capable of outputting a reference voltage according to a change in a driving operation of an external driving voltage, thereby preventing an internal voltage, which should be generated at a specific level, from having a value higher than the specific level by applying a reference voltage at a higher level than the level of an applied reference voltage.

Description

Smart reference board device equipped with improved test reliability}

The present invention relates to a reference board, and more particularly, to a smart IT reference board with improved test reliability.

As the demand for renewable energy increases, the production of solar cells and solar cell arrays is also increasing significantly, and currently, solar power generation systems are being built in a grid-connected type.

Such solar power generation is spotlighted as an alternative energy source in the future because it can be used semi-permanently, maintenance is simple using a solar cell, and uses a pollution-free solar energy source.

However, in order to produce large-capacity photovoltaic electricity, a large number of photovoltaic panels must be installed in a large area. Without detailed monitoring of these multiple photovoltaic panels, whether photovoltaic power generation is operating with appropriate performance or problems arise Therefore, it is not possible to determine whether the efficiency of solar power generation is declining.

Therefore, in order to ensure the efficient operation of an effective photovoltaic power generation system, the need for efficient monitoring of photovoltaic power generation facilities is emerging.

The smart IT reference board that performs this monitoring operation pursues high integration, high performance and low power consumption, and as the integration increases, the internal operating power supply potential is decreasing. In order to determine whether the board or system operates normally or maintains normal data, a process of monitoring the internal power potential through a test and forcing to a desired power level is performed.

During the test, during the power-up sequence of the board or system, a reference voltage of a higher level than the originally applied reference voltage is applied, so that the internal voltage to be generated at a specific level has a value greater than or equal to a specific level, Accordingly, there may be a problem in that the operation reliability of the circuit is lost.

KR 10-0851550 B

The present invention has been proposed to solve the above technical problem, and provides a reference board that outputs a reference voltage according to a change in driving operation of an external driving voltage.

According to an embodiment of the present invention for solving the above problems, a mobile terminal including an application processor for performing arithmetic operations for operations such as execution of a test application, a touch panel for a user interface, and a main memory of the application processor A mobile memory connected to the interface of the application processor, at least one peripheral device controlled by the application processor and detachably connected to the interface of the application processor, and a reference voltage according to a change in the driving operation of the external driving voltage There is provided a reference board including a test reliability circuit unit including a reference voltage transfer unit for outputting .

In addition, the test reliability circuit unit included in the present invention includes a reference voltage transmitting unit that outputs the reference voltage in response to a test mode signal and at least one external driving voltage, and a voltage level output from the reference voltage transmitting unit is set to a predetermined level. It characterized in that it comprises a pumping voltage generator for generating and outputting a pumping voltage when the abnormality.

In addition, the present invention is characterized in that it further includes a power supply noise processing unit connected to the decoupling capacitor connected to the internal circuit unit to reduce the resonance noise caused by the power supply while changing the resistance value.

In addition, the power supply noise processing unit included in the present invention includes an internal circuit unit receiving a power supply voltage and a ground voltage, a decoupling capacitor having one end connected to an input unit of the power supply voltage of the internal circuit unit, and the other end of the decoupling capacitor and an input unit of the ground voltage. The resistance value for reducing resonance noise is variable in response to the power supply voltage or the ground voltage supplied to the internal circuit unit so that the voltage level difference between the power supply voltage or the ground power source and the power supply voltage or the ground power input to the internal circuit unit is minimized. It is characterized in that it includes a variable resistance unit.

In addition, the variable resistor included in the present invention is characterized in that it includes a plurality of resistance elements connected in parallel and a switching element for selecting the plurality of resistance elements.

In addition, the plurality of resistors included in the present invention include a plurality of NMOS transistors having a drain terminal connected to the decoupling capacitor, a source terminal connected to a ground line, a drain terminal connected to the decoupling capacitor, and a source terminal connected to the ground. It is characterized in that it includes an NMOS transistor connected by a line and to which a power supply voltage is applied to a gate terminal.

The reference board according to the embodiment of the present invention can output a reference voltage according to a change in the driving operation of the external driving voltage, so that the internal voltage to be generated at a specific level is applied by applying a reference voltage higher than the applied reference voltage. It can be prevented from having a value above a certain level.

1 is a conceptual diagram of a telemetry photovoltaic power generation test system
2 is a block diagram of the smart IT reference board (1)
3 is a more detailed configuration diagram of the smart IT reference board (1)
4 is a block diagram of the test reliability circuit unit 430 included in the smart IT reference board (1).
5 is a circuit diagram of the reference voltage transfer unit 13 of the test reliability circuit unit 430 according to the first embodiment.
6 is a circuit diagram of the reference voltage transfer unit 13 of the test reliability circuit unit 430 according to the second embodiment.
7 is a circuit diagram of the reference voltage transfer unit 13 of the test reliability circuit unit 430 according to the third embodiment.
8 is a circuit diagram of the power noise processing unit 420 included in the smart IT reference board 1
9 is a first embodiment of the attenuation unit 421 of the power noise processing unit 420 .
10 is a second embodiment of the attenuator 421 of the power noise processing unit 420

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings in order to describe in detail enough that a person of ordinary skill in the art to which the present invention pertains can easily implement the technical idea of the present invention.

1 is a conceptual diagram of a telemetry photovoltaic power generation test system.

Referring to FIG. 1 , a system in which a large number of photovoltaic panels are installed to convert sunlight into electrical energy and store it is proposed.

Through detailed monitoring of such a plurality of solar panels, a system for monitoring whether solar power generation is operating with appropriate performance and whether the efficiency of solar power generation is falling must be established.

That is, in particular, a sensor module for measuring an environment disposed around a solar panel is disposed. For example, a sensor module for measuring panel temperature, panel ambient temperature, sunlight, humidity, and air volume is required.

The data measured by the plurality of sensor modules are transmitted to and processed by the smart IT reference board 1, which is defined as a development board capable of responding to a mobile environment.

On the development board, a test application that can install and test new APs, memory, and peripherals can be installed, and it is configured to be developed corresponding to the Android or iOS operating system, respectively.

Hereinafter, the smart IT reference board 1 will be described in detail.

FIG. 2 is a configuration diagram of the smart IT reference board 1 , and FIG. 3 is a more detailed configuration diagram of the smart IT reference board 1 .

2 and 3, the smart IT reference board 1 is provided with peripheral devices for instructing a compatibility test in the form of a touch panel 163,

It is formed in a structure to which the mobile memory 130 and the nonvolatile memory (flash memory, 130a) can be attached.

In addition, the voice recognition module 161 , the communication module 165 , etc. are configured to be detachably attached to the interface of the application processor 110 .

The smart IT reference board 1 includes a new application processor (AP) and a new mobile memory when applied to the mobile terminal 100, an application processor (AP) and a mobile memory 130, voice A compatibility test between the recognition module 161 and the communication module 165 may be performed.

Therefore, in order to conduct a reliable compatibility test between the application processor (AP), the mobile memory 130 , the touch panel 163 , the voice recognition module 161 , and the communication module 165 , each part is each It is configured to be detachable.

That is, the application processor 110 may be equipped with various types of mobile memory.

For example, when the application processor 110 is newly released, the application processor 110 selectively selects a mobile memory that meets the LPDDR4 (Low Power DDR4) standard and a mobile memory that meets the LPDDR3 (Low Power DDR3) standard. can be applied

Even if the memory 130 for mobile satisfies the standards of DDR3 and DDR4, characteristics for each manufacturer may exist, so the mobile terminal 100 including the new application processor 110 is for mobile to be applied before mass production A mounting test of the memory 130 should be performed.

Therefore, in the smart IT reference board 1 of this embodiment, the mobile memory 130 and the non-volatile memory (flash memory, 130a) are interfaced with the application processor 110 through an interposer or socket. configured to be connected.

For reference, in this embodiment, the method of performing the compatibility test of the memory 130 for mobile is mainly described, but in the same way, various sizes, various standards, and non-volatile memories (flash memory, 130a) and EMMC of various manufacturers (Embedded MultiMediaCard), the voice recognition module 161, and the communication module 165 may be tested for compatibility.

For reference, the method for performing voice recognition in the voice recognition module 161 includes the steps of storing user pronunciation information about the user's voice input to the recognition target whenever the voice recognition for the recognition target fails; The method may include matching user pronunciation information with the highest frequency among user pronunciation information to a recognition target. Through this, it is possible to identify the language of the user with unique pronunciation information. In addition, the voice recognition module 161 may operate in any one selected voice recognition mode from among a plurality of voice recognition modes each divided according to age, gender, a selected day of the week, and a selected time zone.

As described above, the smart IT reference board 1 includes a mobile terminal 100, a mobile memory 130, a memory power supply unit 210, a voice recognition module 161, a communication module 165, a test reliability circuit unit ( 430), and a power source noise processing unit 420 is included.

The mobile terminal 100 includes an application processor 110 that performs arithmetic operations for operations such as execution of a test application, and a touch panel 163 for a user interface.

The mobile memory 130 is used as the main memory of the application processor 110 , and is detachably connected to the interface of the application processor 110 . For example, the mobile memory 130 may be detachably connected to the interface of the application processor 110 through an interposer or a socket.

The memory power supply unit 210 operates to adjust the voltage level of the driving power supplied to the mobile memory 130 according to the control of the test application.

For reference, a plurality of memory power supply units 210 are provided, and according to the operation state of the power supply unit, the power alarm in the memory test is controlled by dualizing it into an alarm mode and a cutoff mode, so that some of the plurality of power supply units has an abnormality. Even if there is, it may be configured so that the memory test can be continued without interruption of the test process.

That is, for example, a backflow prevention diode is provided at each output terminal of the plurality of memory power supplies, and sensing to detect the operation state of the plurality of memory power supplies and generate a signal for indicating the detected operation state of each power supply The unit is provided and has a control logic for classifying and controlling the power state of the test system into a normal mode, an alarm mode and a cut-off mode based on the operation state signal of each power supply unit, the power state of the test system and the operation of each power supply unit An output unit indicating a state may be provided.

The part test application may be stored in storage 140 or ROM 150,

When the mobile terminal 100 is booted, the test operation is performed while being loaded into the mobile memory 130 and accessed by the application processor 110 .

Since the operation process of the test application is displayed on the touch panel 163 , the user can control the test process of the test application or change the test procedure through the touch panel 163 .

For reference, the mobile terminal 100 includes a computer, a portable computer, an Ultra Mobile PC (UMPC), a workstation, a net-book, a PDA, a portable computer, a web tablet, and a wireless phone ( wireless phone, mobile phone, smart phone, digital camera, digital audio recorder, digital audio player, digital picture recorder ), a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting and receiving information in a wireless environment, among various computing systems constituting a home network. It may include at least one, and in this embodiment, it is assumed that the terminal is a smart phone (mobile terminal) type terminal.

In order for the mobile terminal 100 to operate normally, the mobile memory 130 must be mounted. In this embodiment, the mobile memory 130 is detachably mounted from the outside of the mobile terminal 100 , and the mobile memory 130 is 130 is configured to be connected to an interface compatible with the mobile terminal 100 .

The application processor 110 of the mobile terminal 100 may control overall operations of the mobile terminal 100 . For example, the application processor 110 may perform calculation operations for operations such as booting of the mobile terminal 100 , integrity verification, and application execution.

For example, the application processor 110 may include a device integrity verifier (DIV). The terminal integrity verification unit (DIV) is loaded into the memory 130 or accessed from the memory 130 to execute system components, application files executed by the application processor 110, and applications. The integrity values of the required system classes may be extracted and transmitted to the security device 120 .

As a more detailed example, the terminal integrity verification unit (DIV) may extract integrity values of executable files, library files, system modules, system daemons, and the like. For example, the terminal integrity verifier (DIV) may extract the integrity value by hashing the byte values of the verification target files. For example, the terminal integrity verifier (DIV) may perform an integrity verification operation based on a different verification policy according to a booting step or an execution step of the mobile terminal 100 or a verification target.

Exemplarily, the terminal integrity verification unit (DIV) may be implemented in the form of software, hardware, or a combination thereof. Further, the hardware may be an electrical/electronic circuit, a processor, a computer, an integrated circuit, integrated circuit cores, a microelectromechanical system (MEMS), passive components, or a combination thereof.

The software may be machine code, program instructions, firmware, embedded code, application software, or a combination thereof. The terminal integrity verification unit (DIV) implemented in the form of software may be stored in a cache memory in the application processor 110 and driven by the application processor 110 .

The security device 120 may receive an integrity value from the terminal integrity verification unit DIV of the application processor 110 and perform integrity verification on the received integrity value. For example, the security device 120 may include integrity-related data or a key value for each verification target (eg, a system component, an application, a system class, etc.) used in the mobile terminal 100 .

The security device 120 receives the integrity value according to the request of the terminal integrity verifier (DIV), and performs an integrity verification operation based on the received integrity value and related data. The security device 120 may transmit the verification result to the terminal integrity verification unit (DIV).

The security device 120 and the application processor 110 may communicate based on a reliable communication channel or a secure channel. For example, the communication channel may be an encrypted serial communication channel. In addition, the security device 120 may be provided in the form of a system-on-chip (SoC). The security device 120 may be embedded in one integrated circuit and implemented in the form of one chip, one module, or one card. For example, the security device 120 may be included in the application processor 110 .

In addition, the security device 120 may be implemented with a combination of minimum hardware and software required for integrity verification. For example, the security device 120 may be implemented as a calculation processor for performing algorithms such as encryption, decryption, key management, and hashing necessary for integrity verification.

The memory 130 may be used as an operating memory, main memory, buffer memory, or cache memory of the mobile terminal 100 or the application processor 110 . The memory 130 may include random access memory devices such as SRAM, DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, SRAM, PRAM, RRAM, MRAM, and the like.

Files used by the application processor 110 may be loaded into the memory 130 , and files stored in the memory 130 may be accessed by the application processor 110 . The memory 130 may be a cache memory of the application processor 110 .

The storage 140 may store information, data, or files used in the mobile terminal 100 . For example, the storage 140 may store various data such as an application execution file used in the mobile terminal 100 , a boot-loader, a kernel image, an operating system driving file, and the like. For example, the storage 140 may include large-capacity nonvolatile memory devices such as a hard disk and flash memory.

The ROM 150 may store various information or program codes required for the operation of the mobile terminal 100 in the form of firmware. For example, the ROM 150 may include a booting control code required for booting the mobile terminal 100 . For example, data or program code stored in the ROM 150 may be immutable data or program code, and may be data or program code whose integrity has been verified.

The peripheral devices 160 may include interfaces for inputting data or commands to the application processor 110 or outputting data to an external device. Illustratively, the peripheral devices 160 include a user input interface such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, a vibration sensor, a piezoelectric element, or an LCD. User output interfaces such as a liquid crystal display (Liquid Crystal Display), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and a motor may be included.

In addition, the peripheral devices 160 are graphic operation unit (GPU), GPS, heart rate sensor, camera, communication module, geunjo sensor, CIS (cmos image sensor) camera module, touch panel, EMMC (Embedded MultiMediaCard), voice recognition module It may include devices such as 161 and a communication module 165 .

Data from the environmental measurement sensor board 310 of the telemetry photovoltaic test system is received by the communication module 165 , and the data is processed in the test application and displayed on the touch panel 163 .

On the other hand, the smart IT reference board is pursuing high integration, high performance and low power consumption, and as the integration increases, the internal operating power supply potential is decreasing. In order to determine whether the board or system operates normally or maintains normal data, a process of monitoring the internal power potential through a test and forcing to a desired power level is performed.

During the test, during the power-up sequence of the board or system, a reference voltage of a higher level than the originally applied reference voltage is applied, so that the internal voltage to be generated at a specific level has a value greater than or equal to a specific level, Accordingly, there may be a problem in that the operation reliability of the circuit is lost.

Therefore, the proposed reference board 1 includes a test reliability circuit unit 430 .

The test reliability circuit unit 430 generates the pumping voltage VPP after outputting the reference voltage VREF according to the change in the driving operation of the external driving voltage EXT_VDD. The generated pumping voltage VPP may be used as driving power of a memory module such as the memory 130 .

4 is a configuration diagram of the test reliability circuit unit 430 included in the smart IT reference board (1).

Referring to FIG. 4 , the test reliability circuit unit 430 includes a reference voltage transmitting unit 13 and a pumping voltage generating unit 15 .

The reference voltage transfer unit 13 outputs the received reference voltage VREF1 as the output reference voltage VREF_OUT in response to the test mode signal T_MODE and at least one external driving voltage EXT_VDD.

The pumping voltage generating unit 15 generates and outputs the pumping voltage VPP when the voltage level output from the reference voltage transmitting unit 13 is equal to or greater than a predetermined level. The pumping voltage VPP may be supplied to the memory 130 , the memory power supply unit 210 , and the like. Although not shown in the drawing, the pumping voltage generating unit 15 includes a level sensing unit generating an enable signal according to the output reference voltage VREF_OUT, an oscillator operating in response to the enable signal, and an output signal of the oscillator to include a pumping unit for performing a charge pumping operation.

5 is a circuit diagram of the reference voltage transfer unit 13 of the test reliability circuit unit 430 according to the first embodiment.

Referring to FIG. 5 , the reference voltage transfer unit 13 receives the first reference voltage VREF1 according to the operating power of the external driving voltage EXT_VDD1 and outputs the output reference voltage VREF_OUT, and the first buffer unit It includes a 122a, a second buffer unit 124a, and a transfer unit 126a.

The first buffer unit 122a compares the input level of the first reference voltage VREF1 with the external driving voltage EXT_VDD1, and compares the first reference voltage VREF1 output by the comparison with the second external driving voltage EXT_VDD2 ) according to the operating power. In this case, the first buffer unit 122a may be designed as a differential amplifier designed with PMOS transistors T11 and T12 connected in a current mirror type.

The second buffer unit 124a compares the input level of the first reference voltage VREF1 with the third external driving voltage EXT_VDD3 and prevents the input first reference voltage VREF1 from being output by the comparison. In this case, the second buffer unit 124a may be designed as a differential amplifier designed with PMOS transistors T13 and T14 connected in a current mirror type.

When the level of the input test mode signal T_MODE is activated, the transfer unit 126a outputs the first reference voltage VREF1 as the output reference voltage VREF_OUT for forcing, and the input test mode signal ( When the level of T_MODE) is deactivated, the first reference voltage VREF1 is not output. The transmission unit 126a is preferably designed as a transmission gate M11.

Even if the first reference voltage VREF1 is applied before the external driving voltages EXT_VDD1, EXT_VDD2, and EXT_VDD3, the reference voltage transfer unit 13 according to the first embodiment of the present invention maintains the level of the test mode signal T_MODE. In response, the first reference voltage VREF1 is activated and, at the same time, outputted in response to the operating power of the external driving voltages EXT_VDD1, EXT_VDD2, and EXT_VDD3.

Accordingly, when the first reference voltage VREF1 is applied before the external driving voltages EXT_VDD1, EXT_VDD2, and EXT_VDD3 or when the power-up sequence is performed, the loading of the first reference voltage VREF1 causes the external driving voltages EXT_VDD1, EXT_VDD2, and EXT_VDD3 to be applied. Even if the loading is completed before loading, since the first reference voltage VREF1 is output according to the voltage operation of the external driving voltages EXT_VDD1, EXT_VDD2, and EXT_VDD3 through the reference voltage transfer unit 13, the pumping voltage VPP is It does not increase beyond the set value depending on the driving voltage EXT_VDD.

6 is a circuit diagram of the reference voltage transfer unit 13 of the test reliability circuit unit 430 according to the second embodiment.

Referring to FIG. 6 , the reference voltage transfer unit 13 according to the second embodiment outputs the first reference voltage VREF according to the operating power of the external driving voltages EXT_VDD11 and EXT_VDD12, and the first buffer unit ( 122b), a second buffer unit 124b, a first selector 128a, a second selector 128b, and a transfer unit 126b. At this time, the first buffer unit 122b, the second buffer unit 124b, and the transfer unit 126b are the first buffer unit 122a, the second buffer unit 124a, and the transfer unit 126a shown in FIG. 5 . As the same as , redundant description of each configuration will be omitted, and the first and second selection units 128a and 128b will be described.

The first selector 128a is conductive so that the first reference voltage VREF1 is output when the node N13 is at a low level. In this case, the first selector 128a uses the transmission gate M12. The second selector 128b does not conduct so that the first reference voltage VREF1 is not output when the node N16 has a high level.

Accordingly, the first reference voltage VREF1 is applied before the external driving voltages EXT_VDD11 and EXT_VDD12 or the loading of the first reference voltage VREF1 is completed before the loading of the external driving voltages EXT_VDD11 and EXT_VDD12 during the power-up sequence. Even when the first reference voltage VREF1 is output according to the voltage operation of the external driving voltages EXT_VDD11 and EXT_VDD12 through the reference voltage transfer unit 13 , the pumping voltage VPP is applied to the external driving voltage EXT_VDD. It does not increase more than the set value depending on it.

7 is a circuit diagram of the reference voltage transfer unit 13 of the test reliability circuit unit 430 according to the third embodiment.

Referring to FIG. 7 , the reference voltage transfer unit 13 according to the third embodiment includes a reference voltage buffer unit 127 and a voltage transfer unit 129 .

The reference voltage buffer unit 127 compares the levels of the internally generated reference driving voltage IN_VDD and the external driving voltage EXT_VDD, and only when the level of the reference driving voltage IN_VDD is high, the reference driving voltage IN_VDD ) and output the driving voltage to the voltage transfer unit 129 .

The voltage transfer unit 129 outputs and forcing the first reference voltage VREF1 as the output reference voltage VREF_OUT only when the reference driving voltage IN_VDD is at a high level. Here, the voltage transfer unit 129 is preferably designed as an NMOS transistor T25.

Therefore, even if the first reference voltage VREF1 is applied before the external driving voltage EXT_VDD, the first reference voltage VREF is generated as a new output reference voltage VREF_OUT according to the operating power of the external driving voltage EXT_VDD. Because of the output, it is possible to prevent the pumping voltage VPP from increasing beyond a desired level.

Meanwhile, in order to cope with high-function and high-speed operation of electronic device systems in recent years, semiconductor integrated circuits have become more complex and the operation speed of the circuits is also increasing. As circuits constituting semiconductor devices become more complex, parasitic capacitance, parasitic inductance, and parasitic resistance are increasing. Therefore, noise countermeasures for power supply voltage wiring to supply stable power voltage to internal circuits are emerging as an important issue. .

Therefore, the proposed smart IT reference board 1 includes a power noise processing unit 420 . The power source noise processing unit 420 is connected to the decoupling capacitor and serves to reduce resonance noise caused by the power while the resistance value is varied.

8 is a circuit diagram of the power noise processing unit 420 included in the smart IT reference board 1 .

Referring to FIG. 8, the power noise processing unit 420 is electrically connected to the internal circuit unit and the power supply voltage supply pad ( VDD Pad) and the ground voltage supply pad (VSS Pad), and a decoupling capacitor (Cde-cap) connected in parallel with the internal circuit part and connected to the power supply (VDD) line connecting the internal circuit part and the power supply voltage supply pad (VDD Pad). and a variable resistance part (R).

For reference, the internal circuit unit refers to both a peripheral device and a memory device, but in the present embodiment, it is assumed that the memory 130 for mobile is greatly affected by power noise.

Since the voltage value at the location where the internal circuit is located can be expressed as the product of the impedance value at the same location and the operating current consumed by the circuit, if the current consumed by the circuit is determined, eventually the voltage fluctuation is proportional to the size of the impedance value. and, as the parasitic resistance Rde-cap of the decoupling capacitor Cde-cap increases, the impedance value at resonance decreases.

This result is a phenomenon that occurs because the loss in resonance increases as the value of the parasitic resistance (Rde-cap) increases. Similar results can be obtained even when the value of the metal resistance (Rdie) is large, but when the value of the metal resistance (Rdie) increases, Since the voltage drop by DC current becomes large, it is unpreferable.

Therefore, in the present invention, by connecting the series variable resistor R to the decoupling capacitor Cde-cap, the impedance value at resonance is increased similarly to when the parasitic resistance Rde-cap of the decoupling capacitor Cde-cap increases. to limit the voltage drop due to resonance.

The variable resistor unit R connects the decoupling capacitor Cde-cap and the ground (VSS) line so that the level difference between the power supplied to the power voltage supply pad (VDD Pad) and the power input to the internal circuit unit is minimized. It is configured so that it can be used by changing the resistance value.

9 is a first embodiment of the attenuator 421 of the power noise processing unit 420 , and FIG. 10 is a second embodiment of the attenuator 421 of the power noise processing unit 420 .

Referring to FIGS. 9 and 10 , first of all, FIG. 9 is implemented with a plurality of resistance elements R1 to R4 each connected in series with a decoupling capacitor Cde-cap and having a fixed resistance value, through switching on/off The resistance value of the variable resistance unit R may be varied. In this case, it may be preferable to select a resistance element capable of minimizing a voltage drop by using each of the resistance elements R1 to R4 having different resistance values.

Next, FIG. 10 shows a plurality of NMOS transistors T1 to T4 connected to a decoupling capacitor Cde-cap, and an external variable resistance control logic 10 to gates of the plurality of NMOS transistors T1 to T3. It has a structure in which on/off control signals a1, a2, and a3 output from the are input to turn on/off each transistor according to the level of the on/off control signals a1, a2, a3.

At this time, when the levels of the on/off control signals a1, a2, and a3 are all low levels, the connection between the decoupling capacitor Cde-cap and the ground line is released. voltage was applied.

On the other hand, the resistance control unit 10 receives an on/off control signal a1, a2, a3 for turning on or off each of the transistors T1, T2, and T3 connected to the decoupling capacitor Cde-cap. As the output logic, it is enabled by the command signal (COMMAND) from the outside during the training process and outputs a combination of logic levels that each control signal (a1, a2, a3) can have, so that the combination with the least noise can be selected. and input the selected combination of control signals a1, a2, and a3 to the gates of the respective transistors T1, T2, and T3.

Therefore, when the metal resistance value is reduced through the power noise processing device 420 and a problem due to resonance becomes an issue, it is possible to attenuate power noise due to resonance, and accordingly, the driving power of the low-voltage, high-speed operation semiconductor memory is stably processed can do.

In addition, as another embodiment of the variable resistance unit, a switching variable resistance means having a switching operation and a function as a variable resistance element may be used. That is, the switching variable resistance means may include an output pulse generator that generates a variable amplitude output pulse according to a control signal, and a variable resistor that receives a variable amplitude output pulse and changes a switching operation and resistance value.

Also, as another embodiment of the variable resistance unit, when a plurality of resistance segments are included in the variable resistance unit and a plurality of resistance value candidates that the variable resistance unit may have are arranged in an order of magnitude, the plurality of resistance value candidates have the same ratio It may be configured to form a geometric sequence. That is, the variable resistance unit is composed of a plurality of resistance segments and a plurality of switches connected to the plurality of resistance segments, and the plurality of switches are configured to control the resistance of the plurality of resistance segments by using each bit of an N-bit control signal or a combination of each bit. A connection state is controlled, and a resistance value of the variable resistor unit may be determined according to an exponential function based on an N-bit control signal. Therefore, it is easy for the user to intuitively understand the result of the resistance value change through the control code.

The reference board according to the embodiment of the present invention can output a reference voltage according to a change in the driving operation of the external driving voltage, so that the internal voltage to be generated at a specific level is applied by applying a reference voltage higher than the applied reference voltage. It can be prevented from having a value above a certain level.

As such, those skilled in the art to which the present invention pertains will understand that the present invention may be embodied in other specific forms without changing the technical spirit or essential characteristics thereof. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The scope of the present invention is indicated by the following claims rather than the above detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention. do.

Claims (6)

A mobile terminal comprising: an application processor for performing arithmetic operations for operations such as execution of a test application; and a touch panel for a user interface;
a mobile memory connected to an interface of the application processor as a main memory of the application processor;
at least one peripheral device controlled by the application processor and detachably connected to an interface of the application processor; and
a test reliability circuit unit including a reference voltage transmitting unit that outputs a reference voltage according to a change in driving operation of an external driving voltage;
reference board with
According to claim 1,
The test reliability circuit unit,
the reference voltage transfer unit outputting the reference voltage in response to a test mode signal and at least one external driving voltage; and
and a pumping voltage generating unit generating and outputting a pumping voltage when the voltage level output from the reference voltage transmitting unit is greater than or equal to a predetermined level.
According to claim 1,
The reference board further comprising a; power noise processing unit connected to the decoupling capacitor connected to the internal circuit unit to reduce the resonance noise caused by the power supply while the resistance value is variable.
4. The method of claim 3,
The power noise processing unit,
the internal circuit unit receiving a power supply voltage and a ground voltage;
the decoupling capacitor having one end connected to an input unit of the power supply voltage of the internal circuit unit; and
It is connected between the other end of the decoupling capacitor and the input part of the ground voltage, and is supplied to the internal circuit part so that the voltage level difference between the power supply voltage or the ground power and the power supply voltage or the ground power introduced into the internal circuit part is minimized. A reference board comprising: a variable resistance unit having a variable resistance value for reducing resonance noise in response to a power supply voltage or a ground voltage.
5. The method of claim 4,
The variable resistance unit,
a plurality of resistance elements connected in parallel; and
and a switching element that selects the plurality of resistance elements.
6. The method of claim 5,
The plurality of resistive elements,
a plurality of NMOS transistors having a drain terminal connected to the decoupling capacitor and a source terminal connected to the ground line; and
and an NMOS transistor having a drain terminal connected to the decoupling capacitor, a source terminal connected to the ground line, and a power supply voltage applied to a gate terminal.

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