KR20220054143A - Pixel array and image sensor including the same - Google Patents

Abstract

The present invention provides a pixel array with improved optical properties and an image sensor including the same. The pixel array of the image sensor includes a plurality of pixel groups. Each of the pixel groups includes: a plurality of unit pixels including photoelectric transformation elements disposed on a semiconductor substrate, respectively; trench structures vertically extending from a front surface of the semiconductor substrate to the rear surface thereof to be disposed inside the semiconductor substrate in order to electrically and optically isolate the photoelectric transformation elements included in the unit pixels from each other; a common micro lens disposed at an upper portion or a lower portion of the semiconductor substrate to cover the photoelectric transformation elements included in the unit pixels and to concentrate incident light in the photoelectric transformation elements included in the unit pixels. An autofocusing function is implemented and crosstalk between unit cells is suppressed to improve image quality using a pixel group including a plurality of unit cells sharing a micro lens and trench structures extending from a front surface of the semiconductor substrate to the rear surface thereof.

Description

Pixel array and image sensor including the same}

The present invention relates to a semiconductor integrated circuit, and more particularly, to a pixel array supporting an auto-focusing function, and an image sensor including the pixel array.

A CMOS image sensor is a solid-state imaging device using a complementary metal-oxide semiconductor (CMOS). CMOS image sensors have advantages of low manufacturing cost and low power consumption due to a small device size compared to CCD image sensors with high voltage analog circuits. is being mounted

A pixel array constituting a CMOS image sensor includes a photoelectric conversion element such as a photodiode for each pixel. The photoelectric conversion element may generate an electric signal varying according to the amount of incident light, and the CMOS image sensor may process the electric signal to synthesize an image. According to the recent demand for high-resolution images, the pixels constituting the CMOS image sensor are required to be more miniaturized. As the demand for miniaturization increases, incident light may not be properly sensed or noise may be generated due to interference between devices with increased integration. Despite miniaturization of CMOS image sensors, demands for image quality improvement and additional functions are increasing.

SUMMARY OF THE INVENTION An object of the present invention is to provide a pixel array having improved optical characteristics and an image sensor including the pixel array.

In order to achieve the above object, a pixel array according to embodiments of the present invention includes a plurality of pixel groups as a pixel array of an image sensor formed on a semiconductor substrate. Each pixel group of the plurality of pixel groups is configured to electrically and optically isolate a plurality of unit pixels each including photoelectric conversion elements disposed on a semiconductor substrate, and the photoelectric conversion elements included in the plurality of unit pixels. On the upper or lower portion of the semiconductor substrate so as to cover all of the photoelectric conversion elements included in the plurality of unit pixels and trench structures extending in the vertical direction from the front to the rear surface of the semiconductor substrate disposed inside the semiconductor substrate. and a common microlens configured to condense incident light to the photoelectric conversion elements included in the plurality of unit pixels.

In order to achieve the above object, a pixel array according to embodiments of the present invention includes a plurality of pixel groups as a pixel array of an image sensor formed on a semiconductor substrate. Each pixel group of the plurality of pixel groups is configured to electrically and optically isolate a plurality of unit pixels each including photoelectric conversion elements disposed on a semiconductor substrate, and the photoelectric conversion elements included in the plurality of unit pixels. Trench structures extending in a vertical direction from the front side to the back side of the semiconductor substrate and disposed inside the semiconductor substrate, and the photoelectric conversion elements included in the plurality of unit pixels are placed on the upper or lower portion of the semiconductor substrate to cover all of them. a common micro lens disposed and condensing incident light to the photoelectric conversion elements included in the plurality of unit pixels; and

and a color filter disposed between the semiconductor substrate and the common microlens and shared by the plurality of pixels included in each of the pixel groups.

In order to achieve the above object, an image sensor according to embodiments of the present invention includes a pixel array including a plurality of pixel groups configured to collect photocharges generated by incident light and perform a sensing operation, and the pixel array is arranged in a row. and a row driver that drives the unit, and a controller that controls the pixel array and the row driver. Each pixel group of the plurality of pixel groups is configured to electrically and optically isolate a plurality of unit pixels each including photoelectric conversion elements disposed on a semiconductor substrate, and the photoelectric conversion elements included in the plurality of unit pixels. On the upper or lower portion of the semiconductor substrate so as to cover all of the photoelectric conversion elements included in the plurality of unit pixels and trench structures extending in the vertical direction from the front to the rear surface of the semiconductor substrate disposed inside the semiconductor substrate. and a common microlens configured to condense incident light to the photoelectric conversion elements included in the plurality of unit pixels.

A pixel array and an image sensor including the pixel array according to embodiments of the present invention use a pixel group including a plurality of unit pixels sharing a microlens and a trench structure extending from the front to the rear of a semiconductor substrate. It is possible to improve image quality by suppressing crosstalk between unit pixels while implementing the auto-focusing function.

1 is a plan view illustrating a layout of a pixel group included in an image sensor according to embodiments of the present invention.
2A to 2D are cross-sectional views illustrating embodiments of a vertical structure of a pixel group included in an image sensor according to embodiments of the present invention.
3A and 3B are cross-sectional views illustrating embodiments of a trench structure of a pixel group included in an image sensor according to embodiments of the present invention.
4 is a block diagram illustrating an image sensor according to embodiments of the present invention.
5 is a circuit diagram illustrating an embodiment of a unit pixel included in an image sensor according to embodiments of the present invention.
6 is a timing diagram illustrating a sensing operation of an image sensor according to embodiments of the present invention.
7 is a circuit diagram illustrating a pixel group having a shared structure of a floating diffusion region included in an image sensor according to embodiments of the present invention.
8 is a plan view illustrating an embodiment of a layout of the shared structure of FIG. 7 .
9 is a timing diagram illustrating an embodiment of an operation according to a gain in the shared structure of FIG. 7 .
10 is a plan view illustrating a layout of a pixel group included in an image sensor according to embodiments of the present invention.
11A and 11B are cross-sectional views illustrating embodiments of a vertical structure of the pixel group of FIG. 10 .
12 is a plan view illustrating pixel groups employing the shared structure of FIG. 7 .
13A to 14B are diagrams illustrating embodiments of electrical connection of common floating diffusion regions of the pixel groups of FIG. 12 ;
15 is a plan view illustrating a layout of a pixel array according to embodiments of the present invention.
16A to 17B are plan views illustrating embodiments of a 4*4 size unit pattern included in the pixel array of FIG. 15 .
18A to 18C are plan views illustrating embodiments of a unit pattern having a size of 8*8 included in the pixel array of FIG. 15 .
19A and 19B are plan views illustrating embodiments of a unit pattern in which a pixel group and a unit pixel included in the pixel array of FIG. 15 are mixed.
20A to 20C are plan views illustrating exemplary unit patterns in which pixel groups of different sizes included in the pixel array of FIG. 15 are mixed.
21 is a block diagram of an electronic device according to embodiments of the present invention.
22 is a block diagram illustrating a camera module included in the electronic device of FIG. 21 .

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and repeated descriptions of the same components are omitted.

Hereinafter, two directions parallel to and crossing the front and rear surfaces of the semiconductor substrate are defined as a first horizontal direction DR1 and a second horizontal direction DR2, respectively, and a direction substantially perpendicular to the front and rear surfaces of the semiconductor substrate is defined as It is defined in the vertical direction (DR3). The first horizontal direction DR1 may correspond to a row direction and the second horizontal direction DR2 may correspond to a column direction.

The pixel array of the image sensor according to embodiments of the present invention may be formed on a semiconductor substrate and include a plurality of pixel groups as will be described later. In the present disclosure, for convenience of illustration and description, a structure corresponding to BSI (back-side illumination) in which incident light is incident to a rear surface of a semiconductor substrate is mainly described, but embodiments of the present invention are not limited to BSI, and FSI (front-side illumination). It will be understood that embodiments of the present invention may also be applied to side illumination) structures.

1 is a plan view illustrating a layout of a pixel group included in an image sensor according to embodiments of the present invention, and FIGS. 2A to 2D are an embodiment of a vertical structure of a pixel group included in an image sensor according to embodiments of the present invention Cross-sectional views showing examples. Fig. 2a is a cross-sectional view taken along line A-A' in Fig. 1, Fig. 2b is a cross-sectional view taken along line B-B' in Fig. 1, Fig. 2c is a cross-sectional view taken along line HLX of Fig. 1, and Fig. 2d is It is a cross-sectional view taken along the HLY line of FIG. 1 .

1 to 2D , the pixel array may include the semiconductor substrate 100 , the wiring layer 200 , and the light transmitting layer 300 in the vertical direction DR3 . In the case of the BSI structure, the semiconductor substrate 100 may be disposed between the wiring layer 200 and the light transmitting layer 300 . For example, the semiconductor substrate 100 may have a first front surface 100a and a second rear surface 100b opposite to each other, and the wiring layer 200 is disposed on the front surface 100a of the semiconductor substrate 100 , The transmission layer 300 may be disposed under the rear surface 100b of the semiconductor substrate 100 .

The pixel group PXG may include a plurality of unit pixels PX11 , PX12 , PX21 , and PX22 , that is, PX11 to PX22 , trench structures 400 and 500 , and a common micro lens CMLS. The pixel group PXG may be symmetrical with respect to the first horizontal line HLX passing through the center CP of the pixel group PXG and extending in the first horizontal direction DR1 . Also, the pixel group PXG may be symmetrical with respect to a second horizontal line HLY that passes through the center CP and is perpendicular to the first horizontal line HLX. According to an exemplary embodiment, the pixel group PXG may be symmetrical with respect to the vertical line VLZ that passes through the center CP of the pixel group PXG and extends in the vertical direction DR3 .

1 shows a pixel group PXG including four unit pixels PX11 to PX22 arranged in a matrix of two pixel rows PR1 and PR2 and two pixel columns PC1 and PC2 for convenience of illustration and description. ) is shown, the number of pixel rows corresponding to one group row GR and the number of pixel columns corresponding to one group column GC, that is, the number of unit pixels included in one pixel group PXG. The number may be variously determined.

The plurality of unit pixels PX11 to PX22 may each include a plurality of photoelectric conversion elements PD11 , PD12 , PD21 , and PD22 , that is, PD11 to PD22 disposed on the semiconductor substrate 100 . Light incident from the outside may be converted into electrical signals in the photoelectric conversion elements PD11 to PD22.

The trench structures 400 and 500 electrically and optically isolate the photoelectric conversion elements PD11 to PD22 included in the plurality of unit pixels PX11 to PX22 from the front surface 100a to the rear surface of the semiconductor substrate 100 . It may extend up to 100b in the vertical direction DR3 and be disposed inside the semiconductor substrate 100 . The trench structures 400 and 500 are inter-group trench structures 400 separating each pixel group PXG and adjacent pixel groups and a plurality of pixel groups included in each pixel group PXG. Inter-pixel trench structures 500 to isolate (PXG11 to PXG44) from each other may be included.

The inter-pixel trench structures 500 may include a first inter-pixel trench structure 500x and a second inter-pixel trench structure 500y. The first inter-pixel trench structures 500x extend in the first horizontal direction DR1 to be connected to the inter-group trench structures 400 disposed on both sides in the first horizontal direction DR1, and the semiconductor substrate 100 . It may extend in the vertical direction DR3 from the front surface 100a to the rear surface 100b. The second inter-pixel trench structure 500y is connected to the inter-group trench structures 400 disposed on both sides in the second horizontal direction DR2 perpendicular to the first horizontal direction DR1 in a second horizontal direction ( DR2 ) and may extend in the vertical direction DR3 from the front surface 100a to the rear surface 100b of the semiconductor substrate 100 .

The inter-pixel trench structure 500 may prevent incident light incident on each of the plurality of photoelectric conversion elements PD11, PD12, PD21, and PD22 and photocharges generated by the incident light from being incident on adjacent unit pixels. there is. That is, the inter-pixel trench structure 500 may prevent crosstalk between the plurality of photoelectric conversion elements PD11 , PD12 , PD21 , and PD22 . Also, the inter-group trench structure 400 may prevent crosstalk between each pixel group PXG and adjacent pixel groups.

The light transmitting layer 300 may include a color filter CF and a common microlens CMLS. The light transmitting layer 300 may collect and filter light incident from the outside to provide it to the semiconductor substrate 100 . A color filter CF and a common microlens CMLS may be disposed on the rear surface 100b of the semiconductor substrate 100 . In addition, the first planarization layer 310 may be disposed between the second rear surface 100b of the semiconductor substrate 100 and the color filter CF, and the second flat layer 310 may be disposed between the color filter CF and the common microlens CMLS. A flat layer 320 may be disposed.

The color filter CF may include a red, green, or blue color filter. Alternatively, the color filters may include other color filters such as cyan, magenta or yellow. When the unit pixels included in each pixel group PXG have the same color, the unit pixels included in each pixel group PXG may share one color filter CF.

The common microlens CMLS is disposed above or below the semiconductor substrate 100 to cover all of the photoelectric conversion elements PD11 to PD22 included in the plurality of unit pixels PX11 to PX22 and includes the plurality of unit pixels. Incident light may be focused on the photoelectric conversion elements PD11 to PD22 included in the PX11 to PX22.

The wiring layer 200 may include logic transistors electrically connected to the plurality of photoelectric conversion elements PD11, PD12, PD21, and PD22 and wirings connected to the logic transistors. Electrical signals converted by the plurality of photoelectric conversion elements PD11 , PD12 , PD21 , and PD22 may be signal-processed in the wiring layer 200 . The wirings may be stacked with interlayer insulating layers interposed therebetween, and the wirings may be arranged regardless of the arrangement of the plurality of photoelectric conversion elements PD11, PD12, PD21, and PD22. That is, the wirings may cross the upper portions of the plurality of photoelectric conversion elements PD11, PD12, PD21, and PD22.

The semiconductor substrate 100 may be a substrate in which a first conductivity-type epitaxial layer is formed on a first conductivity-type (eg, p-type) bulk silicon substrate. It may be a substrate that has been removed so that only the p-type epitaxial layer remains. Also, the semiconductor substrate 100 may be a bulk semiconductor substrate including wells of the first conductivity type. Alternatively, various types of substrates such as an n-type epitaxial layer, a bulk silicon substrate, and an SOI substrate may be applied to the semiconductor substrate 100 . At least one floating diffusion region is formed in the semiconductor substrate 100 , and transfer gates are provided between each of the photoelectric conversion elements PD11 to PD22 and the floating diffusion region on the front surface 100a of the semiconductor substrate 100 . can be formed. The photoelectric conversion elements PD11 to PD22 may be impurity regions doped with impurities of a second conductivity type (eg, n-type) opposite to the semiconductor substrate 100 . In an example, the photoelectric conversion elements PD11 to PD22 may be adjacent to the first front surface 100a of the semiconductor substrate 100 and may be spaced apart from the rear surface 100b of the semiconductor substrate 100 . More specifically, the photovoltaic elements may be formed by ion implantation of impurities of the second conductivity type (eg, n-type) into the front surface 100a of the semiconductor substrate 100 . The photoelectric conversion elements PD11 to PD22 may have an impurity concentration difference between a region adjacent to the front surface 100a and a region adjacent to the rear surface 100b, and accordingly, the front surface 100a and the rear surface ( 100b) may have a potential gradient between .

Each of the semiconductor substrate 100 of the first conductivity type and the photoelectric conversion elements PD11 to PD22 may constitute a pair of photodiodes. That is, a photodiode may be formed by each junction of the first conductivity type semiconductor substrate 100 and the photoelectric conversion elements PD11 to PD22. The photoelectric conversion elements PD11 to PD22 constituting the photodiode may generate and accumulate photocharges in proportion to the intensity of incident light. In addition, the photodiode may further include a p-type impurity region (not shown) in which the p-type impurity is lightly doped on the surface of the photovoltaic elements.

When the image sensor is not focused, the incident light collected by the common microlens CMLS is non-uniformly incident on the photoelectric conversion elements PD11 to PD22, and thus an electrical signal output from the photoelectric conversion elements PD11 to PD22. will become non-uniform. The image sensor is a focus of a photographing device including an image sensor based on a difference between electrical signals output from the photoelectric conversion elements PD11 to PD22 of the pixel groups PXG11 to PXG44 included in each pixel group PXG It is possible to perform an auto-focusing function to correct

As described above, the pixel array and the image sensor including the pixel array according to embodiments of the present invention include a plurality of unit pixels sharing a microlens and a pixel group including a trench structure extending from the front to the rear of the semiconductor substrate. It is possible to improve image quality by suppressing crosstalk between unit pixels while implementing the auto-focusing function using

3A and 3B are cross-sectional views illustrating embodiments of a trench structure of a pixel group included in an image sensor according to embodiments of the present invention. 3A and 3B are cross-sectional views taken along line A-A' of FIG. 1 . The vertical structure cut along the line B-B' of FIG. 1 is substantially the same as the vertical structure of FIGS. 3A and 3B . Hereinafter, descriptions overlapping those of FIGS. 1 to 2D will be omitted.

The trench structures 400 and 500 may be formed of an insulating material having a lower refractive index than the semiconductor substrate 100 (eg, silicon), and may include one or a plurality of insulating layers. For example, the trench structures 400 and 500 may be formed of a silicon oxide film, a silicon nitride film, an undoped polysilicon film, air, or a combination thereof. The trench structures 400 and 500 may be formed by patterning the front surface 100a and/or the rear surface 100b of the semiconductor substrate 100 to form a deep trench, and then filling the insulating material in the deep trench.

As described above, the trench structures 400 and 500 are the front surface of the semiconductor substrate 100 to electrically and optically isolate the photoelectric conversion elements PD11 to PD22 included in the plurality of unit pixels PX11 to PX22. It may extend in the vertical direction DR3 from 100a to the rear surface 100b and may be disposed inside the semiconductor substrate 100 .

In one embodiment, as shown in FIG. 3A , each of the trench structures 400 , 500 has both sides of the trench coated with a transparent dielectric 410 , 510 and a middle portion of the trench with a transparent dielectric 410 . , 510 and other materials 420 and 520 may be filled. For example, the transparent dielectrics 410 and 510 may be oxides and the middle materials 420 and 520 may be nitrides. That is, each of the trench structures 400 and 500 may have an oxide-nitride-oxide (ONO) structure in a horizontal direction. In another embodiment, each of the trench structures 400 , 500 may have the entire trench filled with a transparent dielectric 420 , 520 .

In one embodiment, as shown in FIG. 3B , each of the trench structures 400 and 500 is an upper trench structure 400t formed by a front trench process performed from the front surface 100a of the semiconductor substrate 100, 500t) and lower trench structures 400b and 500b formed by a back trench process performed from the rear surface 100b of the semiconductor substrate 100 .

According to an embodiment, the upper trench structures 400t and 500t and the lower trench structures 400b and 500b may have different structures or different compositions. For example, as shown in FIG. 3B , both sides of the upper trench structures 400t and 500t are coated with transparent dielectrics 410 and 510 and the middle portion of the trench is different from the transparent dielectrics 410 and 510 . The material 420 and 520 may be filled, and all of the lower trench structures 400b and 500b may be filled with the transparent dielectric 410 and 510 .

4 is a block diagram illustrating an image sensor according to embodiments of the present invention.

Referring to FIG. 4 , the image sensor 600 includes a pixel array 620 , a row driver 630 , and an Analog-to-Digital Conversion (ADC) unit 640 . , a column driver 650 , a controller 660 , and a reference voltage generator (REF) 670 may be included.

The pixel array 620 includes a plurality of pixels 700 that are respectively coupled to the column lines COL, sense incident light, and generate analog signals through the column lines COL. The plurality of pixels may be arranged in a matrix form including a plurality of rows and a plurality of columns. The pixel array 620 may have a structure in which various unit patterns are repeatedly arranged in a first horizontal direction DR1 and a second horizontal direction DR2 as described below with reference to FIGS. 16A to 20C .

The row driver 630 may be connected to each row of the pixel array 620 and generate a driving signal for driving each row. For example, the row driver 630 may drive the plurality of pixels included in the pixel array 620 in units of rows.

The analog-to-digital converter 640 is connected to each column of the pixel array 620 and converts an analog signal output from the pixel array 620 into a digital signal. The analog-to-digital converter 640 includes a plurality of analog-to-digital converters 641, and a column ADC that converts analog signals output for each column line COL into digital signals in parallel (ie, simultaneously). can be done

According to an embodiment, the analog-to-digital converter 640 may include a single correlated double sampling (CDS) unit for extracting an effective signal component. In an embodiment, the correlated double sampling unit may perform analog double sampling for extracting the effective image component based on a difference between the analog reset signal representing the reset component and the analog image signal representing the image component. . In another embodiment, the correlated double sampling unit converts the analog reset signal and the analog image signal into digital signals, respectively, and then extracts the difference between the two digital signals as the effective image component (Digital Double Sampling) can be performed. In another embodiment, the correlated double sampling unit may perform dual correlated double sampling for performing both the analog double sampling and the digital double sampling.

The column driver 650 may sequentially output digital signals from the analog-to-digital converter 640 as output data Dout.

The controller 660 may control the row driver 630 , the analog-to-digital converter 640 , the column driver 650 , and the reference signal generator 670 . The controller 660 provides control signals such as a clock signal and a timing control signal required for the operation of the row driver 630 , the analog-to-digital converter 640 , the column driver 650 , and the reference signal generator 670 . can do. In an embodiment, the controller 660 may include a logic control circuit, a phase lock loop (PLL) circuit, a timing control circuit, a communication interface circuit, and the like.

The reference signal generator 670 may generate a reference signal or a ramp signal having a voltage level that gradually increases or decreases and provides it to the analog-to-digital converter 640 .

5 is a circuit diagram illustrating an embodiment of a unit pixel included in an image sensor according to embodiments of the present invention.

Referring to FIG. 5 , the unit pixel 700a includes a photodiode PD as an optical conversion element, and a transfer transistor TX, a reset transistor RX, a drive transistor DX, and a selection transistor for reading data. (SX) may be included.

For example, the photodiode PD may include an n-type region formed on a p-type semiconductor substrate, and the n-type region and the p-type substrate may be a p-n junction photodiode. The photodiode PD receives light (eg, visible light or infrared light) from the outside, and generates a photo charge based on the received light.

According to an embodiment, the unit pixel 700a may include a phototransistor, a photogate, a pinned photodiode, or the like together with or instead of the photodiode PD.

The photocharge generated by the photodiode PD is transferred to the floating diffusion region FD through the transfer transistor TX. For example, when the transfer control signal TG has a first level (eg, a high level), the transfer transistor TX is turned on, and photocharges generated in the photodiode PD cause the turned-on transfer transistor TX to be turned on. through the floating diffusion area FD.

The drive transistor DX may serve as a source follower buffer amplifier to amplify a signal corresponding to charges charged in the floating diffusion region FD. The selection transistor SX may transmit the amplified signal, that is, the pixel signal Vpix, to the column line COL in response to the selection signal SEL.

The floating diffusion region FD may be reset by the reset transistor RX. For example, the reset transistor RX may discharge the photocharge stored in the floating diffusion region FD in response to the reset signal RS as a constant cycle for a correlated double sampling (CDS) operation. there is.

5 illustrates a unit pixel including one photodiode PD and four transistors TX, RX, DX, and SX, but embodiments according to the present invention are not limited thereto.

6 is a timing diagram illustrating a sensing operation of an image sensor according to embodiments of the present invention.

6 illustrates a sensing period tRPR that is performed corresponding to a sensing operation for one pixel. Such a sensing operation may be simultaneously performed in parallel with respect to a plurality of pixels corresponding to the same transmission control signal TG.

4 to 6 , at time t1 , the row driver 630 provides a row selection signal SEL activated to a logic high level to the pixel array 620 to a plurality of pixels included in the pixel array 620 . Select one pixel row from among the rows.

At time t2, the row driver 630 provides a reset control signal RS to the selected pixel row, and the controller 660 converts an up-down control signal UD having a logic high level to the analog-to-digital converter 641 . ) is provided to a plurality of counters included in At this time, the pixel signal Vpix output from the pixel array 620 becomes the first analog signal representing the reset component.

At time t3, the controller 660 provides the count enable signal CNT_EN having a logic high level to the reference signal generator 670, and the reference signal generator 670 sets the voltage level of the reference signal Vref. It begins to decrease with a constant magnitude of the slope (a). In addition, the controller 660 provides the count clock signal CLKC to the plurality of counters, and each of the plurality of counters starts a down counting operation in synchronization with the count clock signal CLKC.

At time t4, the voltage levels of the reference signal Vref and the pixel signal Vpix become the same, and the comparison signal CMP output from the comparator included in the analog-to-digital converter 641 transitions to a logic low level and goes down. The counting operation ends. At this time, the counting value (-2) corresponding to the reset component (Vrst) is stored in the counter.

At time t5, when the count enable signal CNT_EN is inactivated to a logic low level, the reference signal generator 70 is disabled. A section from time t3 to time t5 represents a maximum section for counting the reset component Vrst and may be set to correspond to an appropriate number of clock cycles according to characteristics of the image sensor.

At time t6, the row driver 630 provides a transfer control signal TG to the selected pixel row, and the controller 660 provides an up-down control signal UD having a logic low level to the counters. In this case, the pixel signal Vpix output from the pixel array 620 becomes a second analog signal representing an image component according to the incident light.

At time t7, the controller 660 again provides the count enable signal CNT_EN having a logic high level to the reference signal generator 670, and the reference signal generator 670 controls the voltage level of the reference voltage Vref. begins to decrease with a slope (a) of the same magnitude as at time t3. In addition, the controller 660 provides the count clock signal CLKC to the counters, and each of the counters is synchronized with the count clock signal CLKC to initiate an up-counting operation.

At time t8, the voltage levels of the reference signal Vref and the pixel signal Vpix become the same, and the comparison signal CMP output from the comparator transitions to a logic low level, thereby ending the up-counting operation. Finally, the counter stores a digital value (Vsig=15) corresponding to the difference between the first analog signal representing the reset component (Vrst=2) and the second analog signal representing the image component (Vrst+Vsig=17) according to the incident light. and a digital value (Vsig=15) is output as a digital signal DS representing an effective component of the incident light.

At time t9, when the count enable signal CNT_EN is inactivated to a logic low level, the reference signal generator 670 is disabled. A section from time t7 to time t9 represents a maximum section for counting image components (Vrst+Vsig) and may be set to correspond to an appropriate number of clock cycles according to characteristics of the image sensor.

At time t10 , the row driver 630 provides the pixel array 620 with the inactivated row select signal SEL at a logic low level to deselect the selected pixel row. Also, each of the counters resets the stored counting value.

Thereafter, the image sensor 600 outputs a digital signal in units of rows while repeating the above-described operation for other rows.

The configuration and sensing operation of an exemplary image sensor have been described above with reference to FIGS. 4 to 6 to help the understanding of the present invention, but embodiments of the present invention are not limited thereto.

7 is a circuit diagram illustrating a pixel group having a shared structure of a floating diffusion region included in an image sensor according to embodiments of the present invention, and FIG. 8 is a plan view illustrating an embodiment of a layout of the shared structure of FIG. . 7 and 9 illustrate a pixel group having a shared structure in which four pixels are connected to one common floating diffusion region CFD.

4 and 6 , the pixel group PXG includes a common floating diffusion area CFD, a first pixel PX1 , a second pixel PX2 , a third pixel PX3 , and a fourth pixel PX4 . and a read circuit 800 . According to an embodiment, the pixel group PXG may further include an analog-to-digital conversion unit (ADC) 810 . The first pixel PX1 , the second pixel PX2 , the third pixel PX3 , and the fourth pixel PX4 are commonly connected to the common floating diffusion area CFD. In the pixel array of the image sensor, the pixel group PXG as shown in FIGS. 7 and 8 may be repeatedly disposed in the first horizontal direction DR1 and the second horizontal direction DR2 .

The control signals TG1, TG2, TG3, TG4, RS, and DCG provided to the pixel group PXG may be transmitted from the row driver 630 of FIG. 4 through the lines MW in the row direction X. there is.

The first pixel PX1 may include a first photodiode PD1 and a first transfer transistor TX1 . The second pixel PX2 may include a second photodiode PD2 and a second transfer transistor TX2 . The third pixel PX3 may include a third photodiode PD3 and a third transfer transistor TX3 . The fourth pixel PX4 may include a fourth photodiode PD4 and a fourth transfer transistor TX4. In FIG. 8 , G1 , G2 , G3 , and G4 indicate transfer gates of the first to fourth transfer transistors TX1 , TX2 , TX3 and TX4 , respectively.

The read circuit 800 may include a reset transistor RX, a gain control transistor GX, a capacitor Cdcg, a source follower transistor or a driving transistor DX, and a selection transistor SX. 7 exemplifies a structure in which each pixel includes one transistor and a read circuit includes three transistors for convenience of description, but it will be understood that embodiments of the present invention may be applied to various other configurations.

The reset transistor RX is connected between the reset voltage VRST and the gain control node Ndcg and may be switched in response to the reset signal RS. The gain control transistor GX is connected between the gain control node Ndcg and the common floating diffusion node CFD and may be switched in response to the gain control signal DCG. The capacitor Cdcg may be connected in parallel with the reset transistor RX between the reset voltage VRST and the gain control node Ndcg.

As described with reference to FIG. 9 , different gains may be implemented using the gain control transistor GX and the capacitor Cdcg.

9 is a timing diagram illustrating an embodiment of an operation according to a gain in the shared structure of FIG. 7 .

7, 8 and 9 , when the common floating diffusion region CFD is reset, both the reset transistor RX and the gain control transistor GX may be turned on.

When the voltage of the common floating diffusion region CFD is read with a first gain (low gain), the reset transistor RX may be turned off and the gain control transistor GX may be turned on. When the voltage of the common common floating diffusion region CFD is read with a second gain higher than the first gain, both the reset transistor RX and the gain control transistor GX may be turned off.

The pixel signal Vpix output from the pixel array may include shot noise that increases according to ambient light and circuit noise that occurs according to circuit characteristics inside the pixel array. When the gain is increased by using the aforementioned gain control transistor GX and capacitor Cdcg or by means outside the pixel array, since noise also increases, sensing sensitivity, that is, signal-to-noise ratio (SNR, signal-to-noise ratio) -noise ratio) is insignificant.

10 is a plan view illustrating a layout of a pixel group included in an image sensor according to embodiments of the present invention, and FIGS. 11A and 11B are cross-sectional views illustrating embodiments of a vertical structure of the pixel group of FIG. 10 . 11A and 11B are cross-sectional views taken along line HLX of FIG. 1 . The vertical structure cut along the HLY line of FIG. 1 is substantially the same as the vertical structure of FIGS. 11A and 11B . Hereinafter, descriptions overlapping those of FIGS. 1 to 2D will be omitted.

As described above, the inter-pixel trench structures 501 may include a first inter-pixel trench structure 501x and a second inter-pixel trench structure 501y. The first inter-pixel trench structures 501x extend in the first horizontal direction DR1 to be connected to the inter-group trench structures 400 disposed on both sides in the first horizontal direction DR1 and the semiconductor substrate 100 . It may extend in the vertical direction DR3 from the front surface 100a to the rear surface 100b. The second inter-pixel trench structures 501y are connected to the inter-group trench structures 400 disposed on both sides in the second horizontal direction DR2 perpendicular to the first horizontal direction DR1 in a second horizontal direction ( DR2 ) and may extend in the vertical direction DR3 from the front surface 100a to the rear surface 100b of the semiconductor substrate 100 .

Referring to FIG. 10 , in the pixel group PXG4 , with respect to the intersection region CREG where the first inter-pixel trench structure 501x and the second inter-pixel trench structure 501y intersect, the first inter-pixel At least a portion of a portion corresponding to the intersection region CREG of the trench structure 501x and the second inter-pixel trench 501y may be removed. For example, the ratio of the removed horizontal length of the first inter-pixel trench structure 501x and the second inter-pixel trench structure 501y to the width of the unit pixel may be 0.15 to 0.40. Electrons may pass between unit pixels through the removed portion of the intersection region CREG, which may be controlled by a removed length and a potential profile formed in the semiconductor substrate 100 according to a manufacturing process.

In one embodiment, as shown in the pixel group PXG5 shown in FIG. 11A , a portion corresponding to the intersection region CREG of the first inter-pixel trench structure 501x and the second inter-pixel trench structure 501y is All of the semiconductor substrate 100 may be removed in the vertical direction DR3 from the front surface 100a to the rear surface 100b.

In one embodiment, as shown in the pixel group PXG6 shown in FIG. 11B , a portion corresponding to the intersection region CREG of the first inter-pixel trench structure 501x and the second inter-pixel trench structure 501y is Only a portion may be removed from the front surface 100a of the semiconductor substrate 100 .

In the removed portion of the intersection region CREG, a common floating diffusion region ( CFD) may be formed.

12 is a plan view illustrating pixel groups adopting the shared structure of FIG. 7 .

The dotted circles shown in FIG. 12 represent common microlenses CMLS shared by a plurality of pixels as described above. For convenience of illustration, only the four pixel groups PXG11 to PXG22 arranged in a matrix of two group rows GR1 and GR2 and two group columns GC1 and GC2 are shown in FIG. 12 , but the pixels of the image sensor Pixel groups may be repeatedly arranged in the first horizontal direction DR1 and the second horizontal direction DR2 in the array.

Referring to FIG. 12 , each of the pixel groups PXG11 to PXG22 may include four unit pixels arranged in a matrix of two pixel rows and two pixel columns. Each of the pixel groups PXG11 to PXG22 may include common floating diffusion regions CFD11 to CFD22 disposed in the aforementioned crossing region and shared by four pixels, respectively.

13A to 14B are diagrams illustrating embodiments of electrical connection of common floating diffusion regions of the pixel groups of FIG. 12 ; 13C is a cross-sectional view taken along line C-C' of FIG. 13B.

As shown in FIG. 13A , four common floating diffusions of four pixel groups PXG11 to PXG22 are arranged in a matrix form of two group rows GR1 and GR2 and two group columns GC1 and GC2 . The regions CFD11 to CFD22 may be electrically connected to each other by the first conductive lines MLN1 . Also, as illustrated in FIG. 13B , the first conductive lines MLN1 may be electrically connected to each other by at least one second conductive line MLN2 .

Referring to FIG. 13C , the first conductive lines MLN1 and the second conductive lines MLN2 may be disposed on the front surface 100a of the semiconductor substrate 100 , that is, on the wiring layer 200 , and may It may be electrically connected to the common floating diffusion regions CFD11 to CFD22 through the same vertical contacts VC. Although FIG. 13C illustrates an example in which the first conductive lines MLN1 and the second conductive line MLN2 are disposed on different conductive layers, the first conductive lines MLN1 and the second conductive line MLN2 according to exemplary embodiments may be illustrated in FIG. 13C . The line MLN2 may be disposed on the same conductive layer.

Electrical connection of the common floating diffusion regions CFD11 to CFD22 may be implemented in various ways. For example, as shown in FIGS. 14A and 14B , two common floating diffusion regions CFD11 and CFD12 are electrically connected by one first conductive line MLN1 and the other two common floating diffusion regions CFD11 and CFD12 are electrically connected to each other as shown in FIGS. 14A and 14B . The fusion regions CFD21 and CFD22 may be electrically connected by another first conductive line MLN1 , and these two conductive lines MLN1 may be electrically connected by second conductive lines MLN2 . there is.

15 is a plan view illustrating a layout of a pixel array according to embodiments of the present invention.

15 , the pixel array 620 included in the image sensor 600 of FIG. 4 repeats in a first horizontal direction DR1 and a second horizontal direction DR2 perpendicular to the first horizontal direction DR1. It may be divided into unit patterns UPTT that are arranged in the following manner. As described above, the unit patterns UPTT may include two or more pixel groups in which a plurality of unit pixels share one common micro lens CMLS.

In an embodiment, all of the unit patterns UPTT may be the same. In this case, each unit pattern UPTT corresponds to a pattern of a minimum unit that cannot be divided into smaller units. In another embodiment, the unit patterns UPTT may include two or more different patterns, and the different patterns may be regularly arranged in the first horizontal direction DR1 and/or the second horizontal direction DR2. can

Hereinafter, embodiments of various color filter arrangements and unit patterns corresponding to various pixel groups will be described with reference to FIGS. 16A to 20C . According to exemplary embodiments, patterns to be described later may be inverted in the first horizontal direction DR1 and/or the second horizontal direction DR2 or may be rotated by 90 degrees or 180 degrees about the vertical direction DR3.

16A to 20C , a unit pixel corresponding to a red filter is a red pixel (R), a unit pixel corresponding to a green filter is a green pixel (G), a unit pixel corresponding to a blue filter is a blue pixel (B), and a yellow filter is used. A unit pixel corresponding to , is referred to as a yellow pixel (Y), and a unit pixel corresponding to the cyan filter is referred to as a cyan pixel (C). The white pixel W corresponds to a unit pixel in which a color filter is not provided. In the pixel group PXGij, i denotes an index of a group row, and j denotes an index of a group column. When the unit pixels included in each pixel group PXG have the same color, the unit pixels included in each pixel group PXG may share one color filter CF.

16A to 17B are plan views illustrating embodiments of a 4*4 size unit pattern included in the pixel array of FIG. 15 .

16A to 17B , each of the unit patterns UPTT1 to UPTT7 having a size of 4*4 is arranged in a matrix form of two group rows GR1 and GR2 and two group columns GC1 and GC2. It may include first to fourth pixel groups PXG11 to PXG22. Each of the first to fourth pixel groups PXG11 to PXG22 may include four unit pixels arranged in a matrix of two pixel rows and two pixel columns.

In an embodiment, like the unit pattern UPTT1 of FIG. 16A , the first pixel group PXG11 includes four red pixels R, and the second and third pixel groups PXG12 and PXG21 Each may include four green pixels G, and the fourth pixel group PXG22 may include four blue pixels B.

In an embodiment, like the unit pattern UPTT2 of FIG. 16B , each of the first to fourth pixel groups PXG11 to PXG22 may include four white pixels W. As shown in FIG.

In an embodiment, like the unit pattern UPTT3 of FIG. 16C , the first pixel group PXG11 includes four red pixels R, and the second pixel group PXG12 includes four green pixels ( G), the third pixel group PXG21 may include four white pixels W, and the fourth pixel group PXG22 may include four blue pixels B.

In an embodiment, like the unit pattern UPTT4 of FIG. 16D , the first pixel group PXG11 includes four red pixels R, and the second and third pixel groups PXG12 and PXG21 Each may include four yellow pixels Y, and the fourth pixel group PXG22 may include four blue pixels B.

In an embodiment, like the unit pattern UPTT5 of FIG. 16E , the first pixel group PXG11 includes four red pixels R, and the second and third pixel groups PX12 and PX21 Each may include four yellow pixels Y, and the fourth pixel group PXG22 may include four cyan pixels C. Referring to FIG.

In an embodiment, like the unit pattern UPTT6 of FIG. 17A , the first pixel group PXG11 includes two white pixels W and two red pixels R, and the second and third Each of the pixel groups PXG12 and PXG21 includes two white pixels W and two green pixels G, and the fourth pixel group PXG22 includes two white pixels W and 2 It may include four blue pixels (B).

In an embodiment, as in the unit pattern UPTT7 of FIG. 17B , each of the first and fourth pixel groups PXG11 and PXG22 includes two white pixels W, one green pixel G, and one 2 red pixels R, and each of the second and third pixel groups PXG12 and PXG21 includes two white pixels W, one green pixel G, and one blue pixel B may include

18A to 18C are plan views illustrating embodiments of a unit pattern having a size of 8*8 included in the pixel array of FIG. 15 .

Referring to FIGS. 18A to 18C , each of the unit patterns UPTT8 to UPTT10 having a size of 8*8 includes the first to fourth group rows GR1 to GR4 and the first to fourth group columns GC1 to GC4 . It may include first to sixteenth pixel groups PXG11 to PXG44 arranged in a matrix form. The first to fourth pixel groups PXG11 , PXG12 , PXG21 , and PXG22 are in the first group row GR1 , the second group row GR2 , the first group column GC1 , and the second group column GC2 . arranged in a matrix form. The fifth to eighth pixel groups PXG13 , PXG14 , PXG23 , and PXG24 are in the first group row GR1 , the second group row GR2 , the third group column GC3 , and the fourth group column GC4 . arranged in a matrix form. The ninth to twelfth pixel groups PXG31 , PXG32 , PXG41 , and PXG42 are of the third group row GR3 , the fourth group row GR4 , the first group column GC1 , and the second group column GC2 . arranged in a matrix form. The thirteenth to sixteenth pixel groups PXG33, PXG34, PXG43, and PXG44 are of the third group row GR3, the fourth group row GR4, the third group column GC3, and the fourth group column GC4. arranged in a matrix form. Each of the first to sixteenth pixel groups PXG11 to PXG44 may include four unit pixels arranged in a matrix of two pixel rows and two pixel columns.

In an embodiment, like the unit pattern UPTT8 of FIG. 18A , each of the first to fourth pixel groups PXG11 , PXG12 , PXG21 , and PXG22 includes four red pixels R, and a fifth Each of the thirteenth to twelfth pixel groups PXG13, PXG14, PXG23, PXG24, PXG31, PXG32, PXG41, and PXG42 includes four green pixels G, and the thirteenth to sixteenth pixel groups PXG33, PXG34 , PXG43, and PXG44 may each include four blue pixels (B).

In an embodiment, like the unit pattern UPTT9 of FIG. 18B , the first, fourth, fifth, eighth, ninth, twelfth, thirteenth, and sixteenth pixel groups PXG11, PXG22, PXG13, PXG24 , PXG31, PXG42, PXG33, and PXG44 each include four white pixels W, and each of the second and third pixel groups PXG12 and PXG21 includes four red pixels R and each of the sixth, seventh, tenth and eleventh pixel groups PXG14, PXG23, PXG32, and PXG41 includes four green pixels G, and the fourteenth and fifteenth pixel groups PXG34 , each of PXG43 may include four blue pixels (B).

In an embodiment, like the unit pattern UPTT10 of FIG. 18C , the first, fourth, fifth, eighth, ninth, twelfth, thirteenth, and sixteenth pixel groups PXG11, PXG22, PXG13, PXG24 , PXG31, PXG42, PXG33, and PXG44 each include four white pixels W, and each of the second and third pixel groups PXG12 and PXG21 includes four red pixels R and each of the second, sixth, tenth and fourteenth pixel groups PXG12, PXG14, PXG32, and PXG34 includes four green pixels G, and the third and fifteenth pixel groups PXG21 , PXG43 may include four red pixels R, and each of the seventh and eleventh pixel groups PXG23 and PXG41 may include four blue pixels B.

19A and 19B are plan views illustrating embodiments of a unit pattern in which a pixel group and a unit pixel included in the pixel array of FIG. 15 are mixed.

19A and 19B , each of the unit patterns UPTT11 and UPTT12 of the mixed structure includes at least one red pixel group RPXG, at least one blue pixel group BPXG, and a plurality of green pixels G may include Each red pixel group RPXG includes four red pixels R arranged in a matrix of two pixel rows and two columns and is focused by one common micro lens CMLS. Each blue pixel group BPXG includes four blue pixels B arranged in a matrix of two pixel rows and two pixel columns, and is focused by one common microlens CMLS. The plurality of green pixels G are focused by each micro lens SMLS.

In an embodiment, as shown in FIG. 19A , the unit pattern UPTT11 includes one red pixel group RPXG and a second group row disposed in the first group row GR1 and the first group column GC1 . One blue pixel group BPXG arranged in GR2 and second group column GC2, four green pixels arranged in a matrix of first group row GR1 and second group column GC2 ( It may include four green pixels G arranged in a matrix form of G) and the second group row GR2 and the first group column CG1 .

In an embodiment, as shown in FIG. 19B , the unit pattern UPTT12 includes a first group row GR1 , a second group row GR2 , a first group column GC1 , and a second group column GC2 . A matrix form of four red pixel groups RPXG, a third group row GR3, a fourth group row GR4, a third group column GC3, and a fourth group column GC4 arranged in a matrix form of The four blue pixel groups BPXG, the first group row GR1 , the second group row GR2 , the third group column GC3 , and the fourth group column GC4 are arranged as 16 green pixels G and 16 green pixels arranged in a matrix form of a third group row GR3 , a fourth group row GR4 , a first group column GC1 , and a second group column CG2 . They may include (G).

Compared to the unit patterns UPTT1 and UPTT8 of FIGS. 16A and 18A , the unit patterns UPTT11 and UPTT12 of FIGS. 19A and 19B have the same color filter array, but a group of green pixels focused by a common micro lens CMLS have an arrangement replaced by green pixels G focused by each micro lens SMLS. In this way, auto-focusing performance and image resolution may be appropriately adjusted by adjusting the ratio and arrangement of the pixel group and unit pixels.

20A to 20C are plan views illustrating exemplary unit patterns in which pixel groups of different sizes included in the pixel array of FIG. 15 are mixed.

20A to 20C , each of the unit patterns UPTT13 to UPTT14 of the mixed structure includes at least one red pixel group RPXG, at least one blue pixel group BPXG, and at least one row green pixel group ( GPXG1) and at least one column green pixel group GPXG2. Each red pixel group RPXG includes four red pixels R arranged in a matrix of two pixel rows and two columns and is focused by one common micro lens CMLS. Each blue pixel group BPXG includes four blue pixels B arranged in a matrix of two pixel rows and two pixel columns, and is focused by one common microlens CMLS. Each row green pixel group GPXG1 includes two green pixels G arranged in a matrix of one pixel row and two pixel columns, and has one elliptical shape having a long axis in the first direction DR1 . It is condensed by the common microlens CMLS1. Each column green pixel group GPXG2 includes two green pixels G arranged in a matrix of two pixel rows and one pixel column, and has one common elliptical shape having a long axis in the second direction DR2 . It is condensed by a micro lens (CMLS2). Two row green pixel groups GPXG1 are disposed adjacent to each other in the second direction DR2 to form a pair, and two column green pixel groups GPXG2 are disposed adjacent to each other in the first direction DR1 to form one pair of

In one embodiment, as in the unit pattern UPTT13 of FIG. 20A , two pairs of row green pixel groups GPXG1 are arranged adjacently in a diagonal direction, and two pairs of column green pixel groups GPXG2 are They may be disposed adjacent to each other in a diagonal direction.

In an embodiment, as in the unit pattern UPTT14 of FIG. 20B , two pairs of the row green pixel groups GPXG1 are disposed adjacent to each other in the first horizontal direction DR1 , and the column green pixel groups GPXG2 Two pairs of may be disposed adjacent to each other in the first horizontal direction DR1 .

In an embodiment, as in the unit pattern UPTT15 of FIG. 20C , two pairs of row green pixel groups GPXG1 are disposed adjacent to each other in the second horizontal direction DR2 , and column green pixel groups GPXG2 Two pairs of , may be disposed adjacent to each other in the second horizontal direction DR2 .

Compared with the unit patterns UPTT1 and UPTT8 in FIGS. 16A and 18A , the unit patterns UPTT13 to UPTT15 in FIGS. 20A to 20C have the same color filter array, but are shared by the four green pixels G It has an arrangement in which the micro lens CMLS is replaced by common micro lenses CMLS1 and CMLS2 of smaller size shared by the two green pixels G. As described above, autofocusing performance and image resolution may be appropriately adjusted by adjusting the ratio and arrangement of the common microlenses CMLS, CMLS1, and CMLS2 of various sizes.

21 is a block diagram of an electronic device according to embodiments of the present disclosure, and FIG. 22 is a block diagram illustrating a camera module included in the electronic device of FIG. 21 .

Referring to FIG. 21 , the electronic device 1000 may include a camera module group 1100 , an application processor 1200 , a PMIC 1300 , and an external memory 1400 .

The camera module group 1100 may include a plurality of camera modules 1100a, 1100b, and 1100c. Although the drawing shows an embodiment in which three camera modules 1100a, 1100b, and 1100c are disposed, the embodiments are not limited thereto. In some embodiments, the camera module group 1100 may be modified to include only two camera modules. Also, in some embodiments, the camera module group 1100 may be modified to include n camera modules (n is a natural number equal to or greater than 4).

Hereinafter, a detailed configuration of the camera module 1100b will be described in more detail with reference to FIG. 22 , but the following description may be equally applied to other camera modules 1100a and 1100b according to an embodiment.

Referring to FIG. 22 , the camera module 1100b includes a prism 1105 , an optical path folding element (hereinafter, “OPFE”) 1110, an actuator 1130, an image sensing device 1140, and storage. A unit 1150 may be included.

The prism 1105 may include the reflective surface 1107 of the light reflective material to change the path of the light L incident from the outside.

In some embodiments, the prism 1105 may change the path of the light L incident in the first direction X to the second direction Y perpendicular to the first direction X. In addition, the prism 1105 rotates the reflective surface 1107 of the light reflective material in the A direction about the central axis 1106 or rotates the central axis 1106 in the B direction in the first direction (X). The path of the incident light L may be changed in the second vertical direction Y. At this time, the OPFE 1110 may also move in a third direction (Z) perpendicular to the first direction (X) and the second direction (Y).

In some embodiments, as shown, the maximum rotation angle of the prism 1105 in the A direction may be 15 degrees or less in the positive (+) A direction and greater than 15 degrees in the negative (-) A direction. However, embodiments are not limited thereto.

In some embodiments, the prism 1105 is movable in a positive (+) or negative (-) B direction around 20 degrees, or between 10 degrees and 20 degrees, or between 15 degrees and 20 degrees, where the angle of movement is positive It can move at the same angle in the (+) or minus (-) B direction, or it can move to a nearly similar angle in the range of 1 degree or less.

In some embodiments, the prism 1105 may move the reflective surface 1106 of the light reflective material in a third direction (eg, the Z direction) parallel to the extension direction of the central axis 1106 .

The OPFE 1110 may include, for example, an optical lens consisting of m (here, m is a natural number) number of groups. The m lenses may move in the second direction Y to change an optical zoom ratio of the camera module 1100b. For example, when the basic optical zoom magnification of the camera module 1100b is Z, when m optical lenses included in the OPFE 1110 are moved, the optical zoom magnification of the camera module 1100b is 3Z or 5Z or It can be changed to an optical zoom magnification of 5Z or higher.

The actuator 1130 may move the OPFE 1110 or an optical lens (hereinafter, referred to as an optical lens) to a specific position. For example, the actuator 1130 may adjust the position of the optical lens so that the image sensor 1142 is located at a focal length of the optical lens for accurate sensing.

The image sensing device 1140 may include an image sensor 1142 , a control logic 1144 , and a memory 1146 . The image sensor 1142 may sense an image of a sensing target using light L provided through an optical lens. The control logic 1144 may control the overall operation of the camera module 1100b. For example, the control logic 1144 may control the operation of the camera module 1100b according to a control signal provided through the control signal line CSLb.

The memory 1146 may store information necessary for the operation of the camera module 1100b, such as calibration data 1147 . The calibration data 1147 may include information necessary for the camera module 1100b to generate image data using the light L provided from the outside. The calibration data 1147 may include, for example, information about a degree of rotation described above, information about a focal length, information about an optical axis, and the like. When the camera module 1100b is implemented in the form of a multi-state camera in which the focal length is changed according to the position of the optical lens, the calibration data 1147 is a focal length value for each position (or state) of the optical lens and Information related to auto focusing may be included.

The storage unit 1150 may store image data sensed by the image sensor 1142 . The storage unit 1150 may be disposed outside the image sensing device 1140 , and may be implemented in a stacked form with a sensor chip constituting the image sensing device 1140 . In some embodiments, the storage unit 1150 may be implemented as an EEPROM (Electrically Erasable Programmable Read-Only Memory), but embodiments are not limited thereto.

21 and 22 , in some embodiments, each of the plurality of camera modules 1100a , 1100b , and 1100c may include an actuator 1130 . Accordingly, each of the plurality of camera modules 1100a, 1100b, and 1100c may include the same or different calibration data 1147 according to the operation of the actuator 1130 included therein.

In some embodiments, one camera module (eg, 1100b) of the plurality of camera modules 1100a, 1100b, 1100c is a folded lens including the prism 1105 and the OPFE 1110 described above. It is a camera module in the form of a camera module, and the remaining camera modules (eg, 1100a and 1100b) may be a camera module in a vertical form in which the prism 1105 and the OPFE 1110 are not included, but embodiments are limited thereto. it is not going to be

In some embodiments, one camera module (eg, 1100c) of the plurality of camera modules 1100a, 1100b, and 1100c uses, for example, IR (Infrared Ray) to extract depth information. It may be a depth camera of the form. In this case, the application processor 1200 merges the image data provided from the depth camera and the image data provided from another camera module (eg, 1100a or 1100b) to obtain a 3D depth image. can create

In some embodiments, at least two camera modules (eg, 1100a, 1100b) among the plurality of camera modules 1100a, 1100b, and 1100c may have different fields of view (Field of View). In this case, for example, optical lenses of at least two camera modules (eg, 1100a and 1100b) among the plurality of camera modules 1100a, 1100b, and 1100c may be different from each other, but is not limited thereto.

Also, in some embodiments, a viewing angle of each of the plurality of camera modules 1100a, 1100b, and 1100c may be different from each other. In this case, the optical lenses included in each of the plurality of camera modules 1100a, 1100b, and 1100c may also be different, but is not limited thereto.

In some embodiments, each of the plurality of camera modules 1100a, 1100b, and 1100c may be disposed to be physically separated from each other. That is, the plurality of camera modules 1100a, 1100b, and 1100c do not divide and use the sensing area of one image sensor 1142, but an independent image inside each of the plurality of camera modules 1100a, 1100b, 1100c. A sensor 1142 may be disposed.

Referring back to FIG. 21 , the application processor 1200 may include an image processing device 1210 , a memory controller 1220 , and an internal memory 1230 . The application processor 1200 may be implemented separately from the plurality of camera modules 1100a, 1100b, and 1100c. For example, the application processor 1200 and the plurality of camera modules 1100a, 1100b, and 1100c may be implemented separately as separate semiconductor chips.

The image processing apparatus 1210 may include a plurality of sub image processors 1212a , 1212b , and 1212c , an image generator 1214 , and a camera module controller 1216 .

The image processing apparatus 1210 may include a plurality of sub-image processors 1212a, 1212b, and 1212c in a number corresponding to the number of the plurality of camera modules 1100a, 1100b, and 1100c.

Image data generated from each of the camera modules 1100a, 1100b, and 1100c may be provided to the corresponding sub-image processors 1212a, 1212b, and 1212c through image signal lines ISLa, ISLb, and ISLc separated from each other. For example, image data generated from the camera module 1100a is provided to the sub-image processor 1212a through an image signal line ISLa, and image data generated from the camera module 1100b is an image signal line ISLb. The image data may be provided to the sub-image processor 1212b through , and image data generated from the camera module 1100c may be provided to the sub-image processor 1212c through the image signal line ISLc. Such image data transmission may be performed using, for example, a Camera Serial Interface (CSI) based on a Mobile Industry Processor Interface (MIPI), but embodiments are not limited thereto.

Meanwhile, in some embodiments, one sub-image processor may be disposed to correspond to a plurality of camera modules. For example, the sub-image processor 1212a and the sub-image processor 1212c are not implemented separately from each other as shown, but are integrated into one sub-image processor, and the camera module 1100a and the camera module 1100c. After the image data provided from the is selected through a selection element (eg, a multiplexer) or the like, it may be provided to the integrated sub-image processor.

The image data provided to each of the sub-image processors 1212a , 1212b , and 1212c may be provided to the image generator 1214 . The image generator 1214 may generate an output image using image data provided from each of the sub-image processors 1212a, 1212b, and 1212c according to image generating information or a mode signal.

Specifically, the image generator 1214 merges at least a portion of the image data generated from the camera modules 1100a, 1100b, and 1100c having different viewing angles according to the image generation information or the mode signal to merge the output image. can create In addition, the image generator 1214 may generate an output image by selecting any one of image data generated from the camera modules 1100a, 1100b, and 1100c having different viewing angles according to image generation information or a mode signal. .

In some embodiments, the image generation information may include a zoom signal or zoom factor. Also, in some embodiments, the mode signal may be, for example, a signal based on a mode selected by a user.

When the image generation information is a zoom signal (zoom factor) and each of the camera modules 1100a, 1100b, and 1100c has different viewing fields (viewing angles), the image generator 1214 performs different operations depending on the type of the zoom signal. can be performed. For example, when the zoom signal is the first signal, after merging the image data output from the camera module 1100a and the image data output from the camera module 1100c, the merged image signal and the camera module not used for merging An output image may be generated using the image data output from 1100b. If the zoom signal is a second signal different from the first signal, the image generator 1214 does not perform such image data merging, and selects any one of the image data output from each camera module 1100a, 1100b, 1100c. You can choose to create an output image. However, embodiments are not limited thereto, and a method of processing image data may be modified and implemented as needed.

In some embodiments, the image generator 1214 receives a plurality of image data having different exposure times from at least one of the plurality of sub-image processors 1212a, 1212b, and 1212c, and performs high dynamic range (HDR) with respect to the plurality of image data. ) processing, it is possible to generate merged image data having an increased dynamic range.

The camera module controller 1216 may provide a control signal to each of the camera modules 1100a, 1100b, and 1100c. Control signals generated from the camera module controller 1216 may be provided to the corresponding camera modules 1100a, 1100b, and 1100c through control signal lines CSLa, CSLb, and CSLc separated from each other.

Any one of the plurality of camera modules (1100a, 1100b, 1100c) is designated as a master camera (eg, 1100b) according to image generation information or a mode signal including a zoom signal, and the remaining camera modules (eg, For example, 1100a and 1100c may be designated as slave cameras. Such information may be included in the control signal and provided to the corresponding camera modules 1100a, 1100b, and 1100c through the control signal lines CSLa, CSLb, and CSLc separated from each other.

A camera module operating as a master and a slave may be changed according to a zoom factor or an operation mode signal. For example, when the viewing angle of the camera module 1100a is wider than that of the camera module 1100b and the zoom factor indicates a low zoom factor, the camera module 1100b operates as a master, and the camera module 1100a is a slave can operate as Conversely, when the zoom factor indicates a high zoom magnification, the camera module 1100a may operate as a master and the camera module 1100b may operate as a slave.

In some embodiments, the control signal provided from the camera module controller 1216 to each of the camera modules 1100a, 1100b, and 1100c may include a sync enable signal. For example, when the camera module 1100b is a master camera and the camera modules 1100a and 1100c are slave cameras, the camera module controller 1216 may transmit a sync enable signal to the camera module 1100b. The camera module 1100b receiving the sync enable signal generates a sync signal based on the received sync enable signal, and transmits the generated sync signal to the camera modules ( 1100a, 1100c) can be provided. The camera module 1100b and the camera modules 1100a and 1100c may be synchronized with the sync signal to transmit image data to the application processor 1200 .

In some embodiments, the control signal provided from the camera module controller 1216 to the plurality of camera modules 1100a, 1100b, and 1100c may include mode information according to the mode signal. Based on the mode information, the plurality of camera modules 1100a, 1100b, and 1100c may operate in the first operation mode and the second operation mode in relation to the sensing speed.

The plurality of camera modules 1100a, 1100b, and 1100c generates an image signal at a first rate (eg, generates an image signal at a first frame rate) at a first speed in a first operation mode to generate the image signal at a second speed higher than the first speed. The encoding speed (eg, encoding an image signal of a second frame rate higher than the first frame rate) may be performed, and the encoded image signal may be transmitted to the application processor 1200 . In this case, the second speed may be 30 times or less of the first speed.

The application processor 1200 stores the received image signal, that is, the encoded image signal, in the memory 1230 provided therein or the storage 1400 external to the application processor 1200, and thereafter, the memory 1230 or the storage An image signal encoded from the 1400 may be read and decoded, and image data generated based on the decoded image signal may be displayed. For example, a corresponding subprocessor among the plurality of subprocessors 1212a , 1212b , and 1212c of the image processing apparatus 1210 may perform decoding, and may also perform image processing on the decoded image signal.

The plurality of camera modules 1100a, 1100b, and 1100c generate an image signal at a third rate lower than the first rate in the second operation mode (eg, an image signal of a third frame rate lower than the first frame rate) generated) and transmit the image signal to the application processor 1200 . The image signal provided to the application processor 1200 may be an unencoded signal. The application processor 1200 may perform image processing on the received image signal or store the image signal in the memory 1230 or the storage 1400 .

The PMIC 1300 may supply power, eg, a power supply voltage, to each of the plurality of camera modules 1100a, 1100b, and 1100c. For example, the PMIC 1300 supplies first power to the camera module 1100a through the power signal line PSLa under the control of the application processor 1200, and the camera module ( The second power may be supplied to 1100b) and the third power may be supplied to the camera module 1100c through the power signal line PSLc.

The PMIC 1300 may generate power corresponding to each of the plurality of camera modules 1100a, 1100b, and 1100c in response to the power control signal PCON from the application processor 1200, and also adjust the power level. . The power control signal PCON may include a power adjustment signal for each operation mode of the plurality of camera modules 1100a, 1100b, and 1100c. For example, the operation mode may include a low power mode, and in this case, the power control signal PCON may include information about a camera module operating in the low power mode and a set power level. Levels of powers provided to each of the plurality of camera modules 1100a, 1100b, and 1100c may be the same or different from each other. Also, the level of power can be changed dynamically.

As described above, a pixel array and an image sensor including the pixel array according to embodiments of the present invention include a plurality of unit pixels sharing a microlens and a trench structure extending from the front to the rear of the semiconductor substrate. Image quality can be improved by suppressing crosstalk between unit pixels while implementing autofocusing using pixel groups.

Embodiments of the present invention may be usefully used in devices and systems including an image sensor. In particular, embodiments of the present invention include a computer, a laptop, a cellular phone, a smart phone, an MP3 player, a personal digital assistant (PDA), and a portable multimedia player (PMP). , digital TV, digital camera, portable game console, navigation device, wearable device, IoT (internet of things;) device, IoE (internet of everything:) device, e-book ( e-book), virtual reality (VR) devices, augmented reality (AR) devices, and electronic devices such as autonomous driving devices.

Although the present invention has been described above with reference to preferred embodiments, those skilled in the art can variously modify and change the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. you will understand that you can

Claims (20)

A pixel array of an image sensor formed on a semiconductor substrate, the pixel array comprising:
comprising a plurality of pixel groups;
Each pixel group of the plurality of pixel groups,
a plurality of unit pixels each including photoelectric conversion elements disposed on a semiconductor substrate;
trench structures extending in a vertical direction from a front surface to a rear surface of the semiconductor substrate and disposed inside the semiconductor substrate to electrically and optically isolate the photoelectric conversion elements included in the plurality of unit pixels; and
a common microlens disposed above or below the semiconductor substrate to cover all the photoelectric conversion elements included in the plurality of unit pixels and condensing incident light to the photoelectric conversion elements included in the plurality of unit pixels; A pixel array of an image sensor comprising. According to claim 1,
The trench structures are
inter-group trench structures isolating each pixel group and adjacent pixel groups; and
and inter-pixel trench structures for isolating the plurality of pixels included in each pixel group from each other. 3. The method of claim 2,
The inter-pixel trench structures are
a first inter-pixel trench structure extending in the first horizontal direction to be connected to inter-group trench structures disposed on both sides of the first inter-pixel trench structure in a vertical direction from a front surface to a rear surface of the semiconductor substrate; and
A second inter-group extending in the second horizontal direction to be connected to inter-group trench structures disposed on both sides in a second horizontal direction perpendicular to the first horizontal direction and extending in a vertical direction from the front surface to the rear surface of the semiconductor substrate - A pixel array of an image sensor, characterized in that it comprises a pixel trench structure. 4. The method of claim 3,
With respect to an intersection region where the first inter-pixel trench structure and the second inter-pixel trench structure intersect, a portion corresponding to the intersection region of the first inter-pixel trench structure and the second inter-pixel trench is formed. A pixel array of an image sensor, wherein at least a portion has been removed. 5. The method of claim 4,
The pixel array of the image sensor according to claim 1 , wherein a portion corresponding to the crossing region of the first inter-pixel trench structure and the second inter-pixel trench structure is removed in the vertical direction from the front surface to the rear surface of the semiconductor substrate. . 5. The method of claim 4,
The pixel array of the image sensor according to claim 1 , wherein a portion corresponding to the intersection region of the first inter-pixel trench structure and the second inter-pixel trench structure is removed from the front surface of the semiconductor substrate. 5. The method of claim 4,
Each pixel group includes four unit pixels arranged in a matrix of two pixel rows and two pixel columns,
and a common floating diffusion region shared by the four pixels is disposed in the crossing region. 8. The method of claim 7,
and conductive lines disposed on the semiconductor substrate and electrically connecting four common floating diffusion regions of four pixel groups disposed adjacent to each other in a matrix of two group rows and two group columns. The pixel array of the image sensor, characterized in that. According to claim 1,
Each trench structure of the trench structures,
A pixel array of an image sensor, characterized in that all of the trenches are filled with a transparent dielectric. According to claim 1,
Each trench structure of the trench structures,
A pixel array for an image sensor, wherein both sides of the trench are coated with a transparent dielectric and a middle portion of the trench is filled with a material different from the transparent dielectric. According to claim 1,
Each trench structure of the trench structures,
an upper trench structure formed by a front trench process performed from the front surface of the semiconductor substrate; and
and a lower trench structure formed by a back trench process performed from the rear surface of the semiconductor substrate. 12. The method of claim 11,
The pixel array of the image sensor, characterized in that the upper trench structure and the lower trench structure have different structures or different compositions. According to claim 1,
The pixel array of an image sensor, characterized in that the plurality of pixels included in each pixel group share one color filter. According to claim 1,
the pixel array is divided into unit patterns repeatedly arranged in a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction;
and each of the unit patterns includes two or more of the pixel groups. 15. The method of claim 14,
The unit pattern is
first to fourth pixel groups arranged in a matrix form of two group rows and two group columns,
Each of the first to fourth pixel groups,
A pixel array of an image sensor comprising four unit pixels arranged in a matrix of two pixel rows and two pixel columns. 15. The method of claim 14,
The unit pattern is
first to fourth pixel groups arranged in a matrix of a first group row, a second group row, a first group column, and a second group column;
fifth to eighth pixel groups arranged in a matrix of the first group row, the second group row, the third group column, and the fourth group column;
ninth to twelfth pixel groups arranged in a matrix form of a third group row, a fourth group row, the first group column, and the second group column;
thirteenth to sixteenth pixel groups arranged in a matrix of the third group row, the third group row, the third group column, and the fourth group column;
Each of the first to sixteenth pixel groups,
A pixel array of an image sensor comprising four unit pixels arranged in a matrix of two pixel rows and two pixel columns. 15. The method of claim 14,
The unit pattern is
at least one group of red pixels each including four red pixels arranged in a matrix of two pixel rows and two columns and condensed by one common micro lens;
at least one blue pixel group each including four blue pixels arranged in a matrix form of two pixel rows and two pixel columns and condensed by one common micro lens; and
A pixel array of an image sensor comprising a plurality of green pixels focused by each micro lens. 15. The method of claim 14,
The unit pattern is
one red pixel group including four red pixels arranged in a matrix of two pixel rows and two pixel columns and condensed by one common micro lens;
at least one blue pixel group including four blue pixels arranged in a matrix of two pixel rows and two pixel columns and focused by one common micro lens;
at least one row green pixel group including two green pixels arranged in a matrix of one pixel row and two pixel columns and focused by one common micro lens; and
A pixel array of an image sensor, comprising: at least one column green pixel group, the group comprising two green pixels arranged in a matrix of two pixel rows and one pixel column, and focused by one common micro lens. A pixel array of an image sensor formed on a semiconductor substrate, the pixel array comprising:
comprising a plurality of pixel groups;
Each pixel group of the plurality of pixel groups,
a plurality of unit pixels each including photoelectric conversion elements disposed on a semiconductor substrate;
trench structures extending in a vertical direction from a front surface to a rear surface of the semiconductor substrate and disposed inside the semiconductor substrate to electrically and optically isolate the photoelectric conversion elements included in the plurality of unit pixels;
a common microlens disposed above or below the semiconductor substrate to cover all the photoelectric conversion elements included in the plurality of unit pixels and condensing incident light to the photoelectric conversion elements included in the plurality of unit pixels; and
and a color filter disposed between the semiconductor substrate and the common microlens and shared by the plurality of pixels included in each of the pixel groups. a pixel array including a plurality of pixel groups performing a sensing operation by collecting photocharges generated by incident light;
a row driver driving the pixel array in row units; and
a control unit for controlling the pixel array and the row driver;
Each pixel group of the plurality of pixel groups,
a plurality of unit pixels each including photoelectric conversion elements disposed on a semiconductor substrate;
trench structures extending in a vertical direction from a front surface to a rear surface of the semiconductor substrate and disposed inside the semiconductor substrate to electrically and optically isolate the photoelectric conversion elements included in the plurality of unit pixels; and
a common microlens disposed above or below the semiconductor substrate to cover all the photoelectric conversion elements included in the plurality of unit pixels and condensing incident light to the photoelectric conversion elements included in the plurality of unit pixels; Including image sensor.

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