KR20220025629A - Semiconductor package - Google Patents

Abstract

According to the present invention, a semiconductor package comprises: a first semiconductor chip including a first semiconductor element, a first semiconductor substrate, a plurality of through-electrodes penetrating the first semiconductor substrate, and a plurality of first chip connection pads disposed on an upper surface thereof; a plurality of second semiconductor chips sequentially stacked on the upper surface of the first semiconductor chip, and separately including a second semiconductor substrate, a second semiconductor element controlled by the first semiconductor chip, and a plurality of second chip connection pads disposed on an upper surface thereof; a plurality of bonding wires for connecting the first and second chip connection pads; a molding layer for surrounding the second semiconductor chips and the bonding wires; and a plurality of external connection terminals disposed on a lower surface of the first semiconductor chip. Therefore, a relatively wide data bus width can be provided at relatively low manufacturing costs.

Description

semiconductor package

The present invention relates to a semiconductor package, and more particularly, to a semiconductor package including a plurality of semiconductor chips.

Electronic products are becoming smaller and lighter in accordance with the rapid development of the electronic industry and user demands. Accordingly, a semiconductor package including a plurality of semiconductor chips has been developed.

An object of the present invention is to provide a semiconductor package including a plurality of semiconductor chips together.

In order to achieve the above technical problem, the present invention provides a semiconductor package as follows.

A semiconductor package according to the present invention includes a first semiconductor chip including a first semiconductor device, a first semiconductor substrate, a plurality of through electrodes penetrating the first semiconductor substrate, and a plurality of first chip connection pads disposed on an upper surface of the semiconductor package. ; A plurality of devices sequentially stacked on the top surface of the first semiconductor chip and each including a second semiconductor substrate, a second semiconductor device controlled by the first semiconductor chip, and a plurality of second chip connection pads disposed on the top surface a second semiconductor chip; a plurality of bonding wires connecting the plurality of first chip connection pads and the plurality of second chip connection pads; a molding layer surrounding the plurality of second semiconductor chips and the plurality of bonding wires; and a plurality of external connection terminals disposed on a lower surface of the first semiconductor chip.

A semiconductor package according to the present invention includes a first semiconductor substrate having a first semiconductor element, a plurality of conductive wiring patterns disposed on an active surface of the first semiconductor substrate, and an inter-wiring insulating layer surrounding the plurality of conductive wiring patterns. a wiring layer having a plurality of through electrodes passing through the first semiconductor substrate and electrically connected to the first semiconductor element, a plurality of first chip connection pads disposed on an upper surface, and a plurality of external connection pads disposed on a lower surface; a first semiconductor chip comprising; A die adhesive film is attached to a lower surface and stacked on the upper surface of the first semiconductor chip, a second semiconductor substrate, a second semiconductor device controlled by the first semiconductor chip, and a plurality of second chips disposed on the upper surface are connected a plurality of second semiconductor chips each including a pad; a plurality of bonding wires extending to connect between the plurality of first chip connection pads and the plurality of second chip connection pads; a molding layer covering an upper surface of the first semiconductor chip and surrounding the plurality of second semiconductor chips and the plurality of bonding wires; and a plurality of external connection terminals attached to the plurality of external connection pads.

A semiconductor package according to the present invention includes a redistribution insulating layer, a plurality of redistribution line patterns disposed on at least one of an upper surface and a lower surface of the redistribution insulating layer, and a plurality of redistribution line patterns passing through the redistribution insulating layer. a redistribution structure including a plurality of redistribution vias connected in contact with a portion of the plurality of redistribution vias and extending horizontally from the lower side to the upper side; a wiring layer disposed on the redistribution structure, a first semiconductor substrate, a wiring layer disposed on an active surface of the first semiconductor substrate and having a plurality of conductive wiring patterns and an inter-wiring insulating layer surrounding the plurality of conductive wiring patterns; a logic semiconductor chip comprising: a plurality of first chip connection pads disposed; a plurality of through electrodes connected to the plurality of first chip connection pads and penetrating the first semiconductor substrate; a supporter disposed on the redistribution structure and spaced apart from the logic semiconductor chip, the supporter having an upper surface positioned at the same vertical level as the upper surface of the first semiconductor substrate; A die adhesive film is attached to the lower surface so that the edges are aligned with each other in the vertical direction and sequentially stacked on the inactive surface of the first semiconductor substrate and on the supporter, controlled by the second semiconductor substrate and the logic semiconductor chip a plurality of DRAM chips each including a DRAM device and a plurality of second chip connection pads disposed on an upper surface thereof and each having a data bus width of 16 bits to 64 bits; a plurality of plurality of first chip connection pads having one end attached to the plurality of first chip connection pads and the other end attached to the plurality of second chip connection pads, and extending from the plurality of second chip connection pads to the plurality of first chip connection pads bonding wire; a molding layer covering an upper surface of the redistribution structure and surrounding the plurality of DRAM chips and the plurality of bonding wires; and a plurality of external connection terminals attached to a lower surface of the redistribution structure.

The semiconductor package according to the present invention may electrically connect the first semiconductor chip and the plurality of second semiconductor chips by a plurality of bonding wires to have a relatively wide data bus width at a relatively low manufacturing cost. In addition, the semiconductor package according to the present invention does not require a high-cost configuration such as a silicon interposer, and can be manufactured at low cost.

1 and 2 are cross-sectional views of semiconductor packages according to embodiments of the present invention.
3A to 3D are cross-sectional views illustrating in stages a method of manufacturing a semiconductor package according to embodiments of the present invention.
4 and 5 are cross-sectional views of semiconductor packages according to embodiments of the present invention.
6A to 6E are cross-sectional views illustrating in stages a method of manufacturing a semiconductor package according to an exemplary embodiment of the present invention.
7 to 16 are cross-sectional views of semiconductor packages according to embodiments of the present invention.
17A and 17B are circuit diagrams illustrating exemplary circuits of a first semiconductor chip included in a semiconductor package according to embodiments of the present invention.
18 to 21 are cross-sectional views of semiconductor packages according to embodiments of the present invention.
22 and 23 are cross-sectional views illustrating a system including a semiconductor package according to an exemplary embodiment.

1 and 2 are cross-sectional views of semiconductor packages according to embodiments of the present invention.

Referring to FIG. 1 , a semiconductor package 1 includes a first semiconductor chip 100 and a plurality of second semiconductor chips 200 sequentially stacked on the first semiconductor chip 100 . In some embodiments, four or eight second semiconductor chips 200 may be stacked on one first semiconductor chip 100 . In some embodiments, each of the plurality of second semiconductor chips 200 may be a memory semiconductor chip having a memory device, and the first semiconductor chip 100 may be a memory device included in the second semiconductor chip 200 , for example, , a logic semiconductor chip having circuits for controlling a DRAM device or a Flash memory device.

The first semiconductor chip 100 may be referred to as a base die, a base chip, a controller die, a controller chip, a buffer die, or a buffer chip. The second semiconductor chip 200 may be referred to as a memory die, a memory chip, a core die, or a core chip. In some embodiments, when the second semiconductor chip 200 includes a DRAM device, the second semiconductor chip 200 may be referred to as a DRAM die or a DRAM chip. In some embodiments, when the second semiconductor chip 200 includes a flash memory device, the second semiconductor chip 200 may be referred to as a flash memory die or a flash memory chip.

The first semiconductor chip 100 may include a first semiconductor substrate 110 having a first semiconductor device 112 formed on an active surface thereof, and a wiring layer 130 disposed on the active surface of the first semiconductor substrate 110 . can The first semiconductor chip 100 may further include a plurality of through electrodes 120 penetrating at least a portion between the upper and lower surfaces of the first semiconductor chip 100 . In some embodiments, the plurality of through electrodes 120 may pass through an inactive surface of the first semiconductor substrate 110 , a top surface of the first semiconductor chip 100 , and an active surface of the first semiconductor substrate 110 . .

The first semiconductor chip 100 may have a face-down arrangement in which the active surface of the first semiconductor substrate 110 faces downward.

In this specification, the upper and lower surfaces of the semiconductor chip mean upper and lower surfaces with reference to the drawings, and the front and rear surfaces of the semiconductor chip mean the active and inactive surfaces of the semiconductor substrate. For example, in FIG. 1 , the upper surface of the first semiconductor chip 100 may be the rear surface, and the lower surface may be the front surface.

The first semiconductor chip 100 is disposed on a lower surface and includes a plurality of front pads 142 connected to the conductive wiring pattern 132 , and a plurality of rear pads disposed on the upper surface and connected to one end of the plurality of through electrodes 120 . 144) may be further included.

The first semiconductor substrate 110 may include, for example, a semiconductor material such as silicon (Si, silicon) or germanium (Ge). Alternatively, the first semiconductor substrate 110 may include a compound semiconductor material such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The first semiconductor substrate 110 may include a conductive region, for example, a well doped with impurities. The semiconductor substrate 110 may have various device isolation structures such as a shallow trench isolation (STI) structure.

A first semiconductor device 112 including a plurality of individual devices of various types may be formed on the active surface of the first semiconductor substrate 110 . The plurality of individual devices are various microelectronic devices, for example, a metal-oxide-semiconductor field effect transistor (MOSFET) such as a complementary metal-insulator-semiconductor transistor (CMOS), a system large scale integration (LSI) , active elements, passive elements, and the like. The plurality of individual devices may be electrically connected to the conductive region of the first semiconductor substrate 110 . The first semiconductor device 112 may further include a conductive wire or a conductive plug electrically connecting at least two of the plurality of individual devices, or the plurality of individual devices and the conductive region of the first semiconductor substrate 110 . can In addition, each of the plurality of individual elements may be electrically isolated from other neighboring individual elements by an insulating layer.

The plurality of through electrodes 120 may pass through at least a portion between the upper and lower surfaces of the first semiconductor chip 100 . The plurality of through electrodes 120 may be electrically connected to the first semiconductor device 112 . In some embodiments, the plurality of through electrodes 120 may penetrate from the upper surface to the lower surface of the first semiconductor substrate 110 . In some other embodiments, the plurality of through electrodes 120 may penetrate from the upper surface to the lower surface of the first semiconductor substrate 110 and then pass through at least a portion of the wiring layer 130 together to extend into the wiring layer 130 . .

Each of the plurality of through electrodes 120 may include a conductive plug passing through at least a portion of the first semiconductor chip 110 and a conductive barrier layer surrounding the conductive plug. The conductive plug may have a cylindrical shape, and the conductive barrier layer may have a cylindrical shape surrounding a sidewall of the conductive plug. A plurality of via insulating layers may be interposed between the first semiconductor substrate 110 and the plurality of through electrodes 120 to surround sidewalls of the plurality of through electrodes 120 .

The conductive plug may be made of Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, CuW, W, or a W alloy, but is not limited thereto. The conductive plug may be, for example, Al, Au, Be, Bi, Co, Cu, Hf, In, Mn, Mo, Ni, Pb, Pd, Pt, Rh, Re, Ru, Ta, Te, Ti, W, It may include one or more of Zn and Zr, and may include one or two or more stacked structures. The conductive barrier layer may include, for example, at least one material selected from W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, or NiB, but is limited thereto. it is not The via insulating layer may be formed of an oxide layer, a nitride layer, a carbide layer, a polymer, or a combination thereof. The via insulating layer may be formed of, for example, an O ₃ /TEOS (ozone/tetra-ethyl ortho-silicate)-based HARP (High Aspect Ratio Process) oxide layer.

The wiring layer 130 may include a plurality of conductive wiring patterns 132 and an inter-wiring insulating layer 134 surrounding the plurality of conductive wiring patterns 132 . The plurality of conductive wiring patterns 132 may include wiring lines and wiring vias. In some embodiments, the plurality of conductive wiring patterns 132 may have a multilayer wiring structure having wiring lines and wiring vias positioned at different vertical levels, and the inter-wiring insulating layer 134 may include a plurality of conductive wiring patterns. A multilayer structure in which a plurality of insulating layers are stacked may be provided corresponding to the multilayer wiring structure of 132 .

The plurality of conductive wiring patterns 132 may include, for example, a metal material such as aluminum, copper, or tungsten. In some embodiments, the plurality of conductive wiring patterns 132 may include a barrier layer for wiring and a metal layer for wiring. The barrier layer for wiring is made of a nitride or oxide of a metal such as Ti, Ta, Ru, Mn, Co, or W, or such as Cobalt Tungsten Phosphide (CoWP), Cobalt Tungsten Boron (CoWB), or Cobalt Tungsten Boron Phosphide (CoWBP). It may be made of an alloy. The metal layer for wiring may include at least one metal selected from W, Al, Ti, Ta, Ru, Mn, and Cu. The inter-wiring insulating layer 134 may be formed of, for example, silicon oxide. In some embodiments, the inter-wiring insulating layer 134 may be formed of tetraethyl orthosilicate (TEOS). In some other embodiments, the inter-wiring insulating layer 134 may be formed of an insulating material having a dielectric constant lower than that of silicon oxide. For example, the inter-wiring insulating layer 134 may be formed of an ultra low k (ULK) layer having an ultra low dielectric constant K of about 2.2 to 2.4. The ULK film may include a SiOC film or a SiCOH film.

A plurality of external connection terminals 150 may be attached to the plurality of front pads 142 . In some embodiments, the external connection terminal 150 may be a conductive bump. The external connection terminal 150 may electrically connect the semiconductor package 1 and an external device. The front pad 142 may be referred to as an external connection pad.

The plurality of second semiconductor chips 200 may be sequentially stacked on the first semiconductor chip 100 . The plurality of second semiconductor chips 200 may be sequentially stacked on the inactive surface of the first semiconductor substrate 110 . The plurality of second semiconductor chips 200 may be sequentially stacked on the first semiconductor chip 100 in a vertical direction. The plurality of second semiconductor chips 200 may be stacked to overlap each other in a vertical direction. Edges of each of the plurality of second semiconductor chips 200 may be aligned with each other in a vertical direction. Each of the plurality of second semiconductor chips 200 may have a face-up arrangement in which the active surface of the second semiconductor substrate 210 faces upward.

Each of the plurality of second semiconductor chips 200 may have a die-adhesive film 250 attached to a lower surface thereof therebetween, and may be attached to a structure under the die-adhesive film 250 . For example, the lowermost second semiconductor chip 200 among the plurality of second semiconductor chips 200 is attached on the first semiconductor chip 100 with the die adhesive film 250 therebetween, and the plurality of second semiconductor chips 200 . The rest of the semiconductor chips 200 have the die adhesive film 250 therebetween, and may be attached to the second semiconductor chip 200 at the lower side. The second semiconductor chip 200 and the die adhesive film 250 attached to the lower surface of the second semiconductor chip 200 may have the same horizontal width and same horizontal area.

In some embodiments, a horizontal width and a horizontal area of the second semiconductor chip 200 may be smaller than a horizontal width and a horizontal area of the first semiconductor chip 100 . For example, the plurality of second semiconductor chips 200 may be stacked to overlap each other in the first semiconductor chip 100 in a vertical direction.

The second semiconductor chip 200 may include a second semiconductor substrate 210 on which a second semiconductor device 212 is formed on an active surface, and a plurality of chip pads 220 disposed on an upper surface of the second semiconductor chip 200 . The plurality of chip pads 220 may be edge pads disposed adjacent to the edge of the top surface of the second semiconductor chip 210 . Since the second semiconductor substrate 210 and the second semiconductor device 212 are substantially similar to the first semiconductor substrate 110 and the first semiconductor device 212 , overlapping descriptions will be omitted. The second semiconductor chip 200 may also include a wiring layer similar to that of the wiring layer 130 of the first semiconductor chip 100 , but is omitted for convenience of illustration.

The second semiconductor device 212 may be, for example, a memory device. For example, the second semiconductor device 212 may be a dynamic random access memory (DRAM) or a flash memory.

One end of the plurality of bonding wires 230 may be attached to the chip pad 220 of the plurality of second semiconductor chips 200 , and the other end of the plurality of bonding wires 230 may be attached to the plurality of rear pads 144 . there is. The plurality of bonding wires 230 may directly connect the plurality of chip pads 220 of each of the plurality of second semiconductor chips 200 corresponding to each other and the plurality of rear pads 144 of the first semiconductor chip 100 to each other. . Each of the plurality of second semiconductor chips 200 and the first semiconductor chip 100 may be electrically connected to each other through different bonding wires 230 among the plurality of bonding wires 230 .

The back pad 144 of the first semiconductor chip 100 may be referred to as a first chip connection pad, and the chip pad 220 of the second semiconductor chip 200 may be referred to as a second chip connection pad. That is, the bonding wire 230 connects the first chip connection pad and the second chip connection pad, and may extend from the first chip connection pad to the second chip connection pad.

The die adhesive film 250 may cover the plurality of chip pads 220 of the lower second semiconductor chip 200 . A portion of one end connected to the plurality of chip pads 220 among the plurality of bonding wires 230 may be embedded in the die adhesive film 250 . The die adhesive film 250 may be formed of, for example, an inorganic adhesive or a polymer adhesive. The polymer adhesive may be made of, for example, a thermosetting resin or a thermoplastic resin. In the case of the thermosetting resin, after the monomer is heat-molded, it has a three-dimensional cross-link structure and is not softened even when reheated. On the other hand, in the case of the thermoplastic resin, it is a resin that exhibits plasticity by heating and has a structure of a linear polymer. In addition, the polymer adhesive may be of a hybrid type made by mixing these two components.

A plurality of second semiconductor chips 200 are attached to a portion of the first semiconductor chip 100 overlapping the plurality of second semiconductor chips 200 in the vertical direction, and the plurality of second semiconductor chips 200 are vertically overlapped with each other in the vertical direction. A plurality of rear pads 144 to which a plurality of bonding wires 230 are connected may be disposed on the remaining portion of the first semiconductor chip 100 that does not overlap with each other.

Some of the plurality of chip pads 220 included in each of the plurality of second semiconductor chips 200 may be data pads for data DQ signal transmission. For example, the number of the data pads of each of the plurality of second semiconductor chips 200 may be 16 to 64. That is, the width of each data bus of the plurality of second semiconductor chips 200 may be 16 bits to 64 bits.

Some of the plurality of back pads 144 of the first semiconductor chip 100 may be data connection pads connected to the data pads of the plurality of second semiconductor chips 200 . Each of the data pads of the plurality of second semiconductor chips 200 and each of the data connection pads of the first semiconductor chip 100 may be connected 1:1 through different bonding wires 230 . That is, the number of the data connection pads of the first semiconductor chip 100 is the number of the plurality of second semiconductor chips 200 stacked on the first semiconductor chip 100 and the number of the plurality of second semiconductor chips 200 . ) may be a product of the number of the data pads each has. For example, the number of the data connection pads of the first semiconductor chip 100 may be 64 to 256, and the width of the data bus of the semiconductor package 1 may be 64 to 256 bits.

In the semiconductor package 1 , the plurality of chip pads 220 of the plurality of second semiconductor chips 200 and the plurality of rear pads 144 of the first semiconductor chip 100 are electrically connected through a plurality of bonding wires 230 . , and the plurality of back pads 144 and the first semiconductor device 112 may be electrically connected through the plurality of through electrodes 120 . The first semiconductor device 112 may transmit/receive data to and from an external device through the plurality of external connection terminals 150 . At least a portion of the plurality of conductive wiring patterns 132 of the wiring layer 130 may electrically connect between the first semiconductor device 112 and the plurality of external connection terminals 150 . In some embodiments, some of the plurality of conductive wiring patterns 132 may electrically connect between the plurality of through electrodes 120 and the first semiconductor device 112 . In some other embodiments, some of the plurality of conductive wiring patterns 132 may directly electrically connect some of the plurality of through electrodes 120 and some of the plurality of external connection terminals 150 .

The semiconductor package 1 has a molding layer 300 on the first semiconductor chip 100 that covers the upper surface of the first semiconductor chip 100 and surrounds the plurality of second semiconductor chips 200 and the plurality of bonding wires 230 . ) may be further included. The molding layer 300 may include, for example, an epoxy mold compound (EMC). In some embodiments, a horizontal width and a horizontal area of the molding layer 300 may have the same values as a horizontal width and a horizontal area of the first semiconductor chip 100 . For example, the sidewall of the first semiconductor chip 100 and the sidewall of the molding layer 300 may be aligned in a vertical direction to form a coplanar surface.

In the semiconductor package 1 according to the present invention, the data of the semiconductor package 1 is obtained by the product of the number of the plurality of second semiconductor chips 200 and the width of each data bus of the plurality of second semiconductor chips 200 . The width of the bus may be determined. For example, when the number of the second semiconductor chips 200 included in the semiconductor package 1 is four and the width of the data bus of the second semiconductor chip 200 is 32 bits, the data of the first semiconductor package 1 is The width of the bus may be 4 x 32 bits, that is, 128 bits. Compared with HBM (High Bandwidth Memory) having a data bus width of 1024 bits or more, the semiconductor package 1 according to the present invention, which can have a data bus width of tens of bits to hundreds of bits, is called WBM (Wide Bandwidth Memory). can be called

Therefore, in the semiconductor package 1 according to the present invention, the first semiconductor chip 100 and the plurality of second semiconductor chips 200 are electrically connected by a plurality of bonding wires 230 to achieve a relatively low manufacturing cost. to have a wide data bus width. In addition, since data can be transmitted/received with an external device through the plurality of external connection terminals 150 attached to the first semiconductor chip 100 , a relatively high-cost configuration such as a silicon interposer is not required, thereby reducing the cost. can be manufactured.

Referring to FIG. 2 , a semiconductor package 1a includes a first semiconductor chip 100a and a plurality of second semiconductor chips 200 sequentially stacked on the first semiconductor chip 100a. The first semiconductor chip 100a may be a logic semiconductor chip having circuits for controlling the memory device of the second semiconductor chip 200 .

The first semiconductor chip 100a includes a first semiconductor substrate 110a having a first semiconductor device 112a formed on an active surface thereof, and a plurality of conductive wiring patterns 132a disposed on the active surface of the first semiconductor substrate 110a. ) and a wiring layer 130a including an inter-wiring insulating layer 134a. The first semiconductor chip 100a may further include a plurality of through electrodes 120a passing through at least a portion between the top and bottom surfaces of the first semiconductor chip 100a. The first semiconductor chip 100a may have a face-up arrangement in which the active surface of the first semiconductor substrate 110a faces upward. The first semiconductor chip 100a has a plurality of front pads 142a disposed on its upper surface and connected to the conductive wiring pattern 132a, and a plurality of rear pads disposed on its lower surface and connected to one end of the plurality of through electrodes 120a ( 144a) may be further included.

The first semiconductor substrate 110a, the first semiconductor device 112a, the through electrode 120a, the wiring layer 130a, the front pad 142a, and the rear pad 144a are the first semiconductor substrate 110 shown in FIG. , the first semiconductor device 112 , the through electrode 120 , the wiring layer 130 , the front pad 142 , and the back pad 144 are substantially similar to each other, and overlapping descriptions will be omitted and the differences will be mainly described.

The plurality of second semiconductor chips 200 may be sequentially stacked on the wiring layer 130a disposed on the active surface of the first semiconductor substrate 110a.

One end of the plurality of bonding wires 230 may be attached to the chip pad 220 of the plurality of second semiconductor chips 200 , and the other end of the plurality of bonding wires 230 may be attached to the plurality of front pads 142a. there is. The bonding wire 230 may connect the chip pads 220 of each of the plurality of second semiconductor chips 200 to the plurality of front pads 142a of the first semiconductor chip 100a.

The front pad 142a of the first semiconductor chip 100 may be referred to as a first chip connection pad, and the chip pad 220 of the second semiconductor chip 200 may be referred to as a second chip connection pad. That is, the bonding wire 230 connects the first chip connection pad and the second chip connection pad, and may extend from the first chip connection pad to the second chip connection pad.

A plurality of second semiconductor chips 200 are attached to a portion of the first semiconductor chip 100a overlapping the plurality of second semiconductor chips 200 in the vertical direction, and the plurality of second semiconductor chips 200 are vertically overlapped with each other in the vertical direction. A plurality of front pads 142a to which a plurality of bonding wires 230 are connected may be disposed on the remaining portion of the first semiconductor chip 100a that does not overlap with each other.

Some of the plurality of chip pads 220 included in each of the plurality of second semiconductor chips 200 may be data pads for data DQ signal transmission. Some of the plurality of front pads 142a of the first semiconductor chip 100a may be data connection pads connected to data pads of the plurality of second semiconductor chips 200 . Each of the data pads of the plurality of second semiconductor chips 200 and each of the data connection pads of the first semiconductor chip 100a may be connected 1:1 through different bonding wires 230 .

In the semiconductor package 1a, a plurality of chip pads 220 of the plurality of second semiconductor chips 200 and a plurality of front pads 142a of the first semiconductor chip 100a are electrically connected through a plurality of bonding wires 230. , and the plurality of front pads 142a and the first semiconductor device 112a may be electrically connected through a plurality of conductive wiring patterns 132a. The first semiconductor device 112a may transmit/receive data to and from an external device through the plurality of external connection terminals 150 attached to the plurality of rear pads 144a. At least some of the plurality of through electrodes 120a may electrically connect between the first semiconductor element 112a and the plurality of external connection terminals 150 . In some embodiments, some of the plurality of through electrodes 120a may directly electrically connect some of the plurality of conductive wiring patterns 132a and some of the plurality of external connection terminals 150 .

The semiconductor package 1a according to the present invention can have a relatively wide data bus width at a relatively low manufacturing cost.

3A to 3D are cross-sectional views illustrating in stages a method of manufacturing a semiconductor package according to embodiments of the present invention. Specifically, FIGS. 3A to 3D are cross-sectional views illustrating the method of manufacturing the semiconductor package shown in FIG. 1 in stages.

Referring to FIG. 3A , a base substrate 10 is prepared. The base substrate 10 may be, for example, a silicon wafer. The base substrate 10 may include a plurality of first semiconductor chips 100 . In this case, the plurality of first semiconductor chips 100 included in the base substrate 10 refers to portions that will be separated and then become a plurality of individualized first semiconductor chips 100 . That is, the first semiconductor device 112 to be included in each of the plurality of first semiconductor chips 100 on the first semiconductor substrate 110 , the plurality of through electrodes 120 , the wiring layer 130 , and the plurality of front pads 142 . , and a plurality of rear pads 144 may be formed to form the base substrate 10 .

In some embodiments, a plurality of external connection terminals 150 may be attached to the plurality of front pads 142 . In some other embodiments, the plurality of external connection terminals 150 may be attached to the plurality of front pads 142 before performing the individualization process shown in FIG. 3D .

Referring to FIG. 3B , a plurality of second semiconductor chips 200 are stacked on a base substrate 10 to correspond to each of the plurality of first semiconductor chips 100 . Each of the plurality of second semiconductor chips 200 may be sequentially laminated on the inactive surface of the first semiconductor substrate 110 included in the base substrate 10 after attaching the die adhesive film 250 to the lower surface thereof. there is. After attaching the lowermost second semiconductor chip 200 corresponding to each of the plurality of first semiconductor chips 100 on the base substrate 10 , the chip pad 220 of the lowermost second semiconductor chip 200 and A bonding wire 230 connecting between the rear pads 144 is formed. Thereafter, another second semiconductor chip 200 is attached to the lowermost second semiconductor chip 200 , and another second semiconductor chip is placed on the base substrate 10 to which the lowermost second semiconductor chip 200 is attached. After attaching the 200 , the process of forming the bonding wire 230 connecting the chip pad 220 and the back pad 144 of the second semiconductor chip 200 may be repeatedly performed.

Referring to FIGS. 3C and 3D together, the molding layer 300 surrounding the plurality of second semiconductor chips 200 and the plurality of bonding wires 230 is formed on the base substrate 10 .

Thereafter, an individualization process of cutting the base substrate 10 and the molding layer 300 is performed so that the base substrate 10 is separated into a plurality of first semiconductor chips 100 to form a plurality of semiconductor packages 1 . can

The direction of the active surface and the inactive surface of the first semiconductor substrate 110a of the semiconductor package 1a shown in FIG. The base substrate including the plurality of first semiconductor chips 100a may be prepared and formed so as to be opposite to the directions of the active and inactive surfaces of the 110 .

4 and 5 are cross-sectional views of semiconductor packages according to embodiments of the present invention.

Referring to FIG. 4 , the semiconductor package 2 includes a redistribution structure 500 , a first semiconductor chip 100 on the redistribution structure 500 , and a plurality of sequentially stacked on the first semiconductor chip 100 . and a second semiconductor chip 200 . The first semiconductor chip 100 may further include a plurality of first chip connection pads 140 disposed on the upper surface and connected to the plurality of through electrodes 120 . The first chip connection pad 140 may be referred to as a rear pad.

One end of the plurality of bonding wires 230 is attached to the chip pad 220 of the plurality of second semiconductor chips 200 , that is, the second chip connection pad 220 , the plurality of first chip connection pads 140 , That is, the other end of the plurality of bonding wires 230 may be attached to the rear pad.

The redistribution structure 500 may include a redistribution insulating layer 510 and a redistribution conductive structure 520 . In some embodiments, the redistribution structure 500 may include a plurality of stacked redistribution insulating layers 510 . The redistribution insulating layer 510 may be formed of, for example, a photo imageable dielectric (PID) or a photosensitive polyimide (PSPI). The redistribution conductive structure 520 may include, for example, copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), or manganese (Mn). ), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), a metal such as ruthenium (Ru), or an alloy thereof However, it is not limited to these. In some embodiments, the redistribution conductive structure 520 may be formed by laminating a metal or an alloy of a metal on a seed layer including titanium, titanium nitride, or titanium tungsten.

The redistribution conductive structure 520 includes a plurality of redistribution line patterns 522 disposed on at least one of an upper surface and a lower surface of the redistribution insulating layer 510 , and a plurality of redistribution line patterns 522 passing through the redistribution insulating layer 510 . It may include a plurality of redistribution vias 524 connected to a portion of the line line pattern 522 , respectively. In some embodiments, at least a portion of the plurality of redistribution line patterns 522 may be formed together with a portion of the plurality of redistribution vias 524 to form an integral body. For example, the redistribution line pattern 522 and the redistribution via 5264 contacting the lower surface of the redistribution line pattern 522 may be integrally formed.

In some embodiments, the plurality of redistribution vias 524 may have a tapered shape extending horizontally from the lower side to the upper side. That is, the horizontal width of the plurality of redistribution vias 524 may become narrower as they move away from the semiconductor chip 100 .

A plurality of external connection pads 540 electrically connected to the redistribution conductive structure 520 may be disposed on a lower surface of the redistribution structure 500 , and a plurality of external connection terminals 540 may be disposed on the plurality of external connection pads 540 . 550) may be attached. In some embodiments, the external connection terminal 550 may be a solder ball.

The redistribution conductive structure 520 may electrically connect the plurality of conductive wiring patterns 132 and the plurality of external connection pads 540 to which the external connection terminals 550 are attached.

In some embodiments, a plurality of front pads similar to the plurality of front pads 142 shown in FIG. 1 may be interposed between the wiring layer 130 of the first semiconductor chip 100 and the redistribution structure 500 . An upper surface of the plurality of front pads may be connected to the conductive wiring pattern 132 of the wiring layer 130 , and a lower surface of the plurality of front pads may be connected to the redistribution conductive structure 520 of the redistribution structure 500 .

The semiconductor package 2 covers the upper surface of the redistribution structure 500 on the redistribution structure 500 , and includes a first semiconductor chip 100 , a plurality of second semiconductor chips 200 , and a plurality of bonding wires 230 . It may further include a molding layer 302 surrounding the. In some embodiments, a horizontal width and a horizontal area of the molding layer 302 may have the same values as a horizontal width and a horizontal area of the redistribution structure 500 . For example, the sidewall of the redistribution structure 500 and the sidewall of the molding layer 300 may be aligned in a vertical direction to form a coplanar surface.

Referring to FIG. 5 , the semiconductor package 2a includes a redistribution structure 500 , a first semiconductor chip 100a on the redistribution structure 500 , and a plurality of sequentially stacked on the first semiconductor chip 100a . and a second semiconductor chip 200 . The first semiconductor chip 100a may further include a plurality of first chip connection pads 140a disposed on the upper surface and connected to the plurality of through electrodes 120a. The first chip connection pad 140a may be referred to as a front pad.

One end of the plurality of bonding wires 230 is attached to the chip pad 220 of the plurality of second semiconductor chips 200 , that is, the second chip connection pad 220 , and a plurality of first chip connection pads 140a; That is, the other end of the plurality of bonding wires 230 may be attached to the front pad.

In some embodiments, a plurality of rear pads similar to the plurality of rear pads 144 shown in FIG. 2 may be interposed between the non-active surface of the first semiconductor chip 100a and the redistribution structure 500 . An upper surface of the plurality of back pads may be connected to the plurality of through electrodes 120a , and a lower surface of the plurality of rear pads may be connected to the redistribution conductive structure 520 of the redistribution structure 500 .

The semiconductor package 2a may further include a molding layer 302 surrounding the first semiconductor chip 100a, the plurality of second semiconductor chips 200 and the plurality of bonding wires 230 on the redistribution structure 500 . can

6A to 6E are cross-sectional views illustrating in stages a method of manufacturing a semiconductor package according to an exemplary embodiment of the present invention. Specifically, FIGS. 6A to 6E are cross-sectional views illustrating the method of manufacturing the semiconductor package shown in FIG. 4 in stages.

Referring to FIG. 6A , a redistribution substrate 50 is prepared. The redistribution substrate 50 may include, for example, a plurality of redistribution structures 500 formed on a support substrate (not shown). In this case, the plurality of redistribution structures 500 included in the redistribution substrate 50 means portions that will be separated and become a plurality of individualized redistribution structures 500 . That is, the redistribution substrate 50 may be formed by repeatedly forming the redistribution insulating layer 510 and the redistribution conductive structure 520 on the support substrate one or more times.

In some embodiments, a plurality of external connection terminals 550 connected to the redistribution conductive structure 520 may be attached to the lower surface of the redistribution substrate 50 . In some other embodiments, the plurality of external connection terminals 550 may be attached to the lower surface of the redistribution board 50 before the individualization process shown in FIG. 6E is performed.

Referring to FIG. 6B , a plurality of first semiconductor chips 100 are attached to the redistribution substrate 50 . The plurality of first semiconductor chips 100 may be disposed on the upper surface of the redistribution substrate 50 to be spaced apart from each other.

Referring to FIG. 6C , a plurality of second semiconductor chips 200 are stacked on the plurality of first semiconductor chips 100 to correspond to each of the plurality of first semiconductor chips 100 . Each of the plurality of second semiconductor chips 200 may be sequentially laminated on the inactive surface of the first semiconductor substrate 110 included in the base substrate 10 after attaching the die adhesive film 250 to the lower surface thereof. there is. After attaching the lowermost second semiconductor chip 200 corresponding to each of the plurality of first semiconductor chips 100 on the base substrate 10 , the chip pad 220 of the lowermost second semiconductor chip 200 and A bonding wire 230 connecting between the rear pads 144 is formed. Thereafter, another second semiconductor chip 200 is attached to the lowermost second semiconductor chip 200 , and another second semiconductor chip is placed on the base substrate 10 to which the lowermost second semiconductor chip 200 is attached. After attaching the 200 , the process of forming the bonding wire 230 connecting the chip pad 220 and the back pad 144 of the second semiconductor chip 200 may be repeatedly performed.

6D and 6E together, a molding layer 302 surrounding the first semiconductor chip 100 , the plurality of second semiconductor chips 200 , and the plurality of bonding wires 230 on the redistribution substrate 50 . to form

Thereafter, an individualization process of cutting the redistribution substrate 50 and the molding layer 300 is performed so that the redistribution substrate 50 is separated into a plurality of redistribution structures 500 , thereby forming a plurality of semiconductor packages 2 . can do.

The direction of the active surface and the inactive surface of the first semiconductor substrate 110a of the semiconductor package 2a shown in FIG. The plurality of first semiconductor chips 100a may be attached to and formed on the redistribution substrate 50 so that the directions of the active surface and the inactive surface of the 110 are opposite to each other.

7 to 16 are cross-sectional views of semiconductor packages according to embodiments of the present invention.

Referring to FIG. 7 , the semiconductor package 3 includes a first semiconductor chip 100b and a plurality of second semiconductor chips 200 sequentially stacked on the first semiconductor chip 100b. In some embodiments, each of the plurality of second semiconductor chips 200 may be a memory semiconductor chip having a memory device, and the first semiconductor chip 100b may be configured to control a memory device included in the second semiconductor chip 200 . It may be a logic semiconductor chip having circuits.

The first semiconductor chip 100b is disposed on the first semiconductor substrate 110b on which the first semiconductor device 112b is formed on the active surface, and on the active surface of the first semiconductor substrate 110b, and includes a plurality of conductive wiring patterns 132b. ) and a wiring layer 130b including an inter-wiring insulating layer 134b. The first semiconductor chip 100b may further include a plurality of through electrodes 120b passing through at least a portion between the top and bottom surfaces of the first semiconductor chip 100b. The first semiconductor chip 100b may have a face-down arrangement in which the active surface of the first semiconductor substrate 110b faces downward. The first semiconductor chip 100b includes a plurality of front pads 142b disposed on the lower surface and connected to the conductive wiring pattern 132b, and a plurality of rear pads 144b disposed on the upper surface and connected to the plurality of through electrodes 120b. may further include.

The first semiconductor substrate 110b, the first semiconductor device 112b, the through electrode 120b, the wiring layer 130b, the front pad 142b, and the rear pad 144b are the first semiconductor substrate 110 shown in FIG. 1 . , the first semiconductor device 112 , the through electrode 120 , the wiring layer 130 , the front pad 142 , and the back pad 144 are substantially similar to each other, and overlapping descriptions will be omitted and the differences will be mainly described.

The first semiconductor device 112b may include a circuit for changing a branch structure electrically connected to the plurality of second semiconductor chips 200 . In some embodiments, the first semiconductor device 112b may include a Serializer/Deserialize (SerDes) circuit. For example, in the first semiconductor device 112b, two branches connected to two of the data pads of the second semiconductor chip 200 are reduced to one, and the external connection terminal ( ) attached to the front pad 142b. 150) can be transferred.

Therefore, in the semiconductor package 3 according to the present invention, the product of the number of the plurality of second semiconductor chips 200 and the width of each data bus of the plurality of second semiconductor chips 200 and the first semiconductor element 112b The width of the data bus of the semiconductor package 3 may be determined by a circuit that changes the number of branch electrical paths. For example, when the number of second semiconductor chips 200 included in the semiconductor package 3 is 4 and the data bus width of the second semiconductor chip 200 is 32 bits, the first semiconductor device 112b is 2 When the number of paths is changed to one, the width of the data bus of the first semiconductor package 3 may be 4×32/2 bits, that is, 64 bits.

Referring to FIG. 8 , the semiconductor package 3a includes a first semiconductor chip 100c and a plurality of second semiconductor chips 200 sequentially stacked on the first semiconductor chip 100c. In some embodiments, each of the plurality of second semiconductor chips 200 may be a memory semiconductor chip having a memory device, and the first semiconductor chip 100c may be configured to control a memory device included in the second semiconductor chip 200 . It may be a logic semiconductor chip having circuits.

The first semiconductor chip 100c is disposed on the first semiconductor substrate 110c on which the first semiconductor device 112c is formed on the active surface, and on the active surface of the first semiconductor substrate 110c, and includes a plurality of conductive wiring patterns 132c. ) and a wiring layer 130c including an inter-wiring insulating layer 134c. The first semiconductor chip 100c may further include a plurality of through electrodes 120c penetrating at least a portion between the upper and lower surfaces of the first semiconductor chip 100c. The first semiconductor chip 100c may have a face-up arrangement in which the active surface of the first semiconductor substrate 110b faces upward. The first semiconductor chip 100c has a plurality of front pads 142c disposed on the upper surface and connected to the conductive wiring pattern 132c, and a plurality of rear pads 144c disposed on the lower surface and connected to the plurality of through electrodes 120c. may further include.

The first semiconductor substrate 110c, the first semiconductor device 112c, the through electrode 120c, the wiring layer 130c, the front pad 142c, and the rear pad 144c are the first semiconductor substrate 110a shown in FIG. 2 . , the first semiconductor device 112a, the through electrode 120a, the wiring layer 130a, the front pad 142a, and the back pad 144a are substantially similar to each other, so the overlapping description will be omitted and the differences will be mainly described.

Similar to the first semiconductor device 112b shown in FIG. 7 , the first semiconductor device 112c may include a circuit for changing a branch structure electrically connected to the plurality of second semiconductor chips 200 . In some embodiments, the first semiconductor device 112c may include a SerDes circuit. For example, the first semiconductor device 112c changes two branches connected to two of the data pads of the second semiconductor chip 200 into one, and the external connection terminal 150 attached to the rear pad 144c. can be forwarded to

Referring to FIG. 9 , the semiconductor package 4 includes a redistribution structure 500 , a first semiconductor chip 100b on the redistribution structure 500 , and a plurality of sequentially stacked on the first semiconductor chip 100b . and a second semiconductor chip 200 . The first semiconductor chip 100b may further include a plurality of first chip connection pads 140b disposed on the upper surface and connected to the plurality of through electrodes 120b. The first chip connection pad 140b may be referred to as a rear pad.

One end of the plurality of bonding wires 230 is attached to the chip pad 220 of the plurality of second semiconductor chips 200 , that is, the second chip connection pad 220 , the plurality of first chip connection pads 140b; That is, the other end of the plurality of bonding wires 230 may be attached to the rear pad.

The semiconductor package 4 may further include a molding layer 302 surrounding the first semiconductor chip 100b, the plurality of second semiconductor chips 200 and the plurality of bonding wires 230 on the redistribution structure 500 . can

The difference between the semiconductor package 4 shown in FIG. 9 and the semiconductor package 3 shown in FIG. 7 is similar to the difference between the semiconductor package 2 shown in FIG. 4 and the semiconductor package 1 shown in FIG. 1 , and overlapping explanations should be omitted.

Referring to FIG. 10 , the semiconductor package 4a includes a redistribution structure 500 , a first semiconductor chip 100c on the redistribution structure 500 , and a plurality of sequentially stacked on the first semiconductor chip 100c . and a second semiconductor chip 200 . The first semiconductor chip 100c may further include a plurality of first chip connection pads 140c disposed on the upper surface and connected to the plurality of through electrodes 120c. The first chip connection pad 140c may be referred to as a front pad.

One end of a plurality of bonding wires 230 is attached to the chip pad 220 of the plurality of second semiconductor chips 200 , that is, the second chip connection pad 220 , and a plurality of first chip connection pads 140c; That is, the other end of the plurality of bonding wires 230 may be attached to the front pad.

The semiconductor package 4a may further include a molding layer 302 surrounding the first semiconductor chip 100c, the plurality of second semiconductor chips 200 and the plurality of bonding wires 230 on the redistribution structure 500 . can

The difference between the semiconductor package 4a shown in FIG. 10 and the semiconductor package 3a shown in FIG. 8 is similar to the difference between the semiconductor package 2a shown in FIG. 5 and the semiconductor package 1a shown in FIG. The description will be omitted.

Referring to FIG. 11 , the semiconductor package 5 includes a first semiconductor chip 100d and a plurality of second semiconductor chips 200 stacked on the first semiconductor chip 100d. In some embodiments, each of the plurality of second semiconductor chips 200 may be a memory semiconductor chip having a memory device, and the first semiconductor chip 100d may be configured to control a memory device included in the second semiconductor chip 200 . It may be a logic semiconductor chip having circuits.

The first semiconductor chip 100d is disposed on the first semiconductor substrate 110d on which the first semiconductor element 112d is formed on the active surface, and on the active surface of the first semiconductor substrate 110d, and includes a plurality of conductive wiring patterns 132d. ) and a wiring layer 130d including an inter-wiring insulating layer 134d. The first semiconductor chip 100d may further include a plurality of through electrodes 120d penetrating at least a portion between the top and bottom surfaces of the first semiconductor chip 100d. The first semiconductor chip 100d includes a plurality of front pads 142d disposed on the lower surface and connected to the conductive wiring pattern 132d, and a plurality of rear pads 144d disposed on the upper surface and connected to the plurality of through electrodes 120d. may further include.

The first semiconductor substrate 110d, the first semiconductor device 112d, the through electrode 120d, the wiring layer 130d, the front pad 142d, and the rear pad 144d are the first semiconductor substrate 110b shown in FIG. 7 . , the first semiconductor device 112b, the through electrode 120b, the wiring layer 130b, the front pad 142b, and the rear pad 144b are substantially similar to each other, so the overlapping description will be omitted and the differences will be mainly described.

Some of the plurality of second semiconductor chips 200 are sequentially stacked on the first semiconductor chip 100d, and other portions of the plurality of second semiconductor chips 200 are sequentially stacked on the plurality of second semiconductors. They may be sequentially stacked on the first semiconductor chip 100d to be spaced apart from some of the chips 200 .

The number of the plurality of second semiconductor chips 200 included in the semiconductor package 3 shown in FIG. 7 and the plurality of second semiconductor chips 200 included in the semiconductor package 5 shown in FIG. 10 are the same, but in FIG. The number of second semiconductor chips 200 vertically stacked on the first semiconductor chip 100b in the semiconductor package 3 shown in FIG. 7 and the first semiconductor chip 100d in the semiconductor package 5 shown in FIG. 10 . The number of the second semiconductor chips 200 stacked in the vertical direction may be different.

For example, the semiconductor package 3 shown in FIG. 7 may have a single stack structure in which eight second semiconductor chips 200 are stacked on the first semiconductor chip 100b, and the semiconductor package shown in FIG. 11 . (5) may have two stacked structures in which four semiconductor chips 200 are stacked on the first semiconductor chip 100d.

That is, the semiconductor package 5 shown in FIG. 11 has substantially the same operating characteristics as the semiconductor package 3 shown in FIG. 7 , but has a size in the vertical direction compared to the semiconductor package 3 shown in FIG. 7 , that is, A vertical height may have a relatively small value, but a width and a horizontal area in a horizontal direction may have a relatively large value.

Referring to FIG. 12 , the semiconductor package 5a includes a first semiconductor chip 100e and a plurality of second semiconductor chips 200 stacked on the first semiconductor chip 100e. In some embodiments, each of the plurality of second semiconductor chips 200 may be a memory semiconductor chip having a memory device, and the first semiconductor chip 100e may be configured to control a memory device included in the second semiconductor chip 200 . It may be a logic semiconductor chip having circuits.

The first semiconductor chip 100e includes a first semiconductor substrate 110e having a first semiconductor device 112e formed on an active surface thereof, and a plurality of conductive wiring patterns 132e disposed on the active surface of the first semiconductor substrate 110e. ) and a wiring layer 130e including an inter-wiring insulating layer 134e. The first semiconductor chip 100e may further include a plurality of through electrodes 120e penetrating at least a portion between the top and bottom surfaces of the first semiconductor chip 100e. The first semiconductor chip 100e has a plurality of front pads 142e disposed on its upper surface and connected to the conductive wiring pattern 132e, and a plurality of rear pads 144e disposed on its lower surface and connected to the plurality of through electrodes 120e. may further include.

The first semiconductor substrate 110e, the first semiconductor device 112e, the through electrode 120e, the wiring layer 130e, the front pad 142e, and the rear pad 144e are the first semiconductor substrate 110c shown in FIG. 8 . , the first semiconductor device 112c, the through electrode 120c, the wiring layer 130c, the front pad 142c, and the rear pad 144c are substantially similar to each other, and thus the overlapping description will be omitted and the differences will be mainly described.

Some of the plurality of second semiconductor chips 200 are sequentially stacked on the first semiconductor chip 100e, and other portions of the plurality of second semiconductor chips 200 are sequentially stacked on the plurality of second semiconductors. They may be sequentially stacked on the first semiconductor chip 100e so as to be spaced apart from some of the chips 200 .

The difference between the semiconductor package 5a shown in FIG. 12 and the semiconductor package 3a shown in FIG. 8 is similar to the difference between the semiconductor package 5 shown in FIG. 11 and the semiconductor package 3 shown in FIG. 7 . The description will be omitted.

That is, the semiconductor package 5a shown in FIG. 12 has substantially the same operating characteristics as the semiconductor package 3a shown in FIG. 8 , but has a size in the vertical direction compared to the semiconductor package 3a shown in FIG. 8 , that is, A vertical height may have a relatively small value, but a width and a horizontal area in a horizontal direction may have a relatively large value.

Referring to FIG. 13 , the semiconductor package 6 includes a first semiconductor chip 100f and a plurality of second semiconductor chips 200 sequentially stacked on the first semiconductor chip 100f. In some embodiments, each of the plurality of second semiconductor chips 200 may be a memory semiconductor chip having a memory device, and the first semiconductor chip 100f may be configured to control a memory device included in the second semiconductor chip 200 . It may be a logic semiconductor chip having circuits.

The first semiconductor chip 100f includes a first semiconductor substrate 110f having a first semiconductor device 112f formed on an active surface thereof, and a plurality of conductive wiring patterns 132f disposed on the active surface of the first semiconductor substrate 110f. ) and a wiring layer 130f including an inter-wiring insulating layer 134f. The first semiconductor chip 100f may further include a plurality of through electrodes 120f passing through at least a portion between the top and bottom surfaces of the first semiconductor chip 100f. The first semiconductor chip 100f includes a plurality of front pads 142f disposed on the lower surface and connected to the conductive wiring pattern 132f, and a plurality of rear pads 144f disposed on the upper surface and connected to the plurality of through electrodes 120f. may further include.

The first semiconductor substrate 110f, the first semiconductor device 112f, the through electrode 120f, the wiring layer 130f, the front pad 142f, and the rear pad 144f are the first semiconductor substrate 110b shown in FIG. 7 . , the first semiconductor device 112b, the through electrode 120b, the wiring layer 130b, the front pad 142b, and the rear pad 144b are substantially similar to each other, so the overlapping description will be omitted and the differences will be mainly described.

The first semiconductor device 112f may include a circuit for changing a branch structure electrically connected to the plurality of second semiconductor chips 200 . In some embodiments, the first semiconductor device 112f may include a SerDes circuit. For example, the first semiconductor device 112f changes four branches connected to four of the data pads of the second semiconductor chip 200 into one, and the external connection terminal 150 attached to the front pad 142f. can be forwarded to For example, the width of the data bus of the semiconductor package 6 may be 16 bits to 64 bits.

Accordingly, in the semiconductor package 6 according to the present invention, the product of the number of the plurality of second semiconductor chips 200 and the width of each data bus of the plurality of second semiconductor chips 200 and the first semiconductor element 112f The width of the data bus of the semiconductor package 6 may be determined by a circuit that changes the number of branch electrical paths. For example, when the number of the second semiconductor chips 200 included in the semiconductor package 6 is four and the width of the data bus of the second semiconductor chip 200 is 32 bits, the number of the first semiconductor elements 112f is 4 When the number of paths is changed to one, the width of the data bus of the first semiconductor package 6 may be 4x32/4 bits, that is, 32 bits.

Referring to FIG. 14 , the semiconductor package 6a includes a first semiconductor chip 100g and a plurality of second semiconductor chips 200 sequentially stacked on the first semiconductor chip 100g. In some embodiments, each of the plurality of second semiconductor chips 200 may be a memory semiconductor chip having a memory device, and the first semiconductor chip 100g may be configured to control a memory device included in the second semiconductor chip 200 . It may be a logic semiconductor chip having circuits.

The first semiconductor chip 100g is disposed on the first semiconductor substrate 110g on which the first semiconductor element 112g is formed on the active surface, and on the active surface of the first semiconductor substrate 110g, and includes a plurality of conductive wiring patterns 132g. ) and a wiring layer 130g including an inter-wiring insulating layer 134g. The first semiconductor chip 100g may further include a plurality of through electrodes 120g penetrating at least a portion between the upper surface and the lower surface of the first semiconductor chip 100g. The first semiconductor chip 100g has a plurality of front pads 142g disposed on its upper surface and connected to the conductive wiring pattern 132g, and a plurality of rear pads 144g disposed on its lower surface and connected to the plurality of through electrodes 120g. may further include.

The first semiconductor substrate 110g, the first semiconductor device 112g, the through electrode 120g, the wiring layer 130g, the front pad 142g, and the rear pad 144g are the first semiconductor substrate 110c shown in FIG. , the first semiconductor device 112c, the through electrode 120c, the wiring layer 130c, the front pad 142c, and the rear pad 144c are substantially similar to each other, and thus the overlapping description will be omitted and the differences will be mainly described.

Similar to the first semiconductor device 112f shown in FIG. 13 , the first semiconductor device 112g may include a circuit for changing a branch structure electrically connected to the plurality of second semiconductor chips 200 . In some embodiments, the first semiconductor device 112g may include a SerDes circuit. For example, the first semiconductor device 112g changes four branches connected to four of the data pads of the second semiconductor chip 200 into one, and the external connection terminal 150 attached to the front pad 142g. can be forwarded to

15 , the semiconductor package 7 includes a redistribution structure 500 , a first semiconductor chip 100f on the redistribution structure 500 , and a plurality of sequentially stacked on the first semiconductor chip 100f . and a second semiconductor chip 200 . The first semiconductor chip 100f may further include a plurality of first chip connection pads 140f disposed on the upper surface and connected to the plurality of through electrodes 120f. The first chip connection pad 140f may be referred to as a rear pad.

One end of the plurality of bonding wires 230 is attached to the chip pad 220 of the plurality of second semiconductor chips 200 , that is, the second chip connection pad 220 , and a plurality of first chip connection pads 140f; That is, the other end of the plurality of bonding wires 230 may be attached to the rear pad.

The semiconductor package 7 may further include a molding layer 302 surrounding the first semiconductor chip 100f, the plurality of second semiconductor chips 200 and the plurality of bonding wires 230 on the redistribution structure 500 . can

The difference between the semiconductor package 7 shown in FIG. 15 and the semiconductor package 5 shown in FIG. 11 is similar to the difference between the semiconductor package 2 shown in FIG. 4 and the semiconductor package 1 shown in FIG. 1 , and overlapping explanations should be omitted.

Referring to FIG. 16 , the semiconductor package 7a includes a redistribution structure 500 , a first semiconductor chip 100g on the redistribution structure 500 , and a plurality of sequentially stacked on the first semiconductor chip 100g . and a second semiconductor chip 200 . The first semiconductor chip 100g may further include a plurality of first chip connection pads 140g disposed on the upper surface and connected to the plurality of through electrodes 120g. The first chip connection pad 140g may be referred to as a front pad.

One end of the plurality of bonding wires 230 is attached to the chip pad 220 of the plurality of second semiconductor chips 200 , that is, the second chip connection pad 220 , the plurality of first chip connection pads 140g; That is, the other end of the plurality of bonding wires 230 may be attached to the front pad.

The semiconductor package 7a may further include a molding layer 302 surrounding the first semiconductor chip 100g, the plurality of second semiconductor chips 200 and the plurality of bonding wires 230 on the redistribution structure 500 . can

The difference between the semiconductor package 7a shown in FIG. 16 and the semiconductor package 5a shown in FIG. 12 is similar to the difference between the semiconductor package 2a shown in FIG. 5 and the semiconductor package 1a shown in FIG. The description will be omitted.

17A and 17B are circuit diagrams illustrating exemplary circuits of a first semiconductor device of a first semiconductor chip included in a semiconductor package according to embodiments of the present invention.

17A and 17B together, the first semiconductor device of the first semiconductor chip included in the semiconductor package may include a SerDes circuit. The circuit shown in FIG. 17A is the first semiconductor device 112b shown in FIGS. 7 and 9 , the semiconductor device 112c shown in FIGS. 8 and 10 , the semiconductor device 112d shown in FIG. 11 , or the semiconductor device shown in FIG. 12 . The device 112e is a SerDes circuit, and the circuit shown in FIG. 17B may be the SerDes circuit included in the semiconductor device 112f shown in FIGS. 13 and 15 or the semiconductor device 112g shown in FIGS. 14 and 16 .

Referring to FIG. 17A , the SerDes circuit includes two dies Die 1 and Die 2 , that is, two different second semiconductor chips 200 among the plurality of second semiconductor chips 200 shown in FIGS. 7 to 12 , respectively. One data (DQ) signal of the (1x) may be input in parallel, and two data signals (2x) may be serially output. Accordingly, two branches connected to two of the data pads of the second semiconductor chip 200 shown in FIGS. 7 to 12 may be changed to one and transmitted to the external connection terminals 150 and 550 .

Referring to FIG. 17B , the SerDes circuit includes four dies Die 1 , Die 2 , Die 3 , and Die 4 , that is, four different second semiconductor chips 200 among the plurality of second semiconductor chips 200 shown in FIGS. 13 to 16 . One data DQ signal 1x of each of the semiconductor chips 200 may be input in parallel, and two data signals 4x may be serially output. Accordingly, four branches connected to four of the data pads of the second semiconductor chip 200 shown in FIGS. 13 to 16 may be changed to one and transmitted to the external connection terminals 150 and 550 .

18 to 21 are cross-sectional views of semiconductor packages according to embodiments of the present invention.

Referring to FIG. 18 , the semiconductor package 8 includes a redistribution structure 500 , a first semiconductor chip 100h on the redistribution structure 500 , and a plurality of sequentially stacked on the first semiconductor chip 100h . and a second semiconductor chip 200a. In some embodiments, each of the plurality of second semiconductor chips 200a may be a memory semiconductor chip having a memory device, and the first semiconductor chip 100h may be configured to control a memory device included in the second semiconductor chip 200a. It may be a logic semiconductor chip having circuits.

The first semiconductor chip 100h is disposed on the first semiconductor substrate 110h on which the first semiconductor element 112h is formed on the active surface, and on the active surface of the first semiconductor substrate 110h, and includes a plurality of conductive wiring patterns 132h. ) and a wiring layer 130h including an inter-wiring insulating layer 134h. The first semiconductor chip 100h may further include a plurality of through electrodes 120h penetrating at least a portion between the top and bottom surfaces of the first semiconductor chip 100h. The first semiconductor chip 100h may further include a plurality of first chip connection pads 140h disposed on the upper surface and connected to the plurality of through electrodes 120h. The first chip connection pad 140h may be referred to as a rear pad.

The second semiconductor chip 200a may include a second semiconductor substrate 210a having a second semiconductor device 212a formed on an active surface thereof, and a plurality of chip pads 220a disposed on an upper surface of the second semiconductor chip 200a. The chip pad 220a of the second semiconductor chip 200a may be referred to as a second chip connection pad.

The first semiconductor substrate 110h, the first semiconductor device 112h, the through electrode 120h, the wiring layer 130h, the first chip connection pad 140h, the second semiconductor substrate 210a, and the second semiconductor device 212a ), and the chip pad 220a shown in FIG. 4 include the first semiconductor substrate 110 , the first semiconductor device 112 , the through electrode 120 , the wiring layer 130 , the first chip connection pad 140 , and the second Since the second semiconductor substrate 210 , the second semiconductor device 212 , and the chip pad 220 are substantially similar to each other, the overlapping description will be omitted and the differences will be mainly described.

One end of the plurality of bonding wires 230a is attached to the chip pad 220a of the plurality of second semiconductor chips 200a, that is, the second chip connection pad 220a, and a plurality of first chip connection pads 140h; That is, the other end of the plurality of bonding wires 230a may be attached to the rear pad.

The plurality of chip pads 220a may be edge pads disposed on a portion adjacent to an edge of the top surface of the second semiconductor chip 210a, that is, a portion of the top surface adjacent to a side surface of the second semiconductor chip 210a. In some embodiments, the plurality of chip pads 220a may be disposed adjacent to only one side surface of the second semiconductor chip 210a.

Each of the plurality of second semiconductor chips 200a may have a die adhesive film 250 attached to a lower surface thereof therebetween, and may be attached to a structure thereunder. The plurality of second semiconductor chips 200a may be stacked over the first semiconductor chip 100h so as to protrude outward from the first semiconductor chip 100h in a horizontal direction. Portions adjacent to at least one side of the plurality of second semiconductor chips 200a may be stacked over the first semiconductor chip 100h to overhang with respect to the first semiconductor chip 100h.

In some embodiments, the horizontal width and horizontal area of the second semiconductor chip 200a may be greater than the horizontal width and horizontal area of the first semiconductor chip 100h. For example, the plurality of second semiconductor chips 200a may partially overlap within the first semiconductor chip 100h in a vertical direction, and the remaining portions may protrude outward so as not to overlap the first semiconductor chip 100h. .

The supporter 190 may be interposed between portions of the plurality of second semiconductor chips 200a that do not overlap the first semiconductor chip 100h in the vertical direction and the redistribution structure 500 . The supporter 190 may be spaced apart from the first semiconductor chip 100h on the redistribution structure 500 . The supporter 190 may be formed of, for example, a semiconductor substrate such as silicon or a ceramic substrate.

The upper surface of the supporter 190 and the upper surface of the first semiconductor substrate 110h may be positioned at the same vertical level. The plurality of second semiconductor chips 200a may be sequentially stacked over the first semiconductor chip 100h and the supporter 190 .

The horizontal width and horizontal area of the supporter 190 may be smaller than the horizontal width and horizontal area of the second semiconductor chip 200a. For example, all portions of the supporter 190 may be overlapped in the plurality of second semiconductor chips 200a in a vertical direction.

At least one side surface of the plurality of semiconductor chips 210a and at least one side surface of the supporter 190 may be vertically aligned. In some embodiments, the other side opposite to one side of the second semiconductor chip 210a on which the plurality of chip pads 220a are adjacently disposed and the side surface of the supporter 190 may be vertically aligned.

The semiconductor package 8 includes a molding layer 304 surrounding the supporter 190 , the first semiconductor chip 100h , the plurality of second semiconductor chips 200a , and the plurality of bonding wires 230a on the redistribution structure 500 . ) may be further included.

Referring to FIG. 19 , the semiconductor package 8a includes a redistribution structure 500 , a first semiconductor chip 100i on the redistribution structure 500 , and a plurality of sequentially stacked on the first semiconductor chip 100i . and a second semiconductor chip 200i.

The first semiconductor chip 100i includes a first semiconductor substrate 110i having a first semiconductor device 112i formed on an active surface thereof, and a plurality of conductive wiring patterns 132i disposed on the active surface of the first semiconductor substrate 110i. ) and a wiring layer 130i including an inter-wiring insulating layer 134i. The first semiconductor chip 100i may further include a plurality of through electrodes 120i penetrating at least a portion between the upper surface and the lower surface of the first semiconductor chip 100i. The first semiconductor chip 100i may further include a plurality of first chip connection pads 140i disposed on the upper surface and connected to the plurality of through electrodes 120i. The first chip connection pad 140i may be referred to as a front pad.

The first semiconductor substrate 110i, the first semiconductor element 112i, the through electrode 120i, the wiring layer 130i, and the first chip connection pad 140i include the first semiconductor substrate 110a and the second semiconductor substrate 110a shown in FIG. Since the first semiconductor element 112a, the through electrode 120a, the wiring layer 130a, and the first chip connection pad 140a are substantially similar to each other, the overlapping description will be omitted and the differences will be mainly described.

One end of the plurality of bonding wires 230a is attached to the chip pad 220a of the plurality of second semiconductor chips 200a, that is, the second chip connection pad 220a, and the plurality of first chip connection pads 140i; That is, the other end of the plurality of bonding wires 230a may be attached to the front pad.

The plurality of second semiconductor chips 200a may be stacked over the first semiconductor chip 100i to protrude outward from the first semiconductor chip 100i. Portions adjacent to at least one side of the plurality of second semiconductor chips 200a may be stacked over and over the first semiconductor chip 100i to overhang the first semiconductor chip 100i.

In some embodiments, a horizontal width and a horizontal area of the second semiconductor chip 200a may be greater than a horizontal width and a horizontal area of the first semiconductor chip 100i. For example, the plurality of second semiconductor chips 200a may partially overlap within the first semiconductor chip 100i in a vertical direction, and the remaining portions may protrude outward so as not to overlap the first semiconductor chip 100i. .

The supporter 190 may be interposed between portions of the plurality of second semiconductor chips 200a that do not overlap the first semiconductor chip 100i in the vertical direction and the redistribution structure 500 . The supporter 190 may be spaced apart from the first semiconductor chip 100 on the redistribution structure 500 . The upper surface of the supporter 190 and the upper surface of the first semiconductor substrate 110i may be positioned at the same vertical level. The plurality of second semiconductor chips 200a may be sequentially stacked over the first semiconductor chip 100i and the supporter 190 .

The semiconductor package 8a has a molding layer 304 surrounding the supporter 190 , the first semiconductor chip 100i , the plurality of second semiconductor chips 200a , and the plurality of bonding wires 230a on the redistribution structure 500 . ) may be further included.

Referring to FIG. 20 , the semiconductor package 8b includes a redistribution structure 500 , a first semiconductor chip 100j on the redistribution structure 500 , and a plurality of sequentially stacked on the first semiconductor chip 100j . and a second semiconductor chip 200a. The first semiconductor chip 100j is a first semiconductor substrate 110j having a first semiconductor device 112j formed on an active surface thereof, and is disposed on the active surface of the first semiconductor substrate 110j and includes a plurality of conductive wiring patterns 132j ) and a wiring layer 130j including an inter-wiring insulating layer 134j. The first semiconductor chip 100j may further include a plurality of through electrodes 120j penetrating at least a portion between the top and bottom surfaces of the first semiconductor chip 100j. The first semiconductor chip 100j may further include a plurality of first chip connection pads 140j disposed on the upper surface and connected to the plurality of through electrodes 120j. The first chip connection pad 140j may be referred to as a rear pad.

The first semiconductor substrate 110j, the first semiconductor element 112j, the through electrode 120j, the wiring layer 130j, and the first chip connection pad 140j are the first semiconductor substrate 110 and the first chip connection pad 140j shown in FIG. 1 The semiconductor element 112 , the through electrode 120 , the wiring layer 130 , and the first chip connection pad 140 , and are substantially similar to each other, and overlapping descriptions will be omitted and the differences will be mainly described.

The first semiconductor device 112j may include a circuit for changing a branch structure electrically connected to the plurality of second semiconductor chips 200a. In some embodiments, the first semiconductor device 112j may include a SerDes circuit. For example, the first semiconductor device 112j may change two branches connected to two of the data pads of the second semiconductor chip 200a to be reduced to one so as to be transferred to the wiring layer 130 .

The plurality of second semiconductor chips 200a may be stacked over the first semiconductor chip 100j to protrude outward from the first semiconductor chip 100j. Portions adjacent to at least one side surface of the plurality of second semiconductor chips 200a may be stacked over and over the first semiconductor chip 100j to overhang with respect to the first semiconductor chip 100j.

In some embodiments, the horizontal width and horizontal area of the second semiconductor chip 200a may be greater than the horizontal width and horizontal area of the first semiconductor chip 100j. For example, the plurality of second semiconductor chips 200a may only partially overlap within the first semiconductor chip 100j in the vertical direction, and the remaining portions may protrude outward so as not to overlap the first semiconductor chip 100j. .

A supporter 190 may be interposed between portions of the plurality of second semiconductor chips 200a that do not overlap the first semiconductor chip 100j in the vertical direction and the redistribution structure 500 . The supporter 190 may be spaced apart from the first semiconductor chip 100j on the redistribution structure 500 . The upper surface of the supporter 190 and the upper surface of the first semiconductor substrate 110j may be positioned at the same vertical level. The plurality of second semiconductor chips 200a may be sequentially stacked over the first semiconductor chip 100j and the supporter 190 .

The semiconductor package 8b has a molding layer 304 surrounding the supporter 190 , the first semiconductor chip 100j , the plurality of second semiconductor chips 200a , and the plurality of bonding wires 230a on the redistribution structure 500 . ) may be further included.

Referring to FIG. 21 , the semiconductor package 8c includes a redistribution structure 500 , a first semiconductor chip 100k on the redistribution structure 500 , and a plurality of sequentially stacked on the first semiconductor chip 100k . and a second semiconductor chip 200a. The first semiconductor chip 100k includes a first semiconductor substrate 110k having a first semiconductor device 112k formed on an active surface thereof, and a plurality of conductive wiring patterns 132k disposed on the active surface of the first semiconductor substrate 110k. ) and a wiring layer 130k including an inter-wiring insulating layer 134k. The first semiconductor chip 100k may further include a plurality of through electrodes 120k penetrating at least a portion between the upper and lower surfaces of the first semiconductor chip 100k. The first semiconductor chip 100k may further include a plurality of first chip connection pads 140k disposed on the upper surface and connected to the plurality of through electrodes 120k. The first chip connection pad 140k may be referred to as a rear pad.

The first semiconductor substrate 110k, the first semiconductor device 112k, the through electrode 120k, the wiring layer 130k, and the first chip connection pad 140k include the first semiconductor substrate 110a and the second semiconductor substrate 110a shown in FIG. 5 . Since the first semiconductor element 112a, the through electrode 120a, the wiring layer 130a, and the first chip connection pad 140a are substantially similar to each other, the overlapping description will be omitted and the differences will be mainly described.

The first semiconductor device 112k may include a circuit for changing a branch structure electrically connected to the plurality of second semiconductor chips 200a. In some embodiments, the first semiconductor device 112k may include a SerDes circuit. For example, the first semiconductor device 112k may change two branches connected to two of the data pads of the second semiconductor chip 200a to be reduced to one, and may be transmitted to the through electrode 120k.

The plurality of second semiconductor chips 200a may be stacked over the first semiconductor chip 100k to protrude outward from the first semiconductor chip 100k. Portions adjacent to at least one side surface of the plurality of second semiconductor chips 200a may be stacked over and over the first semiconductor chip 100k to overhang with respect to the first semiconductor chip 100k.

In some embodiments, a horizontal width and a horizontal area of the second semiconductor chip 200a may be greater than a horizontal width and a horizontal area of the first semiconductor chip 100k. For example, the plurality of second semiconductor chips 200a may only partially overlap in the first semiconductor chip 100k in the vertical direction, and the remaining portions may protrude outward so as not to overlap the first semiconductor chip 100k. .

The supporter 190 may be interposed between portions of the plurality of second semiconductor chips 200a that do not overlap the first semiconductor chip 100k in the vertical direction and the redistribution structure 500 . The supporter 190 may be spaced apart from the first semiconductor chip 100k on the redistribution structure 500 . The upper surface of the supporter 190 and the upper surface of the first semiconductor substrate 110k may be positioned at the same vertical level. The plurality of second semiconductor chips 200a may be sequentially stacked over the first semiconductor chip 100k and the supporter 190 .

The semiconductor package 8c has a molding layer 304 surrounding the supporter 190 , the first semiconductor chip 100k , the plurality of second semiconductor chips 200a , and the plurality of bonding wires 230a on the redistribution structure 500 . ) may be further included.

22 and 23 are cross-sectional views illustrating a system including a semiconductor package according to an exemplary embodiment.

Referring to FIG. 22 , the system 1000 includes a semiconductor package 1 including a first semiconductor chip 100 and a plurality of second semiconductor chips 200 and an interposer to which the third semiconductor chip 400 is attached. 600 , and a main board 700 on which the interposer 600 is mounted.

The third semiconductor chip 400 may include a third semiconductor substrate 410 , a third semiconductor device 412 , a plurality of third chip connection pads 430 , and a plurality of chip connection terminals 450 . . The third semiconductor substrate 410 , the third semiconductor element 412 , the third chip connection pad 430 , and the chip connection terminal 450 include the first semiconductor substrate 110 and the first semiconductor element ( 112 ), the front pad 142 , and the external connection terminal 150 are substantially similar to each other, and overlapping descriptions will be omitted.

The third semiconductor chip 400 may be, for example, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip.

The interposer 600 may include an interposer insulating layer 610 and an interposer conductive structure 620 . A plurality of interposer upper surface pads 632 and a plurality of interposer lower surface pads 644 electrically connected to each other through the interposer conductive structure 620 may be disposed on the upper and lower surfaces of the interposer 600 . In some embodiments, the interposer conductive structure 620 may electrically connect the semiconductor package 1 and the third semiconductor chip 400 .

In some embodiments, the interposer 600 may be a redistribution interposer formed in a manner similar to that of the redistribution structure 500 shown in FIG. 4 . Since the interposer insulating layer 610 and the interposer conductive structure 620 are substantially similar to the redistribution insulating layer 510 and the redistribution conductive structure 510 shown in FIG. 4 , overlapping descriptions will be omitted.

A plurality of external connection terminals 150 of the semiconductor package 1 and a plurality of chip connection terminals 450 of the third semiconductor chip 400 may be attached to the plurality of interposer top pads 632 . An underfill layer 480 may be interposed between the semiconductor package 1 and the interposer 600 and between the third semiconductor chip 400 and the interposer 600 . The underfill layer 480 may surround the plurality of external connection terminals 150 and the third connection bumps 460 .

A plurality of interposer connection terminals 650 may be attached to the plurality of interposer lower surface pads 644 . In some embodiments, the interposer connection terminal 650 may be a conductive bump or a solder ball. The interposer connection terminal 650 may electrically connect the interposer 600 and the main board 700 .

In some embodiments, an encapsulant 900 surrounding the semiconductor package 1 and the third semiconductor chip 400 may be formed on the interposer 600 . The sealing material 900 may be made of, for example, a thermosetting resin.

The main board 700 includes a base board layer 710 , a plurality of board upper surface pads 732 and a plurality of board lower surface pads 734 respectively disposed on upper and lower surfaces of the base board layer 710 , and a plurality of upper surfaces of the boards. A board conductive structure 720 electrically connecting the pad 732 and the plurality of board lower surface pads 734 to each other may be included. In some embodiments, the board conductive structure 720 may electrically connect the semiconductor package 2 and the third semiconductor chip 400 .

In some embodiments, the main board 700 may be a printed circuit board. For example, the main board 700 may be a multi-layer printed circuit board. The base board layer 710 may be made of at least one material selected from phenol resin, epoxy resin, and polyimide. Base board layer 710 is, for example, FR4 (Frame Retardant 4), tetrafunctional epoxy (Tetrafunctional epoxy), polyphenylene ether (Polyphenylene ether), epoxy / polyphenylene oxide (Epoxy / polyphenylene oxide), BT ( Bismaleimide triazine), Thermount, cyanate ester, polyimide, and may include at least one material selected from a liquid crystal polymer (Liquid crystal polymer).

A solder resist layer (not shown) exposing the board upper surface pad 732 and the board lower surface pad 734 may be formed on each of the upper and lower surfaces of the base board layer 710 . A plurality of interposer connection terminals 650 may be attached to the plurality of board upper surface pads 732 , and a plurality of system connection terminals 750 may be attached to the plurality of board lower surface pads 734 . The system connection terminal 750 may be, for example, a solder ball.

In some embodiments, the system 1000 does not include the main board 700 , and the interposer connection terminal 650 may perform a function of the system connection terminal.

Referring to FIG. 23 , a system 2000 includes a semiconductor package 2 including a redistribution structure 500 , a first semiconductor chip 100 , and a plurality of second semiconductor chips 200 , and a third semiconductor chip 400 . ) may include a main board 800 on which it is mounted.

The main board 800 includes a base board layer 810 , a plurality of board upper surface pads 832 and a plurality of board lower surface pads 834 respectively disposed on upper and lower surfaces of the base board layer 810 , and a plurality of upper surfaces of the boards. A board conductive structure 720 electrically connecting the pad 832 and the plurality of board lower surface pads 834 to each other may be included. The main board 800 is substantially similar to the main board 700 shown in FIG. 19 , and overlapping descriptions will be omitted.

A plurality of external connection terminals 450 of the semiconductor package 2 and a plurality of chip connection terminals 450 of the third semiconductor chip 400 may be attached to the plurality of top surface pads 832 . A plurality of system connection terminals 850 may be attached to the plurality of board lower surface pads 834 .

In the above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications and changes are made by those skilled in the art within the technical spirit and scope of the present invention. This is possible.

1, 1a, 2, 2a, 3, 3a, 4, 4a, 5, 5a, 6, 6a, 7, 7a, 8: semiconductor package, 100, 100a, 100b, 100c, 100d, 100e, 100f, 100g, 100h : first semiconductor chip, 120: through electrode, 200, 200a: second semiconductor chip, 230: bonding wire, 300: molding layer, 400: third semiconductor chip, 500: redistribution structure, 600: interposer, 700, 800 : main board

Claims (20)

a first semiconductor chip including a first semiconductor device, a first semiconductor substrate, a plurality of through electrodes passing through the first semiconductor substrate, and a plurality of first chip connection pads disposed on an upper surface of the first semiconductor chip;
A plurality of devices sequentially stacked on the top surface of the first semiconductor chip and each including a second semiconductor substrate, a second semiconductor device controlled by the first semiconductor chip, and a plurality of second chip connection pads disposed on the top surface a second semiconductor chip;
a plurality of bonding wires connecting the plurality of first chip connection pads and the plurality of second chip connection pads;
a molding layer surrounding the plurality of second semiconductor chips and the plurality of bonding wires; and
and a plurality of external connection terminals disposed on a lower surface of the first semiconductor chip. According to claim 1,
The plurality of second semiconductor chips are stacked on the non-active surface of the first semiconductor substrate,
The plurality of first chip connection pads and the first semiconductor device are electrically connected to each other through the plurality of through electrodes. According to claim 1,
The plurality of external connection terminals are stacked on the non-active surface of the first semiconductor substrate,
The plurality of external connection terminals and the first semiconductor device are electrically connected to each other through the plurality of through electrodes. According to claim 1,
The plurality of external connection terminals are attached to a plurality of external connection terminals disposed on a lower surface of the first semiconductor chip,
The molding layer covers an upper surface of the first semiconductor chip on the first semiconductor chip and surrounds the plurality of second semiconductor chips and the plurality of bonding wires, and the horizontal width of the molding layer is the width of the first semiconductor chip. A semiconductor package, characterized in that it has the same value as the horizontal width. According to claim 1,
The plurality of second semiconductor chips, at least a portion of the semiconductor package, characterized in that overhang (overhang) by protruding to the outside of the first semiconductor chip. According to claim 1,
and a redistribution structure disposed between the first semiconductor chip and the plurality of external connection terminals and comprising a redistribution insulating layer and a redistribution conductive structure;
The plurality of external connection terminals are attached to a lower surface of the redistribution structure,
The molding layer covers an upper surface of the redistribution structure on the redistribution structure and surrounds the first semiconductor chip, the plurality of second semiconductor chips, and the plurality of bonding wires, and a horizontal width of the molding layer is determined by the cultivation A semiconductor package, characterized in that it has the same value as the horizontal width of the line structure. 7. The method of claim 6,
and a supporter disposed on the redistribution structure to be spaced apart from the first semiconductor chip and having an upper surface positioned at the same vertical level as the upper surface of the first semiconductor substrate;
The plurality of second semiconductor chips are stacked over the first semiconductor chip and the supporter. According to claim 1,
The plurality of second semiconductor chips is a DRAM chip having a DRAM device, and the first semiconductor chip is a logic semiconductor chip having circuits for controlling the DRAM device included in the plurality of second semiconductor chips. 9. The method of claim 8,
The width of the data bus of each of the plurality of second semiconductor chips is 16 bits to 64 bits,
The semiconductor package, characterized in that the width of the data bus of the semiconductor package is 16 bits to 256 bits.
A semiconductor package, characterized in that 10. The method of claim 9,
and the first semiconductor device includes a Serializer/Deserialize (SerDes) circuit that reduces branching connected to data pads among the plurality of second chip connection pads. According to claim 1,
Each of the plurality of second semiconductor chips and the first semiconductor chip are electrically connected to each other through different bonding wires among the plurality of bonding wires,
The plurality of bonding wires directly connect the plurality of chip pads of each of the plurality of second semiconductor chips corresponding to each other and the plurality of rear pads of the first semiconductor chip. According to claim 1,
Each of the plurality of second semiconductor chips has a die adhesive film attached to its lower surface and is sequentially stacked on the first semiconductor chip so as to overlap each other in a vertical direction,
A portion of one end of the plurality of bonding wires connected to the plurality of second chip connection pads of a second semiconductor chip other than an uppermost second semiconductor among the plurality of second semiconductor chips is embedded in the die adhesive film semiconductor package with A first semiconductor substrate having a first semiconductor element, a wiring layer disposed on an active surface of the first semiconductor substrate and having a plurality of conductive wiring patterns and an inter-wiring insulating layer surrounding the plurality of conductive wiring patterns, the first semiconductor substrate a first semiconductor chip including; a plurality of through electrodes passing through and electrically connected to the first semiconductor device, a plurality of first chip connection pads disposed on an upper surface, and a plurality of external connection pads disposed on a lower surface thereof;
A die adhesive film is attached to a lower surface and stacked on the upper surface of the first semiconductor chip, a second semiconductor substrate, a second semiconductor device controlled by the first semiconductor chip, and a plurality of second chips disposed on the upper surface are connected a plurality of second semiconductor chips each including a pad;
a plurality of bonding wires extending to connect between the plurality of first chip connection pads and the plurality of second chip connection pads;
a molding layer covering an upper surface of the first semiconductor chip and surrounding the plurality of second semiconductor chips and the plurality of bonding wires; and
and a plurality of external connection terminals attached to the plurality of external connection pads. 14. The method of claim 13,
toward the plurality of second semiconductor chips of the inactive surface of the first semiconductor substrate;
One end of the plurality of through electrodes is connected to the plurality of first chip connection pads. 14. The method of claim 13,
toward the plurality of second semiconductor chips of the active surface of the first semiconductor substrate,
One end of the plurality of through electrodes is connected to the plurality of external connection pads. 14. The method of claim 13,
The sidewall of the first semiconductor chip and the sidewall of the molding layer are aligned in a vertical direction to form the same plane. 14. The method of claim 13,
Each of the plurality of second semiconductor chips is a DRAM chip including a DRAM device and having a data bus width of 16 bits to 64 bits;
The first semiconductor chip is a logic semiconductor chip having circuits for controlling a DRAM device of the plurality of second semiconductor chips,
The semiconductor package, characterized in that the width of the data bus of the semiconductor package is 64 bits to 256 bits. 14. The method of claim 13,
Some of the plurality of second semiconductor chips are sequentially stacked on an upper surface of the first semiconductor chip so that edges are aligned with each other in a vertical direction,
Another part of the plurality of second semiconductor chips is spaced apart from some of the plurality of second semiconductor chips, and is sequentially stacked on the top surface of the first semiconductor chip so that edges are aligned with each other in a vertical direction. semiconductor package. A redistribution insulating layer, a plurality of redistribution line patterns disposed on at least one surface of an upper surface and a lower surface of the redistribution insulating layer, and a portion of the plurality of redistribution line patterns passing through the redistribution insulating layer are respectively connected to and connected to a lower side a redistribution structure including a plurality of redistribution vias extending from the horizontal to the upper side;
a wiring layer disposed on the redistribution structure, a first semiconductor substrate, a wiring layer disposed on an active surface of the first semiconductor substrate and having a plurality of conductive wiring patterns and an inter-wiring insulating layer surrounding the plurality of conductive wiring patterns; a logic semiconductor chip comprising: a plurality of first chip connection pads disposed; a plurality of through electrodes connected to the plurality of first chip connection pads and penetrating the first semiconductor substrate;
a supporter disposed on the redistribution structure and spaced apart from the logic semiconductor chip, the supporter having an upper surface positioned at the same vertical level as the upper surface of the first semiconductor substrate;
A die adhesive film is attached to the lower surface so that the edges are aligned with each other in the vertical direction and sequentially stacked on the inactive surface of the first semiconductor substrate and on the supporter, controlled by the second semiconductor substrate and the logic semiconductor chip a plurality of DRAM chips each including a DRAM device and a plurality of second chip connection pads disposed on an upper surface thereof and each having a data bus width of 16 bits to 64 bits;
a plurality of plurality of chip connection pads having one end attached to the plurality of first chip connection pads and the other end attached to the plurality of second chip connection pads, and extending from the plurality of second chip connection pads to the plurality of first chip connection pads bonding wire;
a molding layer covering an upper surface of the redistribution structure and surrounding the plurality of DRAM chips and the plurality of bonding wires; and
and a plurality of external connection terminals attached to a lower surface of the redistribution structure. 20. The method of claim 19,
The sidewall of the redistribution structure and the sidewall of the molding layer are vertically aligned.

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