KR20220017310A - An electronic device including a display - Google Patents

Abstract

According to the present invention, an electronic device comprises: a housing; a display seen through at least a part of the housing and displaying a screen using a plurality of pixels; a display driving circuit providing a data voltage driving each of the plurality of pixels and at least one gate signal to the display; and a processor connected to the display driving circuit. The present invention provides the electronic device including the display, which can maintain a voltage charged in a storage capacitor of the driving circuit of the pixels and maintain brightness of a light emitting element even when a VGL is changed for reducing current consumption.

Description

An electronic device including a display

The content disclosed in this document relates to a technology for implementing an electronic device including a display.

The electronic device may display an image through a display disposed on the surface of the housing. A plurality of pixels for displaying an image may be disposed on the display. Each of the plurality of pixels may include a light emitting device. The light emitting device may be implemented as an organic light emitting diode (OLED).

Each of the plurality of pixels may receive a data voltage corresponding to the brightness and color of an image to be displayed in a current frame from a display driver IC (DDI). Each of the plurality of pixels may receive gate signals for setting a period for writing data voltages from the display driving circuit. Each of the plurality of pixels may include a driving circuit for driving the light emitting device. The driving circuit may adjust the brightness of the light emitting device by charging a data voltage in a storage capacitor formed between the gate electrode of the driving transistor and the driving voltage source.

The gate signal line for supplying gate signals to the driving circuit of each of the plurality of pixels and the gate electrode of the driving transistor may be arranged to overlap at least partially. A parasitic capacitor may be formed in a region where the gate signal line and the gate electrode of the driving transistor overlap. The parasitic capacitor may increase the voltage charged in the storage capacitor when the gate signal is switched from the turn-on state to the turn-off state. A phenomenon in which the voltage charged in the storage capacitor rises may be defined as a boost-up phenomenon. When the boost-up phenomenon occurs, the luminance of the light emitting device may decrease. When VGL, which is the on voltage of the driving transistor, is changed, the magnitude of the boost-up effect may be changed, and thus the luminance may be changed. It is not easy to control the change of luminance when VGL is changed, so VGL can be used by fixing the maximum luminance. If the VGL is fixed to the maximum luminance and used, the current consumed by the pixel may increase.

Various embodiments disclosed in this document are to provide an electronic device including a display that maintains the luminance of a light emitting device while maintaining a voltage charged in a storage capacitor of a driving circuit of a pixel even when VGL is varied to reduce current consumption do.

An electronic device according to an embodiment disclosed in this document includes a housing, a display that is seen through at least a part of the housing and displays a screen using a plurality of pixels, a data voltage that drives each of the plurality of pixels, and a display driving circuit providing at least one gate signal to the display, and a processor connected to the display driving circuit, wherein each of the plurality of pixels comprises: a first transistor driven based on the data voltage; a second transistor connected to a source electrode of a transistor and controlling a driving timing of the first transistor based on a first gate signal among the at least one gate signal; and a second transistor having a polarity opposite to that of the second transistor; A third transistor connected to the drain electrode of the transistor and configured to control the driving timing of the first transistor based on a first inverted gate signal having a polarity opposite to that of the first gate signal among the at least one gate signal, A first gate wiring supplying the first gate signal to the second transistor overlaps at least a portion of the gate electrode of the first transistor, and a first inversion gate wiring supplying the first inversion gate signal to the third transistor. overlaps at least partially with the gate electrode of the first transistor, and a capacitance formed by the first gate line and the gate electrode of the first transistor is equal to the first inverted gate line and the gate of the first transistor It may have a difference value within a specified threshold value and the magnitude of the capacitance formed by the electrode.

In addition, the electronic device according to another exemplary embodiment disclosed in this document includes a housing, a display that is seen through at least a part of the housing, and displays a screen using a plurality of pixels, and data that drives each of the plurality of pixels a first transistor comprising a display driving circuit providing a voltage and at least one gate signal to the display, and a processor connected to the display driving circuit, wherein each of the plurality of pixels is driven based on the data voltage; a second transistor connected to the source electrode of the first transistor and controlling a driving timing of the first transistor based on a first gate signal among the at least one gate signal, and having the same polarity as that of the second transistor, a first transistor connected to the drain electrode of the first transistor, comprising a third transistor controlling a driving timing of the first transistor based on the first gate signal, and supplying the first gate signal to the second transistor A gate line at least partially overlaps a gate electrode of the first transistor, and the display driving circuit generates a first inverted gate signal having a polarity opposite to that of the first gate signal, and the first inverted signal in the third transistor supplying the first inversion gate signal to a first inversion gate wiring supplying a gate signal, wherein the first inversion gate wiring at least partially overlaps with the gate electrode of the first transistor, the first gate wiring and the first inversion gate wiring The magnitude of the capacitance formed by the gate electrode of one transistor may have a difference value within a specified threshold value from the magnitude of the capacitance formed by the first inversion gate line and the gate electrode of the first transistor.

According to the embodiments disclosed in this document, the luminance of the light emitting device is increased by decreasing the voltage by a value substantially equal to the value at which the voltage charged in the storage capacitor by the parasitic capacitor rises to maintain the level of the voltage charged in the parasitic capacitor. can keep

In addition, according to the embodiments disclosed in this document, it is possible to prevent the boost-up phenomenon from occurring and thereby reduce the voltage of the gate signal, thereby reducing the current consumed by the pixel.

In addition, according to the embodiments disclosed in this document, when the magnitude of the gate signal is changed, the luminance of the light emitting device can be maintained, so that a flicker phenomenon in which the light emitting device flickers can be reduced.

In addition, according to the embodiments disclosed in this document, when the size of the gate signal changes, the luminance of the light emitting device can be maintained, so that the pixel circuit can be driven while the size of the gate signal is dynamically changed.

In addition, various effects directly or indirectly identified through this document may be provided.

1 is a circuit diagram illustrating a pixel of a display of an electronic device according to a comparative example.
2 is a waveform diagram illustrating signals supplied to a pixel and a gate voltage of a first transistor of the pixel according to a comparative example.
3 is a diagram illustrating a pixel according to a comparative example.
FIG. 4 is a cross-sectional view illustrating a plane cut along line I-II of FIG. 3 .
5 is a circuit diagram illustrating a pixel of a display of an electronic device according to an exemplary embodiment.
6 is a waveform diagram illustrating signals supplied to a pixel and a gate voltage of a first transistor of the pixel according to an exemplary embodiment.
7 is a diagram illustrating a pixel according to an exemplary embodiment.
8A is a cross-sectional view illustrating a plane taken along line III-IV of FIG. 7 according to an exemplary embodiment.
8B is a cross-sectional view illustrating a plane taken along line III-IV of FIG. 7 according to an exemplary embodiment.
8C is a cross-sectional view illustrating a plane taken along line III-IV of FIG. 7 according to an exemplary embodiment.
8D is a cross-sectional view illustrating a plane taken along line III-IV of FIG. 7 according to an exemplary embodiment.
9 is a circuit diagram illustrating a pixel of a display of an electronic device according to another exemplary embodiment.
10 is a diagram illustrating a pixel according to another exemplary embodiment.
11A is a cross-sectional view illustrating a plane taken along a line V-VI of FIG. 10 according to an exemplary embodiment.
11B is a cross-sectional view illustrating a surface cut along a line V-VI of FIG. 10 according to an exemplary embodiment.
11C is a cross-sectional view illustrating a surface cut along a line V-VI of FIG. 10 according to an exemplary embodiment.
11D is a cross-sectional view illustrating a plane taken along line V-VI of FIG. 10 according to an exemplary embodiment.
12 is a block diagram of an electronic device in a network environment according to various embodiments of the present disclosure;
13 is a block diagram of a display device according to various embodiments.
In connection with the description of the drawings, the same or similar reference numerals may be used for the same or similar components.

Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. However, this is not intended to limit the present invention to specific embodiments, and it should be understood that various modifications, equivalents, and/or alternatives of the embodiments of the present invention are included.

1 is a circuit diagram 100 illustrating a pixel PX of a display (eg, display 1320 of FIG. 13 ) of an electronic device (eg, electronic device 1201 of FIG. 12 ) according to a comparative example. The pixel PX includes a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , and a seventh transistor (T7), a storage capacitor (Cst), and an organic light emitting diode (OLED) may be included. In FIG. 1 , a case in which all transistors included in the pixel PX are PMOS transistors will be described as an example.

The gate electrode G1 of the first transistor T1 may be connected to the first electrode Cst1 of the storage capacitor Cst. The source electrode S1 of the first transistor T1 may receive the driving voltage ELVDD via the fifth transistor T5 . The drain electrode D1 of the first transistor T1 may be electrically connected to the anode of the organic light emitting diode OLED via the sixth transistor T6 . The first transistor T1 may receive the data voltage Vdata based on the switching operation of the second transistor T2 . The first transistor T1 may allow a driving current Id to flow based on the supplied data voltage Vdata. The first transistor T1 may be collectively referred to as a driving transistor for operating the organic light emitting diode OLED.

The gate electrode G2 of the second transistor T2 may receive the first gate signal GW. The source electrode S2 of the second transistor T2 may receive the data voltage DATA. The drain electrode D2 of the second transistor T2 may be connected to the source electrode S1 of the first transistor T1 . The second transistor T2 may transmit the data signal DATA to the source electrode S1 of the first transistor T1 based on the first gate signal GW. The second transistor T2 may be collectively referred to as a switching transistor for switching the operation of the first transistor T1 .

The gate electrode G3 of the third transistor T3 may receive the first gate signal GW. The source electrode S3 of the third transistor T3 may be connected to the drain electrode D1 of the first transistor T1 . The drain electrode D3 of the third transistor T3 may be connected to the gate electrode G1 of the first transistor T1 . The third transistor T3 may connect the gate electrode G1 and the drain electrode D1 of the first transistor T1 to each other based on the first gate signal GW. The third transistor T3 may diode-connect the first transistor T1.

The gate electrode G4 of the fourth transistor T4 may receive the second gate signal GI. The source electrode S4 of the fourth transistor T4 may receive the initialization voltage VINT. The drain electrode D4 of the fourth transistor T4 may be connected to the gate electrode G1 of the first transistor T1 . The fourth transistor T4 may transfer the initialization voltage VINT to the gate electrode G1 of the first transistor T1 based on the second gate signal GI. The fourth transistor T4 may be collectively referred to as an initialization transistor that initializes the voltage of the gate electrode G1 of the first transistor T1 .

The gate electrode G5 of the fifth transistor T5 may receive the emission control signal EM. The source electrode S5 of the fifth transistor T5 may receive the driving voltage ELVDD. The drain electrode D5 of the fifth transistor T5 may be connected to the source electrode S1 of the first transistor T1 . The fifth transistor T5 may transmit the driving voltage ELVDD to the source electrode S1 of the first transistor T1 based on the emission control signal EM.

The gate electrode G6 of the sixth transistor T6 may receive the emission control signal EM. The source electrode S6 of the sixth transistor T6 may be connected to the drain electrode D1 of the first transistor T1 . The drain electrode D6 of the sixth transistor T6 may be connected to the anode of the organic light emitting diode OLED. The sixth transistor T6 may connect the organic light emitting diode OLED to the first transistor T1 based on the light emission control signal EM to allow the light emitting current Ioled to flow through the organic light emitting diode OLED. .

The gate electrode G7 of the seventh transistor T7 may receive the bypass signal GB. The source electrode S7 of the seventh transistor T7 may be connected to the drain electrode D6 of the sixth transistor T6 . The drain electrode D7 of the seventh transistor T7 may receive the initialization voltage VINT. The seventh transistor T7 may allow the bypass current Ibp to flow based on the bypass signal GB.

The first electrode Cst1 of the storage capacitor Cst may be connected to the gate electrode G1 of the first transistor T1 . The second electrode Cst2 of the storage capacitor Cst may receive the driving voltage ELVDD. The storage capacitor Cst may be charged by the data voltage Vdata.

The anode of the organic light emitting diode OLED may be connected to the drain electrode D6 of the sixth transistor T6. A cathode of the organic light emitting diode OLED may be supplied with a common voltage ELVSS. The organic light emitting diode OLED may emit light based on the emission current Ioled.

A connection member (eg, the first connection member 1730 of FIG. 3 ) connected to the first gate line supplying the first gate signal GW and the gate electrode G1 or the gate electrode G1 of the first transistor T1 ) may be arranged to partially overlap each other. When the first gate line overlaps with the gate electrode G1 of the first transistor T1 or the connection member 1730 connected to the gate electrode G1 , the parasitic capacitor Cbst may be formed.

FIG. 2 illustrates signals GW, GI, GB, and EM supplied to a pixel (eg, the pixel PX of FIG. 1 ) according to a comparative example and a gate voltage VG1 of the first transistor T1 of the pixel PX. ) is a waveform diagram 200 showing the. The PMOS transistor may be turned off at a gate high voltage (VGH) and/or a high (HIGH) level. The gate may be turned on at a low voltage VGL and/or a low level. The gate high voltage VGH may be substantially the same as the high level. The gate low voltage VGL may be substantially the same as the low level.

In the first period P1 , the first gate signal GW may have a gate high voltage VGH. In the first period P1 , the second gate signal GI may have a gate low voltage VGL. In the first period P1 , the third gate signal GB may have a gate high voltage VGH. When the second gate signal GI is a gate signal of an nth (n is a natural number) pixel column, the third gate signal GB may be a gate signal of an (n+1)th pixel column. In the first period P1 , the emission control signal EM may have a gate high voltage VGH.

In the first period P1 , the second transistor T2 , the third transistor T3 , the fifth transistor T5 , the sixth transistor T6 , and the seventh transistor T7 may be turned off. In the first period P1 , the fourth transistor T4 may be turned on. In the first period P1 , the initialization voltage Vint is supplied to the gate electrode G1 of the first transistor T1 through the fourth transistor T4 . In the first period P1 , the initialization voltage Vint may be supplied to the anode of the organic light emitting diode OLED through the seventh transistor T4 . The first period P1 may be collectively referred to as an initialization period in which the gate electrode G1 of the first transistor T1 and the anode of the organic light emitting diode OLED are initialized to the initialization voltage Vint.

In the second period P2 , the first gate signal GW may have a gate low voltage VGL. In the second period P2 , the second gate signal GI may have a gate high voltage VGH. In the second period P2 , the third gate signal GB may have a gate low voltage VGL. In the second period P2 , the emission control signal EM may have a gate high voltage VGH.

In the second period P2 , the fourth transistor T4 , the fifth transistor T5 , and the sixth transistor T6 may be turned off. In the second period P2 , the second transistor T2 , the third transistor T3 , and the seventh transistor T7 may be turned on. In the second period P2 , the data voltage DATA may be supplied to the source electrode S1 of the first transistor T1 through the second transistor T2 . In the second section P2 , the gate electrode G1 and the drain electrode D1 of the first transistor T1 may be connected to each other through the third transistor T3 . In the second section P2 , the first transistor T1 may be diode-connected through the third transistor T3 .

In the second period P2 , a current may flow between the source electrode S1 and the drain electrode D1 of the first transistor T1 . Until the voltage difference between the source electrode S1 and the drain electrode D1 of the first transistor T1 becomes equal to the absolute value of the threshold voltage Vth of the first transistor T1 in the second period P2 Voltage levels of the gate electrode G1 and the drain electrode D1 of the first transistor T1 may change. In the second period P2, the gate voltage VG1 of the first transistor T1 may be changed to a difference value Vdata-|Vth| between the level of the data voltage Vdata and the absolute value of the threshold voltage Vth. have.

In order to compensate for the deviation due to the threshold voltage Vth, which is a value set by the physical characteristics of the first transistor T1, a data voltage is applied to the gate electrode G1 of the first transistor T1 in the second period P2. A compensation voltage Vdata-|Vth| may be supplied by subtracting the absolute value of the threshold voltage Vth of the first transistor T1 from (Vdata). In the second section P2 , the compensation voltage Vdata-|Vth| may be supplied to the first electrode Cst1 of the storage capacitor Cst. The second period P2 may be collectively referred to as a data writing period in which the compensation voltage Vdata-|Vth| is supplied to the gate electrode G1 of the first transistor T1 to write the data voltage Vdata. have.

In the third period P3 , the first gate signal GW may have a gate high voltage VGH. In the third period P3 , the second gate signal GI may have a gate high voltage VGH. In the third period P3 , the third gate signal signal GB may have a gate high voltage VGH. In the third period P3 , the emission control signal EM may have the gate low voltage VGL in at least a partial period.

In the third period P3 , the second transistor T2 , the third transistor T3 , and the seventh transistor T4 may be turned off. In the third period P3 , the fifth transistor T5 and the sixth transistor T6 may be turned on in at least a partial period. A ratio of a period in which the fifth transistor T5 and the sixth transistor T6 are turned on in the third period P3 may be defined as a duty ratio. A driving voltage ELVDD is applied to the source electrode S1 of the first transistor T1 through the fifth transistor T5 in a period in which the fifth transistor T5 is turned on during the third period P3 according to the duty ratio. This can be supplied. In a period in which the fifth transistor T5 is turned on during the third period P3 according to the duty ratio, the driving voltage ELVDD and the gate voltage VG1 that are the voltages of the source electrode S1 of the first transistor T1 A driving current Id may flow based on a difference between the phosphorus compensation voltages Vdata-|Vth|. The driving current Id may be supplied to the organic light emitting diode OLED through the sixth transistor T6 in a period in which the sixth transistor T6 is turned on during the third period P3 according to the duty ratio. The third section P3 may be collectively referred to as a light emitting section in which the organic light emitting diode (OLED) operates.

When the second period P2 ends, the data voltage Vdata may rise above the data voltage level Vdata. When the first gate signal GW is switched from the gate low voltage VGL to the gate high voltage VGH, the voltage charged in the storage capacitor Cst by the parasitic capacitor Cbst may be affected. A boost-up phenomenon in which the voltage charged in the storage capacitor Cst is increased by the parasitic capacitor Cbst may occur. As a boost-up phenomenon occurs, the voltage charged in the storage capacitor Cst may rise to the boost-up data voltage Vdatab. When the storage capacitor Cst increases to the boost-up data voltage Vdatab, the luminance of the organic light emitting diode OLED may decrease.

3 is a diagram 300 illustrating a pixel (eg, the pixel PX of FIG. 1 ) according to a comparative example.

The semiconductor patterns 1200 may be integrally connected. The semiconductor pattern 1200 may be bent in various shapes. The semiconductor pattern 1200 may include channel regions 1241 , 1242 , 1243 , 1244 , 1245 , 1246 , and 1247 forming a channel of the transistor and conductive regions forming a source electrode and a drain electrode of the transistor. The channel regions 1241 , 1242 , 1243 , 1244 , 1245 , 1246 , and 1247 may be doped with an n-type impurity or a p-type impurity.

The channel regions 1241 , 1242 , 1243 , 1244 , 1245 , 1246 , and 1247 include a first channel region 1241 , a second channel region 1242 , a third channel region 1243 , a fourth channel region 1244 , It may include a fifth channel region 1245 , a sixth channel region 1246 , and a seventh channel region 1247 . The first channel region 1241 may form a channel region of a first transistor (eg, the first transistor T1 of FIG. 1 ). The second channel region 1242 may form a channel region of a second transistor (eg, the second transistor T2 of FIG. 1 ). The third channel region 1243 may form a channel region of a third transistor (eg, the third transistor T3 of FIG. 1 ). The fourth channel region 1244 may form a channel region of a fourth transistor (eg, the fourth transistor T4 of FIG. 1 ). The fifth channel region 1245 may form a channel region of a fifth transistor (eg, the fifth transistor T5 of FIG. 1 ). The sixth channel region 1246 may form a channel region of a sixth transistor (eg, the sixth transistor T6 of FIG. 1 ). The seventh channel region 1247 may form a channel region of a seventh transistor (eg, the seventh transistor T7 of FIG. 1 ).

The first gate line 1510 may receive the first gate signal GW. The second gate line 1520 may be disposed parallel to the first gate line 1510 . The second gate line 1520 may receive the second gate signal GI. The light emission control wiring 1530 may be disposed parallel to the first gate wiring 1510 . The emission control wiring 1530 may receive the emission control signal EM.

The gate electrode 1540 of the first transistor T1 may overlap the first channel region 1241 . The driving voltage electrode 1310 may partially overlap the gate electrode 1540 of the first transistor T1 . The gate electrode 1540 of the first transistor T1 may receive a voltage charged in the storage capacitor Cst by the data voltage DATA. The driving voltage electrode 1310 may receive the driving voltage ELVDD. The second gate pattern 1350 may constitute a gate electrode of the fifth transistor T5 .

The data line 1710 may be disposed to cross the first gate line 1510 , the second gate line 1520 , and the emission control line 1530 . The data line 1710 may supply the data voltage DATA to the second transistor T2 through the via hole 1650 .

The driving voltage line 1720 may be disposed to be parallel to the data line 1710 . The driving voltage line 1720 may supply the driving voltage ELVDD to the fifth transistor T5 through the via holes 1640 and 1670 .

The first connection member 1730 may connect the gate electrode 1540 of the first transistor T1 to the third transistor T3 through the via hole 1630 . The second connection member 1740 may be connected to the seventh transistor T7 through the via hole 1620 . The third connection member 1750 may be connected to the sixth transistor T6 through the via hole 1610 .

The first gate line 1510 and the first connection member 1730 may partially overlap. A parasitic capacitor Cbst may be formed in a region where the first gate line 1510 and the first connection member 1730 overlap.

FIG. 4 is a cross-sectional view 400 illustrating a plane taken along line I-II of FIG. 3 .

A buffer layer 1110 may be disposed on the substrate 1100 . A semiconductor pattern 1200 may be disposed on the buffer layer 1110 . A first gate insulating layer 1410 may be disposed on the semiconductor pattern 1200 . A gate electrode 1540 of the first transistor T1 may be disposed on the first gate insulating layer 1410 . A second gate insulating layer 1420 may be disposed on the gate electrode 1540 of the first transistor T1 . A driving voltage electrode 1310 may be disposed on the second gate insulating layer 1420 . An interlayer insulating layer 1600 may be disposed on the driving voltage electrode 1310 . A data line 1710 , a driving voltage line 1720 , and a first connection member 1730 may be disposed on the interlayer insulating layer 1600 .

The gate electrode 1540 of the first transistor T1 , the source electrode 1231 of the first transistor T1 , the first channel region 1241 , and the drain electrode 1251 of the first transistor T1 are connected to the first The transistor T1 may be configured. A storage capacitor Cst may be formed between the driving voltage electrode 1310 and the gate electrode 1540 of the first transistor T1 .

The driving voltage electrode 1310 may be connected to the driving voltage line 1720 through the via hole 1640 . The first connection member 1730 may connect the gate electrode 1540 of the first transistor T1 to the semiconductor pattern 1200 through the via hole 1630 . A parasitic capacitor Cbst may be formed in a region where the first gate line 1510 and the first connection member 1730 overlap.

5 is a circuit diagram 500 illustrating a pixel PX of a display (eg, the display 1320 of FIG. 13 ) of an electronic device (eg, the electronic device 1201 of FIG. 12 ) according to an exemplary embodiment. The pixel PX includes a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , and a seventh transistor (T7), a storage capacitor (Cst), and an organic light emitting diode (OLED) may be included. In FIG. 5 , the first transistor T1 , the second transistor T2 , the fifth transistor T5 , the sixth transistor T6 , and the seventh transistor T7 are PMOS transistors, and the third transistor T3 and A case in which the fourth transistor T4 is an NMOS transistor will be described as an example. The third transistor T3 may have a polarity opposite to that of the first transistor T1 .

In an embodiment, the gate electrode G1 of the first transistor T1 may be connected to the first electrode Cst1 of the storage capacitor Cst. The source electrode S1 of the first transistor T1 may receive the driving voltage ELVDD via the fifth transistor T5 . The drain electrode D1 of the first transistor T1 may be electrically connected to the anode of the organic light emitting diode OLED via the sixth transistor T6 . The first transistor T1 may receive the data voltage Vdata based on the switching operation of the second transistor T2 . The first transistor T1 may allow a driving current Id to flow based on the supplied data voltage Vdata. The first transistor T1 may be collectively referred to as a driving transistor for operating the organic light emitting diode OLED.

In an embodiment, the gate electrode G2 of the second transistor T2 may receive the first gate signal GW. The source electrode S2 of the second transistor T2 may receive the data voltage Vdata. The drain electrode D2 of the second transistor T2 may be connected to the source electrode S1 of the first transistor T1 . The second transistor T2 may transmit the data signal DATA to the source electrode S1 of the first transistor T1 based on the first gate signal GW. The second transistor T2 may be collectively referred to as a switching transistor for switching the operation of the first transistor T1 .

In an embodiment, the gate electrode G3 of the third transistor T3 may receive the first inverted gate signal GW_o. The first inverted gate signal GW_o may have a polarity opposite to that of the first gate signal GW. When the first gate signal GW is the gate low voltage VGL, the first inverted gate signal GW_o may be the gate high voltage VGH. When the first gate signal GW is the gate high voltage VGH, the first inverted gate signal GW_o may be the gate low voltage VGL. The source electrode S3 of the third transistor T3 may be connected to the drain electrode D1 of the first transistor T1 . The drain electrode D3 of the third transistor T3 may be connected to the gate electrode G1 of the first transistor T1 . The third transistor T3 may connect the gate electrode G1 and the drain electrode D1 of the first transistor T1 to each other based on the first inverted gate signal GW_o. The third transistor T3 may diode-connect the first transistor T1.

In an embodiment, the gate electrode G4 of the fourth transistor T4 may receive the second inverted gate signal GI_o. The source electrode S4 of the fourth transistor T4 may receive the initialization voltage VINT. The drain electrode D4 of the fourth transistor T4 may be connected to the gate electrode G1 of the first transistor T1 . The fourth transistor T4 may transfer the initialization voltage VINT to the gate electrode G1 of the first transistor T1 based on the second inverted gate signal GI_o. The fourth transistor T4 may be collectively referred to as an initialization transistor that initializes the voltage of the gate electrode G1 of the first transistor T1 .

In an embodiment, the gate electrode G5 of the fifth transistor T5 may receive the emission control signal EM. The source electrode S5 of the fifth transistor T5 may receive the driving voltage ELVDD. The drain electrode D5 of the fifth transistor T5 may be connected to the source electrode S1 of the first transistor T1 . The fifth transistor T5 may transmit the driving voltage ELVDD to the source electrode S1 of the first transistor T1 based on the emission control signal EM.

In an embodiment, the gate electrode G6 of the sixth transistor T6 may receive the emission control signal EM. The source electrode S6 of the sixth transistor T6 may be connected to the drain electrode D1 of the first transistor T1 . The drain electrode D6 of the sixth transistor T6 may be connected to the anode of the organic light emitting diode OLED. The sixth transistor T6 may connect the organic light emitting diode OLED to the first transistor T1 based on the light emission control signal EM to allow the light emitting current Ioled to flow through the organic light emitting diode OLED. .

In an embodiment, the gate electrode G7 of the seventh transistor T7 may receive the bypass signal GB. The source electrode S7 of the seventh transistor T7 may be connected to the drain electrode D6 of the sixth transistor T6 . The drain electrode D7 of the seventh transistor T7 may receive the corrected initialization voltage AVINT. The corrected initialization voltage AVINT may be a voltage having a level separate from the initialization voltage VINT. The seventh transistor T7 may allow the bypass current Ibp to flow based on the bypass signal GB.

In an embodiment, the first electrode Cst1 of the storage capacitor Cst may be connected to the gate electrode G1 of the first transistor T1. The second electrode Cst2 of the storage capacitor Cst may receive the driving voltage ELVDD. The storage capacitor Cst may be charged by the data voltage Vdata.

In an embodiment, the anode of the organic light emitting diode OLED may be connected to the drain electrode D6 of the sixth transistor T6. A cathode of the organic light emitting diode OLED may be supplied with a common voltage ELVSS. The organic light emitting diode OLED may emit light based on the emission current Ioled.

In an embodiment, the first gate line supplying the first gate signal GW to the second transistor T2 and the connecting member connected to the gate electrode G1 or the gate electrode G1 of the first transistor T1 ( Example: The first connecting members 1730 of FIG. 7 may overlap by a first area and may be spaced apart by a first distance. A dielectric material having a specified dielectric constant is disposed between the first gate wire and the gate electrode G1 of the first transistor T1 or a connection member connected to the gate electrode G1 (eg, the first connection member 1730 of FIG. 7 ). can be filled The first gate wiring and the gate electrode G1 of the first transistor T1 or a connection member connected to the gate electrode G1 (eg, the first connection member 1730 of FIG. 7 ) overlap by a first area, The parasitic capacitor Cbst may be formed spaced apart by one distance.

In an embodiment, the first inversion gate wiring supplying the first inversion gate signal GW_o to the third transistor T3 and the connection connected to the gate electrode G1 or the gate electrode G1 of the first transistor T1 The members (eg, the first connecting member 1730 of FIG. 7 ) may overlap by a second area and may be spaced apart by a second distance. A dielectric material having a specified dielectric constant between the first inversion gate wiring and the gate electrode G1 of the first transistor T1 or a connection member connected to the gate electrode G1 (eg, the first connection member 1730 of FIG. 7 ) This can be filled. The first inverted gate wiring and the connecting member connected to the gate electrode G1 or the gate electrode G1 of the first transistor T1 (eg, the first connecting member 1730 of FIG. 7 ) overlap by a second area, The compensation capacitor Cbstc may be formed to be spaced apart by a second distance.

In an exemplary embodiment, the second area may have a first difference value within the first area and a specified first threshold value. A smaller first threshold value may be preferable. For example, the second area may have substantially the same size as the first area.

In an embodiment, the second distance may have a second difference value within the first distance and a second predetermined threshold value. A smaller second threshold value may be preferable. For example, the second distance may have a length substantially equal to the first distance.

In an embodiment, when the third transistor T3 and the fourth transistor T4 are NMOS, a polarity opposite to that of the first gate signal GW in the display driving circuit (eg, the display driver IC 1330 of FIG. 13 ) is reversed. A first inverted gate signal GW_o having a GW_o may be additionally generated. The first inverted gate wiring supplying the first inverted gate signal Gw_o to the third transistor T3 is connected to the gate electrode G1 or the gate electrode G1 of the first transistor T1 by a connection member (eg, in FIG. It may be disposed to overlap with the first connecting member 1730 of FIG. 7 . When the first inversion gate wiring and a connection member connected to the gate electrode G1 or the gate electrode G1 of the first transistor T1 (eg, the first connection member 1730 of FIG. 7 ) overlap each other, the compensation capacitor Cbstc ) can be formed.

In an embodiment, the first inversion gate wiring and a connection member connected to the gate electrode G1 or the gate electrode G1 of the first transistor T1 (eg, the first connection member 1730 of FIG. 7 ) overlap each other. A third difference within a specified third threshold value with the compensation capacitor Cbstc and the parasitic capacitor Cbst by adjusting the area and/or the distance between the first inversion gate wiring and the gate electrode G1 of the first transistor T1 can have a value. A smaller third threshold value may be preferable. For example, the compensation capacitor Cbstc may have substantially the same size and/or capacity although the polarity is opposite to that of the parasitic capacitor Cbst.

In an embodiment, the first and second areas A1 and A2 and the first and second distances l1 and l2 as shown in Equation 1 below so that the parasitic capacitor Cbst and the compensation capacitor Cbstc may be substantially the same ) can be determined.

In Equation 1, the first dielectric constant ε1 may be the dielectric constant of an internal material filled in the space between the two electrodes of the parasitic capacitor Cbst. In Equation 1, the second dielectric constant ε2 may be the dielectric constant of an internal material filled in the space between the two electrodes of the compensation capacitor Cbstc. In Equation 1, the first area A1 may be an overlapping area of two electrodes of the parasitic capacitor Cbst. In Equation 1, the second area A2 may be an overlapping area of the two electrodes of the compensation capacitor Cbstc. The first and second areas A1 and A2 may be effective electrode areas affecting capacitance. In Equation 1, the first distance l1 may be a distance between two overlapping electrodes of the parasitic capacitor Cbst. In Equation 1, the second distance l2 may be a distance between two overlapping electrodes of the compensation capacitor Cbstc. The first and second distances l1 and l2 may be effective electrode distances that affect capacitance.

In an embodiment, since the first inverted gate line transfers the first inverted gate signal GW_o having a polarity opposite to that of the first gate signal GW, the polarity of the voltage stored in the compensation capacitor Cbstc is the parasitic capacitor Cbst. It can have a polarity opposite to the voltage stored in The compensation capacitor Cbstc may cancel an effect of the parasitic capacitor Cbst on the pixel PX. For example, the compensation capacitor Cbstc may maintain the voltage level of the storage capacitor Cst by offsetting a change in the level of the voltage stored in the storage capacitor Cst due to the parasitic capacitor Cbst.

6 illustrates signals GW, GW_o, GI_o, GB, EM supplied to a pixel (eg, the pixel PX of FIG. 5 ) and a gate voltage VG1 of a first transistor of the pixel PX according to an exemplary embodiment. ) is a waveform diagram 600 showing the. A PMOS transistor is turned off at a gate high voltage (VGH) and/or a high (HIGH) level and is turned on at a gate low voltage (VGL) and/or a low (LOW) level. can be The NMOS transistor may be turned on at a gate high voltage VGH and/or a high level and may be turned off at a gate low voltage VGL and/or a low level. The gate high voltage VGH may be substantially the same as the high level. The gate low voltage VGL may be substantially the same as the low level.

In an embodiment, in the first period P1 , the first gate signal GW may have a gate high voltage VGH. In the first period P1 , the first inverted gate signal GW_o may have a gate low voltage VGL. In the first period P1 , the second inverted gate signal GI_o may have a gate high voltage VGL. In the first period P1 , the third gate signal GB may have a gate high voltage VGH. When the second gate signal GI is a gate signal of an nth (n is a natural number) pixel column, the third gate signal GB may be a gate signal of an (n+1)th pixel column. In the first period P1 , the emission control signal EM may have a gate high voltage VGH.

In an embodiment, in the first period P1 , the second transistor T2 , the third transistor T3 , the fifth transistor T5 , the sixth transistor T6 , and the seventh transistor T7 turn- can be off In the first period P1 , the fourth transistor T4 may be turned on. In the first period P1 , the initialization voltage Vint may be supplied to the gate electrode G1 of the first transistor T1 through the fourth transistor T4 . The first period P1 may be collectively referred to as an initialization period in which the gate electrode G1 of the first transistor T1 is initialized to the initialization voltage Vint.

In an embodiment, in the second period P2 , the first gate signal GW may have a gate low voltage VGL. In the second period P2 , the first inverted gate signal GW_o may have a gate high voltage VGH. In the second period P2 , the second inverted gate signal GI_o may have a gate low voltage VGL. In the second period P2 , the third gate signal GB may have a gate low voltage VGL. In the second period P2 , the emission control signal EM may have a gate high voltage VGH.

In an embodiment, in the second period P2 , the fourth transistor T2 , the fifth transistor T3 , and the sixth transistor T6 may be turned off. In the second period P2 , the second transistor T2 , the third transistor T3 , and the seventh transistor T7 may be turned on. In the second period P2 , the data voltage Vdata may be supplied to the source electrode S1 of the first transistor T1 through the second transistor T2 . In the second section P2 , the gate electrode G1 and the drain electrode D1 of the first transistor T1 may be connected to each other through the third transistor T3 . In the second section P2 , the first transistor T1 may be diode-connected through the third transistor T3 . In the second period P2 , the corrected initialization voltage AVINT may be supplied to the anode of the organic light emitting diode OLED through the seventh transistor T7 .

In an embodiment, a current may flow between the source electrode S1 and the drain electrode D1 of the first transistor T1 in the second period P2 . Until the voltage difference between the source electrode S1 and the drain electrode D1 of the first transistor T1 becomes equal to the absolute value of the threshold voltage Vth of the first transistor T1 in the second period P2 Voltage levels of the gate electrode G1 and the drain electrode D1 of the first transistor T1 may change. In the second period P2, the gate voltage VG1 of the first transistor T1 may be changed to a difference value DATA-|Vth| between the level of the data voltage Vdata and the absolute value of the threshold voltage Vth. have.

In one embodiment, in order to compensate for a deviation due to the threshold voltage Vth, which is a value set by the physical characteristics of the first transistor T1 , the gate electrode ( A compensation voltage Vdata-|Vth| may be supplied to G1 ) by subtracting the absolute value of the threshold voltage Vth of the first transistor T1 from the data voltage Vdata. In the second section P2 , the compensation voltage Vdata-|Vth| may be supplied to the first electrode Cst1 of the storage capacitor Cst. The second period P2 may be collectively referred to as a data writing period in which the compensation voltage Vdata-|Vth| is supplied to the gate electrode G1 of the first transistor T1 to write the data voltage Vdata. have.

In an embodiment, in the third period P3 , the first gate signal GW may have a gate high voltage VGH. In the third period P3 , the first inverted gate signal GW_o may have a gate low voltage VGL. In the third period P3 , the second inverted gate signal GI_o may have a gate low voltage VGH. In the third period P3 , the bypass signal GB may have a gate high voltage VGH. In the third period P3 , the emission control signal EM may have a gate high voltage VGH in at least a partial period.

In an embodiment, in the third period P3 , the second transistor T2 , the third transistor T3 , and the seventh transistor T7 may be turned off. In the third period P3 , the fifth transistor T5 and the sixth transistor T6 may be turned on in at least a partial period. A ratio of a period in which the fifth transistor T5 and the sixth transistor T6 are turned on in the third period P3 may be defined as a duty ratio. A driving voltage ELVDD is applied to the source electrode S1 of the first transistor T1 through the fifth transistor T5 in a period in which the fifth transistor T5 is turned on during the third period P3 according to the duty ratio. This can be supplied. In a period in which the fifth transistor T5 is turned on during the third period P3 according to the duty ratio, the driving voltage ELVDD and the gate voltage VG1 that are the voltages of the source electrode S1 of the first transistor T1 A driving current Id may flow based on a difference between the phosphorus compensation voltages Vdata-|Vth|. The driving current Id may be supplied to the organic light emitting diode OLED through the sixth transistor T6 in a period in which the sixth transistor T6 is turned on during the third period P3 according to the duty ratio. The third section P3 may be collectively referred to as a light emitting section in which the organic light emitting diode (OLED) operates.

In an embodiment, the compensation capacitor Cbstc may maintain the gate voltage VG1 of the first transistor. The compensation capacitor Cbstc may cancel a change in the gate voltage VG1 of the first transistor due to the parasitic capacitor Cbst. Compensation capacitor Cbstc boosts up in which data voltage DATA charged in storage capacitor Cst rises above the level of data voltage Vdata when second period P2 is terminated by parasitic capacitor Cbst. phenomenon can be counteracted. When the level of the data voltage Vdata increases to the boost-up data voltage Vdatab by the parasitic capacitor Cbst, the compensation capacitor Cbstc changes the level of the data voltage Vdata to the boost-down data voltage Vdatac. may try to reduce Boost-up in which the voltage charged in the storage capacitor Cst by the parasitic capacitor Cbst rises when the magnitude of the voltage decreased by the compensation capacitor Cbstc is the same as the magnitude of the voltage to be increased by the parasitic capacitor Cbst The phenomenon can be counteracted. When the boost-up phenomenon is canceled and the voltage charged in the storage capacitor Cst is maintained at the level of the data voltage Vdata, the luminance of the organic light emitting diode OLED may be maintained.

7 is a diagram 700 illustrating a pixel (eg, the pixel PX of FIG. 5 ) according to an exemplary embodiment.

In an embodiment, the semiconductor patterns 1200 may be integrally connected. The semiconductor pattern 1200 may be curved in various shapes. The semiconductor pattern 1200 may include channel regions 1241 , 1242 , 1243 , 1245 , 1246 , and 1247 forming a channel of the transistor and conductive regions forming a source electrode and a drain electrode of the transistor. The channel regions 1241 , 1242 , 1243 , 1245 , 1246 , and 1247 may be doped with an n-type impurity or a p-type impurity.

In an embodiment, the channel regions 1241 , 1242 , 1243 , 1245 , 1246 , and 1247 include a first channel region 1241 , a second channel region 1242 , a third channel region 1243 , and a fifth channel region ( 1245 , a sixth channel region 1246 , and a seventh channel region 1247 may be included. The first channel region 1241 may form a channel region of a first transistor (eg, the first transistor T1 of FIG. 5 ). The second channel region 1242 may form a channel region of a second transistor (eg, the second transistor T2 of FIG. 5 ). The third channel region 1243 may form a channel region of a third transistor (eg, the third transistor T3 of FIG. 5 ). The fifth channel region 1245 may form a channel region of a fifth transistor (eg, the fifth transistor T5 of FIG. 5 ). The sixth channel region 1246 may form a channel region of a sixth transistor (eg, the sixth transistor T6 of FIG. 5 ). The seventh channel region 1247 may form a channel region of a seventh transistor (eg, the seventh transistor T7 of FIG. 5 ).

In an embodiment, oxide pattern regions 1244 and 1248 may be formed. The oxide pattern regions 1244 and 1248 may include a channel region 1244 forming a channel of a transistor and a conductive region forming an electrode of a capacitor. For example, the oxide pattern regions 1244 and 1248 are the fourth channel region 1244 forming the channel region of the fourth transistor (eg, the fourth transistor T4 of FIG. 5 ) and the electrode of the compensation capacitor Cbstc. may include a conductive region 1248 forming a

In an embodiment, the first gate line 1510 may receive the first gate signal GW. The first inverted gate line 1550 may be disposed parallel to the first gate line 1510 . The first inverted gate line 1550 may receive the first inverted gate signal GW_o.

In an embodiment, the second inversion gate line 1525 may be disposed parallel to the first gate line 1510 . The second inverted gate line 1525 may receive the second inverted gate signal GI_o. The light emission control wiring 1530 may be disposed parallel to the first gate wiring 1510 . The emission control wiring 1530 may receive the emission control signal EM.

In an embodiment, the gate electrode 1540 of the first transistor T1 may overlap the first channel region 1241 . The driving voltage electrode 1310 may partially overlap the gate electrode 1540 of the first transistor T1 . The gate electrode 1540 of the first transistor T1 may receive a voltage charged in the storage capacitor Cst by the data voltage DATA. The driving voltage electrode 1310 may receive the driving voltage ELVDD. The second gate pattern 1350 may constitute a gate electrode of the fifth transistor T5 .

In an embodiment, the data line 1710 may be disposed to cross the first gate line 1510 , the first inverted gate line 1550 , the second inverted gate line 1525 , and the emission control line 1530 . have. The data line 1710 may supply the data voltage DATA to the second transistor T2 through the via hole 1650 .

In an embodiment, the driving voltage line 1720 may be disposed parallel to the data line 1710 . The driving voltage line 1720 may supply the driving voltage ELVDD to the fifth transistor T5 through the via holes 1640 and 1670 .

In an embodiment, the first connection member 1730 may connect the gate electrode 1540 of the first transistor T1 to the third transistor T3 through the via hole 1630 . The second connection member 1740 may be connected to the seventh transistor T7 through the via hole 1620 . The third connection member 1750 may be connected to the sixth transistor T6 through the via hole 1610 .

In an embodiment, the first gate line 1510 and the first connection member 1730 may partially overlap. A parasitic capacitor Cbst may be formed in a region where the first gate line 1510 and the first connection member 1730 overlap.

In an embodiment, the first inversion gate line 1550 and the first connection member 1730 may partially overlap. A compensation capacitor Cbstc may be formed in a region where the first inversion gate line 1550 and the first connection member 1730 overlap.

8A is a cross-sectional view 810 illustrating a plane taken along line III-IV of FIG. 7 according to an exemplary embodiment.

In an embodiment, a buffer layer 1110 may be disposed on the substrate 1100 . A source electrode 1231 of the first transistor T1 , a first channel region 1241 , and a drain electrode 1251 of the first transistor T1 may be disposed on the buffer layer 1110 . A first gate insulating layer 1410 may be disposed on the source electrode 1231 of the first transistor T1 , the first channel region 1241 , and the drain electrode 1251 of the first transistor T1 . A gate electrode 1540 of the first transistor T1 may be disposed on the first gate insulating layer 1410 . A second gate insulating layer 1420 may be disposed on the gate electrode 1540 of the first transistor T1 . A driving voltage electrode 1310 may be disposed on the second gate insulating layer 1420 . A third gate insulating layer 1430 may be disposed on the driving voltage electrode 1310 . An interlayer insulating layer 1600 may be disposed on the third gate insulating layer 1430 . A data line 1710 , a driving voltage line 1720 , and a first connection member 1730 may be disposed on the interlayer insulating layer 1600 .

In an embodiment, the gate electrode 1540 of the first transistor T1, the source electrode 1231 of the first transistor T1, the first channel region 1241, and the drain electrode ( 1251 may constitute the first transistor T1. A storage capacitor Cst may be formed between the driving voltage electrode 1310 and the gate electrode 1540 of the first transistor T1 .

In an embodiment, the driving voltage electrode 1310 may be connected to the driving voltage line 1720 through the via hole 1640 . The first connection member 1730 may be connected to the driving voltage electrode 1310 through the via hole 1630 . At least a portion of the first connection member 1730 may have an oxide pattern. A portion of the oxide pattern may form a portion of the third transistor T3 .

In an embodiment, a parasitic capacitor Cbst may be formed in a region where the first gate line 1510 and the first connection member 1730 overlap. A compensation capacitor Cbstc may be formed in a region where the first inversion gate line 1550 and the first connection member 1730 overlap.

In an embodiment, the first gate wiring 1510 may be disposed between the first gate insulating layer 1410 and the second gate insulating layer 1420 . The first gate wiring 1510 may be disposed on the same layer as the gate electrode 1540 of the first transistor T1 . The first inversion gate wiring 1550 may be disposed between the first gate insulating layer 1410 and the second gate insulating layer 1420 . The first inversion gate wiring 1550 may be disposed on the same layer as the gate electrode 1540 of the first transistor T1 . The first inverted gate line 1550 may be disposed on the same layer as the first gate line 1510 .

FIG. 8B is a cross-sectional view 820 illustrating a plane taken along line III-IV of FIG. 7 according to an exemplary embodiment.

In an embodiment, the first gate wiring 1510 may be disposed between the second gate insulating layer 1420 and the interlayer insulating layer 1600 . The first gate wiring 1510 may be disposed on the same layer as the gate electrode 1540 of the first transistor T1 . The first inversion gate wiring 1550 may be disposed between the first gate insulating layer 1410 and the second gate insulating layer 1420 . The first inversion gate wiring 1550 may be disposed on the same layer as the driving voltage electrode 1310 .

8C is a cross-sectional view 830 illustrating a plane taken along line III-IV of FIG. 7 according to an exemplary embodiment.

In an embodiment, the first gate wiring 1510 may be disposed between the second gate insulating layer 1420 and the interlayer insulating layer 1600 . The first gate wiring 1510 may be disposed on the same layer as the driving voltage electrode 1310 . The first inversion gate wiring 1550 may be disposed between the second gate insulating layer 1420 and the interlayer insulating layer 1600 . The first inversion gate wiring 1550 may be disposed on the same layer as the driving voltage electrode 1310 . The first inverted gate line 1550 may be disposed on the same layer as the first gate line 1510 .

FIG. 8D is a cross-sectional view 840 illustrating a plane taken along line III-IV of FIG. 7 according to an exemplary embodiment.

In an embodiment, the first gate wiring 1510 may be disposed between the first gate insulating layer 1410 and the second gate insulating layer 1420 . The first gate wiring 1510 may be disposed on the same layer as the gate electrode 1540 of the first transistor T1 . The first inversion gate wiring 1550 may be disposed between the second gate insulating layer 1420 and the interlayer insulating layer 1600 . The first inversion gate wiring 1550 may be disposed on the same layer as the driving voltage electrode 1310 .

9 is a circuit diagram 900 illustrating a pixel PX of a display (eg, the display 1320 of FIG. 13 ) of an electronic device (eg, the electronic device 1201 of FIG. 12 ) according to another exemplary embodiment. The pixel PX includes a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , and a seventh transistor (T7), a storage capacitor (Cst), and an organic light emitting diode (OLED) may be included. In FIG. 9 , a case in which all transistors included in the pixel PX are PMOS transistors will be described as an example. The third transistor T3 may have the same polarity as that of the first transistor T1 .

In an embodiment, the gate electrode G1 of the first transistor T1 may be connected to the first electrode Cst1 of the storage capacitor Cst. The source electrode S1 of the first transistor T1 may receive the driving voltage ELVDD via the fifth transistor T5 . The drain electrode D1 of the first transistor T1 may be electrically connected to the anode of the organic light emitting diode OLED via the sixth transistor T6 . The first transistor T1 may receive the data voltage Vdata based on the switching operation of the second transistor T2 . The first transistor T1 may allow a driving current Id to flow based on the supplied data voltage Vdata. The first transistor T1 may be collectively referred to as a driving transistor for operating the organic light emitting diode OLED.

In an embodiment, the gate electrode G2 of the second transistor T2 may receive the first gate signal GW. The source electrode S2 of the second transistor T2 may receive the data voltage Vdata. The drain electrode D2 of the second transistor T2 may be connected to the source electrode S1 of the first transistor T1 . The second transistor T2 may transmit the data signal DATA to the source electrode S1 of the first transistor T1 based on the first gate signal GW. The second transistor T2 may be collectively referred to as a switching transistor for switching the operation of the first transistor T1 .

In an embodiment, the gate electrode G3 of the third transistor T3 may receive the first gate signal GW. The source electrode S3 of the third transistor T3 may be connected to the drain electrode D1 of the first transistor T1 . The drain electrode D3 of the third transistor T3 may be connected to the gate electrode G1 of the first transistor T1 . The third transistor T3 may connect the gate electrode G1 and the drain electrode D1 of the first transistor T1 to each other based on the first gate signal GW. The third transistor T3 may diode-connect the first transistor T1.

In an embodiment, the display driving circuit (eg, the display driver IC 1330 of FIG. 13 ) may generate a first inverted gate signal GW_o having a polarity opposite to that of the first gate signal GW. The first inverted gate signal GW_o may have a polarity opposite to that of the first gate signal GW. When the first gate signal GW is the gate low voltage VGL, the first inverted gate signal GW_o may be the gate high voltage VGH. When the first gate signal GW is the gate high voltage VGH, the first inverted gate signal GW_o may be the gate low voltage VGL. The display driving circuit 1330 may supply the first inverted gate signal GW_o to the first inverted gate line.

In an embodiment, the first inversion gate line supplying the first inversion gate signal GW_o may not be electrically connected to the third transistor T3 and/or the fourth transistor T4 . The first inverted gate signal GW_o may be independent of driving of the display 1320 . The first inverted gate signal GW_o may be used to generate the compensation capacitor Cbstc.

In an embodiment, the gate electrode G4 of the fourth transistor T4 may receive the second gate signal GI. The source electrode S4 of the fourth transistor T4 may receive the initialization voltage VINT. The drain electrode D4 of the fourth transistor T4 may be connected to the gate electrode G1 of the first transistor T1 . The fourth transistor T4 may transfer the initialization voltage VINT to the gate electrode G1 of the first transistor T1 based on the second gate signal GI. The fourth transistor T4 may be collectively referred to as an initialization transistor that initializes the voltage of the gate electrode G1 of the first transistor T1 .

In an embodiment, the gate electrode G5 of the fifth transistor T5 may receive the emission control signal EM. The source electrode S5 of the fifth transistor T5 may receive the driving voltage ELVDD. The drain electrode D5 of the fifth transistor T5 may be connected to the source electrode S1 of the first transistor T1 . The fifth transistor T5 may transmit the driving voltage ELVDD to the source electrode S1 of the first transistor T1 based on the emission control signal EM.

In an embodiment, the gate electrode G6 of the sixth transistor T6 may receive the emission control signal EM. The source electrode S6 of the sixth transistor T6 may be connected to the drain electrode D1 of the first transistor T1 . The drain electrode D6 of the sixth transistor T6 may be connected to the anode of the organic light emitting diode OLED. The sixth transistor T6 may connect the organic light emitting diode OLED to the first transistor T1 based on the light emission control signal EM to allow the light emitting current Ioled to flow through the organic light emitting diode OLED. .

In an embodiment, the gate electrode G7 of the seventh transistor T7 may receive the bypass signal GB. The source electrode S7 of the seventh transistor T7 may be connected to the drain electrode D6 of the sixth transistor T6 . The drain electrode D7 of the seventh transistor T7 may receive the initialization voltage VINT. The seventh transistor T7 may allow the bypass current Ibp to flow based on the bypass signal GB.

In an embodiment, the first electrode Cst1 of the storage capacitor Cst may be connected to the gate electrode G1 of the first transistor T1. The second electrode Cst2 of the storage capacitor Cst may receive the driving voltage ELVDD. The storage capacitor Cst may be charged by the data voltage Vdata.

In an embodiment, the anode of the organic light emitting diode OLED may be connected to the drain electrode D6 of the sixth transistor T6. A cathode of the organic light emitting diode OLED may be supplied with a common voltage ELVSS. The organic light emitting diode OLED may emit light based on the emission current Ioled.

In an embodiment, the first gate line supplying the first gate signal GW to the second transistor T2 and the connecting member connected to the gate electrode G1 or the gate electrode G1 of the first transistor T1 ( Example: The first connecting members 1730 of FIG. 10 may overlap by a first area and may be spaced apart by a first distance. A dielectric material having a specified dielectric constant is disposed between the first gate wiring and the gate electrode G1 of the first transistor T1 or a connection member connected to the gate electrode G1 (eg, the first connection member 1730 of FIG. 10 ). can be filled The first gate wiring and the gate electrode G1 of the first transistor T1 or a connection member connected to the gate electrode G1 (eg, the first connection member 1730 of FIG. 7 ) overlap by a first area, The parasitic capacitor Cbst may be formed spaced apart by one distance.

In an embodiment, the first inversion gate line supplying the first inversion gate signal GW_o and a connection member connected to the gate electrode G1 or the gate electrode G1 of the first transistor T1 (eg, as shown in FIG. 7 ) The first connecting members 1730 may overlap by a second area and may be spaced apart by a second distance. A dielectric material having a specified dielectric constant between the first inversion gate wiring and the gate electrode G1 of the first transistor T1 or a connection member connected to the gate electrode G1 (eg, the first connection member 1730 of FIG. 7 ) This can be filled. The first inverted gate wiring and the connecting member connected to the gate electrode G1 or the gate electrode G1 of the first transistor T1 (eg, the first connecting member 1730 of FIG. 7 ) overlap by a second area, The compensation capacitor Cbstc may be formed to be spaced apart by a second distance.

In an exemplary embodiment, the second area may have a first difference value within the first area and a specified first threshold value. A smaller first threshold value may be preferable. For example, the second area may have substantially the same size as the first area.

In an embodiment, the second distance may have a second difference value within the first distance and a second predetermined threshold value. A smaller second threshold value may be preferable. For example, the second distance may have a length substantially equal to the first distance.

In an embodiment, the display driving circuit 1330 may additionally generate a first inverted gate signal GW_o having a polarity opposite to that of the first gate signal GW. A connecting member (eg, the first connecting member of FIG. 7 ) connected to the first inverted gate wiring supplying the first inverted gate signal Gw_o to the gate electrode G1 or the gate electrode G1 of the first transistor T1 1730)) and can be arranged to overlap. When the first inversion gate wiring and a connection member connected to the gate electrode G1 or the gate electrode G1 of the first transistor T1 (eg, the first connection member 1730 of FIG. 7 ) overlap each other, the compensation capacitor Cbstc ) can be formed.

In an embodiment, the first inversion gate wiring and a connection member connected to the gate electrode G1 or the gate electrode G1 of the first transistor T1 (eg, the first connection member 1730 of FIG. 7 ) overlap each other. A third difference within a specified third threshold value with the compensation capacitor Cbstc and the parasitic capacitor Cbst by adjusting the area and/or the distance between the first inversion gate wiring and the gate electrode G1 of the first transistor T1 can have a value. A smaller third threshold value may be preferable. For example, the compensation capacitor Cbstc may have substantially the same size and/or capacity although the polarity is opposite to that of the parasitic capacitor Cbst.

In an embodiment, the first and second areas A1 and A2 and the first and second distances l1 and l2 as shown in Equation 2 below so that the parasitic capacitor Cbst and the compensation capacitor Cbstc may be substantially the same ) can be determined.

In Equation 2, the first dielectric constant ε1 may be the dielectric constant of an internal material filled in the space between the two electrodes of the parasitic capacitor Cbst. In Equation 2, the second dielectric constant ε2 may be the dielectric constant of an internal material filled in the space between the two electrodes of the compensation capacitor Cbstc. In Equation 2, the first area A1 may be an overlapping area of two electrodes of the parasitic capacitor Cbst. In Equation 2, the second area A2 may be an overlapping area of the two electrodes of the compensation capacitor Cbstc. The first and second areas A1 and A2 may be effective electrode areas affecting capacitance. In Equation 2, the first distance l1 may be a distance between two overlapping electrodes of the parasitic capacitor Cbst. In Equation 2, the second distance l2 may be a distance between two overlapping electrodes of the compensation capacitor Cbstc. The first and second distances l1 and l2 may be effective electrode distances that affect capacitance.

In an embodiment, since the first inverted gate line transfers the first inverted gate signal GW_o having a polarity opposite to that of the first gate signal GW, the polarity of the voltage stored in the compensation capacitor Cbstc is the parasitic capacitor Cbst. It can have a polarity opposite to the voltage stored in The compensation capacitor Cbstc may cancel an effect of the parasitic capacitor Cbst on the pixel PX. For example, the compensation capacitor Cbstc may maintain the voltage level of the storage capacitor Cst by offsetting a change in the level of the voltage stored in the storage capacitor Cst due to the parasitic capacitor Cbst.

10 is a diagram 2000 illustrating a pixel (eg, the pixel PX of FIG. 9 ) according to another exemplary embodiment.

In an embodiment, the semiconductor patterns 1200 may be integrally connected. The semiconductor pattern 1200 may be curved in various shapes. The semiconductor pattern 1200 may include channel regions 1241 , 1242 , 1243 , 1244 , 1245 , 1246 , and 1247 forming a channel of the transistor and conductive regions forming a source electrode and a drain electrode of the transistor. The channel regions 1241 , 1242 , 1243 , 1244 , 1245 , 1246 , and 1247 may be doped with an n-type impurity or a p-type impurity.

In one embodiment, the channel regions 1241 , 1242 , 1243 , 1244 , 1245 , 1246 , and 1247 include a first channel region 1241 , a second channel region 1242 , a third channel region 1243 , and a fourth channel region. It may include a region 1244 , a fifth channel region 1245 , a sixth channel region 1246 , and a seventh channel region 1247 . The first channel region 1241 may form a channel region of a first transistor (eg, the first transistor T1 of FIG. 5 ). The second channel region 1242 may form a channel region of a second transistor (eg, the second transistor T2 of FIG. 5 ). The third channel region 1243 may form a channel region of a third transistor (eg, the third transistor T3 of FIG. 5 ). The fourth channel region 1244 may form a channel region of a fourth transistor (eg, the fourth transistor T4 of FIG. 5 ). The fifth channel region 1245 may form a channel region of a fifth transistor (eg, the fifth transistor T5 of FIG. 5 ). The sixth channel region 1246 may form a channel region of a sixth transistor (eg, the sixth transistor T6 of FIG. 5 ). The seventh channel region 1247 may form a channel region of a seventh transistor (eg, the seventh transistor T7 of FIG. 5 ).

In an embodiment, the first gate line 1510 may receive the first gate signal GW. The first inverted gate line 1560 may be disposed parallel to the first gate line 1510 . The first inverted gate line 1560 may receive the first inverted gate signal GW_o.

In an embodiment, the second gate line 1520 may be disposed parallel to the first gate line 1510 . The second gate line 1520 may receive the second gate signal GI. The light emission control wiring 1530 may be disposed parallel to the first gate wiring 1510 . The emission control wiring 1530 may receive the emission control signal EM.

In an embodiment, the gate electrode 1540 of the first transistor T1 may overlap the first channel region 1241 . The driving voltage electrode 1310 may partially overlap the gate electrode 1540 of the first transistor T1 . The gate electrode 1540 of the first transistor T1 may receive a voltage charged in the storage capacitor Cst by the data voltage DATA. The driving voltage electrode 1310 may receive the driving voltage ELVDD. The second gate pattern 1350 may constitute a gate electrode of the fifth transistor T5 .

In an embodiment, the data line 1710 may be disposed to cross the first gate line 1510 , the first inversion gate line 1560 , the second gate line 1520 , and the emission control line 1530 . . The data line 1710 may supply the data voltage DATA to the second transistor T2 through the via hole 1650 .

In an embodiment, the driving voltage line 1720 may be disposed parallel to the data line 1710 . The driving voltage line 1720 may supply the driving voltage ELVDD to the driving voltage electrode 1310 and the fifth transistor T5 through the via holes 1640 and 1670 .

In an embodiment, the first connection member 1730 may connect the gate electrode 1540 of the first transistor T1 to the third transistor T3 through the via hole 1630 . The second connection member 1740 may be connected to the seventh transistor T7 through the via hole 1620 . The third connection member 1750 may be connected to the sixth transistor T6 through the via hole 1610 .

In an embodiment, the first gate line 1510 and the first connection member 1730 may partially overlap. A parasitic capacitor Cbst may be formed in a region where the first gate line 1510 and the first connection member 1730 overlap.

In an embodiment, the first inversion gate line 1560 and the first connection member 1730 may partially overlap. A compensation capacitor Cbstc may be formed in a region where the first inversion gate line 1560 and the first connection member 1730 overlap.

11A is a cross-sectional view 2110 illustrating a plane taken along line V-VI of FIG. 10 according to an exemplary embodiment.

In an embodiment, a buffer layer 1110 may be disposed on the substrate 1100 . A semiconductor pattern 1200 may be disposed on the buffer layer 1110 . A first gate insulating layer 1410 may be disposed on the semiconductor pattern 1200 . A gate electrode 1540 of the first transistor T1 may be disposed on the first gate insulating layer 1410 . A second gate insulating layer 1420 may be disposed on the gate electrode 1540 of the first transistor T1 . A driving voltage electrode 1310 may be disposed on the second gate insulating layer 1420 . An interlayer insulating layer 1600 may be disposed on the gate electrode 1540 of the first transistor T1 . A data line 1710 , a driving voltage line 1720 , and a first connection member 1730 may be disposed on the interlayer insulating layer 1600 .

In an embodiment, the gate electrode 1540 of the first transistor T1, the source electrode 1231 of the first transistor T1, the first channel region 1241, and the drain electrode ( 1251 may constitute the first transistor T1 . A storage capacitor Cst may be formed between the driving voltage electrode 1310 and the gate electrode 1540 of the first transistor T1 .

In an embodiment, the driving voltage electrode 1310 may be connected to the driving voltage line 1720 through the via hole 1640 . The first connection member 1730 may connect the driving voltage electrode 1310 to a portion of the semiconductor pattern 1200 through the via hole 1630 . A part of the semiconductor pattern 1200 may constitute a part of the third transistor T3 .

In an embodiment, a parasitic capacitor Cbst may be formed in a region where the first gate line 1510 and the first connection member 1730 overlap. A compensation capacitor Cbstc may be formed in a region where the first inversion gate line 1550 and the first connection member 1730 overlap.

In an embodiment, the first gate wiring 1510 may be disposed between the first gate insulating layer 1410 and the second gate insulating layer 1420 . The first gate wiring 1510 may be disposed on the same layer as the gate electrode 1540 of the first transistor T1 . The first inversion gate wiring 1550 may be disposed between the first gate insulating layer 1410 and the second gate insulating layer 1420 . The first inversion gate wiring 1550 may be disposed on the same layer as the gate electrode 1540 of the first transistor T1 . The first inverted gate line 1550 may be disposed on the same layer as the first gate line 1510 .

11B is a cross-sectional view 2120 illustrating a plane cut along the line V-VI of FIG. 10 according to an exemplary embodiment.

In an embodiment, the first gate wiring 1510 may be disposed between the second gate insulating layer 1420 and the interlayer insulating layer 1600 . The first gate wiring 1510 may be disposed on the same layer as the driving voltage electrode 1310 . The first inversion gate wiring 1550 may be disposed between the first gate insulating layer 1410 and the second gate insulating layer 1420 . The first inversion gate wiring 1550 may be disposed on the same layer as the gate electrode 1540 of the first transistor T1 .

11C is a cross-sectional view 2130 illustrating a plane cut along the line V-VI of FIG. 10 according to an exemplary embodiment.

In an embodiment, the first gate wiring 1510 may be disposed between the second gate insulating layer 1420 and the interlayer insulating layer 1600 . The first gate wiring 1510 may be disposed on the same layer as the driving voltage electrode 1310 . The first inversion gate wiring 1550 may be disposed between the second gate insulating layer 1420 and the interlayer insulating layer 1600 . The first inversion gate wiring 1550 may be disposed on the same layer as the driving voltage electrode 1310 . The first inverted gate line 1550 may be disposed on the same layer as the first gate line 1510 .

11D is a cross-sectional view 2140 illustrating a plane cut along the line V-VI of FIG. 10 according to an exemplary embodiment.

In an embodiment, the first gate wiring 1510 may be disposed between the first gate insulating layer 1410 and the second gate insulating layer 1420 . The first gate wiring 1510 may be disposed on the same layer as the gate electrode 1540 of the first transistor T1 . The first inversion gate wiring 1550 may be disposed between the second gate insulating layer 1420 and the interlayer insulating layer 1600 . The first inversion gate wiring 1550 may be disposed on the same layer as the driving voltage electrode 1310 .

In an embodiment, an effective area acting on the parasitic capacitor Cbst formed between the first gate wire 1510 and the first connection member 1730 is the first inverted gate wire 1550 and the first connection member 1730 . ) may be larger than the effective area acting on the compensation capacitor Cbstc formed between them. An effective area acting on the capacitor formed between the two electrodes may be larger than an area where the two electrodes overlap.

The electronic device disclosed in this document (eg, the electronic device 1201 of FIG. 12 ) offsets the boost-up phenomenon caused by the parasitic capacitor Cbst to maintain the current consumption of the pixel PX while maintaining the current consumption of the pixel PX. brightness can be maintained.

In the electronic device 1201 disclosed herein, when the gate low voltage VGL is decreased to increase the maximum luminance, the data voltage level Vdata and the gate low voltage VGL are not further decreased due to the boost-up phenomenon. The luminance of the light emitting diode (OLED) may be increased. When the luminance of the organic light emitting diode (OLED) is increased, an additional increase in current consumption may be reduced and a load on a circuit for generating the data voltage level Vdata and the gate low voltage VGL may be reduced.

The electronic device 1201 disclosed in this document may maintain the luminance of the organic light emitting diode (OLED) even when the gate low voltage VGL is varied. A flickering phenomenon caused by the gate low voltage VGL may be reduced. By applying this, it can be driven while dynamically changing the gate low voltage (VGL). When the gate low voltage VGL is varied to match the luminance emitted by the pixel PX, the pixel PX may be driven while reducing the current consumed by the pixel PX.

12 is a block diagram of an electronic device 2201 in a network environment 2200 according to various embodiments of the present disclosure. Referring to FIG. 12 , in a network environment 2200 , the electronic device 2201 communicates with the electronic device 2202 through a first network 2298 (eg, a short-range wireless communication network) or a second network 2299 . It may communicate with the electronic device 2204 or the server 2208 through (eg, a long-distance wireless communication network). According to an embodiment, the electronic device 2201 may communicate with the electronic device 2204 through the server 2208 . According to an embodiment, the electronic device 2201 includes a processor 2220 , a memory 2230 , an input device 2250 , a sound output device 2255 , a display device 2260 , an audio module 2270 , and a sensor module ( 2276), interface 2277, haptic module 2279, camera module 2280, power management module 2288, battery 2289, communication module 2290, subscriber identification module 2296, or antenna module 2297 ) may be included. In some embodiments, at least one of these components (eg, the display device 2260 or the camera module 2280 ) may be omitted or one or more other components may be added to the electronic device 2201 . In some embodiments, some of these components may be implemented as one integrated circuit. For example, the sensor module 2276 (eg, a fingerprint sensor, an iris sensor, or an illuminance sensor) may be implemented while being embedded in the display device 2260 (eg, a display).

The processor 2220, for example, executes software (eg, a program 2240) to execute at least one other component (eg, a hardware or software component) of the electronic device 2201 connected to the processor 2220. It can control and perform various data processing or operations. According to one embodiment, as at least part of data processing or operation, the processor 2220 converts commands or data received from other components (eg, the sensor module 2276 or the communication module 2290) to the volatile memory 2232 . may be loaded into the volatile memory 2232 , may process commands or data stored in the volatile memory 2232 , and may store the resulting data in the non-volatile memory 2234 . According to an embodiment, the processor 2220 includes a main processor 2221 (eg, a central processing unit or an application processor), and a co-processor 2223 (eg, a graphics processing unit or an image signal processor) capable of operating independently or in conjunction with the main processor 2221 . , a sensor hub processor, or a communication processor). Additionally or alternatively, the auxiliary processor 2223 may be configured to use less power than the main processor 2221 or to specialize in a specified function. The secondary processor 2223 may be implemented separately from or as a part of the main processor 2221 .

The coprocessor 2223 may be, for example, on behalf of the main processor 2221 while the main processor 2221 is in an inactive (eg, sleep) state, or the main processor 2221 is active (eg, executing an application). ), together with the main processor 2221, at least one of the components of the electronic device 2201 (eg, the display device 2260, the sensor module 2276, or the communication module 2290) It is possible to control at least some of the related functions or states. According to one embodiment, the coprocessor 2223 (eg, an image signal processor or a communication processor) may be implemented as part of another functionally related component (eg, the camera module 2280 or the communication module 2290). have.

The memory 2230 may store various data used by at least one component of the electronic device 2201 (eg, the processor 2220 or the sensor module 2276). The data may include, for example, input data or output data for software (eg, the program 2240 ) and instructions related thereto. The memory 2230 may include a volatile memory 2232 or a non-volatile memory 2234 .

The program 2240 may be stored as software in the memory 2230 , and may include, for example, an operating system 2242 , middleware 2244 , or an application 2246 .

The input device 2250 may receive a command or data to be used in a component (eg, the processor 2220 ) of the electronic device 2201 from the outside (eg, a user) of the electronic device 2201 . The input device 2250 may include, for example, a microphone, a mouse, a keyboard, or a digital pen (eg, a stylus pen).

The sound output device 2255 may output a sound signal to the outside of the electronic device 2201 . The sound output device 2255 may include, for example, a speaker or a receiver. The speaker can be used for general purposes such as multimedia playback or recording playback, and the receiver can be used to receive an incoming call. According to one embodiment, the receiver may be implemented separately from or as part of the speaker.

The display device 2260 may visually provide information to the outside (eg, a user) of the electronic device 2201 . The display device 2260 may include, for example, a display, a hologram device, or a projector and a control circuit for controlling the corresponding device. According to an embodiment, the display device 2260 may include a touch circuitry configured to sense a touch or a sensor circuit (eg, a pressure sensor) configured to measure the intensity of a force generated by the touch. have.

The audio module 2270 may convert a sound into an electric signal or, conversely, convert an electric signal into a sound. According to an embodiment, the audio module 2270 acquires a sound through the input device 2250 or an external electronic device (eg, a sound output device 2255 ) directly or wirelessly connected to the electronic device 2201 . The electronic device 2202) (eg, a speaker or headphones) may output sound.

The sensor module 2276 detects an operating state (eg, power or temperature) of the electronic device 2201 or an external environmental state (eg, user state), and generates an electrical signal or data value corresponding to the sensed state. can do. According to an embodiment, the sensor module 2276 may include, for example, a gesture sensor, a gyro sensor, a barometric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, It may include a temperature sensor, a humidity sensor, or an illuminance sensor.

The interface 2277 may support one or more specified protocols that may be used for the electronic device 2201 to directly or wirelessly connect with an external electronic device (eg, the electronic device 2202). According to an embodiment, the interface 2277 may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface.

The connection terminal 2278 may include a connector through which the electronic device 2201 can be physically connected to an external electronic device (eg, the electronic device 2202). According to an embodiment, the connection terminal 2278 may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (eg, a headphone connector).

The haptic module 2279 may convert an electrical signal into a mechanical stimulus (eg, vibration or movement) or an electrical stimulus that the user can perceive through tactile or kinesthetic sense. According to an embodiment, the haptic module 2279 may include, for example, a motor, a piezoelectric element, or an electrical stimulation device.

The camera module 2280 may capture still images and moving images. According to one embodiment, the camera module 2280 may include one or more lenses, image sensors, image signal processors, or flashes.

The power management module 2288 may manage power supplied to the electronic device 2201 . According to an embodiment, the power management module 2288 may be implemented as, for example, at least a part of a power management integrated circuit (PMIC).

The battery 2289 may supply power to at least one component of the electronic device 2201 . According to one embodiment, battery 2289 may include, for example, a non-rechargeable primary cell, a rechargeable secondary cell, or a fuel cell.

The communication module 2290 is a direct (eg, wired) communication channel or a wireless communication channel between the electronic device 2201 and an external electronic device (eg, the electronic device 2202, the electronic device 2204, or the server 2208). It can support establishment and communication performance through the established communication channel. The communication module 2290 may include one or more communication processors that operate independently of the processor 2220 (eg, an application processor) and support direct (eg, wired) communication or wireless communication. According to one embodiment, the communication module 2290 is a wireless communication module 2292 (eg, a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module 2294 (eg, : It may include a LAN (local area network) communication module, or a power line communication module). Among these communication modules, the corresponding communication module is a first network 2298 (eg, a short-range communication network such as Bluetooth, WiFi direct or IrDA (infrared data association)) or a second network 2299 (eg, a cellular network, the Internet, Alternatively, it may communicate with the external electronic device 2204 through a computer network (eg, a telecommunication network such as a LAN or WAN). These various types of communication modules may be integrated into one component (eg, a single chip) or may be implemented as a plurality of components (eg, multiple chips) separate from each other. The wireless communication module 2292 uses subscriber information (eg, International Mobile Subscriber Identifier (IMSI)) stored in the subscriber identification module 2296 within a communication network such as the first network 2298 or the second network 2299 . The electronic device 2201 may be identified and authenticated.

The antenna module 2297 may transmit or receive a signal or power to the outside (eg, an external electronic device). According to an embodiment, the antenna module 2297 may include one antenna including a conductor formed on a substrate (eg, a PCB) or a radiator formed of a conductive pattern. According to an embodiment, the antenna module 2297 may include a plurality of antennas. In this case, at least one antenna suitable for a communication method used in a communication network such as the first network 2298 or the second network 2299 is connected from the plurality of antennas by, for example, the communication module 2290 . can be chosen. A signal or power may be transmitted or received between the communication module 2290 and an external electronic device through the selected at least one antenna. According to some embodiments, other components (eg, RFIC) other than the radiator may be additionally formed as a part of the antenna module 2297 .

At least some of the components are connected to each other through a communication method between peripheral devices (eg, a bus, general purpose input and output (GPIO), serial peripheral interface (SPI), or mobile industry processor interface (MIPI)) and a signal ( eg commands or data) can be exchanged with each other.

According to an embodiment, the command or data may be transmitted or received between the electronic device 2201 and the external electronic device 2204 through the server 2208 connected to the second network 2299 . Each of the external electronic devices 2202 and 2204 may be the same as or different from the electronic device 2201 . According to an embodiment, all or a part of operations executed by the electronic device 2201 may be executed by one or more of the external electronic devices 2202 , 2204 , or 2208 . For example, when the electronic device 2201 needs to perform a function or service automatically or in response to a request from a user or other device, the electronic device 2201 may perform the function or service itself instead of executing the function or service itself. Alternatively or additionally, one or more external electronic devices may be requested to perform at least a part of the function or the service. One or more external electronic devices that have received the request may execute at least a part of the requested function or service, or an additional function or service related to the request, and transmit a result of the execution to the electronic device 2201 . The electronic device 2201 may process the result as it is or additionally and provide it as at least a part of a response to the request. For this purpose, for example, cloud computing, distributed computing, or client-server computing technology may be used.

13 is a block diagram 1300 of a display device 2260 according to various embodiments. Referring to FIG. 13 , a display device 2260 may include a display 2320 and a display driver IC (DDI) 2330 for controlling the display 2320 . The DDI 2330 may include an interface module 2331 , a memory 2333 (eg, a buffer memory), an image processing module 2335 , or a mapping module 2337 . The DDI 2330 receives, for example, image data or image information including an image control signal corresponding to a command for controlling the image data from other components of the electronic device 2201 through the interface module 2331 . can do. For example, according to one embodiment, the image information is the processor 2220 (eg, the main processor 2221 (eg, an application processor) or the auxiliary processor 2223 ( For example: graphic processing device) The DDI 2330 may communicate with the touch circuit 2350 or the sensor module 2276 through the interface module 2331. In addition, the DDI 2330 may be At least a portion of the received image information may be stored in the memory 2333, for example, in units of frames. Pre-processing or post-processing (eg, adjusting resolution, brightness, or size) may be performed based at least on the characteristics of the display 2320. The mapping module 2337 may be pre-processed or post-processed through the image processing module 2235 A voltage value or a current value corresponding to the image data may be generated. According to an embodiment, the generation of the voltage value or current value may include, for example, a property of pixels of the display 2320 (eg, an arrangement of pixels ( RGB stripe or pentile structure), or the size of each of the sub-pixels) At least some pixels of the display 2320 are, for example, based at least in part on the voltage value or the current value. By being driven, visual information (eg, text, image, or icon) corresponding to the image data may be displayed through the display 2320 .

According to an embodiment, the display device 2260 may further include a touch circuit 2350 . The touch circuit 2350 may include a touch sensor 2351 and a touch sensor IC 2353 for controlling the touch sensor 2351 . The touch sensor IC 2353 may control the touch sensor 2351 to sense, for example, a touch input or a hovering input for a specific location of the display 2320 . For example, the touch sensor IC 2353 may detect a touch input or a hovering input by measuring a change in a signal (eg, voltage, light amount, resistance, or electric charge amount) for a specific position of the display 2320 . The touch sensor IC 2353 may provide information (eg, location, area, pressure, or time) regarding the sensed touch input or hovering input to the processor 2220 . According to an embodiment, at least a part of the touch circuit 2350 (eg, the touch sensor IC 2353 ) is disposed as a part of the display driver IC 2330 , the display 2320 , or outside the display device 2260 . may be included as a part of another component (eg, the coprocessor 2223).

According to an embodiment, the display device 2260 may further include at least one sensor (eg, a fingerprint sensor, an iris sensor, a pressure sensor, or an illuminance sensor) of the sensor module 2276 or a control circuit therefor. In this case, the at least one sensor or a control circuit therefor may be embedded in a part of the display device 2260 (eg, the display 2320 or the DDI 2330 ) or a part of the touch circuit 2350 . For example, when the sensor module 2276 embedded in the display device 2260 includes a biometric sensor (eg, a fingerprint sensor), the biometric sensor provides biometric information related to a touch input through a partial area of the display 2320 . (eg fingerprint image) can be acquired. As another example, when the sensor module 2276 embedded in the display device 2260 includes a pressure sensor, the pressure sensor may acquire pressure information related to a touch input through a part or the entire area of the display 2310 . can According to an embodiment, the touch sensor 2351 or the sensor module 2276 may be disposed between pixels of the pixel layer of the display 2320 , or above or below the pixel layer.

The electronic device according to various embodiments disclosed in this document may have various types of devices. The electronic device may include, for example, a portable communication device (eg, a smart phone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance device. The electronic device according to the embodiment of the present document is not limited to the above-described devices.

The various embodiments of this document and terms used therein are not intended to limit the technical features described in this document to specific embodiments, but it should be understood to include various modifications, equivalents, or substitutions of the embodiments. In connection with the description of the drawings, like reference numerals may be used for similar or related components. The singular form of the noun corresponding to the item may include one or more of the item, unless the relevant context clearly dictates otherwise. As used herein, “A or B”, “at least one of A and B”, “at least one of A or B”, “A, B or C”, “at least one of A, B and C” and “A; Each of the phrases such as "at least one of B, or C" may include any one of, or all possible combinations of, items listed together in the corresponding one of the phrases. Terms such as "first", "second", or "first" or "second" may be used simply to distinguish an element from other elements in question, and may refer elements to other aspects (e.g., importance or order) is not limited. that one (eg first) component is “coupled” or “connected” to another (eg, second) component with or without the terms “functionally” or “communicatively” When referenced, it means that one component can be connected to the other component directly (eg by wire), wirelessly, or through a third component.

As used herein, the term “module” may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with terms such as, for example, logic, logic block, component, or circuit. A module may be an integrally formed part or a minimum unit or a part of the part that performs one or more functions. For example, according to an embodiment, the module may be implemented in the form of an application-specific integrated circuit (ASIC).

According to various embodiments of the present document, one or more instructions stored in a storage medium (eg, internal memory 2236 or external memory 2238) readable by a machine (eg, electronic device 2201) may be implemented as software (eg, the program 2240) including For example, a processor (eg, processor 2220 ) of a device (eg, electronic device 2201 ) may call at least one command among one or more commands stored from a storage medium and execute it. This makes it possible for the device to be operated to perform at least one function according to the called at least one command. The one or more instructions may include code generated by a compiler or code executable by an interpreter. The device-readable storage medium may be provided in the form of a non-transitory storage medium. Here, 'non-transitory storage medium' is a tangible device and only means that it does not contain a signal (eg, electromagnetic wave). It does not distinguish the case where it is stored as For example, the 'non-transitory storage medium' may include a buffer in which data is temporarily stored.

According to an embodiment, the method according to various embodiments disclosed in this document may be included and provided in a computer program product. Computer program products may be traded between sellers and buyers as commodities. The computer program product is distributed in the form of a machine-readable storage medium (eg compact disc read only memory (CD-ROM)), or via an application store (eg Play Store™) or on two user devices ( It can be distributed (eg downloaded or uploaded) directly or online between smartphones (eg: smartphones). In the case of online distribution, at least a portion of the computer program product (eg, a downloadable app) is stored at least on a machine-readable storage medium, such as a memory of a manufacturer's server, a server of an application store, or a relay server. It may be temporarily stored or temporarily created.

According to various embodiments, each component (eg, a module or a program) of the above-described components may include a singular or a plurality of entities. According to various embodiments, one or more components or operations among the above-described corresponding components may be omitted, or one or more other components or operations may be added. Alternatively or additionally, a plurality of components (eg, a module or a program) may be integrated into one component. In this case, the integrated component may perform one or more functions of each component of the plurality of components identically or similarly to those performed by the corresponding component among the plurality of components prior to the integration. . According to various embodiments, operations performed by a module, program, or other component are executed sequentially, in parallel, repeatedly, or heuristically, or one or more of the operations are executed in a different order, or omitted. or one or more other operations may be added.

Claims (20)

In an electronic device,
housing;
a display that is seen through at least a part of the housing and displays a screen using a plurality of pixels;
a display driving circuit that provides a data voltage and at least one gate signal for driving each of the plurality of pixels to the display; and
a processor connected to the display driving circuit;
Each of the plurality of pixels,
a first transistor driven based on the data voltage;
a second transistor connected to the source electrode of the first transistor and configured to control a driving timing of the first transistor based on a first gate signal among the at least one gate signal; and
Based on a first inverted gate signal having a polarity opposite to that of the second transistor, connected to a drain electrode of the first transistor, and having a polarity opposite to that of the first gate signal among the at least one gate signal, the first transistor A third transistor for controlling the driving timing of
a first gate line for supplying the first gate signal to the second transistor overlaps at least partially with a gate electrode of the first transistor;
a first inversion gate wiring supplying the first inversion gate signal to the third transistor overlaps at least partially with the gate electrode of the first transistor;
The magnitude of the capacitance formed by the first gate wiring and the gate electrode of the first transistor is a difference value within a specified threshold value from the magnitude of the capacitance formed by the first inversion gate wiring and the gate electrode of the first transistor An electronic device with The method according to claim 1,
the first gate wiring overlaps the gate electrode of the first transistor by a first area;
the first inversion gate wiring overlaps the gate electrode of the first transistor by a second area;
The second area has a first difference value between the first area and a first threshold value. The method according to claim 1,
the first gate wiring is spaced apart from the gate electrode of the first transistor by a first distance;
the first inversion gate wiring is spaced apart from the gate electrode of the first transistor by a second distance;
The first distance and the second distance have a second difference value within a second threshold value. The method according to claim 1,
the first gate wiring forms a parasitic capacitor with the gate electrode of the first transistor;
the first inversion gate wiring forms the gate electrode of the first transistor and a compensation capacitor;
The value of the parasitic capacitor and the value of the compensation capacitor have a third difference value within a third threshold value. 5. The method according to claim 4,
Further comprising a first connecting member connecting the gate electrode of the first transistor and the third transistor to each other through via holes,
a parasitic capacitor is formed in a region where the first gate line and the first connection member overlap;
The compensation capacitor is formed in a region where the first inversion gate line and the first connection member overlap. 6. The method of claim 5,
an interlayer insulating film is disposed on the gate electrode of the first transistor;
The electronic device in which the first connection member is disposed on the interlayer insulating layer. The method according to claim 1,
The first gate line and the first inverted gate line are disposed between the first gate insulating layer and the second gate insulating layer. The method according to claim 1,
the first gate wiring is disposed on the same layer as the gate electrode of the first transistor;
The first inversion gate wiring is disposed between the first gate insulating layer and the second gate insulating layer. The method according to claim 1,
The first gate line and the first inverted gate line are disposed on the same layer as the gate electrode of the first transistor. The method according to claim 1,
the first gate wiring is disposed between the first gate insulating layer and the second gate insulating layer;
and the first inversion gate wiring is disposed on the same layer as the gate electrode of the first transistor. In an electronic device,
housing;
a display that is seen through at least a part of the housing and displays a screen using a plurality of pixels;
a display driving circuit that provides a data voltage and at least one gate signal for driving each of the plurality of pixels to the display; and
a processor connected to the display driving circuit;
Each of the plurality of pixels,
a first transistor driven based on the data voltage;
a second transistor connected to the source electrode of the first transistor and configured to control a driving timing of the first transistor based on a first gate signal among the at least one gate signal; and
a third transistor having the same polarity as that of the second transistor, connected to the drain electrode of the first transistor, and controlling a driving timing of the first transistor based on the first gate signal;
a first gate line for supplying the first gate signal to the second transistor overlaps at least partially with a gate electrode of the first transistor;
The display driving circuit,
generating a first inverted gate signal having a polarity opposite to that of the first gate signal;
supplying the first inverted gate signal to a first inverted gate wiring that supplies the first inverted gate signal to the third transistor;
the first inversion gate wiring at least partially overlaps the gate electrode of the first transistor;
The magnitude of the capacitance formed by the first gate wiring and the gate electrode of the first transistor is a difference value within a specified threshold value from the magnitude of the capacitance formed by the first inversion gate wiring and the gate electrode of the first transistor An electronic device set up to have 12. The method of claim 11,
the first gate wiring overlaps the gate electrode of the first transistor by a first area;
the first inversion gate wiring overlaps the gate electrode of the first transistor by a second area;
The second area has a first difference value between the first area and a first threshold value. 12. The method of claim 11,
the first gate wiring is spaced apart from the gate electrode of the first transistor by a first distance;
the first inversion gate wiring is spaced apart from the gate electrode of the first transistor by a second distance;
The first distance and the second distance have a second difference value within a second threshold value. 12. The method of claim 11,
the first gate wiring forms a parasitic capacitor with the gate electrode of the first transistor;
the first inversion gate wiring forms the gate electrode of the first transistor and a compensation capacitor;
The value of the parasitic capacitor and the value of the compensation capacitor have a third difference value within a third threshold value. 15. The method of claim 14,
Further comprising a first connecting member connecting the gate electrode of the first transistor and the third transistor to each other through via holes,
The parasitic capacitor is formed in a region where the first gate line and the first connection member overlap;
The compensation capacitor is formed in a region where the first inversion gate line and the first connection member overlap. 16. The method of claim 15,
an interlayer insulating film is disposed on the gate electrode of the first transistor;
The electronic device in which the first connection member is disposed on the interlayer insulating layer. 12. The method of claim 11,
The first gate line and the first inverted gate line are disposed between the first gate insulating layer and the second gate insulating layer. 12. The method of claim 11,
the first gate wiring is disposed on the same layer as the gate electrode of the first transistor;
The first inversion gate wiring is disposed between the first gate insulating layer and the second gate insulating layer. 12. The method of claim 11,
The first gate line and the first inverted gate line are disposed on the same layer as the gate electrode of the first transistor. 12. The method of claim 11,
the first gate wiring is disposed between the first gate insulating layer and the second gate insulating layer;
and the first inversion gate wiring is disposed on the same layer as the gate electrode of the first transistor.

Images