KR20220014794A - Ion controllable transistor for neuromorphic synapse device and manufacturing method thereof - Google Patents

Abstract

Disclosed is an ion-controlled transistor-based neuromorphic synaptic device used for a memory and neuromorphic computing by analogically updating and maintaining a synaptic weighted value. According to one embodiment, the ion-controlled transistor-based neuromorphic synaptic device comprises: a channel region formed on a semiconductor substrate; a source region and a drain region formed on both sides of the channel region; an interlayer insulating film disposed on the channel region; a gate region formed on an interlayer insulating film; and a solid electrolyte layer interposed between the interlayer insulating film and the gate region.

Description

Ion control transistor-based neuromorphic synaptic device and manufacturing method thereof

The following embodiments relate to an ion-controlled transistor-based neuromorphic synaptic device and a method for manufacturing the same, and are techniques for a neuromorphic synaptic device utilized as a system for implementing memory and neuromorphic computing.

With the advent of the big data era, the demand for computation, processing, and storage of vast amounts of data is explosively increasing. The previously used von Neumann structure in computer systems is a structure in which a central processing unit that processes and calculates data and a memory that stores processed and calculated data are separated. In the data exchange process between the central processing unit and the memory according to the increase in the amount of data in the data era, bottlenecks and energy consumption are emerging as problems that must be solved.

As a solution to the problems of the existing computer systems, there is a movement to implement a system that mimics the human brain, which is called neuromorphic computing. Among neuromorphic computing, a deep neural network requires a synapse with a specific synaptic weight connected in parallel and a neuron that passes it to the next synapse, unlike the existing von Neumann computing. Fast learning and reasoning can be performed with efficient energy consumption.

Most of these deep neural networks have been studied in a way that processes data using software. However, in order to realize true ultra-low-power neuromorphic computing, suitable hardware must exist indispensably, and it is essential to secure synaptic and neuron devices that enable parallel operation from the device stage and have energy efficiency.

For an ideal synaptic device for realizing a deep neural network, the analog synaptic weight update characteristic, in which the channel conductivity value changes as the same pulse voltage is applied, and the synaptic weight update are linearly strengthened according to the number of pulses (potentiation) ) and weakening characteristics, non-volatile to store updated synaptic weights regardless of power supply, and good durability in which characteristics do not change even when synaptic weights are updated multiple times are required.

In devices such as 2-terminal-based RRAM (Resistive Random Access Memory), PCRAM (Phase-Change Random Access Memory), and memristor, the resistance of the channel through which current flows is changed and stored by applying a voltage pulse. Like the human nervous system, it has the principle of changing analog weights and has received much attention as a synaptic device in that it can be integrated with low power consumption.

However, since the variable resistance characteristic of the channel through which the current flows rapidly changes due to the device characteristics, the linearity of the weight change is low and the durability is not good. In addition, in the case of a two-terminal-based synaptic device, it has a fatal disadvantage that additional selector devices and circuit elements are required when manufactured in the form of an array for the overall system configuration.

As a solution to these problems, research on transistor-based synaptic devices has been actively connected in recent years. In the case of a transistor-based synaptic device, parallel write and read operations are possible, and an additional selection device is not required. Among them, in the case of an ion-controlled transistor, it is possible to update channel conductivity and analog synaptic weights by ion potential control similar to the neurotransmission system of real organisms, as well as update linear synaptic weights by analog ion movement in the electrolyte. It has the advantage that

However, in the case of the conventional ion-controlled transistor, it has been manufactured using a liquid or ion-gel type electrolyte, which has the disadvantage that it is not suitable for manufacturing a synaptic device that requires a large-area process and integration. In addition, in the case of a liquid or ionic gel electrolyte, it is difficult to secure device characteristics that are stable over time.

In one embodiment, by utilizing a solid electrolyte layer that analogically updates channel conductivity and synaptic weight by the movement of ions present therein, while securing stable device characteristics, large-area processing and integration are possible neuromorphic We propose a synaptic device.

More specifically, one embodiment implements a memory operation by the linear movement of cations and anions present in the solid electrolyte layer, and a synaptic weight (Conductance) change due to ion movement. We propose a neuromorphic synaptic device that remembers weight).

In addition, some embodiments control the width and frequency of the voltage pulse applied to the gate region, or by adjusting the material forming the channel region, the solid electrolyte region, the gate region, and the source region, like the synapse of a real organism, STDP (Spike We propose a neuromorphic synaptic device that implements Timing Dependent Plasticity), STP (Short Term Plasticity), and LTP (Long Term Plasticity) characteristics.

According to an embodiment, the ion-controlled transistor-based neuromorphic synaptic device includes: a channel region formed on a semiconductor substrate; a source region and a drain region formed on both sides of the channel region; an interlayer insulating film disposed on the channel region; a gate region formed on the interlayer insulating layer; and a solid electrolyte layer interposed between the interlayer insulating film and the gate region.

According to one side, in the ion-controlled transistor-based neuromorphic synaptic device, in response to a voltage pulse being applied to the gate region, the channel conductivity is updated analogously by movement of ions present in the solid electrolyte layer. can be done with

According to the other side, the ion-controlled transistor-based neuromorphic synaptic device uses the characteristics of the solid electrolyte layer in which ions are linearly and analogously distributed, the movement of ions present in the solid electrolyte layer It can be characterized in that the channel conductivity is updated analogously by

According to another side, the ion-controlled transistor-based neuromorphic synaptic device may be characterized in that by analogically updating the channel conductivity, the synaptic weight may be analogically expressed.

According to another aspect, the solid electrolyte layer has high ionic conductivity and is a sulfide-based material [Li10GeP2S12, Li9.54Si1.74P1.44S11.7Cl0.3, Argyrodite, LPS (Lithium phosphorus sulfide), LPS + LiCl]; , PEG (Polyethylene glycol), PEGDMA (Polyethylene glycol dimethacrylate), PTFE (Polytetrafluoroethylene), PEEK (Polyether ether ketone), Nafion (C7HF13O5S · C2F4)] at least one material.

According to another aspect, the channel region, the source region, and the drain region may form a semiconductor region having a structure formed in a horizontal direction or a vertical direction.

According to another aspect, the channel region may include at least one semiconductor material of silicon (Si), germanium (Ge, SiGe), a group III-V compound, or a 2-D material (carbon nanotube, MoS2, graphene, etc.). It may be characterized by including.

According to another aspect, the source region and the drain region are formed in a form in which impurity ions are implanted into the semiconductor material forming the channel region, or at least one of Al, W, Ti, Co, Ni, Er, or Pt. It may be formed of a silicide alloy containing, or may be characterized in that it is formed of at least one metal of Au, Al, Ag, Mg, Ca, Yb, Cs-ITO, Ti, Cr, or Ni.

According to another aspect, the interlayer insulating layer may include silicon oxide (SiO2), germanium, which can insulate between the gate region and the channel region when the synaptic weight of the ion-controlled transistor-based neuromorphic synaptic device is updated or when the transistor is operating. It may include at least one material of an oxide (GeO2), a solid oxide layer, or a low dielectric constant (Low-k) dielectric layer.

According to another side, the ion-controlled transistor-based neuromorphic synaptic device, while positioned on the source region and the drain region, silicon oxide (SiO2), germanium oxide (GeO2), a solid oxide film (Oxide) or low A sacrificial insulating layer formed of at least one material among dielectric layers having a dielectric constant may be further included.

According to another side, the ion-controlled transistor-based neuromorphic synapse device has three terminals comprising a terminal of the gate region, a terminal of the source region, and a terminal of the drain region or a terminal of the gate region, the source region It may be characterized in that it is implemented as four terminals consisting of a body terminal together with a terminal and the drain region.

According to an embodiment, a gate-first manufacturing method of a neuromorphic synaptic device based on an ion-controlled transistor includes depositing an interlayer insulating film, a solid electrolyte layer, and a gate region on a semiconductor substrate; patterning a portion of the interlayer insulating film, the solid electrolyte layer, and the gate region positioned on the channel region formed on the semiconductor substrate; forming a source region and a drain region on a portion of the semiconductor substrate exposed as a result of the patterning, wherein a portion of the semiconductor substrate is located on both sides of the channel region; and depositing a sacrificial insulating layer on the source region and the drain region.

According to an embodiment, the gate-last manufacturing method of the neuromorphic synaptic device based on the ion-controlled transistor comprises: forming a source region and a drain region on a semiconductor substrate - a dummy gate on the upper portion of the channel region formed on the semiconductor substrate is located-; depositing a sacrificial insulating layer on the semiconductor substrate; selectively removing the dummy gate; and forming an interlayer insulating layer, a solid electrolyte layer, and a gate region in a space where the dummy gate is removed.

According to one embodiment, a synapse array consisting of a plurality of ion-controlled transistor-based neuromorphic synaptic elements, each of the plurality of ion-controlled transistor-based neuromorphic synaptic elements includes: a channel region formed on a semiconductor substrate; a source region and a drain region formed on both sides of the channel region; an interlayer insulating film disposed on the channel region; a gate region formed on the interlayer insulating layer; and a solid electrolyte layer interposed between the interlayer insulating film and the gate region.

According to one side, the synapse array updates the synaptic weight through the terminal of the gate region in each of the plurality of ion-controlled transistor-based neuromorphic synaptic devices and reads the updated synaptic weight through the terminal of the drain region It may be characterized in that it supports parallel operations that perform

According to an embodiment, the ion-controlled transistor-based neuromorphic synaptic device includes: a channel region formed on a semiconductor substrate; a source region and a drain region formed on both sides of the channel region; an interlayer insulating film disposed on the channel region; a gate region formed on the interlayer insulating layer; and movement of the ions present therein in response to a voltage pulse being applied to the gate region based on the linear and analog distribution of ions therein while being interposed between the interlayer insulating layer and the gate region. It comprises a solid electrolyte layer for analogically updating the channel conductivity by the analog, and by analogly updating the channel conductivity, it is characterized in that the synaptic weight is expressed analogously.

In one embodiment, by utilizing a solid electrolyte layer that analogically updates channel conductivity and synaptic weight by the movement of ions present therein, while securing stable device characteristics, large-area processing and integration are possible neuromorphic A synaptic device can be proposed.

More specifically, one embodiment proposes a neuromorphic synaptic device that implements a memory operation by the linear movement of positive and negative ions existing inside the solid electrolyte layer, and stores the channel conductivity change due to ion movement as a synaptic weight. can do.

In addition, some embodiments control the width and frequency of the voltage pulse applied to the gate region, or by adjusting the material forming the channel region, the solid electrolyte region, the gate region, and the source region, STDP, STP like a synapse of a real organism. , it is possible to propose a neuromorphic synaptic device that implements LTP characteristics.

Accordingly, embodiments may propose a neuromorphic synaptic device that can be used not only in a deep neural network but also in a spiking neural network.

The exemplary embodiments are not limited to the above effects, and may be variously expanded without departing from the technical spirit and technical scope.

1 is a perspective view showing an ion-controlled transistor-based neuromorphic synaptic device according to an embodiment.
Figure 2a is a graph measuring the drain current ( _ID ) to the gate voltage (V _G ) of the ion-controlled transistor-based neuromorphic synaptic device according to an embodiment.
2B to 2C are diagrams for explaining an operation of updating channel conductivity by ion movement in a solid electrolyte layer in an ion-controlled transistor-based neuromorphic synaptic device according to an embodiment.
3 is a graph for explaining the weight strengthening characteristics and weight weakening characteristics of the solid electrolyte layer included in the ion-controlled transistor-based neuromorphic synaptic device according to an embodiment.
4 is a flowchart illustrating a gate-first manufacturing method of an ion-controlled transistor-based neuromorphic synaptic device according to an embodiment.
5A to 5D are XZ cross-sectional views illustrating a gate-first manufacturing method of an ion-controlled transistor-based neuromorphic synaptic device according to an embodiment.
6 is a flowchart illustrating a gate-last manufacturing method of an ion-controlled transistor-based neuromorphic synaptic device according to an embodiment.
7A to 7D are XZ cross-sectional views for explaining a gate-last manufacturing method of an ion-controlled transistor-based neuromorphic synaptic device according to an embodiment.
8 is a diagram illustrating a synaptic array composed of an ion-controlled transistor-based neuromorphic synaptic device according to an embodiment.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or limited by the examples. Also, like reference numerals in each figure denote like members.

In addition, the terms (Terminology) used in this specification are terms used to properly express a preferred embodiment of the present invention, which may vary depending on the intention of a user or operator or customs in the field to which the present invention belongs. Accordingly, definitions of these terms should be made based on the content throughout this specification.

1 is a perspective view showing an ion-controlled transistor-based neuromorphic synaptic device according to an embodiment. Hereinafter, the ion-controlled transistor-based neuromorphic synaptic device 100 is described as having a structure formed in a horizontal direction for convenience, but may have a structure formed in a vertical direction in terms of integration.

Referring to FIG. 1 , an ion-controlled transistor-based neuromorphic synaptic device 100 according to an embodiment includes a semiconductor substrate 110 , a channel region 120 , a source region 130 and a drain region 140 , and an interlayer It may include an insulating layer 150 , a gate region 160 , and a solid electrolyte layer 170 .

The semiconductor substrate 110 is one of a silicon wafer, a strained silicon wafer, a germanium wafer, a strained germanium wafer, or a silicon germanium wafer. Any one may be selected and used.

The channel region 120 may include at least one semiconductor selected from silicon (Si), germanium (Ge, SiGe), a group III-V compound, or a 2-D material (eg, carbon nanotube, MoS2, graphene, etc.) on the semiconductor substrate 110 . It may be formed of a material.

The source region 130 and the drain region 140 may be formed on both sides of the channel region 120 , and in more detail, impurity ions (arsenic (As) and phosphorus (P)) in the semiconductor material forming the channel region 120 . N-type impurities such as ) or P-type impurities such as boron (B)) are implanted, or formed of a silicide alloy containing at least one of Al, W, Ti, Co, Ni, Er, or Pt, It may be formed of at least one metal of Au, Al, Ag, Mg, Ca, Yb, Cs-ITO, Ti, Cr, or Ni. For example, when the semiconductor region that is the semiconductor substrate 110 including the channel region 120 , the source region 130 , and the drain region 140 is formed by impurity ion implantation, the source region 130 and the drain region 140 . Silver may be formed by disposing a silicide alloy such as Al, W, Ti, Co, Ni, Er, or Pt. As another example, when the semiconductor region is formed of a 2-D material, the source region 130 and the drain region 140 may include at least one of Au, Al, Ag, Mg, Ca, Yb, Cs-ITO, Ti, Cr, or Ni. of metal may be disposed.

In this case, the source region 130 and the drain region 140 must have the same impurity ion type, and the impurity ion type of the channel region 120 is the impurity ion type of each of the source region 130 and the drain region 140 . It may be different from the type. However, in the junctionless structure, the impurity ion type of the channel region 120 may be the same as the impurity ion type of each of the source region 130 and the drain region 140 .

The channel region 120 , the source region 130 , and the drain region 140 form a semiconductor region, and among silicon wafers, germanium wafers, group III-V compound wafers, and 2-D materials (CNT, MoS2, etc.) It may be formed of at least one, and may be isolated from the outside.

This semiconductor region is formed by implanting impurity ions into N+ type/P type/N+ type (source region 130/channel region 120/drain region 140) or P+ type/N type/P+ type (source region 130). )/channel region 120/drain region 140). For example, the semiconductor region may be formed on the semiconductor substrate 110 through ion implantation, epitaxial growth, or selective epitaxial growth. When epitaxial growth is used, the semiconductor region may be formed of at least one of silicon, strained silicon, silicon germanium, or silicon carbide.

Accordingly, the semiconductor region composed of the source region 130/channel region 120/drain region 140 in this order has N+ type/P-type/N+ type or P+ type/N-type/P+ type in the case of a junction structure. In the case of a non-junction structure, it may have an N+ type/N+ type/N+ type.

The interlayer insulating film 150 is disposed on the channel region 120 and between the gate region 160 and the channel region 120 when the synaptic weight of the ion-controlled transistor-based neuromorphic synaptic device 100 is updated or when the transistor is operating. It may be formed of at least one of silicon oxide (SiO2), germanium oxide (GeO2), a solid oxide layer (Oxide), or a low-k dielectric layer that can insulate.

The gate region 160 may be formed on the interlayer insulating layer 150 , and the solid electrolyte layer 170 may be inserted between the gate region 160 and the interlayer insulating layer 150 .

The solid electrolyte layer 170 is a sulfide-based material [Li10GeP2S12, Li9.54Si1.74P1.44S11.7Cl0.3, Argyrodite that has high ion conductivity and exists in a solid state so that ions are linearly and analogically distributed therein. , LPS (Lithium phosphorus sulfide), LPS + LiCl], oxide materials [Perovskite, NASICON (Na1+xZr2SixP3-xO12, 0<x<3), LISICON (Li2+2xZn1-xGeO4), LiPON (LixPOyNz), Garnet] or at least one of ion conductive polymers [PEO (Polyethylene oxide), PEG (Polyethylene glycol), PEGDMA (Polyethylene glycol dimethacrylate), PTFE (Polytetrafluoroethylene), PEEK (Polyether ether ketone), Nafion (C7HF13O5S C2F4)] can be

At this time, the solid electrolyte layer 170 may be used to change the channel conductivity (hereinafter, channel conductivity means the conductivity of the channel region 120) of the ion-controlled transistor-based neuromorphic synaptic device 100 . That is, in the ion-controlled transistor-based neuromorphic synaptic device 100 including the solid electrolyte layer 170 , a voltage greater than or equal to a threshold voltage is applied to the gate region 160 , and a specific voltage is applied to the drain region 140 . As this is applied, it may be driven according to the operating principle of a field effective transistor (FET) in which current flows through the channel region 120 . A detailed description thereof will be described with reference to FIGS. 2A to 2C below.

In addition, the ion-controlled transistor-based neuromorphic synaptic device 100, while positioned on the source region 130 and the drain region 140, silicon oxide (SiO2), germanium oxide (GeO2), a solid oxide film (Oxide) Alternatively, the sacrificial insulating layer 180 formed of at least one of a low-k dielectric layer may be further included.

Figure 2a is a graph measuring the drain current (I _D ) with respect to the gate voltage (V _G ) of the ion-controlled transistor-based neuromorphic synaptic device according to an embodiment, Figures 2b to 2c are ion-controlled according to an embodiment It is a diagram for explaining the channel conductivity update operation by ion movement in the solid electrolyte layer in the transistor-based neuromorphic synaptic device.

Referring to FIGS. 2A to 2C , the ion-controlled transistor-based neuromorphic synaptic device 100 can change the channel conductivity with charges caused by ion movement inside the solid electrolyte layer 170 inserted into the gate region 160 . Accordingly, as shown in the graph of FIG. 2A , the drain current I _D according to the gate voltage V _G may have a hysteresis curve (hysteresis) in a counterclockwise direction (①→②→③→④).

For example, when a positive voltage pulse is applied to the gate region 160 as shown in FIG. 2B , positive ions existing in the solid electrolyte layer 170 move closer to the channel region 120 or negative ions move to the gate region 160 . ) (or as positive ions move closer to the channel region 120 and negative ions move closer to the gate region 160 at the same time), the potential near the channel region 120 increases. Accordingly, inversion of the semiconductor channel may be facilitated, so that a threshold voltage may be reduced and channel conductivity may be increased.

For another example, when a negative voltage pulse is applied to the gate region 160 as shown in FIG. 2C , anions existing in the solid electrolyte region 170 move closer to the channel region 120 or positive ions move to the gate region ( 160) As it moves closer (or as negative ions move closer to the channel region 120 and positive ions move closer to the gate region 160 at the same time), the potential near the channel region 120 decreases. Accordingly, inversion of the semiconductor channel becomes difficult, so that a threshold voltage may increase and channel conductivity may decrease.

The channel conductivity, which is changed and updated by electric charge due to ion movement in the solid electrolyte layer 170 , may represent the synaptic weight of the ion-controlled transistor-based neuromorphic synaptic device 100 . That is, the ion-controlled transistor-based neuromorphic synaptic device 100 can express an increase (Potentiation) or a decrease (Depression) of the synaptic weight by updating the channel conductivity based on the ion movement in the solid electrolyte layer 170 . have.

For example, the ion-controlled transistor-based neuromorphic synaptic device 100 may increase or decrease the channel conductivity synaptic weight, as described in relation to FIGS. 2B and 2C above. As a more specific example, the ion-controlled transistor-based neuromorphic synaptic device 100 applies a positive voltage pulse to the gate region 160 as shown in FIG. 2b to remove positive ions present in the solid electrolyte layer 170 By moving the negative ions closer to the channel region 120 or moving the negative ions closer to the gate region 160 , the potential in the vicinity of the channel region 120 may be increased, thereby increasing the synaptic weight expressed as channel conductivity. As another specific example, the ion-controlled transistor-based neuromorphic synaptic device 100 applies a negative voltage pulse to the gate region 160 as shown in FIG. 2c to remove negative ions present in the solid electrolyte layer 170 . By moving closer to the channel region 120 or moving positive ions closer to the gate region 160 , the potential in the vicinity of the channel region 120 may be lowered, thereby reducing the synaptic weight expressed by channel conductivity.

As such, in the ion-controlled transistor-based neuromorphic synaptic device 100, a memory operation can be implemented by the movement of cations and anions present in the solid electrolyte layer 170, and channel conductivity changes due to ion movement are stored as synaptic weights. Synaptic device characteristics in neuromorphic computing operations can be implemented.

As described above, the ion-controlled transistor-based neuromorphic synaptic device 100 has been described as implementing a synaptic device characteristic that expresses a synaptic weight by a change in channel conductivity, but is not limited thereto and the voltage applied to the gate region 160 is not limited thereto. By controlling the width, frequency, or material of the channel region 120, the solid electrolyte layer 170, and the gate region 160 of the pulse, spike timing dependent plasticity (STDP), short term plasticity (STP) like a synapse of a real organism , LTP (Long term plasticity) characteristics can be implemented, so it can be used not only in deep neural networks but also in spiking neural networks.

In particular, the ion-controlled transistor-based neuromorphic synaptic device 100 may linearly and analogically update the synaptic weight, which is channel conductivity. A detailed description thereof will be described with reference to FIG. 3 below.

3 is a graph for explaining the weight strengthening characteristics and weight weakening characteristics of the solid electrolyte layer included in the ion-controlled transistor-based neuromorphic synaptic device according to an embodiment.

Referring to FIG. 3 , the ion-controlled transistor-based neuromorphic synaptic device 100 may have a large number of linear and analog synaptic weight stages throughout the synaptic weight strengthening and weakening stages as shown in the graph of the figure. This is due to the linear and analog distribution of ions inside the solid electrolyte layer 170, and the ion-controlled transistor-based neuromorphic synaptic device 100 uses the properties of the solid electrolyte layer 170 as described above. By doing so, in response to the voltage pulse being applied to the gate region 160, the channel conductivity is linearly and analogly updated by the movement of ions present in the solid electrolyte layer 170 to express the synaptic weight in a linear and analog manner. can

The above-described ion-controlled transistor-based neuromorphic synaptic device 100 is a stable device by utilizing the solid electrolyte layer 170 that analogically updates channel conductivity and synaptic weight by the movement of ions present therein. While securing properties, large-area processing and integration may be possible. The method of manufacturing such an ion-controlled transistor-based neuromorphic synapse device 100 is a gate-first process of forming the gate region 160 first or a gate-last process of forming the gate region 160 last. Any one of the (Gate-last) processes may be selectively used. The gate-first manufacturing method of the ion-controlled transistor-based neuromorphic synaptic device 100 using the gate-first process will be described with reference to FIGS. 4 and 5a to 5d, and the ion-controlled transistor-based neuromorphic synaptic device 100 using the gate-last process will be described. The gate-first manufacturing method of the lomorphic synaptic device 100 will be described with reference to FIGS. 6 and 7A to 7D .

In addition, the ion-controlled transistor-based neuromorphic synaptic device 100 described above is to be implemented with three terminals consisting of a terminal of the gate region 160 , a terminal of the source region 130 , and a terminal of the drain region 140 . can However, the ion-controlled transistor-based neuromorphic synapse device 100 is not limited thereto and is not limited thereto, and is composed of a body terminal together with a terminal of the gate region 160 , a terminal of the source region 130 , and a terminal of the drain region 140 . It may be implemented with 4 terminals.

In addition, the ion-controlled transistor-based neuromorphic synaptic device 100 described above is provided in plurality, thereby forming a single synaptic array. A detailed description thereof will be described with reference to FIG. 8 .

4 is a flowchart illustrating a gate-first manufacturing method of an ion-controlled transistor-based neuromorphic synaptic device according to an embodiment, and FIGS. 5A to 5D are gates of an ion-controlled transistor-based neuromorphic synaptic device according to an embodiment -XZ cross-sectional view for explaining the first manufacturing method. Hereinafter, the ion-controlled transistor-based neuromorphic synaptic device 100 that is manufactured through the gate-first manufacturing method of the ion-controlled transistor-based neuromorphic synaptic device 100 is the structure and characteristics described through FIGS. may have, and the subject performing the gate-first manufacturing method of the ion-controlled transistor-based neuromorphic synaptic device 100 may be an automated and mechanized manufacturing system.

Referring to FIGS. 4 to 5A to 5D , the manufacturing system sequentially forms the interlayer insulating film 150 , the solid electrolyte layer 170 , and the gate region 160 on the semiconductor substrate 110 as shown in FIG. 5A in step S410 . can be deposited with In particular, the manufacturing system uses sulfide-based materials [Li10GeP2S12, Li9.54Si1.74P1.44S11.7Cl0.3, Argyrodite, LPS (Lithium phosphorus sulfide), LPS + LiCl], oxide-based materials [Li10GeP2S12, Li9.54Si1.74P1.44S11.7Cl0.3, Perovskite, NASICON (Na1+xZr2SixP3-xO12, 0<x<3), LISICON (Li2+2xZn1-xGeO4), LiPON (LixPOyNz), Garnet] or an ionically conductive polymer [PEO (Polyethylene oxide), PEG (Polyethylene glycol), By forming the solid electrolyte layer 170 with at least one of PEGDMA (Polyethylene glycol dimethacrylate), PTFE (Polytetrafluoroethylene), PEEK (Polyether ether ketone), and Nafion (C7HF13O5S C2F4)], the manufactured ion-controlled transistor-based neuromo The pick synaptic device may linearly and analogically update the channel conductivity by using the characteristic of the solid electrolyte layer 170 in which ions are linearly and analogically distributed therein.

In this case, the channel region 120 may be formed in the upper region of the semiconductor substrate 100 .

Subsequently, in the manufacturing system, as shown in FIG. 5B in step S420 , the interlayer insulating film 150 , the solid electrolyte layer 170 , and the gate region 160 positioned on the channel region 120 formed on the semiconductor substrate 110 . ) of a portion 510 may be patterned. For example, in the manufacturing system, the interlayer insulating film 150 positioned above the channel region 120 , the solid electrolyte layer 170 , and a photoresistance (PR) 511 in a portion 510 of the gate region 160 . By disposing , patterning may be performed to leave a portion 510 of the interlayer insulating film 150 , the solid electrolyte layer 170 , and the gate region 160 positioned on the channel region 120 .

The PR 511 used in step S420 may be removed before step S430.

Then, in step S430 , as shown in FIGS. 5B to 5C , a part 520 of the semiconductor substrate 110 exposed as a result of patterning (a part 520 of the semiconductor substrate 110 is a channel region 120 ) The source region 130 and the drain region 140 may be formed on both sides of the . For example, the fabrication system may include impurity ion implantation, silicide alloy deposition including at least one of Al, W, Ti, Co, Ni, Er, or Pt, on a portion 520 of the semiconductor substrate 110 exposed as a result of patterning. Alternatively, the source region 130 and the drain region 140 may be formed through any one of deposition of at least one of Au, Al, Ag, Mg, Ca, Yb, Cs-ITO, Ti, Cr, or Ni. At this time, when the source region 130 and the drain region 140 are formed by silicide alloy deposition or metal deposition, inkjet printing, a printing process such as spraying, chemical vapor deposition, vacuum deposition, or One method of sputtering may be utilized.

Thereafter, the manufacturing system may deposit the sacrificial insulating layer 180 on the source region 130 and the drain region 140 as shown in FIG. 5D in operation S440 . Also, in step S440 , the manufacturing system may form a contact (not shown) through a back-end of line (BEOL).

6 is a flowchart illustrating a gate-last manufacturing method of an ion-controlled transistor-based neuromorphic synapse device according to an embodiment, and FIGS. 7a to 7d are gates of an ion-controlled transistor-based neuromorphic synaptic device according to an embodiment -XZ cross-sectional view for explaining the last manufacturing method. Hereinafter, the ion-controlled transistor-based neuromorphic synaptic device 100 that is manufactured through the gate-last manufacturing method of the ion-controlled transistor-based neuromorphic synaptic device 100 is the structure and characteristics described with reference to FIGS. 1 to 3 . may have, and the subject performing the gate-last manufacturing method of the ion-controlled transistor-based neuromorphic synaptic device 100 may be an automated and mechanized manufacturing system.

6 to 7A to 7D , the manufacturing system may form a source region 130 and a drain region 140 on the semiconductor substrate 110 in operation S610 as shown in FIG. 7A . In this case, the channel region 120 is formed on the semiconductor substrate 110 , and the dummy gate 190 may be positioned on the channel region 120 .

For example, in the manufacturing system, a silicide including at least one of Al, W, Ti, Co, Ni, Er, or Pt by implanting impurity ions into a region disposed on both sides of the channel region 120 on the semiconductor substrate 110 . The source region 130 and the drain region 140 may be formed through either alloy deposition or metal deposition of at least one of Au, Al, Ag, Mg, Ca, Yb, Cs-ITO, Ti, Cr, or Ni. have. At this time, when the source region 130 and the drain region 140 are formed by silicide alloy deposition or metal deposition, inkjet printing, a printing process such as spraying, chemical vapor deposition, vacuum deposition, or One method of sputtering may be utilized.

Subsequently, the manufacturing system may deposit the sacrificial insulating layer 180 on the semiconductor substrate 110 in operation S620 as shown in FIG. 7B .

Next, the manufacturing system may selectively remove the dummy gate 190 as shown in FIGS. 7B to 7C in operation S630 . For example, the manufacturing system may chemically polish and planarize the sacrificial insulating layer 180 until the dummy gate 190 is exposed, and then selectively remove only the dummy gate 1890 .

Thereafter, the manufacturing system forms an interlayer insulating film 150 , a solid electrolyte layer 170 , and a gate region 160 in the space 710 in which the dummy gate 190 is removed, as shown in FIGS. 7c to 7d in step S640 . can be formed In particular, the manufacturing system uses sulfide-based materials [Li10GeP2S12, Li9.54Si1.74P1.44S11.7Cl0.3, Argyrodite, LPS (Lithium phosphorus sulfide), LPS + LiCl], oxide-based materials [Li10GeP2S12, Li9.54Si1.74P1.44S11.7Cl0.3, Perovskite, NASICON (Na1+xZr2SixP3-xO12, 0<x<3), LISICON (Li2+2xZn1-xGeO4), LiPON (LixPOyNz), Garnet] or an ionically conductive polymer [PEO (Polyethylene oxide), PEG (Polyethylene glycol), By forming the solid electrolyte layer 170 with at least one of PEGDMA (Polyethylene glycol dimethacrylate), PTFE (Polytetrafluoroethylene), PEEK (Polyether ether ketone), and Nafion (C7HF13O5S C2F4)], the manufactured ion-controlled transistor-based neuromo The pick synaptic device may linearly and analogically update the channel conductivity by using the characteristic of the solid electrolyte layer 170 in which ions are linearly and analogically distributed therein.

Also, in step S640 , the manufacturing system may form a contact (not shown) through a back-end of line (BEOL).

8 is a diagram illustrating a synaptic array composed of an ion-controlled transistor-based neuromorphic synaptic device according to an embodiment.

Referring to FIG. 8 , the synapse array 800 may be implemented with a plurality of ion-controlled transistor-based neuromorphic synaptic devices 100 described with reference to FIGS. 1 to 3 , as shown in FIG. 8 . Accordingly, the synapse array 800 may be composed of a plurality of ion-controlled transistor-based neuromorphic synaptic elements, and each of the plurality of ion-controlled transistor-based neuromorphic synaptic elements 100 is a semiconductor substrate as described above. A channel region 120 formed on (110). The source region 130 and the drain region 140 formed on both sides of the channel region 120 , the interlayer insulating layer 150 disposed on the channel region 120 , and the gate region formed on the interlayer insulating layer 150 . 160 and a solid electrolyte layer 170 interposed between the interlayer insulating film 150 and the gate region 160 may be included.

Since the synapse array 800 has a structure in which the terminal of the gate region 160 and the terminal of the drain region 140 are separated in each of the plurality of ion-controlled transistor-based neuromorphic synaptic devices 100 , the gate region A parallel operation of updating the synaptic weight through the terminal 160 and reading the synaptic weight through the terminal of the drain region 140 may be supported.

As described above, although the embodiments have been described with reference to the limited embodiments and drawings, various modifications and variations are possible from the above description by those skilled in the art. For example, the described techniques are performed in an order different from the described method, and/or the described components of the system, structure, apparatus, circuit, etc. are combined or combined in a different form than the described method, or other components Or substituted or substituted by equivalents may achieve an appropriate result.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

110: semiconductor substrate
120: channel area
130: source area
140: drain region
150: interlayer insulating film
160: gate area
170: solid electrolyte layer
180: sacrificial insulating film
190: dummy gate

Claims (16)

a channel region formed on a semiconductor substrate;
a source region and a drain region formed on both sides of the channel region;
an interlayer insulating film disposed on the channel region;
a gate region formed on the interlayer insulating layer; and
A solid electrolyte layer interposed between the interlayer insulating film and the gate region
An ion-controlled transistor-based neuromorphic synaptic device comprising a. According to claim 1,
The ion-controlled transistor-based neuromorphic synaptic device,
An ion-controlled transistor-based neuromorphic synaptic device, characterized in that in response to the voltage pulse being applied to the gate region, the channel conductivity is analogically updated by the movement of ions present in the solid electrolyte layer. 3. The method of claim 2,
The ion-controlled transistor-based neuromorphic synaptic device,
Ion control transistor, characterized in that by using the characteristic of the solid electrolyte layer in which ions are linearly and analogically distributed therein, channel conductivity is updated analogically by the movement of ions present in the solid electrolyte layer based neuromorphic synaptic devices. 3. The method of claim 2,
The ion-controlled transistor-based neuromorphic synaptic device,
Ion-controlled transistor-based neuromorphic synaptic device, characterized in that by analogically updating the channel conductivity, synaptic weights are expressed analogously. According to claim 1,
The solid electrolyte layer,
Sulfide-based materials with high ionic conductivity [Li10GeP2S12, Li9.54Si1.74P1.44S11.7Cl0.3, Argyrodite, LPS (Lithium phosphorus sulfide), LPS + LiCl], oxide-based materials [Perovskite, NASICON (Na1) +xZr2SixP3-xO12, 0<x<3), LISICON (Li2+2xZn1-xGeO4), LiPON (LixPOyNz), Garnet] or ion conductive polymer [PEO (Polyethylene oxide), PEG (Polyethylene glycol), PEGDMA (Polyethylene glycol dimethacrylate) ), PTFE (Polytetrafluoroethylene), PEEK (Polyether ether ketone), Nafion (C7HF13O5S · C2F4)] ion control transistor-based neuromorphic synaptic device comprising at least one material. According to claim 1,
The channel region, the source region, and the drain region,
An ion-controlled transistor-based neuromorphic synaptic device, characterized in that it forms a semiconductor region having a structure formed in a horizontal or vertical direction. According to claim 1,
The channel region is
Silicon (Si), germanium (Ge, SiGe), group III-V compound, or 2-D material (Carbon nanotube, MoS2, graphene, etc.) characterized in that it contains at least one semiconductor material Lomorphic synaptic element. According to claim 1,
The source region and the drain region are
It is formed in a form in which impurity ions are implanted into the semiconductor material forming the channel region, or formed of a silicide alloy containing at least one of Al, W, Ti, Co, Ni, Er, or Pt, or Au, Al, Ag, Mg, Ca, Yb, Cs-ITO, Ti, Cr or Ni, characterized in that formed of at least one metal ion-controlled transistor-based neuromorphic synaptic device. According to claim 1,
The interlayer insulating film,
Silicon oxide (SiO2), germanium oxide (GeO2), a solid oxide film (Oxide) or An ion-controlled transistor-based neuromorphic synaptic device comprising at least one material of a dielectric layer having a low dielectric constant (Low-k). According to claim 1,
A sacrificial insulating layer disposed on the source region and the drain region and formed of at least one of silicon oxide (SiO2), germanium oxide (GeO2), a solid oxide layer, or a low dielectric constant dielectric layer.
An ion-controlled transistor-based neuromorphic synaptic device further comprising a. According to claim 1,
The ion-controlled transistor-based neuromorphic synaptic device,
3 terminals composed of a terminal in the gate region, a terminal in the source region, and a terminal in the drain region, or 4 terminals consisting of a body terminal together with a terminal in the gate region, a terminal in the source region, and the drain region Ion control transistor-based neuromorphic synaptic device, characterized in that. depositing an interlayer insulating film, a solid electrolyte layer, and a gate region on a semiconductor substrate;
patterning a portion of the interlayer insulating film, the solid electrolyte layer, and the gate region positioned on the channel region formed on the semiconductor substrate;
forming a source region and a drain region on a portion of the semiconductor substrate exposed as a result of the patterning, wherein a portion of the semiconductor substrate is located on both sides of the channel region; and
depositing a sacrificial insulating layer on the source region and the drain region;
A gate-first manufacturing method of an ion-controlled transistor-based neuromorphic synaptic device comprising a. forming a source region and a drain region on a semiconductor substrate, wherein a dummy gate is positioned over a channel region formed on the semiconductor substrate;
depositing a sacrificial insulating layer on the semiconductor substrate;
selectively removing the dummy gate; and
Forming an interlayer insulating film, a solid electrolyte layer, and a gate region in the space where the dummy gate is removed
A gate-last manufacturing method of an ion-controlled transistor-based neuromorphic synaptic device comprising a. In the synapse array consisting of a plurality of ion-controlled transistor-based neuromorphic synaptic elements,
Each of the plurality of ion-controlled transistor-based neuromorphic synaptic devices,
a channel region formed on a semiconductor substrate;
a source region and a drain region formed on both sides of the channel region;
an interlayer insulating film disposed on the channel region;
a gate region formed on the interlayer insulating layer; and
A solid electrolyte layer interposed between the interlayer insulating film and the gate region
A synaptic array comprising a. 14. The method of claim 13,
The synaptic array is
In each of the plurality of ion-controlled transistor-based neuromorphic synaptic devices, the parallel operation of updating the synaptic weight through the terminal of the gate region and reading the updated synaptic weight through the terminal of the drain region is supported. Synaptic array characterized. a channel region formed on a semiconductor substrate;
a source region and a drain region formed on both sides of the channel region;
an interlayer insulating film disposed on the channel region;
a gate region formed on the interlayer insulating layer; and
Based on the linear and analog distribution of ions inside the interlayer insulating film and the gate region, in response to a voltage pulse being applied to the gate region, the movement of the ions present therein A solid electrolyte layer that analogically renews channel conductivity by
including,
Ion-controlled transistor-based neuromorphic synaptic device, characterized in that by analogically updating the channel conductivity, synaptic weights are expressed analogously.

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