KR20220012968A - Display panel - Google Patents

Abstract

The present invention is to prevent a decrease in a gate-on voltage level output from a gate driving unit embedded in a display panel or problems caused by a current leakage. A display panel according to an embodiment includes a display area including a plurality of gate lines and a plurality of data lines, and a gate driver including a plurality of stages connected to one end of the plurality of gate lines to generate and transmit gate voltages, respectively. One of the plurality of stages includes a first transistor, a third transistor, an eleventh transistor, a fifteenth transistor, and a first capacitor, wherein the first transistor includes an input terminal receiving a clock signal, a control terminal electrically connected to a Q contact, and an output terminal electrically connected to a gate voltage output terminal for outputting the gate voltages; the fifteenth transistor includes an input terminal receiving a clock signal, a control terminal electrically connected to the Q contact, and an output terminal electrically connected to a transmission signal output terminal to output a transmission signal; the third transistor lowers the voltage of the output terminal of the first transistor to a first low voltage by an inverter signal; the eleventh transistor lowers the voltage of the transmission signal to a third low voltage by the inverter terminal; the inverter signal has a second low voltage; and the first low voltage, the second low voltage, and the third low voltage have voltage values different from each other.

Description

display panel {DISPLAY PANEL}

The present invention relates to a display panel, and to a display panel having a gate driver integrated in the display panel.

Among display panels, a liquid crystal display panel is one of the most widely used flat panel display panels at present, and includes two display panels on which field generating electrodes such as a pixel electrode and a common electrode are formed and a liquid crystal layer interposed therebetween. do. A liquid crystal display panel displays an image by applying a voltage to an electric field generating electrode to generate an electric field in the liquid crystal layer, thereby determining the direction of liquid crystal molecules in the liquid crystal layer and controlling the polarization of incident light. In addition to the liquid crystal display panel, the display panel includes an organic light emitting display panel, a plasma display panel, an electrophoretic display panel, and the like.

The display panel includes a gate driver and a data driver. Among them, the gate driver may be patterned together with a gate line, a data line, a thin film transistor, and the like and integrated on the panel. As such, the integrated gate driver does not need to form a separate gate driver chip, so manufacturing cost is reduced.

However, in the thin film transistor formed inside the integrated gate driver as described above, a leakage current of a certain level is generated while outputting the gate signal, so that the output is lowered and the level of the gate voltage is lowered.

An object of the present invention is to prevent the level of a gate-on voltage output from a gate driver mounted on a display panel from being lowered or a problem from occurring due to leakage current.

In order to solve the above problems, a display panel according to an embodiment of the present invention includes a display area including a plurality of gate lines and a plurality of data lines, and a gate driver connected to one end of the plurality of gate lines and including a plurality of stages. wherein one stage of the plurality of stages applies a transfer signal generator for outputting a transfer signal to a transfer signal output terminal connected to the first input terminal of the next stage, and a gate voltage to a gate voltage output terminal connected to a gate line. It includes an output unit for outputting, and an inverter unit for outputting an inverter signal to an inverter signal output terminal connected to a fourth input terminal of the next stage.

The transfer signal output terminal may be connected to a second input terminal of the previous stage.

The transfer signal output terminal may be connected to a third input terminal of the previous stage.

The output unit includes a first transistor and a first capacitor, and the first transistor is connected to an input terminal to which a clock signal is applied, a control terminal connected to a Q contact, and a gate voltage output terminal to generate a first low-voltage gate voltage. an output terminal for outputting, wherein the inverter unit outputs a voltage of a second low voltage, the transmission signal generator generates the transmission signal at a third low voltage, and the second low voltage generates a voltage level lower than the first voltage. and the third low voltage may have a lower voltage level than the second low voltage.

The stage may further include a Q-contact stabilizing unit, and the Vgs voltage of the transistor included in the Q-contact stabilizing unit may have a value of 0V or less when the output unit outputs a gate-on voltage.

The Q contact stabilizer includes an input terminal and a control terminal to which the transfer signal of the previous stage is applied through a first input terminal, a fourth transistor including an output terminal connected to the Q contact, and then through a third input terminal A sixth transistor including a control terminal to which the transfer signal of the stage is applied, an input terminal connected to the Q contact, and an output terminal to which the second low voltage is applied, the transfer signal of the next stage through the second input terminal A ninth transistor including a control terminal to be applied, an input terminal connected to the Q contact, and an output terminal to which the second low voltage is applied, and a control terminal connected to an I contact connected to the inverter signal output terminal, the Q It may include a tenth transistor including an input terminal connected to the contact point and an output terminal to which the second low voltage is applied.

The Q contact stabilizer includes an input terminal and a control terminal to which the transfer signal of the previous stage is applied through a first input terminal, a fourth transistor including an output terminal connected to the Q contact, and then through a third input terminal A sixth transistor including a control terminal to which the transfer signal of the stage is applied, an input terminal connected to the Q contact, and an output terminal to which the third low voltage is applied, the transfer signal of the next stage through the second input terminal A ninth transistor including a control terminal to be applied, an input terminal connected to the Q contact, an output terminal to which the third low voltage is applied, and a control terminal connected to an I contact connected to the inverter signal output terminal, the Q It may include a tenth transistor including an input terminal connected to the contact point and an output terminal to which the second low voltage is applied.

The Q contact stabilizer includes an input terminal and a control terminal to which the transfer signal of the previous stage is applied through a first input terminal, a fourth transistor including an output terminal connected to the Q contact, and then through a third input terminal A sixth transistor including a control terminal to which the transmission signal of the stage is applied, an input terminal connected to the Q contact, and an output terminal to which the second low voltage is applied, a control terminal to which the second low voltage is applied, and the Q contact a ninth transistor including an input terminal connected to, an output terminal to which the third low voltage is applied, and a control terminal connected to an I contact connected to the inverter signal output terminal, an input terminal connected to the Q contact; A tenth transistor including an output terminal to which the second low voltage is applied may be included.

The Q contact stabilizing unit connects an input terminal and a control terminal to which the transmission signal of the previous stage is applied through a first input terminal, a fourth transistor including an output terminal connected to the Q contact, an input terminal and an output terminal, and A pair of transistors having a control terminal connected to the same terminal, the control terminals all receiving the transfer signal of the next stage through a second input terminal, the input terminals of the pair of transistors are connected to the Q contact, The output terminal is a ninth transistor and a 9-1 th transistor to which the second low voltage is applied, and a pair of transistors connecting an input terminal and an output terminal to each other and having a control terminal connected to the same terminal, and the control terminals are all the inverter signals It is connected to the I contact connected to the output terminal, the input terminal of the pair of transistors is connected to the Q contact, and the output terminal may include a tenth transistor and a 10-1 th transistor to which the second low voltage is applied. have.

A fifth transistor including an input terminal connected to the I contact connected to the inverter signal output terminal, a control terminal to which the transmission signal of the previous stage is applied through the first input terminal, and an output terminal to which the second low voltage is applied. may include

The output unit may further include a pull-down unit including a second transistor and a third transistor for lowering the voltage of the output terminal of the first transistor to the first low voltage.

The pull-down unit further includes an eleventh transistor for lowering the voltage of the transfer signal to the third low voltage, wherein the eleventh transistor includes a control terminal connected to an I contact connected to the inverter signal output terminal, a control terminal connected to the transfer signal output terminal, and It may include a connected input terminal and an output terminal to which the third low voltage is applied.

The pull-down unit further includes a seventeenth transistor for lowering the voltage of the transfer signal to the third low voltage, wherein the seventeenth transistor includes a control terminal that receives a transfer signal of a next stage through a second input terminal, and outputs the transfer signal It may include an input terminal connected to the terminal and an output terminal to which the third low voltage is applied.

The pull-down unit further includes an 11-1 transistor for lowering the gate voltage to the first low voltage, wherein the 11-1 transistor is connected to a control terminal to which an inverter signal of the previous stage is applied and the gate voltage output terminal It may include an input terminal and an output terminal to which the first low voltage is applied.

The pull-down unit further includes an eleventh transistor for lowering the voltage of the transfer signal to the second low voltage, wherein the eleventh transistor includes a control terminal connected to an I contact connected to the inverter signal output terminal, a control terminal connected to the transfer signal output terminal; It may include a connected input terminal and an output terminal to which the second low voltage is applied.

The pull-down unit further includes an eleventh transistor for lowering the low voltage of the transfer signal to the first low voltage, wherein the eleventh transistor includes a control terminal connected to an I contact connected to the inverter signal output terminal, a control terminal connected to the transfer signal output terminal, and It may include a connected input terminal and an output terminal to which the first low voltage is applied.

The channel of the transistor includes an oxide semiconductor or an amorphous semiconductor, and when the voltage applied to the stage is -10V or more, the amorphous semiconductor or the oxide semiconductor is formed as a channel of the transistor, and the voltage applied to the stage is When the voltage is less than -10V, the oxide semiconductor may be formed as a channel of the transistor.

As described above, the output terminal of some of the transistors of the gate driver mounted on the display panel is connected to a lower voltage to reduce the voltage difference applied to the corresponding transistor, so that the level of the gate-on voltage output by the gate driver does not decrease or the leakage current is reduced. to avoid causing any problems.

1 is a plan view of a display panel according to an exemplary embodiment of the present invention.
FIG. 2 is a detailed block diagram illustrating a gate driver and a gate line of FIG. 1 .
3 is an enlarged circuit diagram illustrating one stage of a gate driver according to an embodiment of the present invention.
4 is a graph of current versus voltage in a transistor using an amorphous silicon semiconductor and a transistor using an oxide semiconductor.
5 is a diagram illustrating an area occupied by the gate driver when the gate driver according to the embodiment of the present invention is installed.
6 is an enlarged circuit diagram of one stage of the gate driver according to another embodiment of the present invention.
7 and 8 illustrate output characteristics of a gate driver according to an embodiment of the present invention.
9 to 17 are enlarged circuit diagrams of one stage of the gate driver according to another embodiment of the present invention.

With reference to the accompanying drawings, the embodiments of the present invention will be described in detail so that those of ordinary skill in the art to which the present invention pertains can easily implement them. However, the present invention may be embodied in several different forms and is not limited to the embodiments described herein.

In order to clearly express various layers and regions in the drawings, the thicknesses are enlarged. Throughout the specification, like reference numerals are assigned to similar parts. When a part, such as a layer, film, region, plate, etc., is “on” another part, it includes not only cases where it is “directly on” another part, but also cases where there is another part in between. Conversely, when we say that a part is "just above" another part, we mean that there is no other part in the middle.

A display panel according to an exemplary embodiment of the present invention will now be described in detail with reference to FIG. 1 .

1 is a plan view of a display panel according to an exemplary embodiment of the present invention.

Referring to FIG. 1 , a display panel 100 according to an exemplary embodiment includes a display area 300 for displaying an image, and a gate driver 500 for applying a gate voltage to a gate line of the display area 300 . include Meanwhile, the data line of the display area 300 receives a data voltage from the data driver IC 460 formed on a film such as a flexible printed circuit film (FPC) 450 attached to the display panel 100 . get approved Meanwhile, the gate driver 500 and the data driver IC 460 are controlled by the signal controller 600 . A printed circuit board (PCB) is formed on the outside of the film such as the flexible printed circuit film 450 to transmit a signal from the signal controller 600 to the data driver IC 460 and the gate driver 500 . . Signals provided from the signal controller 600 include signals such as the first clock signal CKV, the second clock signal CKVB, and the scan start signal STVP and low voltages Vss1, Vss2, and Vss3 of a specific level. Includes signals to provide. In an embodiment of the present invention, three or more low voltage levels may be provided as a low voltage, and an embodiment in which three low voltages are applied will be mainly described.

In the case of a liquid crystal display panel, the display area 300 includes a thin film transistor Trsw, a liquid crystal capacitor Clc, and a storage capacitor Cst. In FIG. 1 , a liquid crystal display panel is illustrated as an example. Meanwhile, in an organic light emitting display panel, a thin film transistor and an organic light emitting diode are included, and in other display panels, a thin film transistor or the like is included to form the display area 300 . Although the present invention is not limited to a liquid crystal display panel, for clarity purposes, a liquid crystal display panel will be exemplified below.

The display area 300 includes a plurality of gate lines G1-Gn and a plurality of data lines D1-Dm, and the plurality of gate lines G1-Gn and the plurality of data lines D1-Dm are insulated. has been intersected.

Each pixel PX includes a thin film transistor Trsw, a liquid crystal capacitor Clc, and a storage capacitor Cst. A control terminal of the thin film transistor Trsw is connected to one gate line, an input terminal of the thin film transistor Trsw is connected to one data line, and an output terminal of the thin film transistor Trsw is one side of the liquid crystal capacitor Clc. It is connected to one terminal of the terminal and the holding capacitor Cst. The other terminal of the liquid crystal capacitor Clc is connected to the common electrode, and the other terminal of the storage capacitor Cst receives the sustain voltage Vcst applied from the signal controller 600 . Various embodiments of the structure of the pixel PX of the liquid crystal display panel exist, and the present invention may also be applied to a pixel PX having an additional configuration from the basic structure of the pixel PX shown in FIG. 1 .

The plurality of data lines D1 - Dm receive a data voltage from the data driver IC 460 , and the plurality of gate lines G1 - Gn receive a gate voltage from the gate driver 500 .

The data driver IC 460 is formed on the upper or lower side of the display panel 100 and is connected to the data lines D1-Dm extending in the vertical direction. In the embodiment of FIG. 1 , the data driver IC 460 is displayed An embodiment positioned on the upper side of the panel 100 is shown.

The gate driver 500 includes a first low voltage Vss1 corresponding to the clock signals CKV and CKVB, a scan start signal STVP, and a gate-off voltage, a second low voltage Vss2 and a third low voltage Vss3 lower than the gate-off voltage. ) to generate gate voltages (a gate-on voltage and a gate-off voltage), and sequentially apply the gate-on voltage to the gate lines G1-Gn.

The clock signals CKV and CKVB, the scan start signal STVP, the first low voltage Vss1, the second low voltage Vss2, and the third low voltage Vss3 applied to the gate driver 500 are data as shown in FIG. 1 . The application may be applied to the gate driver 500 through the flexible printed circuit film 450 closest to the gate driver 500 among the flexible printed circuit films 450 in which the driver IC 460 is positioned. Such a signal is transmitted from the outside or the signal controller 600 to a film such as the flexible printed circuit film 450 through the printed circuit board 400 .

In the above, the overall structure of the display panel has been reviewed.

Hereinafter, the gate driver 500 and the gate lines G1-Gn related to the present invention will be mainly examined.

FIG. 2 is a detailed block diagram illustrating a gate driver and a gate line of FIG. 1 .

In FIG. 2 , the gate driver 500 is shown in detail in blocks.

In FIG. 2 , the display area 300 is represented by a resistance Rp and a capacitance Cp. The gate lines G1-Gn, the liquid crystal capacitor Clc, and the storage capacitor Cst each have a resistance value and a capacitance, and the sum of them is expressed as one resistance Rp and one capacitance Cp. That is, as shown in FIG. 2 , the gate line can be represented as having a resistance Rp and a capacitance Cp in terms of circuitry. These values are values of one gate line as a whole, and may have different values depending on the structure and characteristics of the display area 300 . The gate voltage output from the stage SR is transmitted to the gate line.

Hereinafter, the gate driver 500 will be described.

The gate driver 500 includes a plurality of stages SR1 , SR2 , SR3 , SR4 ... connected to each other subordinately. Each stage (SR1, SR2, SR3, SR4...) has four input terminals (IN1, IN2, IN3, IN4), one clock input terminal (CK), three voltage input terminals (Vin1, Vin2, Vin3), a gate and a gate voltage output terminal OUT for outputting a voltage, a transfer signal output terminal CRout, and an inverter signal output terminal IVTout.

First, the first input terminal IN1 is connected to the transfer signal output terminal CRout of the previous stage to receive the transfer signal CR of the previous stage. Since the previous stage does not exist in the first stage, the first input terminal IN1 ) to receive the scan start signal STVP.

The second input terminal IN2 is connected to the transfer signal output terminal CRout of the next stage to receive the transfer signal CR of the next stage. The third input terminal IN3 is connected to the transfer signal output terminal CRout of the next stage to receive the transfer signal CR of the next stage.

The stage SRn-1 (not shown) connected to the n-1th gate line Gn-1 and the stage SRn (not shown) connected to the nth gate line Gn are the next stage and the next stage. Two dummy stages may be formed to receive the transfer signal CR from the . The dummy stages SRn+1 and SRn+2 (not shown) are stages that generate and output a dummy gate voltage, unlike the other stages SR1 -SRn. That is, the gate voltage output from the other stages SR1 - SRn is transmitted through the gate line, and the data voltage is applied to the pixel to display an image. However, the dummy stages SRn+1 and SRn+2 may not be connected to the gate line, and are connected to the gate line of a dummy pixel (not shown) that does not display an image even though it is connected to the gate line to display an image. may not be used.

On the other hand, the fourth input terminal IN4 is connected to the inverter signal output terminal IVTout of the previous stage to receive the inverter signal IVT of the previous stage. It may be separately generated and input or may be transmitted by generating a signal having a timing suitable therewith in the dummy stages SRn+1 and SRn+2 (not shown). Here, in the 1H period to which the gate-on voltage is applied in the corresponding stage, a signal having a timing at which the low voltage Vss1, Vss2, or Vss3 is applied is also referred to as an output control signal OCS.

A clock signal is applied to the clock input terminal CK, the first clock signal CKV is applied to the clock input terminal CK of an odd-numbered stage among the plurality of stages, and the clock input terminal CK of an even-numbered stage is applied to the clock signal. The second clock signal CKVB is applied. The first clock signal CKV and the second clock signal CKVB are clock signals whose phases are opposite to each other.

A first low voltage Vss1 corresponding to the gate-off voltage is applied to the first voltage input terminal Vin1 , and a second low voltage Vss2 lower than the first low voltage Vss1 is applied to the second voltage input terminal Vin2 . and a third low voltage Vss3 lower than the second low voltage Vss2 is applied to the third voltage input terminal Vin3. Voltage values of the first low voltage Vss1 , the second low voltage Vss2 , and the third low voltage Vss3 may vary according to exemplary embodiments.

The operation of the gate driver 500 is as follows.

First, the first stage SR1 receives the first clock signal CKV provided from the outside through the clock input terminal CK, the scan start signal STVP through the first input terminal IN1, and first to The first to third low voltages Vss1, Vss2, and Vss3 are applied to the third voltage input terminals Vin1, Vin2, and Vin3, and the transmission signal CR provided from the second stage SR2 through the second input terminal IN2. ), the transfer signal CR provided from the third stage SR3 through the third input terminal IN3 and the output control signal through the fourth input terminal IN4 are inputted to the first gate line as the gate voltage output terminal The gate-on voltage is output through (OUT). In addition, the transfer signal output terminal CRout outputs the transfer signal CR and transfers it to the first input terminal IN1 of the second stage SR2 , and the inverter signal output terminal IVTout receives the inverter signal IVT It is transmitted to the fourth input terminal IN4 of the second stage SR2 .

The second stage SR2 receives the second clock signal CKVB provided from the outside through the clock input terminal CK and the transmitted signal CR of the first stage SR1 through the first input terminal IN1. , first to third voltage input terminals Vin1 , Vin2 , and Vin3 are provided with first to third low voltages Vss1 , Vss2 , and Vss3 from the third stage SR3 through the second input terminal IN2 . The transfer signal CR, the transfer signal CR provided from the fourth stage SR4 through the third input terminal IN3, and the transfer signal CR provided from the first stage SR1 through the fourth input terminal IN4 It receives the inverter signal IVT and outputs a gate-on voltage to the second gate line through the gate voltage output terminal OUT. In addition, the transfer signal output terminal CRout outputs the transfer signal CR and transmits it to the first input terminal IN1 of the third stage SR3 and the second input terminal IN2 of the first stage SR1, , the inverter signal output terminal IVTout transfers the inverter signal IVT to the fourth input terminal IN4 of the third stage SR3 .

Meanwhile, the third stage SR3 receives the first clock signal CKV provided from the outside through the clock input terminal CK, and receives the transmitted signal of the second stage SR2 through the first input terminal IN1 . (CR), the first to third low voltages (Vss1, Vss2, Vss3) to the first to third voltage input terminals (Vin1, Vin2, Vin3), and the fourth stage (SR4) through the second input terminal (IN2) The transfer signal CR provided from ), the transfer signal CR provided from the fifth stage SR5 through the third input terminal IN3, and the second stage CR through the fourth input terminal IN4 SR2) receives the input of the inverter signal IVT, and outputs the gate-on voltage to the third gate line through the gate voltage output terminal OUT. In addition, the transfer signal output terminal CRout outputs the transfer signal CR to the first input terminal IN1 of the fourth stage SR4 , the second input terminal IN2 of the second stage SR2 , and the first It is transmitted to the third input terminal IN3 of the stage SR1 , and the inverter signal IVT is transmitted from the inverter signal output terminal IVTout to the fourth input terminal IN4 of the fourth stage SR4 .

In the same manner as described above, the n-th stage SRn receives the second clock signal CKVB provided from the outside through the clock input terminal CK, and receives the n-th stage SRn through the first input terminal IN1 The transfer signal CR of the stage SR2 is applied to the first to third voltage input terminals Vin1, Vin2, and Vin3, and the first to third low voltages Vss1, Vss2, and Vss3 are applied to the second and third input terminals. The transfer signal CR provided from the n+1th stage SRn+1 (dummy stage) and the n+2th stage SRn+2 (dummy stage) through (IN2, IN3), respectively, and a fourth input terminal The inverter signal IVT provided from the n-1 th stage SRn-1 is received through IN4 and a gate-on voltage is output to the n-th gate line through the gate voltage output terminal OUT. In addition, the transfer signal output terminal CRout outputs the transfer signal CR to the first input terminal IN1 of the n+1th stage SRn+1 (dummy stage) and the n-1th stage SRn-1. of the second input terminal IN2 and the third input terminal IN3 of the n-2 th stage SRn-2, and the inverter signal output terminal IVTout transmits the inverter signal IVT to the n+1 th stage It is transferred to the fourth input terminal IN4 of (SRn+1; dummy stage).

The overall stage SR connection structure of the gate driver 500 has been described with reference to FIG. 2 . Hereinafter, the structure of the stage SR of the gate driver connected to one gate line will be described in more detail with reference to FIG. 3 .

3 is an enlarged circuit diagram illustrating one stage of a gate driver according to an embodiment of the present invention.

Each stage SR of the gate driver 500 according to the present embodiment includes an output unit 511 , an inverter unit 512 , a transmission signal generating unit 513 , a Q-contact stabilizing unit 514 , and an I-contact stabilizing unit ( 515 ) and a pull-down unit 516 .

First, the output unit 511 includes one transistor (first transistor Tr1) and one capacitor (first capacitor C1). The control terminal of the first transistor Tr1 is connected to the Q contact (hereinafter also referred to as the first contact), and the input terminal is the first clock signal CKV or the second clock signal CKVB through the clock input terminal CK. is input, a first capacitor C1 is formed between the control terminal and the output terminal, and the output terminal is connected to the gate voltage output terminal OUT. Also, the output terminal is connected to the pull-down unit 516 and is connected to the first voltage input terminal Vin1 through the pull-down unit 516 . As a result, the voltage value of the gate-off voltage has the first low voltage Vss1 value. The output unit 511 outputs a gate voltage according to the voltage at the Q contact and the first clock signal CKV. A voltage difference is generated between the control terminal and the output terminal of the first transistor Tr1 by the voltage of the Q contact, and after the voltage difference is stored in the first capacitor C1 and a high voltage is applied by the clock signal, the charged voltage is During boosting, a high voltage is output as the gate-on voltage.

The inverter unit 512 includes four transistors (a twelfth transistor Tr12 , a seventh transistor Tr7 , an eighth transistor Tr8 , and a thirteenth transistor Tr13 ). First, the twelfth transistor Tr12 is diode-connected, and one end (input terminal) to which the control terminal is connected is connected to the clock input terminal CK, and the other end (output terminal) is connected to the control terminal and the thirteenth transistor of the seventh transistor Tr7. It is connected to the input terminal of (Tr13). The seventh transistor Tr7 has a control terminal connected to an output terminal of the twelfth transistor Tr12, an input terminal connected to a clock input terminal CK, and an output terminal connected to an I contact (also referred to as an inverter contact or a second contact). ) is connected with The eighth transistor Tr8 has a control terminal connected to the transfer signal output terminal CRout of the present stage, an input terminal connected to an I contact, and an output terminal connected to a second voltage input terminal Vin2. The thirteenth transistor Tr13 has an input terminal connected to an output terminal of the twelfth transistor Tr12, a control terminal connected to a transfer signal output terminal CRout of the present stage, and an output terminal connected to a second voltage input terminal ( Vin2) is connected. When a high signal is applied as a clock signal through the above connection, it is transmitted to the input terminals of the eighth and thirteenth transistors Tr8 and Tr13 by the twelfth and seventh transistors Tr12 and Tr7, respectively, so that the I contact becomes high. It has a voltage, and when the transfer signal CR is output from the transfer signal output terminal CRout of the present stage, the transferred high signal lowers the voltage of the I contact to the second low voltage VSS2. As a result, the I contact of the inverter unit 512 has a voltage level opposite to that of the transfer signal CR and the gate-on voltage of the present stage.

The transfer signal generator 513 includes one transistor (the fifteenth transistor Tr15). The clock input terminal CK is connected to the input terminal of the fifteenth transistor Tr15 to receive the first clock signal CKV or the second clock signal CKVB, the control terminal is connected to the Q contact, and the output terminal is It is connected to the transmission signal output terminal CRout for outputting the transmission signal CR. Here, a capacitor (which may be a parasitic capacitor) may be formed between the control terminal and the output terminal. The output terminal of the fifteenth transistor Tr15 is connected to the transfer signal output terminal CRout as well as the eleventh transistor Tr11 and the seventeenth transistor Tr17 of the pull-down unit 516 to apply the third low voltage Vss3 receive As a result, the voltage value when the transmission signal CR is low has the third low voltage Vss3 value.

The Q contact stabilizer 514 includes four transistors (a fourth transistor Tr4 , a sixth transistor Tr6 , a ninth transistor Tr9 , and a tenth transistor Tr10 ). First, the input terminal and the control terminal of the fourth transistor Tr4 are commonly connected to the first input terminal IN1 (diode connection), and the output terminal is connected to the Q contact. When a high voltage is applied to the first input terminal IN1 , the fourth transistor Tr4 transfers it to the Q contact. The sixth transistor Tr6 has a control terminal connected to the third input terminal IN3 , an input terminal connected to the Q contact, and an output terminal connected to the second voltage input terminal Vin2 . The sixth transistor Tr6 causes the voltage of the Q contact to become the second low voltage Vss2 when the transfer signal CR of the next stage is applied with a high value. The ninth transistor Tr9 has a control terminal connected to the second input terminal IN2 , an input terminal connected to the Q contact, and an output terminal connected to the second voltage input terminal Vin2 . As a result, when the transfer signal CR of the next stage is applied with a high value, the voltage of the Q contact becomes the second low voltage Vss2. The tenth transistor Tr10 has a control terminal connected to an I contact, an input terminal connected to a Q contact, and an output terminal connected to a second voltage input terminal Vin2. The tenth transistor Tr10 changes the voltage of the Q contact to the second low voltage Vss2 by the high output of the inverter unit 512 . As described above, the voltage at the Q contact is stabilized in each section by the fourth transistor Tr4 , the sixth transistor Tr6 , the ninth transistor Tr9 and the tenth transistor Tr10 connected to the Q contact.

The I-contact stabilizer 515 includes one transistor (the fifth transistor Tr5). The input terminal of the fifth transistor Tr5 is connected to the I contact, the control terminal is connected to the first input terminal IN1, and the output terminal is connected to the second voltage input terminal Vin2. When a high voltage is applied to the first input terminal IN1 , the fifth transistor Tr5 lowers the voltage of the I-junction to the second low voltage Vss2 .

The pull-down unit 516 includes five transistors (a second transistor Tr2 , a third transistor Tr3 , an eleventh transistor Tr11 ) connected to the output terminals of the output unit 511 and the transfer signal generation unit 513 ; an 11-1th transistor Tr11-1 and a 17th transistor Tr17). The second transistor Tr2 has a control terminal connected to a second input terminal IN2 , an input terminal connected to a gate voltage output terminal OUT, and an output terminal connected to a first voltage input terminal Vin1 . has been The second transistor Tr2 changes the voltage of the gate voltage output terminal OUT to the first low voltage Vss1 according to the next stage transfer signal CR. The third transistor Tr3 has a control terminal connected to the I contact, an input terminal connected to the gate voltage output terminal OUT, and an output terminal connected to the first voltage input terminal Vin1 . The third transistor Tr3 changes the voltage of the gate voltage output terminal OUT to the first low voltage Vss1 according to the voltage of the I junction. The eleventh transistor Tr11 has a control terminal connected to the I contact, an input terminal connected to the transfer signal output terminal CRout, and an output terminal connected to a third voltage input terminal Vin3 . That is, the eleventh transistor Tr11 changes the voltage of the transfer signal output terminal CRout to the third low voltage Vss3 according to the voltage of the I contact. The 11-1 th transistor Tr11-1 has a control terminal connected to a fourth input terminal IN4, an input terminal connected to a gate voltage output terminal OUT, and an output terminal connected to a first voltage input terminal IN4. Vin1) is connected. The 11-1 th transistor Tr11-1 causes the gate voltage to become the first low voltage Vss1 when the inverter output signal of the previous stage is applied with a high value. The seventeenth transistor Tr17 has a control terminal connected to a second input terminal IN2 , an input terminal connected to a transfer signal output terminal CRout, and an output terminal connected to a third voltage input terminal Vin3 . has been The seventeenth transistor Tr17 changes the voltage of the transfer signal output terminal CRout to the third low voltage Vss3 according to the transfer signal of the next stage.

The three low voltage values, the clock signal voltage value, the gate voltage value, and the voltage value of the transfer signal may vary. In this embodiment, the first low voltage Vss1 is -7V, the second low voltage Vss2 is -11V, and the second low voltage Vss2 is -11V. 3 The low voltage (Vss3) has -15V, and the voltage value of the clock signal swings between 15V and -15V. The gate-on voltage value has a different voltage value according to the characteristics of the output unit 511 , and the gate-off voltage value has a first low voltage Vss1 value. The high voltage value of the transmission signal has a different voltage value according to the characteristics of the transmission signal generator 513 , and the low voltage value has a third low voltage Vss3 value.

The operation of the stage according to this structure will be described as follows.

In one stage SR, the transfer signal generator 513 and the output unit 511 operate according to the voltage at the Q contact to output the high voltage and the gate-on voltage of the transfer signal CR. On the other hand, the transfer signal CR is lowered from the high voltage to the third low voltage Vss3 by the output of the inverter unit 512 of this stage and the transfer signal CR of the next stage, and the gate-on voltage is the inverter unit ( 512), the next stage and the transfer signal CR of the next stage are lowered from the high voltage to the first low voltage Vss1 to become the gate-off voltage.

At this time, the Q contact stabilizing unit 514 and I contact stabilizing unit 515 serves to stabilize the voltage of the Q contact and the I contact, which is the basis of the operation in which the gate voltage and the transfer signal CR are periodically changed.

The Vgs voltage, which is the voltage difference between the source side and the gate side of each transistor of the Q contact stabilization unit 514, is as follows when the gate-on voltage is output.

Vgs of the fourth transistor Tr4 is 0V, Vgs of the sixth transistor Tr6 is -4V, Vgs of the ninth transistor Tr9 is -4V, and Vgs of the tenth transistor Tr10 is 0V.

Here, although the Vgs voltage is changed, when the gate-on voltage is output from the corresponding stage, it is formed to have a value of 0 or less to generate the gate-on voltage. As a result, the voltage of the Q contact is stabilized and the leakage current does not increase, so that the voltage of the Q contact can be kept constant.

In addition, the Vgs value of the eighth transistor Tr8 connected to the output terminal of the inverter unit 512 is -4V.

The transistors included in each stage are formed together through the same process as the thin film transistors Trsw formed in the plurality of pixels of the display area 300 . In this case, an oxide semiconductor such as amorphous silicon or IGZO may be used as a semiconductor material for forming the thin film transistor Trsw and the channel layer of the transistor of each stage. However, since the two semiconductor materials have different characteristics, there is a case where only one of the two semiconductors needs to be used. In the embodiment of FIG. 3 , an oxide semiconductor such as IGZO may be used, but amorphous silicon cannot be used.

The reason is that, as shown in FIG. 4 , the characteristics of amorphous silicon and oxide semiconductor are different.

4 is a graph of current versus voltage in a transistor using an amorphous silicon semiconductor and a transistor using an oxide semiconductor.

Here, the left graph (ASG; amorphous silicon gate) is the case of amorphous silicon, the right graph (OSG; oxide semiconductor gate) is the case of using IGZO as an oxide semiconductor, the horizontal axis is Vgs, and the vertical axis is the current flowing through the channel represents a value.

In the case of a transistor using amorphous silicon (ASG), as shown in the left graph of FIG. 4 , when the voltage Vgs is lowered, the current increases again. Accordingly, a transistor using amorphous silicon cannot have a Vgs voltage below a certain level. As a result, when a voltage lower than -10V is applied to the voltage applied to each stage, the driving characteristics of the stage may be deteriorated, so that amorphous silicon may not be used. In this case, an oxide semiconductor such as IGZO is used.

Also in the embodiment of FIG. 3 , the third low voltage of -15V and the clock signal are used, so it is suitable for the oxide semiconductor to be used for the channel layer.

In the embodiment of FIG. 3 , the lower of the voltage value of the third low voltage and the voltage value of the clock signal are both equal to -15V. This is to reduce the number of voltage values generated by the display panel to form a simpler driving voltage generator. Depending on the embodiment, it may have various voltage values.

When the oxide semiconductor is used as shown in FIG. 3 , the area occupied by the integrated gate driver as shown in FIG. 5 can be significantly reduced.

5 is a diagram illustrating an area occupied by the gate driver when the gate driver according to the embodiment of the present invention is installed.

As shown in FIG. 5 , about 2 mm is formed of the light blocking member BM positioned outside the display area 300 , and the gate driver OSG using an oxide semiconductor can be formed to a width of 0.65 mm. Since the width of the light blocking member BM can be further reduced, a slim bezel can be formed.

Hereinafter, a case having the same structure as that of FIG. 3 but having different levels of applied voltage will be described with reference to FIG. 6 .

6 is an enlarged circuit diagram illustrating one stage of a gate driver according to another embodiment of the present invention.

In the embodiment of FIG. 6 , unlike FIG. 3 , the first low voltage Vss1 has -9V, the second low voltage Vss2 has -12V, and the third low voltage Vss3 has -15V. The voltage values of the clock signal have 15V and -15V as in the embodiment of FIG. 3 .

Such a voltage change changes the gate-off voltage and the low voltage of the transfer signal CR, but only decreases the voltage in the display panel and does not change during driving. However, a voltage change occurs at the output of the Q contact stabilization unit 514 and the inverter unit 512 as follows.

The Vgs voltage, which is the voltage difference between the source side and the gate side of each transistor of the Q contact stabilization unit 514, is as follows when the gate-on voltage is output.

Vgs of the fourth transistor Tr4 is 0V, Vgs of the sixth transistor Tr6 is -3V, Vgs of the ninth transistor Tr9 is -3V, and Vgs of the tenth transistor Tr10 is 0V.

Here, although the Vgs voltage is changed, when the gate-on voltage is output from the corresponding stage, it is formed to have a value of 0 or less to generate the gate-on voltage. As a result, the voltage of the Q contact is stabilized and the leakage current does not increase, so that the voltage of the Q contact can be kept constant.

Meanwhile, the Vgs value of the eighth transistor Tr8 connected to the output terminal of the inverter unit 512 is -3V.

Since the voltage of -15V is applied also in the embodiment of FIG. 6, an oxide semiconductor such as IGZO is suitable to be used, and is also suitable for a slim bezel as shown in FIG. 5 .

High-temperature reliability based on changes in the gate voltage and the voltage of the Q contact according to the embodiment of FIG. 3 and the embodiment of FIG. 6 will be reviewed with reference to FIGS. 7 and 8 .

7 and 8 illustrate output characteristics of a gate driver according to an embodiment of the present invention.

In FIG. 7 , the gate voltage and the voltage at the point Q are plotted over time, and a comparative example is shown together with the example of FIG. 3 and the example of FIG. 6 .

The comparative example has a structure in which there is no third low voltage Vss3 and is connected to the second low voltage Vss2 instead of the third low voltage Vss3.

In addition, in Fig. 7(a), the channel length of the transistor is 7 µm, and in Fig. 7(b), the channel length is 3 µm.

Referring to FIGS. 7A and 7B , it can be seen that the example of FIG. 3 , the example of FIG. 6 , and the comparative example all provide similar gate voltages. However, it can be seen that the comparative example has a large drop in the voltage of the Q contact.

When the voltage of the Q contact is not maintained and dropped, the gate voltage may be generated without a problem in the operation at room temperature as shown in FIG. 7 , but a problem may occur at a high or low temperature. This is shown in FIG. 8 .

In FIG. 8, the high temperature characteristics of the Example of FIG. 3, the Example of FIG. 6, and the comparative example are shown.

As shown in FIG. 8, typical characteristics (typical characteristics) have a value higher than the determination criterion (80%) in the example of FIG. 3, the example of FIG. 6, and the comparative example, so there is no problem in operation at room temperature can confirm.

However, when the threshold voltage (Vth) has a voltage value of -2V by operating at a high temperature, it can be confirmed that the comparative example is lower than the determination criterion (80%), so that a defect at high temperature is highly likely. In addition, as evaluated in FIG. 8 , the comparative example is higher than the criterion for long-term reliability, and thus the long-term reliability is good, and it can be seen that the comparative example can also be used except in an environment in which a high temperature state is maintained for a long time.

An example in which only two low voltages are applied like a comparative example will be described later with reference to FIGS. 14 and 15 .

On the other hand, operation characteristics may be a problem even at a low temperature. In the case of a low temperature, a separate additional circuit may be formed to compensate for the low temperature characteristics so that there is no problem in operation. Therefore, the characteristics at low temperature can be compensated with a compensation circuit, so there is no major problem, so it was not evaluated separately.

Hereinafter, various modified embodiments of the present invention will be described with reference to FIGS. 9 to 17 .

9 to 17 are enlarged circuit diagrams of one stage of the gate driver according to another embodiment of the present invention.

First, the embodiment of FIG. 9 will be described.

The embodiment of FIG. 9 has the same structure as the embodiment of FIGS. 3 and 6 . However, the voltage value of the low voltage and the voltage value of the clock signal are different.

In the embodiment of FIG. 9 , unlike FIG. 3 , the first low voltage Vss1 has -6V, the second low voltage Vss2 has -8V, and the third low voltage Vss3 has -10V. The voltage values of the clock signal have 20V and -10V.

The Vgs voltage, which is the voltage difference between the source side and the gate side of each transistor of the Q contact stabilization unit 514, is as follows when the gate-on voltage is output.

Vgs of the fourth transistor Tr4 is 0V, Vgs of the sixth transistor Tr6 is -2V, Vgs of the ninth transistor Tr9 is -2V, and Vgs of the tenth transistor Tr10 is 0V.

Here, although the Vgs voltage is changed, when the gate-on voltage is output from the corresponding stage, it is formed to have a value of 0 or less to generate the gate-on voltage. As a result, the voltage of the Q contact is stabilized and the leakage current does not increase, so that the voltage of the Q contact can be kept constant.

Meanwhile, the Vgs value of the eighth transistor Tr8 connected to the output terminal of the inverter unit 512 is -2V.

In the embodiment of FIG. 9 , since -10V is applied as the lowest voltage, amorphous silicon as well as an oxide semiconductor can be used as the channel of the transistor.

Meanwhile, although the embodiment of FIG. 10 has the same structure as FIGS. 3, 6, and 9 structurally, the applied voltage value is different from these.

The embodiment of FIG. 10 has the same three low voltage values as in FIG. 3 . That is, the first low voltage Vss1 has -7V, the second low voltage Vss2 has -11V, and the third low voltage Vss3 has -15V. However, the voltage value of the clock signal is different from that of FIG. 3 . That is, the voltage values of the clock signal have 15V and -11V. The embodiment of FIG. 10 is an embodiment showing that the voltage values of three low voltages and the low voltage values of the clock signal may be different from each other.

The Vgs voltage, which is the voltage difference between the source side and the gate side of each transistor of the Q contact stabilization unit 514, is as follows when the gate-on voltage is output.

Vgs of the fourth transistor Tr4 is 0V, Vgs of the sixth transistor Tr6 is 0V, Vgs of the ninth transistor Tr9 is 0V, and Vgs of the tenth transistor Tr10 is 0V.

Here, the Vgs voltage varies, but when the gate-on voltage is output from the corresponding stage, it is formed to have a value of 0 or less to generate the gate-on voltage. As a result, the voltage of the Q contact is stabilized and the leakage current does not increase, making it possible to keep the voltage at the Q contact constant.

Meanwhile, the Vgs value of the eighth transistor Tr8 connected to the output terminal of the inverter unit 512 is -4V.

In the embodiment of FIG. 10 , since -15V is applied as the third low voltage Vss3 as the lowest voltage, it is suitable to use an oxide semiconductor as a channel of the transistor.

Meanwhile, the embodiment of FIG. 11 is an embodiment having a structural difference from the embodiment of FIG. 3 .

In the embodiment of FIG. 11 , the output terminal of the eleventh transistor Tr11 of the pull-down unit 516 is connected to the second voltage input terminal Vin2. That is, the eleventh transistor Tr11 changes the voltage of the transfer signal output terminal CRout to the second low voltage Vss2 according to the voltage of the I junction. Since the transfer signal CR is not a signal that is actually applied to the pixel, even if the level of the low voltage is changed, the pixel has no effect on displaying an image.

Meanwhile, the voltage values applied in the embodiment of FIG. 11 are as follows.

11, the first low voltage Vss1 has -7V, the second low voltage Vss2 has -11V, and the third low voltage Vss3 has -15V like the embodiment of FIG. The voltage values of the clock signal also have 15V and -15V as shown in FIG. 3 .

The Vgs voltage, which is the voltage difference between the source side and the gate side of each transistor of the Q contact stabilization unit 514, is as follows when the gate-on voltage is output.

Vgs of the fourth transistor Tr4 is 0V, Vgs of the sixth transistor Tr6 is -4V, Vgs of the ninth transistor Tr9 is -4V, and Vgs of the tenth transistor Tr10 is -4V.

Here, although the Vgs voltage is changed, when the gate-on voltage is output from the corresponding stage, it is formed to have a value of 0 or less to generate the gate-on voltage.

Meanwhile, the Vgs value of the eighth transistor Tr8 connected to the output terminal of the inverter unit 512 is 0V.

In the embodiment of FIG. 11 , since -15V is applied as the lowest voltage, it is suitable to use an oxide semiconductor as a channel of the transistor.

The embodiment of FIG. 12 is also structurally different from the embodiment of FIG. 3 .

In the embodiment of FIG. 12 , the output terminals of the sixth transistor Tr6 and the ninth transistor Tr9 of the Q-contact stabilizer 514 are connected to the third low voltage Vss3. That is, the sixth transistor Tr6 of the Q contact stabilizing unit 514 has a control terminal connected to the third input terminal IN3, an input terminal connected to the Q contact, and an output terminal connected to the third voltage input terminal. (Vin3) is connected. The sixth transistor Tr6 causes the voltage of the Q contact to become the third low voltage Vss3 when the transfer signal CR of the next stage is applied with a high value. In addition, the ninth transistor Tr9 of the Q contact stabilizing unit 514 has a control terminal connected to the second input terminal IN2, an input terminal connected to the Q contact, and an output terminal connected to the third voltage input terminal. (Vin3) is connected. As a result, when the transfer signal CR of the next stage is applied with a high value, the voltage of the Q contact becomes the third low voltage Vss3. The Q contact is changed to a third low voltage Vss3 lower than the second low voltage Vss2 by the sixth transistor Tr6 and the ninth transistor Tr9, so that leakage current is more likely to occur in the transistor connected to the Q contact Since it is lowered, the voltage of the Q contact can be maintained.

Meanwhile, the voltage values applied in the embodiment of FIG. 12 are as follows.

In the embodiment of FIG. 12 , the first low voltage Vss1 has -7V, the second low voltage Vss2 has -11V, and the third low voltage Vss3 has -15V, like the embodiment of FIG. 3 . The voltage values of the clock signal also have 15V and -15V as shown in FIG. 3 .

The Vgs voltage, which is the voltage difference between the source side and the gate side of each transistor of the Q contact stabilization unit 514, is as follows when the gate-on voltage is output.

Vgs of the fourth transistor Tr4 is 0V, Vgs of the sixth transistor Tr6 is 0V, Vgs of the ninth transistor Tr9 is 0V, and Vgs of the tenth transistor Tr10 is 0V.

Here, although the Vgs voltage is changed, when the gate-on voltage is output from the corresponding stage, it is formed to have a value of 0 or less to generate the gate-on voltage. As a result, the voltage of the Q contact is stabilized and the leakage current does not increase, so that the voltage of the Q contact can be kept constant.

Meanwhile, the Vgs value of the eighth transistor Tr8 connected to the output terminal of the inverter unit 512 is -4V.

In the embodiment of FIG. 12 , since -15V is applied as the lowest voltage, it is suitable to use an oxide semiconductor as a channel of the transistor.

The embodiment of FIG. 13 is also structurally different from the embodiment of FIG. 3 .

In the embodiment of FIG. 13 , the control terminal of the ninth transistor Tr9 of the Q contact stabilizer 514 is connected to the second low voltage Vss2 , and the output terminal is connected to the third low voltage Vss3 . Also, the output terminal of the eighth transistor Tr8 of the inverter unit 512 is connected to the third low voltage Vss3.

That is, the ninth transistor Tr9 of the Q contact stabilizing unit 514 has a control terminal connected to the second voltage input terminal Vin2, an input terminal connected to the Q contact, and an output terminal connected to the third voltage input It is connected to the terminal (Vin3). Since the control terminal receives the second low voltage Vss2, the turn-off state can be continuously maintained, so that the voltage of the Q contact is not leaked. Also, the output terminal of the eighth transistor Tr8 of the inverter unit 512 is connected to the third low voltage Vss3. The I contact that is the output of the inverter unit 512 has a third low voltage (Vss3) value as a low voltage. This is an embodiment for more strongly controlling the leakage current by making the voltage of the I contact, which is the output of the inverter unit 512, have the third low voltage Vss3 when the gate-on voltage is output.

Meanwhile, the voltage values applied in the embodiment of FIG. 13 are as follows.

In the embodiment of FIG. 13 , as in the embodiment of FIG. 3 , the first low voltage Vss1 has -7V, the second low voltage Vss2 has -11V, and the third low voltage Vss3 has -15V. The voltage values of the clock signal also have 15V and -15V as shown in FIG. 3 .

The Vgs voltage, which is the voltage difference between the source side and the gate side of each transistor of the Q contact stabilization unit 514, is as follows when the gate-on voltage is output.

Vgs of the fourth transistor Tr4 is 0V, Vgs of the sixth transistor Tr6 is -4V, Vgs of the ninth transistor Tr9 is -4V, and Vgs of the tenth transistor Tr10 is -4V.

Here, although the Vgs voltage is changed, when the gate-on voltage is output from the corresponding stage, it is formed to have a value of 0 or less to generate the gate-on voltage. As a result, the voltage of the Q contact is stabilized and the leakage current does not increase, so that the voltage of the Q contact can be kept constant.

Meanwhile, the Vgs value of the eighth transistor Tr8 connected to the output terminal of the inverter unit 512 is 0V.

In the embodiment of FIG. 13 , since -15V is applied as the lowest voltage, it is suitable to use an oxide semiconductor as a channel of the transistor.

Hereinafter, the embodiments of FIGS. 14 and 15 will be described. 14 and 15 are embodiments in which only two low voltages Vss1 and Vss2 are applied because the third low voltage Vss3 is not applied.

First, the embodiment of FIG. 14 will be described.

The embodiment of FIG. 14 has a structure in which the third voltage input terminal Vin3 to which the third low voltage Vss3 is applied and the wiring connected thereto are removed from the embodiment of FIG. 3 . In addition, the 11-1 transistor 11-1 is also omitted.

That is, the output terminals of the eleventh transistor Tr11 and the seventeenth transistor Tr17 of the pull-down unit 516 are connected to the third low voltage Vss3 in the embodiment of FIG. 3 , but in the embodiment of FIG. 14 , the second It is connected to the low voltage (Vss2). This causes the second low voltage Vss2 to have a voltage value when the transmission signal CR is low.

A comparative example in which the third low voltage Vss3 is not used has been described in FIGS. 7 and 8 . The embodiment of FIG. 14 may also have characteristics similar to those of the comparative example of FIGS. 7 and 8 . However, even in the embodiment of FIG. 14 , the gate voltage is not different from the embodiment using the third low voltage Vss3 , so there is no problem in using the embodiment of FIG. 14 except in a high temperature environment.

Meanwhile, voltage values of the first and second low voltages applied in the embodiment of FIG. 14 may have various values. Also, the voltage value of the clock signal may vary. As the voltage values available in FIG. 14 , voltage values of other embodiments may be borrowed, and other voltage values may be used.

In the embodiment of FIG. 14 , the first low voltage Vss1 has -5V and the second low voltage Vss2 has -10V. The voltage values of the clock signal have 15V and -15V.

The Vgs voltage, which is the voltage difference between the source side and the gate side of each transistor of the Q contact stabilization unit 514, is as follows when the gate-on voltage is output.

Vgs of the fourth transistor Tr4 is 0V, Vgs of the sixth transistor Tr6 is -5V, Vgs of the ninth transistor Tr9 is -5V, and Vgs of the tenth transistor Tr10 is 0V.

Here, although the Vgs voltage is changed, when the gate-on voltage is output from the corresponding stage, it is formed to have a value of 0 or less to generate the gate-on voltage. As a result, the voltage of the Q contact is stabilized and the leakage current does not increase, so that the voltage of the Q contact can be kept constant.

Meanwhile, the Vgs value of the eighth transistor Tr8 connected to the output terminal of the inverter unit 512 is 0V.

In the embodiment of FIG. 14 , since -15V is applied as the lowest voltage, it is suitable to use an oxide semiconductor as a channel of the transistor.

Meanwhile, in the embodiment of FIG. 15 , unlike the embodiment of FIG. 14 , the output terminal of the eleventh transistor Tr11 is connected to the first low voltage Vss1 .

15, as in the 14th embodiment, the first low voltage Vss1 has -5V and the second low voltage Vss2 has -10V. The voltage values of the clock signal have 15V and -15V.

The Vgs voltage, which is the voltage difference between the source side and the gate side of each transistor of the Q contact stabilization unit 514, is as follows when the gate-on voltage is output.

Vgs of the fourth transistor Tr4 is 0V, Vgs of the sixth transistor Tr6 is -5V, Vgs of the ninth transistor Tr9 is -5V, and Vgs of the tenth transistor Tr10 is 0V.

Here, although the Vgs voltage is changed, when the gate-on voltage is output from the corresponding stage, it is formed to have a value of 0 or less to generate the gate-on voltage. As a result, the voltage of the Q contact is stabilized and the leakage current does not increase, so that the voltage of the Q contact can be kept constant.

Meanwhile, the Vgs value of the eighth transistor Tr8 connected to the output terminal of the inverter unit 512 is -5V.

In the embodiment of FIG. 15 , unlike the embodiment of FIG. 14 , the possibility of leakage of the voltage of the I contact, which is the output of the inverter unit 512 , is reduced as the Vgs value of the eighth transistor Tr8 decreases.

Since -15V is also applied as the lowest voltage in the embodiment of FIG. 15, it is a suitable embodiment to use an oxide semiconductor as a channel of the transistor.

Hereinafter, the embodiment of FIG. 16 will be described.

In the embodiment of FIG. 16 , the output unit 511 , the inverter unit 512 , the transmission signal generating unit 513 , and the Q contact stabilizing unit 514 have the same structure as the embodiment of FIG. 3 . On the other hand, the fifth transistor Tr5 constituting the I-contact stabilizing unit 515 and the 11-1 th transistor Tr11-1 and the 17th transistor Tr17 constituting the pull-down unit 516 are removed.

That is, the pull-down unit 516 includes three transistors (the second transistor Tr2 , the third transistor Tr3 , and the eleventh transistor Tr11 ) connected to the output terminals of the output unit 511 and the transfer signal generation unit 513 . )) is included. The second transistor Tr2 has a control terminal connected to a second input terminal IN2 , an input terminal connected to a gate voltage output terminal OUT, and an output terminal connected to a first voltage input terminal Vin1 . has been The second transistor Tr2 changes the voltage of the gate voltage output terminal OUT to the first low voltage Vss1 according to the next stage transfer signal CR. The third transistor Tr3 has a control terminal connected to the I contact, an input terminal connected to the gate voltage output terminal OUT, and an output terminal connected to the first voltage input terminal Vin1. The third transistor Tr3 changes the voltage of the gate voltage output terminal OUT to the first low voltage Vss1 according to the voltage of the I junction. The eleventh transistor Tr11 has a control terminal connected to the I contact, an input terminal connected to the transfer signal output terminal CRout, and an output terminal connected to a third voltage input terminal Vin3 . That is, the eleventh transistor Tr11 changes the voltage of the transfer signal output terminal CRout to the third low voltage Vss3 according to the voltage of the I contact.

16, the first low voltage Vss1 has -5V, the second low voltage Vss2 has -10V, and the third low voltage Vss3 has -15V. The voltage values of the clock signal have 15V and -15V.

The Vgs voltage, which is the voltage difference between the source side and the gate side of each transistor of the Q contact stabilization unit 514, is as follows when the gate-on voltage is output.

Vgs of the fourth transistor Tr4 is 0V, Vgs of the sixth transistor Tr6 is -5V, Vgs of the ninth transistor Tr9 is -5V, and Vgs of the tenth transistor Tr10 is 0V.

Here, although the Vgs voltage is changed, when the gate-on voltage is output from the corresponding stage, it is formed to have a value of 0 or less to generate the gate-on voltage. As a result, the voltage of the Q contact is stabilized and the leakage current does not increase, so that the voltage of the Q contact can be kept constant.

Meanwhile, the Vgs value of the eighth transistor Tr8 connected to the output terminal of the inverter unit 512 is -5V.

Since -15V is also applied as the lowest voltage in the embodiment of FIG. 16, it is a suitable embodiment to use an oxide semiconductor as a channel of the transistor.

However, when a voltage of -10V or more is applied as the minimum voltage by changing the voltage level, amorphous silicon may be used as a channel of the transistor even in the embodiment of FIG. 16 .

Hereinafter, the embodiment of FIG. 17 will be described.

In the embodiment of FIG. 17 , the output unit 511 , the inverter unit 512 , and the transmission signal generating unit 513 have the same structure as the embodiment of FIG. 3 . On the other hand, the fifth transistor Tr5 constituting the I-contact stabilizing unit 515 is removed, and the connection relationship between the seventeenth transistor Tr17 of the pull-down unit 516 is also changed. In addition, there is a difference in the structure of the Q contact stabilizer 514 .

It will be described in detail below.

The output unit 511 , the inverter unit 512 , and the transmission signal generation unit 513 that are the same as in the embodiment of FIG. 3 are omitted.

The Q contact stabilizer 514 includes five transistors (a fourth transistor Tr4 , a ninth transistor Tr9 , a 9-1 th transistor Tr9-1 , a tenth transistor Tr10 , and a 10-1 th transistor ( ) Tr10-1)). First, the input terminal and the control terminal of the fourth transistor Tr4 are commonly connected to the first input terminal IN1 (diode connection), and the output terminal is connected to the Q contact. When a high voltage is applied to the first input terminal IN1 , the fourth transistor Tr4 transfers it to the Q contact.

The ninth transistor Tr9 and the ninth transistor Tr9-1 are a pair of transistors in which an input terminal and an output terminal are connected to each other and a control terminal is connected to the same terminal (hereinafter, simply referred to as an additional connection) Thus, all of the control terminals are connected to the second input terminal IN2 , the input terminals of the pair of transistors are connected to the Q contact, and the output terminals are connected to the second voltage input terminal Vin2 . As described above, by using a pair of additionally connected transistors, the two transistors are applied by dividing the voltage difference between the second low voltage and the carry signal of the next stage (especially the voltage at the low voltage), so that the leakage current at the Q contact is small. to do it According to an embodiment, the ninth and ninth-first transistors Tr9 and Tr9-1 may be formed in a structure in which three or more thin film transistors are additionally connected. In this case, the additionally formed transistor may also have an input terminal and an output terminal connected to each other and a control terminal connected to the same second input terminal IN2 .

On the other hand, the tenth and tenth transistors (Tr10, Tr10-1) are a pair of transistors that connect an input terminal and an output terminal to each other and have a control terminal additionally connected to the same terminal, and the control terminals are all connected to the I contact, The input terminal of the pair of transistors is connected to the Q contact, and the output terminal is connected to the second voltage input terminal Vin2. The tenth and tenth transistors Tr10 and Tr10-1 change the voltage of the Q contact to the second low voltage Vss2 according to the voltage of the I contact. By using a pair of additionally connected transistors, the two transistors are applied by dividing the voltage difference between the second low voltage and the I contact, so that the leakage current at the Q contact is small. According to an embodiment, the tenth and tenth transistors Tr10 and Tr10-1 may be formed in a structure in which three or more thin film transistors are additionally connected. In this case, the additionally formed transistor may also have an input terminal and an output terminal connected to each other and a control terminal connected to the same I contact.

As described above, by the fourth transistor Tr4, the ninth transistor Tr9, the 9-1 th transistor Tr9-1, the 10th transistor Tr10, and the 10-1 th transistor Tr10-1 connected to the Q contact In each section, the voltage of the Q contact is stabilized.

Meanwhile, the pull-down unit 516 of the embodiment of FIG. 17 is as follows.

The pull-down unit 516 includes five transistors (a second transistor Tr2 , a third transistor Tr3 , an eleventh transistor Tr11 ) connected to the output terminals of the output unit 511 and the transfer signal generation unit 513 ; an 11-1th transistor Tr11-1 and a 17th transistor Tr17).

The second transistor Tr2 has a control terminal connected to a second input terminal IN2, an input terminal connected to a gate voltage output terminal OUT, and an output terminal connected to a first voltage input terminal Vin1. has been The second transistor Tr2 changes the voltage of the gate voltage output terminal OUT to the first low voltage Vss1 according to the next stage transfer signal CR. The third transistor Tr3 has a control terminal connected to the I contact, an input terminal connected to the gate voltage output terminal OUT, and an output terminal connected to the first voltage input terminal Vin1 . The third transistor Tr3 changes the voltage of the gate voltage output terminal OUT to the first low voltage Vss1 according to the voltage of the I junction. The eleventh transistor Tr11 has a control terminal connected to the I contact, an input terminal connected to the transfer signal output terminal CRout, and an output terminal connected to the second voltage input terminal Vin2. That is, the eleventh transistor Tr11 changes the voltage of the transfer signal output terminal CRout to the second low voltage Vss2 according to the voltage of the I junction. The 11-1 th transistor Tr11-1 has a control terminal connected to a fourth input terminal IN4, an input terminal connected to a gate voltage output terminal OUT, and an output terminal connected to a first voltage input terminal IN4. Vin1) is connected. The 11-1 th transistor Tr11-1 causes the gate voltage to become the first low voltage Vss1 when the inverter output signal of the previous stage is applied with a high value. The seventeenth transistor Tr17 has a control terminal connected to a second input terminal IN2 , an input terminal connected to a transfer signal output terminal CRout, and an output terminal connected to a third voltage input terminal Vin3 . has been As a result, the seventeenth transistor Tr17 changes the voltage of the transfer signal output terminal CRout to the third low voltage Vss3 according to the next stage transfer signal CR.

Meanwhile, the voltage applied in the embodiment of FIG. 17 may be as follows.

In the embodiment of FIG. 17 , the first low voltage Vss1 has -5V, the second low voltage Vss2 has -10V, and the third low voltage Vss3 has -15V. The voltage values of the clock signal are 15V and -10V.

In the embodiment of FIG. 17 , the Vgs voltage, which is the voltage difference between the source side and the gate side of each transistor of the Q contact stabilizing unit 514 , is as follows when the gate-on voltage is output.

Vgs of the fourth transistor Tr4 is 0V, Vgs of the ninth and ninth transistors Tr9 and Tr9-1 is -5V, and Vgs of the tenth and tenth transistors Tr10 and Tr10-1 is Vgs. is 0V.

Here, although the Vgs voltage is changed, when the gate-on voltage is output from the corresponding stage, it is formed to have a value of 0 or less to generate the gate-on voltage. As a result, the voltage of the Q contact is stabilized and the leakage current does not increase, so that the voltage of the Q contact can be kept constant.

Meanwhile, the Vgs value of the eighth transistor Tr8 connected to the output terminal of the inverter unit 512 is -5V.

In the embodiment of FIG. 17, since -10V is applied as the lowest voltage, not only an oxide semiconductor but also amorphous silicon can be used as a channel of the transistor.

In each embodiment, amorphous silicon may be used as a channel material of a transistor or an oxide semiconductor such as IGZO may be used as a channel material of a transistor according to an applied voltage value. In an embodiment of the present invention, when a voltage of -10V or more is applied, amorphous silicon or an oxide semiconductor may be used as the channel of the transistor, and when the voltage is less than -10V, the oxide semiconductor is used as the channel of the transistor.

Although preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present invention as defined in the following claims are also provided. is within the scope of the

100: display panel 300: display area
400: printed circuit board 450: flexible printed circuit film
460: data driver IC 500: gate driver
511: output unit 512: inverter unit
513: transmission signal generation unit 514: Q contact stabilization unit
515: I contact stabilization part 516: pull-down part
600: signal control

Claims (17)

a display area including a plurality of gate lines and a plurality of data lines; and
and a gate driver connected to one end of the plurality of gate lines and including a plurality of stages for generating and transmitting a gate voltage, respectively;
one of the plurality of stages includes a first transistor, a third transistor, an eleventh transistor, a fifteenth transistor, and a first capacitor;
The first transistor includes an input terminal receiving a clock signal, a control terminal electrically connected to the Q contact, and an output terminal electrically connected to a gate voltage output terminal for outputting the gate voltage,
The fifteenth transistor includes an input terminal receiving a clock signal, a control terminal electrically connected to the Q contact, and an output terminal electrically connected to a transfer signal output terminal to output a transfer signal,
The third transistor lowers the voltage of the output terminal of the first transistor to a first low voltage by an inverter signal,
The eleventh transistor lowers the voltage of the transfer signal to a third low voltage by the inverter signal,
The inverter signal has a second low voltage,
The first low voltage, the second low voltage, and the third low voltage have different voltage values. In claim 1,
Channels of the first transistor, the third transistor, the eleventh transistor, and the fifteenth transistor include an oxide semiconductor. In claim 1,
The second low voltage has a voltage level lower than that of the first low voltage, and the third low voltage has a voltage level lower than that of the second low voltage. In claim 1,
The transfer signal is transferred to the first input terminal of the next stage,
The inverter signal is transmitted to a fourth input terminal of the stage immediately following the display panel. In claim 4,
The transfer signal is also transferred to the second input terminal of the previous stage. In claim 5,
The transfer signal is also transferred to the third input terminal of the previous stage. In claim 1,
The one stage is
and a second transistor for lowering the voltage of the output terminal of the first transistor to the first low voltage. In claim 7,
The second transistor includes a control terminal electrically connected to a second input terminal receiving the transfer signal of the next stage through a second input terminal, an input terminal electrically connected to the gate voltage output terminal, and the first low voltage including an output terminal to which this is applied;
The third transistor includes a control terminal electrically connected to an I contact electrically connected to an inverter signal output terminal for outputting the inverter signal, an input terminal electrically connected to the gate voltage output terminal, and the first A display panel including an output terminal to which a low voltage is applied. In claim 7,
The eleventh transistor includes a control terminal electrically connected to an I contact electrically connected to an inverter signal output terminal for outputting the inverter signal, an input terminal electrically connected to the transmission signal output terminal, and the third A display panel including an output terminal to which a low voltage is applied. In claim 7,
The one stage further includes a 17th transistor for lowering the voltage of the transfer signal to the third low voltage,
The seventeenth transistor includes a control terminal receiving the transfer signal of the next stage through a second input terminal, an input terminal electrically connected to the transfer signal output terminal, and an output terminal to which the third low voltage is applied display panel. In claim 10,
The one stage further comprises an 11-1 transistor for lowering the gate voltage to the first low voltage,
The 11-1 transistor includes a control terminal to which the inverter signal of the previous stage is applied, an input terminal electrically connected to the gate voltage output terminal, and an output terminal to which the first low voltage is applied. In claim 1,
The inverter signal controls the third transistor to transfer the first low voltage to the gate voltage output terminal,
The inverter signal controls the eleventh transistor to transfer the third low voltage to the transfer signal output terminal. In claim 12,
The one stage further includes a seventh transistor, a twelfth transistor, and a thirteenth transistor,
The seventh transistor includes a control terminal electrically connected to an input terminal of the thirteenth transistor and an output terminal of the twelfth transistor, an input terminal electrically connected to an input terminal and a control terminal of the twelfth transistor, and the and an output terminal electrically connected to an inverter signal output terminal for outputting an inverter signal,
and the thirteenth transistor includes an output terminal to which the second low voltage is applied. In claim 13,
The one stage further comprises an eighth transistor,
The eighth transistor includes a control terminal electrically connected to the control terminal of the thirteenth transistor, an input terminal electrically connected to an inverter signal output terminal for outputting the inverter signal, and an output terminal to which the second low voltage is applied A display panel comprising a. In claim 1,
The one stage further includes a Q contact stabilization unit,
The Q contact stabilizing part
The input terminal and the control terminal receive the transfer signal of the previous stage through the first input terminal, the output terminal is a fourth transistor connected to the Q contact;
a sixth transistor to which a control terminal receives the transfer signal of the next stage through a third input terminal, the input terminal is connected to the Q contact, and the output terminal receives the second low voltage;
a ninth transistor to which a control terminal receives the transfer signal of the next stage through a second input terminal, an input terminal is connected to the Q contact, and an output terminal receives the second low voltage; and
A control terminal is connected to an I contact connected to an inverter signal output terminal for outputting the inverter signal, an input terminal is connected to the Q contact, and an output terminal includes a tenth transistor to which the second low voltage is applied display panel. In claim 1,
The one stage further includes a Q contact stabilization unit,
The Q contact stabilizing part
The input terminal and the control terminal receive the transfer signal of the previous stage through the first input terminal, and the output terminal is a fourth transistor connected to the Q contact;
a pair of a ninth transistor and a 9-1 transistor, and
It includes a pair of tenth transistor and 10-1 th transistor,
An input terminal of the 9-1 th transistor is electrically connected to an output terminal of the ninth transistor, and a pair of ninth transistors and a control terminal of the 9-1 th transistor are connected to the next stage through a second input terminal. is electrically connected to a second input terminal receiving the transfer signal, an input terminal of a ninth transistor is electrically connected to the Q contact, and an output terminal of the ninth transistor is applied with the second low voltage;
An input terminal of the 10-1 th transistor is electrically connected to an output terminal of the 10 th transistor, and a pair of 10 th transistors and a control terminal of the 10-1 th transistor are inverter signal output terminals for outputting the inverter signal is electrically connected to an I contact that is electrically connected to, an input terminal of a tenth transistor is electrically connected to the Q contact, and an output terminal of the 10-1 transistor is applied with the second low voltage,
The transfer signal is a low voltage, the display panel having the second low voltage in addition to the third low voltage. In claim 1,
The one stage further comprises a fifth transistor,
The input terminal of the fifth transistor is electrically connected to an I contact that is electrically connected to an inverter signal output terminal for outputting the inverter signal, and the control terminal of the fifth transistor is transferred to the previous stage through the first input terminal A display panel to which a signal is applied and the second low voltage is applied to an output terminal of the fifth transistor.

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