KR20210153376A - Manufacturing method of unclonable security device and unclonable security device thereof - Google Patents

Abstract

According to an embodiment of the present invention, a security device manufacturing method comprises the following steps of: forming a gate on a substrate; forming a gate insulating film; forming a CNT layer; forming a source and a drain; and removing an exposed CNT layer to form a channel pattern.

Description

MANUFACTURING METHOD OF UNCLONABLE SECURITY DEVICE AND UNCLONABLE SECURITY DEVICE THEREOF

The present technology relates to a method of manufacturing a non-replicable security device and a security device.

The proliferation of the Internet of Things (IoT) environment requires more interconnected devices to manage personal and sensitive information, increasing the need for strong security primitives. In particular, while traditional software-based encryption and decryption procedures are cost-effective and easy to update, they can be easily compromised if the operating system has security flaws. Alternatively, physical unclonable functions (PUFs) are considered as one of the most promising hardware-based security methods to solve the above shortcomings.

US Patent Publication No. 2018/0006230 (2016.06.29)

The PUF concept is to generate random digital values using intrinsic deviations that are difficult to predict due to uncontrollable variability and high randomness in the semiconductor manufacturing process. The physical parameters are random variations that occur during manufacturing, making key duplication very difficult. Although many researchers have demonstrated low-power and high-performance security devices using flash memory, nanoelectronic switches (NEMS) and resistive random access memory (RRAM), the process is complex and the cost is still burdensome.

The present technology is intended to solve the above disadvantages of the prior art. One of the problems to be solved by the present technology is to provide a security device that cannot be simply copied without complicated process steps or circuit configuration, and to provide a method for manufacturing the same.

The method of manufacturing a security device according to this embodiment comprises the steps of forming a gate on a substrate, forming a gate insulating film, forming a CNT layer, forming a source and drain, and removing the exposed CNT layer to form a channel forming a pattern.

The security device according to this embodiment includes a substrate, a gate positioned on the substrate, a gate insulating film positioned on the gate, a channel pattern positioned on the gate insulating film, drain and source electrically connected to the channel pattern, respectively , the channel pattern is a semiconducting CNT network.

According to the security device and the method for manufacturing the security device according to the present embodiment, an advantage is provided that a device having a very low copyability can be provided.

1 is a diagram schematically illustrating a state in which a substrate and an oxide film formed on the substrate are formed.
2 is a diagram schematically illustrating a step of forming a gate on a substrate.
3 is a view schematically illustrating a state in which a gate insulating layer is formed.
4 is a view schematically illustrating a state in which a CNT layer is formed.
5 is a diagram schematically illustrating a state in which a source and a drain are formed.
6 is a diagram schematically illustrating a state in which a channel pattern is formed.
7 is a cross-sectional view taken along line A-A' of FIG. 6 .
Fig. 8 (a) is a photomicrograph of the security device 10 according to the present embodiment, and Fig. 8 (b) is a photomicrograph of the arrangement of the security device according to the present embodiment in a matrix form. 8(c) is a diagram illustrating the formation of an encrypted key using each security device arranged in a matrix form.
Figure 9 (a) is a micrograph of the security device according to the present embodiment, Figure 9 (b) is an enlarged view of the channel pattern.
10( a ) shows a result of counting the security devices included in the security device matrix according to the magnitude of the threshold voltage. 10( b ) is a diagram illustrating a result of measuring the drain current with respect to the gate voltage. FIG. 10( c ) is a diagram illustrating a result of counting the security device according to the value of the conduction current ION flowing between the drain and the source when the gate voltage is -6V.

Hereinafter, a method for manufacturing a non-copyable security device and a security device according to the present embodiment will be described with reference to the accompanying drawings. 1 to 6 are views schematically illustrating each step of the method for manufacturing a non-copyable security device according to the present embodiment. 1 is a diagram schematically illustrating a state in which a substrate (sub) and an oxide film 110 formed on the substrate are formed. Referring to FIG. 1 , a substrate sub may be a semiconductor substrate or a flexible substrate. For example, the substrate sub may be a silicon substrate, a polyethylene terephthalate (PET) substrate, a polydimethylsiloxane (PDMS) substrate, or the like. In an embodiment, a silicon oxide layer 110 may be formed on a surface of the substrate sub on which the security device 10 is formed. For example, the silicon oxide layer 110 may be formed by thermal evaporation, e-beam evaporation, sputtering, ion plating, plasma enhanced chemical vapor deposition (PECVD), atmospheric pressure plasma deposition, and/or plasma deposition. It may be formed by performing an oxidation process on a silicon substrate.

2 is a diagram schematically illustrating a step of forming a gate on a substrate sub. Referring to FIG. 2 , the gate 200 may be formed by forming a gate metal layer and patterning the gate metal layer to have a desired shape. In one embodiment, forming the gate metal layer may include thermal evaporation of the gate metal, e-beam evaporation, sputtering, ion plating, and plasma enhanced chemical vapor deposition (PECVD). ) and so on.

The formed gate metal layer may be patterned by lithography including forming a photoresist (PR) layer, providing light corresponding to a desired pattern, developing, and etching. In an embodiment, the etching process may be performed by etching the exposed metal layer with oxygen plasma.

In an embodiment, the gate metal layer may be formed by stacking a gate metal layer and a barrier metal layer preventing oxidation of the gate metal layer. For example, the gate metal layer may be titanium (Ti), palladium (Pd), gold (Au), or platinum (Pt), and the barrier metal layer may be titanium nitride (TiN). For example, a thickness ratio of the gate metal layer and the barrier metal layer may be 4:1. For example, the thickness of the gate metal layer and the barrier metal layer may be 20 nm and 5 nm, respectively.

3 is a diagram schematically illustrating a state in which the gate insulating layer 300 is formed. Referring to FIG. 3 , a gate insulation layer 300 is formed to cover at least a portion of the gate 200 . In an embodiment, the gate insulating film 300 may be formed of a metal oxide film, for example, forming at least one of an aluminum oxide (Al ₂ O ₃ ) film and a silicon oxide (SiO ₂ ) film and a patterning step. It can be formed by performing For example, the aluminum oxide (Al ₂ O ₃ ) film may be formed by an atomic layer deposition (ALD) process. The silicon oxide layer (SiO ₂ ) may be formed by an electron beam deposition process. In an embodiment, the gate insulating layer 300 _{may be formed by stacking an aluminum oxide (Al 2} O ₃ ) layer and a silicon oxide (SiO2) layer.

4 is a view schematically illustrating a state in which the CNT layer 400 is formed. Referring to FIG. 4 , the step of forming the CNT layer 400 may be performed by forming a semiconducting CNT layer. In one embodiment, an adhesion improvement treatment of treating the surface of the gate insulating film 300 with poly-L-lysine before the step of forming the semiconducting CNT layer in order to improve the adhesion of the semiconducting CNT layer (adhesion improvement treatment) More steps may be performed.

Forming the CNT layer 400 includes spraying a solution in which semiconducting CNTs are dispersed on the gate insulating layer 300, ink-jet printing, spin coating, and dip coating. (dip coating) may be performed, or may be performed by a deposition process. Since the formed CNT layer 400 is formed in the form of a random percolated network, the electrical characteristics of the security device 10 are random as will be described later.

5 is a diagram schematically illustrating a state in which a source 610 and a drain 620 are formed. Referring to FIG. 5 , the forming of the source 610 and the drain 620 may be performed using a shadow mask. As an embodiment of the step of forming the source 610 and the drain 620, a shadow mask having an open region where the source and drain are to be formed is placed, and electron beam deposition is performed to form a metal pattern in the open region in the shadow mask. It can be carried out by depositing and lifting the shadow mask off (lift-off).

In another embodiment, in the step of forming the source 610 and the drain 620, a metal layer is formed on the CNT layer 400, and photolithography is performed to form the source 610 and the drain 620 in a desired shape. ) can be formed. The source 610 and the drain 620 formed in this way may be electrically connected to the CNT layer 400 underneath.

6 is a diagram schematically illustrating a state in which a channel pattern 410 is formed. Referring to FIG. 6 , the channel pattern 410 may be performed by removing CNTs disposed at an undesired location away from between the source 610 and the drain 620 . In the illustrated embodiment, the channel pattern 410 is exposed in the CNT layer 400 except for CNTs located between one end (S) of the source 610 and one end (D) of the drain 620 . to remove

The gate insulating layer 300 is removed to form a gate pad 210 (refer to FIG. 8 ) connected to the gate 200 . In an embodiment, the process of forming the gate pad 210 (refer to FIG. 8 ) may be performed by removing the gate insulating layer 300 using a photolithography process to open a desired position. The gate pad 210 (refer to FIG. 8) formed as described above, the source 610, the drain 620, and the channel pattern 410 form a transistor. In addition, the transistor has random electrical characteristics according to the random network characteristics of the CNT layer constituting the channel pattern 410 .

Hereinafter, the security device 10 according to the present embodiment will be described with reference to FIGS. 6 and 7 . However, descriptions of elements that are the same as or similar to those described above may be omitted. 7 is a cross-sectional view taken along line A-A' of FIG. 6 . 6 and 7 , the security device 10 according to the present embodiment includes a substrate sub, a gate 200 positioned on the substrate sub, and a gate insulating film ( 300), a channel pattern 410 positioned on the gate insulating film 300, and a drain 610 and a source 620 electrically connected to the channel pattern, respectively, and the channel pattern 410 is a semiconducting CNT network. to be.

One side of the channel pattern 410 is electrically connected to the source 610 and the other side is connected to the drain 620 . As the contact area between the channel pattern 410 and the source 610 and the drain 620 increases, the contact resistance decreases, so that the current driving characteristic may be improved.

The channel pattern 410 may be formed of a semiconducting CNT network as described above. In one embodiment, in the process of forming the semiconducting CNT layer 400 (refer to FIG. 5 ), the number of carbon nanotubes connected to one carbon nanotube, the contact area, etc. have random characteristics. In addition, the semiconducting CNT layer 400 (see FIG. 5 ) uses a semiconducting CNT solution of 99% purity, but metallic CNTs may be mixed among them. Furthermore, the concentration of the CNT solution used in the process of forming the semiconducting CNT layer 400 (refer to FIG. 5 ) is macroscopically uniform, but locally, the concentration may be different from each other. Accordingly, these elements randomly form the electrical characteristics of the channel pattern 410 , and randomly form the threshold voltage of the transistor forming the security device 10 .

implementation

Hereinafter, an implementation example of the security device 10 of the present embodiment will be described with reference to FIG. 8 . 8 (a) is a photomicrograph of the security device 10 according to the present embodiment, and FIG. 8 (b) is a security device matrix 1 in which the security device 10 according to the present embodiment is arranged in a matrix form. ) is a photomicrograph, and FIG. 8( c ) is a diagram schematically illustrating an encryption key formed from the security device matrix 1 .

Referring to FIG. 8A , it can be seen that the security device 10 has a source 610 and a drain 210 formed thereon, and the gate insulating layer is opened to form the gate pad 210 . Figure 8 (b) is a photomicrograph of the security device matrix (1). The security devices 10 included in the security device matrix 1 also have random threshold voltages due to random electrical characteristics of the channel pattern 410 .

The electrical characteristics of the security devices 10 included in the security device matrix 1 may be identified, and an average value thereof may be calculated. The electrical characteristics of each of the security devices 10 may be compared with the average value, and a value of “0” or “1” may be assigned according to the comparison result. As an example, threshold voltage values of the security devices 10 included in the security device matrix 1 may be obtained, and an average value thereof may be calculated. Values of “0” and “1” may be assigned by comparing the magnitude of the threshold voltage value and the average value of each of the security devices 10 . As another example, when a predetermined gate voltage is provided, a value of “0” and “1” may be assigned by measuring a current flowing between the drain and the source and comparing the magnitude with the average value thereof.

FIG. 8( c ) is a diagram illustrating a comparison result between a threshold voltage value of each security device 10 and an average threshold voltage value. When the threshold voltage value of each security device 10 was smaller than the average threshold voltage value, a value of “0” was assigned, and when the threshold voltage value was greater than the average threshold voltage value, “1” was assigned. “0” is shown in black and “1” is shown in white. An encryption key can be formed with the value formed in this way. Furthermore, even if the same process is performed, since the possibility of forming a combination of the same values is slim, an encryption key that cannot be copied can be formed.

evaluation

Hereinafter, examples of the security device according to the present embodiment will be evaluated with reference to FIGS. 9 and 10 . Figure 9 (a) is a micrograph of the security device 10 according to the present embodiment, Figure 9 (b) is an enlarged view of the channel pattern. Referring to FIG. 9A , it can be seen that the security device according to the present embodiment is formed in the form of a transistor including a source, a drain, a gate, and a channel. Referring to FIG. 9B , it can be seen that the carbon nanotubes forming the channel pattern are arranged to randomly form a percolate network with each other.

10 is a diagram illustrating an example of detecting electrical characteristics of a security device matrix including 20*20 security devices. Each security device has a channel width of 5 μm and a channel length of 3 μm. 10 (a) shows the result of counting the security devices included in the security device matrix _{according to the magnitude of the threshold voltage (V T ).} Referring to FIG. 10( a ), _{it can be seen that the threshold voltage (V T} ) of the security devices varies from 0.5V to 1.2V. Security devices with a security device threshold voltage of 0.8V were the most common, and it is understood that they have an approximate Gaussian distribution based on 0.8V.

Figure 10 (b) is a result of measuring the drain current (I _DS) to the gate voltage (V _GS), the value of the same gate voltage (V _GS) current flows even when applying as shown is seen that significant conversion It is understood that this is because the threshold voltage of the security device 10 is randomly formed as described above.

FIG. 10( c ) is a view showing the counting result of the security device 10 according to the value of the _{conduction current I ON} flowing between the drain and the source when the gate voltage is -6V. As shown, it can be seen that the conduction current (I _ON ) is widely distributed from 0.4 μA to 1.25 μA.

Although it has been described with reference to the embodiment shown in the drawings in order to help the understanding of the present invention, this is an embodiment for implementation, merely exemplary, and those of ordinary skill in the art will find various modifications and equivalents therefrom It will be appreciated that other embodiments are possible. Accordingly, the true technical protection scope of the present invention should be defined by the appended claims.

1: Security Device Matrix 10: Security Device
110: oxide film sub: substrate
200: gate 210: gate pad
300: gate insulating film 400: CNT layer
410: channel pattern 610: source
620: drain S: one end of the source
D: one end of the drain

Claims (15)

forming a gate in the substrate;
forming a gate insulating film;
forming a CNT layer;
forming a source and a drain; and
A method of manufacturing a security device comprising removing the exposed CNT layer to form a channel pattern. According to claim 1,
Forming the gate comprises:
forming a gate metal layer;
and patterning a gate metal layer to form the gate. 3. The method of claim 2,
Forming the gate comprises:
forming a barrier metal layer on the gate metal layer;
and patterning the barrier metal layer together with the gate metal layer to form the gate. According to claim 1,
The step of forming the gate insulating film,
A method of manufacturing a security device performed by forming at least one of aluminum oxide (Al ₂ O ₃ ) and silicon oxide (SiO _{2 ).} According to claim 1,
The step of forming the CNT layer,
forming an adhesion-improving layer on the gate insulating film;
A method of manufacturing a security device comprising forming a semiconducting CNT layer. According to claim 1,
Forming the source and the drain comprises:
positioning a shadow mask that opens a desired area;
forming a metal layer; and
and lifting off the shadow mask. According to claim 1,
Forming the channel pattern comprises:
A method of manufacturing a security device performed by removing CNTs that have deviated between the source and the drain. According to claim 1,
The method of manufacturing the security device,
and removing the gate insulating film to form a gate pad. Board;
a gate positioned on the substrate;
a gate insulating film positioned over the gate;
a channel pattern positioned on the gate insulating layer;
and a drain and a source electrically connected to the channel pattern, respectively,
wherein the channel pattern is a semiconducting CNT network. 10. The method of claim 9,
the gate is
a gate electrode pattern of any one of titanium (Ti), palladium (Pd), gold (Au), and platinum (Pt); and
A security device comprising any one of a pattern in which a gate pattern of titanium (Ti), palladium (Pd), gold (Au), and platinum (Pt) and a barrier pattern of titanium nitride (TiN) are stacked. 10. The method of claim 9,
The gate insulating film is
A security device comprising at least one of aluminum oxide (Al ₂ O ₃ ) and silicon oxide (SiO _{2 ).} 10. The method of claim 9,
The drain and the source may include any one of patterned gold (Au) and palladium (Pd). 10. The method of claim 9,
The security device is
and a gate pad exposed from the gate insulating layer and connected to the gate. 10. The method of claim 9,
The security device is
A security device formed by disposing a plurality of the security devices having random electrical characteristics in a matrix. 15. The method of claim 14,
The security device is a transistor,
wherein the electrical characteristic is any one of a threshold voltage and a conduction current of the transistor.

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