KR20210149559A - Method For Power-saving Realtime and Interactive Task Scheduling for Intelligent Embedded System - Google Patents

Abstract

The present invention relates to a scheduling method capable of guaranteeing a deadline of a real time task and reducing a response time of an interactive task, while reducing the power consumption of a whole system by using various power-saving techniques and genetic algorithms on real time tasks and interactive tasks in a multicore processor system. DGIA, which is a concept of 'a virtual task', enables a real time task and an interactive task to be scheduled together by reserving the execution of the interactive task offline. DVS, HM techniques are applied to save power of the whole system. Here, a genetic algorithm is used to determine the degree of application of a power-saving technique so as to guarantee a deadline of the real time task while maximizing the power-saving of the system. Meanwhile, as the rate of utilization of virtual tasks is allowed to be dynamically changed during performance in accordance with a load of the interactive task, the efficient execution of a noncyclic task can be guaranteed. Therefore, an improvement in the performance of an intelligent embedded system based on real time and interactive tasks can be made through the guaranteeing of the deadline of the real time task, the power-saving of the system, and the reduction in the response time of the interactive task.

Description

{Method For Power-saving Realtime and Interactive Task Scheduling for Intelligent Embedded System}

The present invention deals with a real-time task-interactive task power-saving scheduling scheme for a multi-core processor system. For the integrated scheduling of two tasks, the concept of a virtual task is used, and by varying the weight of the virtual task, it dynamically responds to the load of the interactive task. DVS (Dynamic Voltage Scaling) and HM (Hybrid Memory) are used as power saving techniques, and the application and degree of application is determined using a genetic algorithm.

Recently, the number of systems using high-performance-ultra-small microprocessor technology is increasing. In addition, as the Internet of Things and cyber-physical systems become active, various services are provided to users by using various sensors and processors together. These systems are “real-time embedded systems” that have to guarantee the deadlines of each task with limited battery power, and reducing the power consumption of the system along with the deadline guarantees is an important goal of system management.

Although research on power saving of a real-time system has been widely conducted, recently, an environment in which an interactive task that occurs intermittently according to a user's request in addition to a real-time task is processed together in a single system is increasing. For example, in the case of a system for a smart vehicle, a control unit (ECU) for each subsystem, such as engine control, sensor recognition, and electric field, existed separately in the past, but a method for integrating them is being studied recently. Therefore, there is a need for a method for efficiently managing such a mixed task rather than a method for scheduling only a single type of real-time task or interactive task. The present invention proposes a new scheduling scheme that considers the deadline guarantee of real-time task, the guarantee of response time of interactive task, and the power saving of the system.

Real-time tasks can cause great damage if deadlines are not met, whereas interactive tasks require fast response times for human interaction, but there is no deadline. Accordingly, an object of the present invention is to increase the responsiveness of an interactive task while satisfying the deadline of a real-time task. In addition, the present invention pursues scheduling that satisfies this goal as a prerequisite and ultimately minimizes power saving of the system. To this end, the present invention utilizes DVS (Dynamic Voltage Scaling) technology, which dynamically adjusts the processor voltage according to system load, and HM (Hybrid Memory) technology, which reduces memory power consumption by using low-power nonvolatile memory and DRAM together. do.

The present invention targets a multicore system in which a real-time task set and an interactive task set are integrated. The first task is to ensure that tasks in the set of real-time tasks do not violate deadlines. The next challenge is to reduce the power consumption of the system and at the same time reduce the response time of the interactive task.

In order to solve this problem, the present invention periodically detects the load of an interactive task and includes it in offline scheduling as if a “virtual real-time task” (hereinafter referred to as a virtual task) exists to determine the real-time schedule of the next cycle. For interactive tasks that arrive online, schedule them in a pre-allocated virtual task place so that they do not affect other real-time tasks In this case, the scheduling for interactive tasks uses round-robin scheduling to minimize response time. .

That is, in the present invention, an offline scheduler in charge of scheduling a real-time task including a virtual task and an online scheduler that maps an interactive task to a virtual task allocation slot perform dual scheduling. In addition, the response delay of the interactive task that occurs through online scheduling is periodically monitored, and the size of the virtual task is reallocated according to the load, and then this is reflected in the next offline real-time scheduling. This will continuously improve the response time of interactive tasks as well as satisfying deadlines for real-time tasks.

On the other hand, the problem to be solved by the present invention is the problem of determining the power mode of the processor and the location of the memory for each task, which is an NP-hard problem having exponential time complexity. Therefore, in the present invention, a combination of a processor voltage and a memory type for each task capable of maximizing the power saving effect of the system is determined using a genetic algorithm.

By using the method of the present invention, the power consumption of the system can be greatly reduced within the range that does not violate the deadline of the task by using the DVS method, the HM method, and the task optimization method (genetic algorithm) in combination. The response time of the task can be shortened.

go. virtual task

To schedule a real-time task set and an imperative task set within one system, a method of defining a virtual real-time task as if it exists and leaving the corresponding time blank for offline scheduling is used. Specifically, after scheduling the created virtual task with the real-time task, when the actual real-time task comes to be executed, the interactive task is executed through online scheduling. In other words, a part of system resources are reserved for interactive task execution using 'virtual tasks' during offline scheduling.

In addition, multiple scheduling policies are created in such a way as to vary the utilization rate of a hypothetical set of tasks. Then, at the actual scheduling time, an appropriate policy is selected based on the change in the load state of the interactive task. In this case, the time point at which the scenario is selected is the least common multiple of the period of all real-time task sets. Through this method, a fast response time is ensured by effectively responding to the load of irregular interactive tasks.

me. Power Savings Using the Dynamic Voltage Scaling (DVS) Method

As a representative method used to save power of the processor, there is a DVS technique that dynamically adjusts the voltage of the processor based on CMOS circuit technology. This greatly reduces the dynamic power consumption by lowering the processor's voltage based on the fact that the processor's power consumption is proportional to the square of the voltage as shown in the equation below. On the other hand, since the number of instructions to be executed per unit time is reduced, the execution time of the task is increased. Therefore, it is important to properly adjust the frequency and voltage in a range that does not violate the deadline of the task.

(식. 1.)

(Eq. 1.)

It is assumed that there are a finite number of voltage modes in our system, as in the general DVS support scheme, and that each task T can be assigned this combination.

All. Power Saving Using HM (Hybrid Memory) Method

DRAM, which is mainly used in current main memory systems, is a volatile medium and requires continuous power refresh operation even in an idle state to maintain data. On the other hand, next-generation low-power memories such as PRAM and STT-MRAM (hereinafter referred to as LPM, Low Power Memory) are non-volatile, and thus do not require power resupply operation, thereby reducing power consumption.

However, as shown in Table 1 below, since the performance of LPM is inferior to that of DRAM, it is difficult to completely replace the memory medium with LPM. Accordingly, the present invention reduces the power consumption of the memory by using the HM method using both the DRAM and the LPM. Consequently, tasks in the system are performed in DRAM or LPM.

(표.1.)

(Table 1.)

La. genetic algorithm

In order to reduce the overall power consumption of the system, the DVS technique, which dynamically adjusts the processor's voltage, and the HM technique, which uses both non-volatile memory and DRAM, are applied to real-time tasks. However, the application of this power saving technique may result in violating the deadline of the real-time task by increasing the execution time of the task. Therefore, it is important to find a point that can maximize the power saving effect while satisfying the system conditions. For this purpose, a genetic algorithm, a type of meta-heuristic algorithm, is used.

If you want the lowest possible power consumption in your system, you can simply place all real-time tasks in low-power memory and run them in the lowest voltage mode through DVS. This method will be acceptable when the utilization of the total real-time task is very low compared to the available system resources. However, this is because, when the utilization rate is high, the deadline of the real-time task may be violated due to the increased task execution time using the power saving technique. Therefore, it is important to find a point that satisfies the system conditions while maximizing the power saving effect. For this purpose, a genetic algorithm, a type of meta-heuristic algorithm, is used. Using this, we want to find the optimal processor voltage mode and memory type for performing real-time tasks and virtual tasks, respectively.

Claims (1)

A method of shortening response time by dynamically responding according to the load of an interactive task using the concept of 'virtual task' for a task set in which real-time and interactive tasks are mixed in a multi-core system, DRAM and non-volatile next-generation A method of reducing power consumption of memory by using memory together (hereinafter referred to as HM: Hybrid Memory), a method of lowering power consumption of a processor by dynamically adjusting the voltage of a processor (hereinafter referred to as DVFS: Dynamic Voltage Frequency Scaling) method, A real-time scheduling method that shows the power saving effect by using the 'task optimization' method that pre-specifies whether and how to perform the power saving technique through a genetic algorithm for the task.