KR20210063706A - Method For Power-saving Real-time Scheduling for Intelligent Embedded System - Google Patents

Abstract

The present invention relates to a scheduling method capable of reducing power consumption in a memory and a processor by applying dynamic voltage frequency scaling (DVFS), hybrid memory (HM), and task optimization methods together. The present invention proposes a real-time scheduling method for maximizing the power saving effect of a system by combining a method (hereinafter HM) for reducing power consumption in a memory by using DRAM and non-volatile next-generation memory together for hard tasks with a method (hereinafter DVFS) for reducing power consumption in a processor by dynamically adjusting the voltage of the processor. In addition, the method accelerates the power saving effect by using a method for pre-specifying hardware resources to be allocated for the tasks of a task set. The present invention provides a basis for constructing an intelligent embedded system using a limited battery as a power supply source through the scheduling method having the power saving effect.

Description

{Method For Power-saving Real-time Scheduling for Intelligent Embedded System}

The present invention is a real-time scheduling method in a multi-core environment, and more specifically, through a DVFS (Dynamic Voltage/Frequency Scaling) method, HM (Hybrid Memory), and a 'task optimization' method of pre-designating hardware resources to be allocated to tasks. It relates to a scheduling method capable of reducing power consumption of a memory and a processor.

Recently, IT technology is undergoing a revolution in which the core of product competitiveness moves from H/W production technology to S/W optimization technology according to the low cost, miniaturization, and high performance of microprocessors. Using these microprocessors, high-performance development, including 5G communication and advanced artificial intelligence (AI), is underway in various fields. For example, in the Internet of Things (IoT), a technology that connects and embeds communication functions and sensors in things such as mobile devices and home appliances, research is underway to create faster intelligent systems by introducing 5G and artificial intelligence technologies. In addition, research is underway to provide more advanced services to users by using technologies such as artificial intelligence, 5G, multiple cameras, multi-display, and ultrasonic sensors for embedded systems such as smart cars.

These systems are a kind of “real-time embedded system” that must perform a specific task within a given time, and are characterized by using a battery with a limited capacity as a means of supplying power. However, the above techniques that are newly applied require relatively complex and large-capacity calculations. Accordingly, the importance of a technology capable of saving power in such a real-time embedded system environment is increasing.

In mobile devices such as smartphones, memory is an important power source, accounting for 48% of total power consumption. The power consumption of memory has increased dramatically, especially with DRAM, which can accommodate more applications. The cause of such power consumption is the DRAM's power refresh operation. Since DRAM is a volatile medium, continuous power re-supply operation is required to maintain stored data even in an idle state in which read and write operations are not performed, which consumes a lot of energy.

In an attempt to reduce the power consumption of such DRAMs, non-volatile low-power memory (LPM) technology has emerged. LPMs such as PC-RAM (Phase Change Random Access Memory) and STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) Since data can be maintained without resupply operation, memory power consumption can be greatly reduced. That is, the LPM consumes no power at all during idle time. However, since the access time for LPM read/write is slower than that of DRAM, it is impossible to completely replace the LPM with DRAM. Therefore, by using LPM and DRAM together, it is possible to compromise the power consumption due to the DRAM power resupply operation and the LPM access time delay. LPM may not violate the deadline of a real-time task when running in low voltage/frequency mode.

With the development of the computing power of the processor, the voltage and frequency adjustment technique (DVFS) of the processor is being used for task scheduling. Based on CMOS circuit technology, the DVFS technique dynamically changes the supply voltage and frequency according to the task load. In this technique, when the supply voltage to the processor is lowered, the amount of execution is proportionally reduced, but the power consumption can be significantly reduced in proportion to the square. In a situation where the amount of work to be processed falls short of the processing capacity of the processor, the deadline of the task can be guaranteed even if the power consumption is reduced by lowering the supply voltage of the processor. Therefore, when real-time task scheduling is performed by adjusting the processing speed of the processor using DVFS, energy can be saved more flexibly.

We propose a new low-power scheduling method for intelligent embedded systems that use a limited battery as a power source to ensure longer battery life.

In the present invention, a Dynamic Voltage Frequency Scaling (DVFS) method for dynamically adjusting the voltage and frequency of the CPU to reduce power based on CMOS circuit technology is used. This saves power by allowing tasks to run at the appropriate voltage and frequency within the range that meets the deadlines.

Second, the present invention supports a mode in which a mixture of conventional DRAM and nonvolatile next-generation memory is used to save power. The system's power consumption can be reduced by running some of the DRAM's work in non-volatile next-generation memory that requires a continuous re-powering process to retain data.

Third, the present invention uses a task optimization method to save power. This is a technology for reducing power consumption by designating hardware resources to be allocated to tasks in advance before scheduling. The present invention intends to apply a genetic algorithm to this.

According to the method of the present invention, power consumed by the system can be greatly reduced within a range that does not violate the task deadline by using the DVFS method, the HM method, and the task optimization method in combination.

First, the DVFS (Dynamic Voltage/Frequency Scaling) method used in the present invention will be described. This is a CMOS circuit technology-based method, and was designed in the sense that if the voltage supplied to the processor is lowered by the equation shown in [Figure 1], the throughput is lowered, but the power consumption can be greatly saved as the power consumption is proportional to the square. That is, in a situation where the amount of work to be processed falls short of the processing capacity of the processor, the supply voltage of the processor is lowered to reduce power consumption and to perform within the deadline.

Second, the next-generation memory used in the present invention will be described. Since DRAM used in many existing systems is a volatile medium, a power resupply operation must be performed periodically to maintain data even in an idle state in which read and write operations are not performed. On the other hand, non-volatile memories (hereinafter referred to as LPMs) typified by PC-RAM (Phase Change Random Access Memory) and STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory), etc. can reduce power consumption. However, since such an LPM requires more access time than DRAM, in the present invention, the HM (Hybrid Memory) method using both the LPM and DRAM reduces power consumption within a range that does not violate the task deadline. .

Finally, a description will be given of a 'task optimization' method in which hardware resources to be allocated to each task in the task set are designated in advance. In the present invention, a voltage/frequency combination of a processor to perform a task and a memory type are previously determined by using a genetic algorithm, which is a type of meta-heuristic algorithm. Therefore, when there are n tasks as input, each one element is encoded into two chromosomes of length n with numbers indicating the type of memory and voltage/frequency mode assigned to each task in order. The cost function, which is the basis for solution selection, is calculated by reflecting the penalty depending on power consumption and scheduling availability, and the solution is selected using the Roulette Wheel Selection method. After that, the best approximation solution is obtained by evolving the chromosome through crossover and mutation.

[Figure 1] Power calculation formula of processor

Next, in the present invention, the worst execution time of the task is determined based on the allocated hardware resources, and it is used for scheduling by determining whether the task is schedulable or not. The worst execution time of a task is determined according to the CPU voltage/frequency mode in which the task is to be executed and the type of memory. (For example, if it is performed in low voltage/frequency mode, execution time will increase, but power consumption decreases with the square of voltage according to the equation in [Figure 1], so the total power consumption decreases.) Also, in this process, the CPU There is an overlap between the increased execution time by lowering the voltage/frequency and the increased execution time by performing in non-volatile memory. Therefore, it can be said that the worst-case execution time (ti, wcet) is determined by the slower factor among the CPU voltage/frequency mode in which the task is to be performed and the type of memory. Therefore, a function f that scales the worst-case execution time (ti) is applied in consideration of DVFS and LPM.

In addition, among the scheduling algorithms of real-time tasks, the earliest deadline first (EDF), which schedules the task with the closest deadline first, is known optimally. In this case, if scheduling is not possible with EDF, scheduling is impossible with any other algorithm. is used to determine whether scheduling is possible.

In conclusion, in order for all tasks to be executed while observing the deadline, the processor utilization U must at least satisfy the condition [Figure 2].

[Figure 2] Equation for determining whether task set scheduling is possible

To describe the above expression a little more in the text, n is the number of tasks, m is the number of cores, pii is the period of the i-th task, and ti is the number of tasks that the i-th task will normally be performed (when DVFS is not applied in DRAM). This is the worst running time. f(ti) can be said to be the worst execution time newly defined by applying DVFS and HM. If the sum of (determined worst execution time)/(period) of all tasks exceeds the number of cores, scheduling is impossible.

In the present invention, based on the above method, power consumption is minimized by allocating a processor voltage/frequency mode and memory with the lowest possible power consumption to each task within a scheduleable range of the task set.

Claims (1)

A method of reducing memory power consumption by using DRAM and non-volatile next-generation memory together for a task set consisting of hard tasks (hereinafter referred to as HM: Hybrid Memory) and a method of lowering processor power consumption by dynamically adjusting the processor voltage ( Hereinafter, the DVFS: Dynamic Voltage Frequency Scaling) method, a real-time scheduling method showing the power saving effect by using the 'task optimization' method in which the hardware resources to be allocated for the tasks of the task set are designated in advance.