KR20210148857A - Back-end-of-line selector for memory device - Google Patents

Abstract

In some embodiments, the present disclosure relates to a memory device. In some embodiments, a memory device has a substrate and a lower interconnecting metal line disposed on the substrate. The memory device also has a selector channel disposed on the lower interconnect metal line, and a selector gate electrode that wraps around the sidewall of the selector channel and is separated from the selector channel by a selector gate dielectric. The memory device also has a memory cell disposed on the selector channel and electrically coupled to the selector channel, and an upper interconnecting metal line disposed on the memory cell. A front end space is secured and more integration flexibility is provided by placing a selector within a back end interconnect structure.

Description

BACK-END-OF-LINE SELECTOR FOR MEMORY DEVICE

This application claims priority to U.S. Provisional Application No. 63/031,046, filed on May 28, 2020, the contents of which are incorporated herein by reference in their entirety.

Many modern electronic devices include an electronic memory configured to store data. Electronic memory may be volatile memory or non-volatile memory. Volatile memory stores data when power is applied, whereas non-volatile memory can store data when power is removed. Resistive random access memory is a promising candidate for next-generation non-volatile memory technology. This is because resistive random access memory devices provide many advantages including fast write time, high durability, low power consumption, and low vulnerability to radiation damage.

Aspects of the present disclosure are best understood from the detailed description below when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features have not been drawn to scale. Indeed, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.
1 illustrates a cross-sectional view of some embodiments of a memory device that includes a back-end-of-line (BEOL) selector.
2 illustrates a cross-sectional view of some additional embodiments of a memory device that includes a BEOL selector.
3 illustrates a block diagram of some embodiments of a portion of a memory array having a plurality of memory units.
4A illustrates a perspective view of some embodiments of a memory device that includes stacked memory arrays.
4B illustrates a cross-sectional view of some embodiments of the memory device of FIG. 4A taken along a row direction.
4C illustrates a cross-sectional view of some embodiments of the memory device of FIG. 4A taken along a column direction.
5A illustrates a perspective view of some additional embodiments of a memory device that includes stacked memory arrays.
5B illustrates a cross-sectional view of some embodiments of the memory device of FIG. 5A taken along a row direction.
5C illustrates a cross-sectional view of some embodiments of the memory device of FIG. 5A taken along a column direction.
6-7 illustrate top views of some embodiments of a memory array showing corresponding selectors.
8A-23C illustrate various views of some embodiments of a method of forming a memory device including a BEOL selector.
24 illustrates a flow diagram of some embodiments of a method of forming a memory device including a BEOL selector.

The disclosure below provides many different embodiments or examples for implementing different features of the presented subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following details the formation of a first feature on or over a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and also It may include embodiments in which additional features may be formed between the first and second features such that the features and second features may not be in direct contact. Also, this disclosure may repeat reference numbers and/or letters in different examples. These repetitions are for the purpose of clarity, and such repetitions themselves do not delineate the relationship between the various embodiments and/or configurations disclosed. However, features described in one figure may be incorporated in embodiments described in connection with another figure as additional embodiments, where applicable, and may not be repeated for reasons of simplification.

Also, spatially relative terms such as “below,” “below,” “below,” “above,” “above,” and the like are used in one reference to another element(s) or feature(s) illustrated in the figures. It may be used herein for ease of description to describe the relationship of elements or features. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), or spatially relative descriptors used herein may be interpreted similarly accordingly.

The semiconductor industry continues to develop a variety of electronic devices (eg, transistors, diodes, resistors, capacitors, etc.) by, for example, reduction of minimum feature sizes and/or arrangement of electronic devices closer to each other. The integration density has been improved, which allows more components to be integrated into a given area. As manufacturing nodes continue to shrink, front-end-of-line (FEOL) transistors are becoming increasingly popular in high-density non-volatile memory (NVM), such as in magnetoresistive random access memory (MRAM) devices. It becomes a major bottleneck for driving non-volatile memories). The operation of MRAM requires high write currents (eg greater than 200 μA/μm). One way to achieve this high write current is to increase the transistor dimensions or employ multiple transistors in one memory element. For example, some proposed schematics use two or more transistors for one memory element to have sufficient drive current. These approaches impose a large FEOL area penalty.

In view of the above, the present disclosure relates to a back end of line (BEOL) transistor as a selector for a memory device and associated manufacturing methods for enabling high density non-volatile memory devices. In some embodiments, a memory device is disposed over a substrate and includes a back end interconnect structure comprising a lower interconnect metal line and an upper interconnect metal line. A selector and a memory cell electrically connected to the selector are disposed between the upper interconnect metal line and the lower interconnect metal line. By placing the selector in the back end interconnect structure above the lower interconnect metal line, front end space is freed up and more integration flexibility is provided.

In some further embodiments, the selector has a vertical gate all around structure that provides better gate control compared to a planar selector. The selector may include a selector channel disposed on the lower interconnecting metal line, and a selector gate electrode that wraps around sidewalls of the selector channel and is separated from the selector channel by a selector gate dielectric. The lower interconnect metal line can serve as one source/drain region for the selector and either a bit line or a source line for the memory device. A memory cell may be disposed on a selector channel, and an upper interconnecting metal line may be arranged over the memory cell and serve as another source/drain region for the selector and the other of a source line or bit line for the memory device. can do. By stacking the memory cells directly on top of the selector channel, the wire connection between the memory cell and the selector channel is eliminated and electrical performance is improved.

In some embodiments, the selector channel may be or consist of polysilicon, amorphous silicon, or an oxide semiconductor (OS) material. For example, the selector channel may be or consist of indium gallium zinc oxide (IGZO). The OS material channel region provides ultra-low leakage current (I _ON /I _OFF >10 ¹³ ) and can be used to fabricate BEOL-compatible transistors for memory devices. In some embodiments, the selector channel may have various shapes. For example, the selector channel may be a circle, square, single fin, multiple fin, oval, or column with a top view of other application shapes. The selector gate electrode may have a block shape or may be a conformal layer surrounding the selector channel.

1 illustrates a cross-sectional view of some embodiments of a memory device 100 that includes a selector 118 . In some embodiments, the memory device 100 includes an interconnect structure 104 disposed over a substrate 102 and a memory cell 108 disposed within the interconnect structure 104 . The interconnect structure 104 is disposed within the lower ILD layer 106L and is arranged between the memory cell 108 and the substrate 102, a lower interconnect metal line 130, and the upper ILD layer 106U and within the memory cell. a plurality of stacked interconnect metal layers including a top interconnect metal line 116 disposed over 108 . The lower ILD layer 106L and the upper ILD layer 106U may each include one or more dielectric layers.

The memory cell 108 may include a bottom electrode 110 , a data storage structure 112 arranged over the bottom electrode 110 , and a top electrode 114 arranged over the data storage structure 112 . Top interconnect metal line 116 may extend through top ILD layer 106U to reach top electrode 114 . In some embodiments, bottom electrode 110 and top electrode 114 each include tantalum nitride, titanium nitride, tantalum, titanium, platinum, nickel, hafnium, zirconium, ruthenium, iridium, or the like. In some embodiments, the data storage structure 112 is a magnetic tunnel junction (MTJ) or spin valve. In this case, the memory cell 108 is referred to as a magnetic memory cell, and the memory device 100 made up of an array of such memory cells 108 is referred to as a magnetoresistive random access memory (MRAM) device. In some alternative embodiments, data storage structure 112 is a high-k dielectric material or other semiconductor material, such as nickel oxide (NiO), strontium titanate (Sr(Zr)TiO ₃ ), hafnium dioxide (HfO ₂ ) , zirconium dioxide (ZrO ₂ ), aluminum oxide (Al ₂ O ₃ ), tantalum pentoxide (Ta ₂ O ₅ ), hafnium aluminum oxide (HfAlO), hafnium zirconium oxide (HfZrO), and the like. In this case, the memory cell 108 is referred to as a resistive memory cell, and the memory device 100 made up of an array of such memory cells 108 is referred to as a resistive random access memory (ReRAM) device. In some further embodiments, data storage structure 112 comprises a _{phase change material, such as Ge 2} Sb ₂ Te _{5 ,} and memory device 100 comprised of an array of such data storage structures 112 is a PCRAM device. is referred to Other structures for data storage structure 112 and/or other memory cell types for memory cell 108 are also possible.

The selector 118 is electrically coupled to the memory cell 108 and is configured to control write/read operations of the memory cell 108 by controlling the current flowing through the selector 118 . In some embodiments, the selector 118 is disposed below and electrically coupled to the bottom electrode 110 of the memory cell 108 . In some further embodiments, the selector 118 wraps around a sidewall of the selector channel 126 , and the selector channel 126 disposed between the bottom interconnection metal line 130 and the bottom electrode 11 , and includes a selector gate and a selector gate electrode 124 separated from the selector channel 126 by a dielectric 132 . During operation, a biasing voltage is applied between the lower interconnect metal line 130 and the upper interconnect metal line 116 . A gate voltage is applied to the selector gate electrode 124 . When the gate voltage is sufficient, the channel path of the selector channel 126 is turned on and the memory cell 108 can be read/written. By having the selector gate electrode 124 wrap the entire selector channel 126, better gate control is provided compared to using a planar selector. In some embodiments, the memory cell 108 is disposed directly over the selector channel 126 . The memory cell 108 may have sidewalls vertically aligned with the sidewalls of the selector channel 126 . By placing the selector 118 back-end within the interconnect structure 104 , the front-end is made available for other logic functions and more integration flexibility is provided. By stacking the memory cell 108 directly over the selector channel 126 , the hard-wired interconnection between the memory cell 108 and the selector channel 126 is eliminated and electrical performance is improved.

In some embodiments, the selector channel 126 comprises polysilicon or amorphous silicon. In some other embodiments, the selector channel 126 comprises an oxide semiconductor (OS) material. For example, the channel layer may be formed of, for example, indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium tin oxide or indium titanium oxide (ITO) or other oxide semiconductor. can be made of materials. The selector channel 126 may have a thickness ranging from about 10 nm to about 50 nm. The OS material channel region provides ultra-low leakage and can be used to fabricate BEOL-compatible transistors for memory devices. In some embodiments, the selector gate dielectric 132 is aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), tantalum oxide (Ta ₂ O ₅ ), zirconium oxide (ZrO ₂ ), titanium oxide (TiO _{2 )} ), strontium titanium oxide (SrTiO ₃ ) or other high-k dielectric materials. The selector gate dielectric 132 may have a thickness ranging from about 1 nm to about 15 nm or from about 1 nm to about 5 nm. In some embodiments, the lower interconnection metal line 130 and the upper interconnection metal line 116 may include metallic materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), copper (Cu), etc. include The lower interconnect metal line 130 and the upper interconnect metal line 116 may each have a thickness ranging from about 5 nm to about 30 nm.

2 illustrates in greater detail a cross-sectional view of a memory device 200 including a selector 118 for inserting into a back end of line in accordance with some further embodiments. 2 , in some embodiments, the logic device 202 is disposed within the substrate 102 and the ILD layer 106a. The logic device 202 may include a transistor device (eg, a MOSFET device, a BJT, etc.). By inserting the selector 118 into the back end of the line rather than the front end of the line, other front end devices, including the logic device 202, are not limited by the structures of the select device, and more integration flexibility is provided. . The logic device 202 may be a planar device, a FinFET device, a nanowire device, or other gate-all-arround (GAA) devices.

An interconnect structure 104 is disposed over the logic device 202 and the substrate 102 . The interconnect structure 104 includes a plurality of stacked interconnect metal layers surrounded by the stacked ILD layers and configured to provide electrical connection. In some embodiments, interconnect metal layers are conductive contact 204 landing on logic device 202 and interconnect lines disposed over conductive contact 204 and surrounded by stacked ILD layers 106a - 106c. 206a - 206c and interconnect vias 208a - 208b. In some embodiments, the stacked ILD layers 106a - 106c are silicon dioxide, fluorosilicate glass, silicate glass (eg, borophosphate silicate glass (BSG), phosphosilicate glass (PSG, phosphosilicate glass), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), etc. Some In embodiments, adjacent ILD layers 106a - 106c may be separated by an etch stop layer (not shown) comprising a nitride, carbide, etc. The plurality of metal layers may be separated from an underlying location industrially closer to the substrate. The upper position away from the substrate is designated by the numbers M0, M1, M2, M3....

Selector 118 is disposed over at least some of the plurality of stacked interconnect metal layers, for example over interconnect lines 206a - 206c as shown in FIG. 2 . In some embodiments, lower ILD layer 106L is disposed over interconnect lines 206a - 206c and stacked ILD layers 106a - 106c , and lower interconnect metal line 130 is lower ILD layer 106L ) is placed in In some embodiments, the selector 118 includes a selector channel 126 disposed on a lower interconnecting metal line 130 . A selector gate dielectric 132 is disposed over the lower ILD layer 106L and extends upwardly along sidewalls of the selector channel 126 . The selector gate dielectric 132 is aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), tantalum oxide (Ta ₂ O ₅ ), zirconium oxide (ZrO ₂ ), titanium oxide (TiO ₂ ), strontium titanium oxide ( may be or consist of one or more dielectric layers of high-k dielectric materials, such as SrTiO _{3 ) and the like.} The selector gate dielectric 132 may be a conformal liner lining the top surface of the lower ILD layer 106L and the sidewall surface of the selector channel 126 . A selector gate electrode 124 is disposed on the selector gate dielectric 132 and may wrap around a sidewall of the selector channel 126 . By having the selector gate electrode 124 wrap the entire selector channel 126, better gate control is provided compared to using a planar selector.

In some embodiments, the memory cell 108 is disposed directly on top of the top of the selector channel 126 . The memory cell 108 may have sidewalls vertically aligned with the sidewalls of the selector channel 126 . In some embodiments, the upper interconnect metal line 116 is disposed within the upper ILD layer 106U and directly over the memory cell 108 . Lower ILD layer 106L and upper ILD layer 106U may each include one or more dielectric layers (eg, oxide, low-k dielectric, or ultra low-k dielectric). By placing the selector 118 and the memory cell 108 between the upper interconnect metal line 116 and the lower interconnect metal line 130 in the interconnect structure 104 , front end space is saved for other logic functions. and more integration flexibility is provided. By stacking the memory cell 108 directly over the selector channel 126 , the hard-wired interconnection between the memory cell 108 and the selector channel 126 is eliminated and electrical performance is improved.

Interconnection lines 206a - 206c below lower interconnection metal line 130 are shown for purposes of non-limiting illustration only. Selector 118 and memory cell 108 may be flexibly positioned within various metal layers. The exact location of selector 118 and memory cell 108 may be determined with reference to routing needs, thus providing design flexibility.

3 illustrates a block diagram of a portion of a memory array 300 having a plurality of memory units C11 - C33. The memory units C11 - C33 are arranged in rows and/or columns in the memory array 300 . Although the memory array 300 is illustrated as having three rows and three columns, the memory array 300 may have any number of rows and any number of columns. Each of memory units C11 - C33 may include a memory cell 108 coupled to a selector 118 . The selector 118 is configured to selectively provide access to the selected memory cell 108 while suppressing leakage current through the unselected memory units. The device structures disclosed in connection with FIG. 1 or 2 may be incorporated as some embodiments of individual memory units C11 - C33 of memory array 300 .

The memory units C11 - C33 may be controlled through bit lines BL ₁ -BL ₃ , word lines WL ₁ -WL ₃ , and source lines SL ₁ -SL ₃ . The word lines WL ₁ -WL ₃ may be used to operate the selectors 118 corresponding to the memory units C11 - C33 . When the selector 118 for a memory cell 108 is turned on, a voltage may be applied to that memory cell. The bit line decoder 119 applies a read voltage or a write voltage to one of the _{bit lines BL 1} -BL _{3 .} The word line decoder 127 _{applies a different voltage to one of the word lines WL 1} -WL ₃ , which turns on the selector 118 for the memory units C11 - C33 in the corresponding row. Together, these operations cause a read voltage or a write voltage to be applied to a selected one of the memory units C11-C33.

Applying a voltage to the selected memory cell 108 results in a current. During read operations, the sense amplifier 117 determines the programming state of the selected memory cell based on the current. The sense amplifier 117 may be connected to the _{source lines SL 1} -SL _{3 .} Alternatively, the sense amplifier 117 may be connected to the _{bit lines BL 1} -BL _{3 .} The sense amplifier 117 may determine the programming state of the memory cell 108 based on the current. In some embodiments, the sense amplifier 117 determines the programmed state of the memory cell 108 by comparing the current to one or more reference currents. Sense amplifier 117 may communicate programming state decisions to an I/O buffer that may be coupled to driver circuitry to implement write and write verify operations. The driver circuit is configured to select a voltage to apply to the selected memory unit for read, write, and write verify operations.

It will be appreciated that the critical voltage is the absolute value of the potential difference across the memory cell 108 . In the case of memory array 300 , applying a voltage to a selected memory cell _{operates word lines WL 1 -} WL ₃ to turn on the selector 118 corresponding to that memory cell, and uses driver circuitry to activate that cell. This means making the absolute value of the potential difference between the bit lines BL ₁ -BL ₃ and the source lines SL ₁ -SL _{3 corresponding to the voltage equal to the voltage.} In some embodiments, applying a voltage to the memory cell is accomplished by coupling the corresponding bit line BL ₁ -BL _{3 to a voltage while maintaining the corresponding source line SL 1} -SL _{3 at ground potential.} Also, the source lines SL ₁ -SL ₃ may be maintained at different potentials, _{and roles of the bit lines BL 1} -BL ₃ and the source lines SL ₁ -SL ₃ may be reversed.

4A-4C provide various views of a memory device 400 including stacked memory arrays in accordance with some embodiments. Memory device 400 includes stacked memory arrays 300a and 300b , each of which is disposed within interconnect structure 104 and has a plurality of selectors coupled corresponding to a plurality of memory cells 108 ( 118) including a plurality of memory units. Selectors 118 are configured to selectively provide access to selected memory cells 108 while suppressing leakage current through unselected memory units. The memory array 300 and memory units C11 - C33 disclosed in connection with FIG. 3 may be incorporated as some embodiments of the memory arrays 300a , 300b of the memory device 400 . The device structures disclosed in connection with FIG. 1 or 2 may be incorporated as some embodiments of memory units of memory array 400 . Although the memory device 400 is illustrated as having two stacked memory arrays 300a, 300b for purposes of illustration, the memory device 400 includes more memory arrays monolithically stacked for greater integration. can have

As shown in FIG. 4A , which is a perspective view of a memory device 400 , and FIG. 4B , which is a cross-sectional view of the memory device 400 along a row direction, in accordance with some embodiments, one row of memory units includes both ends of the memory units. The first signal line and the second signal line disposed thereon may be shared. For example, the memory units C11 , C12 , and C13 may include a common bit line BL ₁ disposed below and connected to the selectors 118 , and a common source line SL disposed over and coupled to the memory cells 108 . ₁ ) can be shared. In addition, as shown in FIG. 4C , which is a cross-sectional view of the memory device 400 along a column direction according to some embodiments, the memory units in one column connect a third signal line connecting the gate electrodes of the selectors 118 . can share For example, the memory units C11 , C21 , and C31 may share _{a common word line WL 1 surrounding and connecting the respective selector gate electrodes 124 of the selectors 118 .} The first, second and third signal lines may be further connected to higher level interconnects through vias and more metal layers not shown in the figure. In some embodiments, common word line WL ₁ and selector gate electrodes 124 include the same conductive material or are made of one seamless, integral layer. That is, the selector gate electrodes 124 may extend between the memory units and may also serve as a common word line. In some embodiments, the selector gate electrodes 124 are a conformal conductive layer disposed between the rows of selectors 118 and extending upwardly along sidewalls of the selector channels 126 .

5A-5C provide various views of a memory device 500 including stacked memory arrays in accordance with some additional embodiments. Compared to FIGS. 4A-4C , in some alternative embodiments, the selector gate electrodes 124 have a different shape. A plurality of conductive blocks are disposed on the selector gate dielectric 132 , extend in parallel and along a column direction, and serve as the _{selector gate electrodes 124 and common word lines WL 1} , WL ₂ , WL _{3 .} and provides control to the selector channels 126 surrounding each.

6-7 illustrate top views of the memory array 300 of FIG. 3 showing corresponding selectors 118 in accordance with some embodiments. The numbers are labeled only for one memory unit C11 for the sake of simplicity, but similarly apply to other memory units. 6-7 , the selector channels 126 may be separate islands surrounded by the selector gate dielectric 132 . The selector gate dielectric 132 may have distinct ring shapes in plan view. The selector channels 126 may have a variety of shapes. The selector gate electrode 124 surrounds the perimeter of the selector gate dielectric 132 . In some embodiments, the selector channel 126 has a centrosymmetric shape, such as a circle, square, or other orthogonal polygons as shown in FIG. 6 . In some alternative embodiments, the selector channel 126 is common word line in the (WL _1, WL _2, WL ₃₎ common word line than the width direction in the longitudinal direction of the (WL _1, WL _2, WL _{3) The word lines WL 1} , WL ₂ , WL ₃ need to be separated so that the area of the selector channel 126 can be enlarged by arranging a longer length of the selector channel 126 here. Examples of such selector channels 126 include ovals or rectangles as shown in FIG. 7 . In some further alternative embodiments, the selector channel 126 has a plurality of fins to further enlarge the perimeter of the selector channel 126 such that the selector channel 126 is better controlled by the selector gate electrodes 124 . may include Other applicable shapes not shown in the figures (eg, square, multiple fins, multiple circular fins, etc.) are also possible.

8A-18C illustrate various views of some embodiments of a method of forming a memory device including a BEOL selector. Although FIGS. 8A-18C have been described in connection with the method, it will be understood that the structures disclosed in FIGS. 8A-18C are not limited in such a way and may be independent as structures separate from the method.

As shown in the perspective view of FIG. 8A and the cross-sectional view of FIG. 8B , a substrate 102 is provided and an underlying ILD layer 106L is formed over the substrate 102 . In various embodiments, the substrate 102 is a semiconductor wafer and/or any type of semiconductor body (eg, silicon, SiGe, SOI, etc.) such as a semiconductor wafer and/or one or more dies on the wafer, as well as any other type associated therewith. semiconductor and/or epitaxial layers. Semiconductor devices are formed in the substrate 102 . Semiconductor devices may include transistor devices (eg, MOSFET devices, BJTs, etc.). Semiconductor devices may include planar devices, FinFET devices, nanowire devices, or other gate-all-arround (GAA) devices. For example, as shown in FIG. 8B , the logic device 202 may be formed in the substrate 102 and surrounded by the first ILD layer 106a. Prior to forming the lower ILD layer 106L, one or more interconnecting metal layers are formed on the substrate 102 . In some embodiments, the one or more interconnect metal layers include a conductive contact 204 for the logic device 202 , a first interconnect line 206a of the first ILD layer 106a , and a second ILD layer ( by forming a second interconnection line 206b and a first interconnection via 208a of 106b and a third interconnection line 206c and a second interconnection via 208b of the third ILD layer 106c. can be formed. The one or more interconnect metal layers repeatedly form an ILD layer (eg, oxide, low-k dielectric, or ultra low-k dielectric) over the substrate 102 , and selectively etching the ILD layer to vias within the ILD layer. Define holes and/or trenches, form conductive material (eg, copper, aluminum, etc.) within the via holes and/or trenches, and perform a planarization process (eg, chemical mechanical planarization process) over the ILD layer It can be formed by removing excess conductive material from Conductive contact 204 , interconnect line 206a / 206b / 206c , and interconnect via 208a / 208b shown in FIG. 8B are shown for illustrative purposes, and interconnect lines, vias, and bottom ILD layer are shown. More or fewer layers of these can be tailored for a variety of applications. Semiconductor devices and interconnecting metal layers are omitted from the figures below.

As shown in the perspective view of FIG. 9A and the cross-sectional views of FIGS. 9B and 9C , in some embodiments, a plurality of lower interconnecting metal lines, such as 130a, 130b, 130c shown in the figures, are connected to the lower interconnection structure 104a. ) as part of the lower ILD layer 106L. The lower interconnecting metal lines 130a , 130b , 130c may function as first signal lines of the memory devices. In some embodiments, the first signal lines are bit lines. The lower interconnect metal lines 130a, 130b, 130c selectively etch the lower ILD layer 106L to define a trench in the lower ILD layer 106L, and a conductive material (e.g., tungsten, copper, aluminum, etc.) and performing a planarization process (eg, a chemical mechanical planarization process) to remove excess conductive material from over the lower ILD layer 106L. In some embodiments, lower interconnection metal lines 130a , 130b , 130c are formed by the same conductive material as interconnect lines 206a - 206c . In some alternative embodiments, the lower interconnect metal lines are formed by a different conductive material than interconnect lines 206a - 206c. In some embodiments, lower interconnecting metal lines 130a , 130b , 130c are formed by a deposition process followed by a planarization process (eg, a chemical mechanical planarization process) and have a thickness in a range of about 5 nm to about 20 nm. can have

As shown in the perspective view of FIG. 10A and the cross-sectional views of FIGS. 10B and 10C , in some embodiments, a selector channel layer 126 ′ and a stack 108 ′ of memory layers are disposed on the lower interconnect structure 104a . is formed In some embodiments, the selector channel layer 126 ′ and the memory layers 108 ′ may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or atomic layer deposition (ALD). layer deposition) and the like. The selector channel layer 126 ′ may have a thickness ranging from about 10 nm to about 50 nm. In some embodiments, the selector channel layer 126 ′ includes an oxide semiconductor (OS) material. For example, the selector channel layer 126 ′ may be made of, for example, indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium tin oxide or indium titanium oxide (ITO) or other oxide semiconductor material. The OS material provides ultra-low leakage current (I _ON /I _OFF >10 ¹³ ) and is compatible with BEOL processes. In some embodiments, the memory layers 108 ′ include a bottom electrode layer and a top electrode layer separated by a data storage structure. In some embodiments, the bottom electrode layer and the top electrode layer are made of tantalum nitride, titanium nitride, tantalum, titanium, platinum, nickel, hafnium, zirconium, ruthenium, iridium, or the like. The data storage structure may be made of a magnetic tunnel junction (MTJ), a spin valve, a ferroelectric capacitor or junction, a high-k dielectric material, or a phase change material. Other structures for the stack of memory layers 108' are also possible. In some embodiments, a hard mask layer (not shown) may be formed over the stack of memory layers 108 ′ to provide a masking function for a subsequent patterning process. In various embodiments, the hard mask layer may include a metal (eg, titanium, titanium nitride, tantalum, etc.) and/or a dielectric material (eg, silicon-nitride, silicon-carbide, etc.).

As shown in the perspective view of FIG. 11A and the cross-sectional views of FIGS. 11B and 11C , in some embodiments, the selector channel layer 126 ′ and the stack 108 ′ of memory layers are arranged in rows and columns. ) and an array of memory cells 108 . In some embodiments, selector channels 126 and memory cells 108 are formed with vertically aligned sidewalls. By sequentially forming the memory layers 108' and the selector channel layers 126' prior to patterning to form the selector channels 126 and the memory cells 108, manufacturing processes are simplified. Also, by stacking the memory cells 108 directly over the selector channels 126 , the connection between the memory cells 108 and the selector channels 126 is eliminated, thus improving electrical performance. In some embodiments, the selector channels 126 may be formed as circles, squares, or other orthogonal polygons. In some alternative embodiments, the selector channels 126 may have an axisymmetric shape, such as an elliptical or rectangular shape. In some further alternative embodiments, the selector channels 126 may include multiple pins to further enlarge the perimeter of the selector channels 126 , thus increasing control of the selector channels 126 . have.

In some alternative embodiments, the selector channel layer 126 ′ and the stack 108 ′ of memory layers are formed and patterned separately. The stack of memory layers 108' may be formed after patterning the selector channel layer 126' to form the selector channels 126'. The stack of memory layers 108' is then patterned by a further additional patterning process. For example, a first patterning process is performed to define a top electrode and data storage structure. Thereafter, sidewall spacers may be formed along the top electrode and sidewalls of the data storage structure, and used as a mask with the top electrode to perform a second patterning process on the bottom metal layer to define the bottom electrode. By forming and patterning the stack of memory layers 108 ′ after forming the selector channels 126 , more flexibility is provided in the layout design of the memory cells 108 .

As shown in the perspective view of FIG. 12A and the cross-sectional views of FIGS. 12B and 12C , in some embodiments, the selector gate dielectric layer 132' comprises a lower ILD layer 106L and lower interconnecting metal lines 130a, 130b. , 130c) and extends upwardly to cover the sidewalls of the selector channels 126 and the memory cells 108 . In some embodiments, the select gate dielectric layer 132 ′ is formed by deposition techniques such as atomic layer deposition (ALD). The selector gate dielectric layer 132 ′ may have a thickness in the range of about 1 nm to about 15 nm. In some embodiments, the selector gate dielectric layer 132 ′ is, among others, aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), tantalum oxide (Ta ₂ O ₅ ), zirconium oxide (ZrO ₂ ), titanium oxide. (TiO ₂ ), strontium titanium oxide (SrTiO ₃ ), or other high-k dielectric materials.

As shown in the perspective view of FIG. 13A and the cross-sectional views of FIGS. 13B and 13C , in some embodiments, the selector gate electrode layer 124 ′ surrounds the selector channels 126 and the memory cells 108 . It is formed on the dielectric layer 132'. In some embodiments, the selector gate electrode layer 124 ′ is formed by a deposition process. The selector gate electrode layer 124 ′ may have a thickness ranging from about 20 nm to about 150 nm. In some embodiments, the selector gate electrode layer 124' is made of titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), copper (Cu) or other CMOS contact metals and/or doped semiconductor material ( For example, p-doped or n-doped polysilicon).

As shown in the perspective view of FIG. 14A and the cross-sectional views of FIGS. 14B and 14C , in some embodiments, the selector gate electrode layer 124 ′ is patterned to form a plurality of selector gate electrodes 124 . In some embodiments, the plurality of selector gate electrodes 124 are lowered to a position substantially aligned with a top surface of the selector channels 126 , and a plurality of parallel rows each connecting the column of selector channels 126 . It is further patterned as conductive lines. A plurality of parallel conductive lines may act as word lines for the memory device.

As shown in the perspective view of FIG. 15A and the cross-sectional views of FIGS. 15B and 15C , in some embodiments, the selector gate dielectric layer 132 ′ is patterned to form the selector gate dielectric 132 . In some embodiments, a masking layer (not shown) is used to protect the selector gate dielectric layer 132' between the memory cells from being removed during the patterning process. The selector gate dielectric layer 132 ′ outside the memory region may be removed depending on the masking layer or other structures with high selectivity to the selector gate dielectric layer 132 ′. For example, the selector gate electrodes 124 may be used with a masking layer during the patterning process, and the formed selector gate dielectric 132 may have outer sidewalls aligned with the sidewalls of the selector gate electrodes 124 . . The selector gate dielectric 132 may cover the entire sidewalls of the memory cells 108 and thus may provide isolation and protection for the memory cells 108 .

As shown in the perspective view of FIG. 16A and the cross-sectional views of FIGS. 16B and 16C , in some embodiments, top ILD layer 106U includes memory cells 108 , selector gate dielectric 132 and selector gate electrodes 124 . ) is formed on A plurality of upper interconnect metal lines, such as 116a, 116b, 116c shown in the figures, are formed in the upper ILD layer 106U as part of the upper interconnect metal layer 104b. The plurality of upper interconnecting metal lines 116a , 116b , 116c may function as second signal lines of the memory devices. In some embodiments, the second signal lines are source lines. The upper interconnect metal lines 116a, 116b, 116c selectively etch the upper ILD layer 106U to define a trench in the upper ILD layer 106U, and a conductive material (e.g., tungsten, copper, aluminum, etc.) and performing a planarization process (eg, a chemical mechanical planarization process) to remove excess conductive material from over the upper ILD layer 106U. In some embodiments, the upper interconnecting metal lines 116a , 116b , 116c are formed by the same conductive material as the lower interconnecting metal lines 130a , 130b , 130c . In some alternative embodiments, the upper interconnecting metal lines 116a , 116b , 116c are formed by a different conductive material than the lower interconnecting metal lines 130a , 130b , 130c . In some embodiments, the upper interconnecting metal lines 116a , 116b , 116c are formed by a deposition process followed by a planarization process (eg, a chemical mechanical planarization process) and have a thickness in a range of about 5 nm to about 20 nm. can have

As shown in the perspective view of FIG. 17A and the cross-sectional views of FIGS. 17B and 17C , the processes described in FIGS. 8A-16C may be repeated one or more times to form additional memory arrays stacked thereon. For example, the second memory array 300b is shown in the drawings stacked on the first memory array 300a.

As shown in the perspective view of FIG. 18A and the cross-sectional views of FIGS. 18B and 18C , additional interconnect structures are formed for the memory arrays. For example, interconnect vias may be formed through the ILD layers 106L, 106U reaching the signal lines.

19A-23C illustrate various views of some embodiments of a method of forming a memory device including an alternative BEOL selector to FIGS. 13A-18C having selector gate electrodes 124 having a different shape. 19A-19C, the selector gate electrode layer 124' is a conformal conductive layer lining the top surface of the selector gate dielectric layer 132' on the selector gate dielectric layer 132'. is formed 20A-20C , the selector gate electrode layer 124 ′ is patterned to form a plurality of selector gate electrodes 124 lining the sidewall surfaces of the selector channels 126 . In some embodiments, the plurality of selector gate electrodes 124 are lowered to a position lower than the top surface of the memory cells 108 , further as a plurality of parallel conductive lines each connecting the column of selector channels 126 . patterned. A plurality of parallel conductive lines may act as word lines for the memory device. 21A-21C , the selector gate dielectric layer 132 ′ is patterned to form the selector gate dielectric layer 132 . In some embodiments, selector gate dielectric 132 may have outer sidewalls aligned with sidewalls of selector gate electrodes 124 . The selector gate dielectric 132 may cover the entire sidewalls of the memory cells 108 and thus may provide isolation and protection for the memory cells 108 . 22A-22C , an upper ILD layer 106U is formed over the memory cells 108 , the selector gate dielectric 132 and the selector gate electrodes 124 . A plurality of upper interconnect metal lines, such as 116a, 116b, 116c shown in the figures, are formed in the upper ILD layer 106U as part of the upper interconnect metal layer 104b. The plurality of upper interconnecting metal lines 116a , 116b , 116c may function as second signal lines of the memory devices. In some embodiments, the second signal lines are source lines. 23A to 23C , the second memory array 300b is formed on the first memory array 300a. Additional memory arrays may subsequently be formed over the second memory array 300b. Additionally, additional interconnect structures are formed for memory arrays including through-substrate vias, and may also include more interconnect metal layers formed over top interconnect metal layer 104b.

24 illustrates a flow diagram of some embodiments of a method 2400 of forming a memory device including a BEOL selector.

Although method 2400 is illustrated and described herein as a series of acts or events, it will be appreciated that the order in which they appear should not be construed in a limiting sense. For example, some acts may occur in a different order than that shown and/or described herein and/or may occur concurrently with other acts or events. Moreover, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Furthermore, one or more of the acts depicted herein may be performed in one or more separate acts and/or steps.

At operation 2402 , a substrate is prepared and a lower interconnect metal layer is formed in a lower inter-level dielectric (ILD) layer over the substrate. In some embodiments, the logic devices may be formed in the substrate prior to forming the underlying interconnect metal layer. 8A-9C illustrate some embodiments corresponding to operation 2402 .

At operation 2404 , an array of selectors and an array of memory cells are formed into rows and columns. In some embodiments, operation 2404 may be formed through operations 2406 - 2412 .

At operation 2406 , in some embodiments, a stack of selector channel layer and memory layers is formed on the underlying interconnect metal layer. 10A-10C illustrate some embodiments corresponding to operation 2406 .

At operation 2408 , the stack of selector channel layer and memory layers is patterned to form selector channels and memory cells. 11A-11C illustrate some embodiments corresponding to operation 2408 .

At operation 2410 , in some embodiments, a selector gate dielectric layer is formed to cover the array of memory cells and the selector channels, and a selector gate electrode layer is formed over the selector gate dielectric layer. 12A-13C or 19A-19C illustrate some embodiments corresponding to operation 2410 .

At operation 2412 , the selector gate electrode layer is patterned to form a plurality of selector gate electrodes, and the selector gate dielectric layer is patterned to form a selector gate dielectric layer. 14A-15C or 20A-21C illustrate some embodiments corresponding to operation 2412 .

At operation 2414 , a top interconnect metal layer having a plurality of top interconnect metal lines is formed to be formed within top ILD layer 106U in some embodiments. 16A-16C or 22A-22C illustrate some embodiments corresponding to operation 2414 .

At operation 2416 , one or more additional memory arrays are stacked. 17A-17C or 23A-23C illustrate some embodiments corresponding to operation 2416 .

At operation 2418 , additional interconnect structures are formed for the memory arrays. 18A-18C or 23A-23C illustrate some embodiments corresponding to operation 2418 .

Accordingly, in some embodiments, the present disclosure relates to a memory device (eg, MRAM or ReRAM, or PCRAM device) having a BEOL selector inserted into a BEOL interconnect structure.

In some embodiments, the present disclosure relates to a memory device. The memory device includes a substrate and an underlying interconnecting metal line disposed over the substrate. The memory device further includes a selector channel disposed over the lower interconnect metal line, and a selector gate electrode that wraps around sidewalls of the selector channel and is separated from the selector channel by a selector gate dielectric. The memory device further includes a memory cell disposed over the selector channel and electrically coupled to the selector channel, and an upper interconnecting metal line disposed over the memory cell.

In other embodiments, the present disclosure relates to a memory device. A memory device includes a substrate and an interconnect structure disposed over the substrate. The interconnect structure has a plurality of interconnecting metal layers stacked on top of each other and including a plurality of lower interconnecting metal lines and a plurality of upper interconnecting metal lines. The memory device further includes a plurality of selectors disposed within the interconnect structure and over the underlying interconnect metal lines. The plurality of selectors are arranged in an array of rows and columns. The memory device further includes a plurality of memory cells disposed on top of the corresponding plurality of selectors in an array of rows and columns.

In yet other embodiments, the present disclosure relates to a method of forming a memory device. The method includes forming a lower interconnect metal layer over a substrate, and forming a plurality of selectors and a plurality of memory cells over the lower interconnect metal layer. The method further includes forming an upper interconnect metal layer over the plurality of memory cells.

The foregoing has outlined features of some embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. You have to realize that you can. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that those skilled in the art can make various changes, substitutions, and alterations in the present invention without departing from the spirit and scope of the present disclosure. should know

Examples

Embodiment 1. A memory device comprising:

Board;

a lower interconnection metal line disposed over the substrate;

a selector channel disposed above the lower interconnecting metal line;

a selector gate electrode wrapped around a sidewall of the selector channel and separated from the selector channel by a selector gate dielectric;

a memory cell disposed over the selector channel and electrically coupled to the selector channel; and

a top interconnect metal line disposed over the memory cell

A memory device comprising:

Example 2. The method of Example 1,

and the memory cell is in direct contact with the selector channel.

Example 3. The method of Example 1,

and the selector channel has a sidewall aligned with a sidewall of the memory cell.

Example 4. The method of Example 1,

and the selector gate electrode comprises a metal layer covering a lower sidewall of the selector gate dielectric.

Example 5. The method of Example 1,

wherein the selector channel comprises an oxide semiconductor material.

Example 6. The method of Example 1,

wherein the selector channel has a circular or elliptical shape in plan view.

Example 7. The method of Example 1,

The memory cell comprises:

a bottom electrode disposed above the selector channel;

a data storage structure disposed on the lower electrode; and

a top electrode disposed over the data storage structure

A memory device comprising:

Example 8. The method of Example 1,

wherein the selector channel has a square or rectangular shape in plan view.

Example 9. The method of Example 1,

wherein the selector gate dielectric comprises aluminum oxide (Al ₂ O ₃ ).

Example 10. The method of Example 1,

wherein the selector channel is made of indium gallium zinc oxide (IGZO).

Embodiment 11. A memory device comprising:

Board;

an interconnect structure disposed over the substrate, the interconnect structure having a plurality of interconnect metal layers stacked on top of each other and comprising a plurality of lower interconnecting metal lines and a plurality of upper interconnecting metal lines;

a plurality of selectors disposed within the interconnect structure and above the lower interconnecting metal lines, the plurality of selectors arranged in an array of rows and columns; and

a plurality of memory cells disposed on top of the plurality of selectors corresponding to the array of rows and columns

A memory device comprising:

Example 12. The method of Example 11,

Each of the plurality of selectors is:

a selector channel disposed above the lower interconnecting metal line;

a selector gate dielectric that wraps around sidewalls of the selector channel; and

a selector gate electrode disposed around the selector gate dielectric and separated from the selector channel by the selector gate dielectric

A memory device comprising:

Example 13. The method of Example 12,

Each of the plurality of memory cells includes:

bottom electrode;

a data storage structure disposed on the lower electrode; and

a top electrode disposed over the data storage structure

A memory device comprising:

Example 14. The method of Example 13,

wherein the row of selectors shares a lower interconnecting metal line of the plurality of lower interconnecting metal lines disposed directly below the selector channels of the row of selectors.

Example 15. The method of Example 14,

wherein the row of selectors shares an upper interconnecting metal line of the plurality of upper interconnecting metal lines disposed directly over the top electrodes of the row of memory cells.

Example 16. The method of Example 15,

and the column of selectors share a word line connecting the selector gate electrodes of the column of selectors.

Example 17. The method of Example 16,

wherein the selector gate electrodes are a conformal conductive layer disposed between the column of selectors and extending along lower sidewalls of the selector channels of the column of selectors.

Embodiment 18. A method of manufacturing a memory device, comprising:

forming a lower interconnect metal layer over the substrate;

forming a plurality of selectors and a plurality of memory cells over the lower interconnect metal layer; and

forming a top interconnect metal layer over the plurality of memory cells;

A method of manufacturing a memory device comprising:

Example 19. The method of Example 18,

Forming the plurality of selectors and the plurality of memory cells may include:

forming a selector channel layer on the lower interconnect metal layer;

forming a stack of memory layers on the selector channel layer;

patterning the stack of memory layers and the selector channel layer to form a plurality of selector channels and a plurality of memory cells in an array of rows and columns; and

forming and patterning a selector gate electrode layer and a selector gate dielectric layer surrounding the plurality of selector channels;

A method of manufacturing a memory device comprising:

Example 20. The method of Example 18,

and forming a second plurality of selectors and a second plurality of memory cells stacked over the upper interconnect metal layer.

Claims (10)

A memory device comprising:
Board;
a lower interconnection metal line disposed over the substrate;
a selector channel disposed above the lower interconnecting metal line;
a selector gate electrode wrapped around a sidewall of the selector channel and separated from the selector channel by a selector gate dielectric;
a memory cell disposed over the selector channel and electrically coupled to the selector channel; and
a top interconnect metal line disposed over the memory cell
A memory device comprising: According to claim 1,
and the memory cell is in direct contact with the selector channel. According to claim 1,
and the selector channel has a sidewall aligned with a sidewall of the memory cell. According to claim 1,
and the selector gate electrode comprises a metal layer covering a lower sidewall of the selector gate dielectric. According to claim 1,
wherein the selector channel comprises an oxide semiconductor material. According to claim 1,
wherein the selector channel has a circular or elliptical shape in plan view. According to claim 1,
The memory cell comprises:
a bottom electrode disposed above the selector channel;
a data storage structure disposed on the lower electrode; and
a top electrode disposed over the data storage structure
A memory device comprising: According to claim 1,
wherein the selector channel has a square or rectangular shape in plan view. A memory device comprising:
Board;
an interconnect structure disposed over the substrate, the interconnect structure having a plurality of interconnect metal layers stacked on top of each other and comprising a plurality of lower interconnecting metal lines and a plurality of upper interconnecting metal lines;
a plurality of selectors disposed within the interconnect structure and above the lower interconnecting metal lines, the plurality of selectors arranged in an array of rows and columns; and
a plurality of memory cells disposed on top of the plurality of selectors corresponding to the array of rows and columns
A memory device comprising: A method of manufacturing a memory device, comprising:
forming a lower interconnect metal layer over the substrate;
forming a plurality of selectors and a plurality of memory cells over the lower interconnect metal layer; and
forming a top interconnect metal layer over the plurality of memory cells;
A method of manufacturing a memory device comprising:

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