KR20210147861A - Semiconductor device and method - Google Patents

Abstract

In an embodiment, a device comprises: a power rail contact; an isolation region on the power rail contact; a first dielectric fin on the isolation region; a second dielectric pin adjacent to the isolation region and the power rail contact; a first source/drain region on the second dielectric fin; and a source/drain contact between the first source/drain region and the first dielectric fin. The source/drain contact is in contact with the top surface of the first source/drain region, the side surface of the first source/drain region, and the top surface of the power rail contact.

Description

Semiconductor device and method

Priority Claims and Cross-References

This application claims the benefit of US Provisional Patent Application No. 63/030,544, filed on May 27, 2020, the application of which is incorporated herein by reference.

The technology behind the invention

BACKGROUND Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically made by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and panning the various layers of material using lithography to form circuit components and elements thereon. is manufactured

In the semiconductor industry, the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) continues to increase due to the continuous decrease in the minimum feature size, which means that more and more components can be placed within a given area. allow to be aggregated. However, as the minimum feature size decreases, additional problems arise that need to be addressed.

Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is noted that, in accordance with standard practice in the industry, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.
1 shows an example of a nanostructure field-effect transistor (nano-FET) in accordance with some embodiments.
2 - 23C are cross-sectional views of intermediate steps in the fabrication of a semiconductor device in accordance with some embodiments.
24A-29C are various views of additional intermediate steps in the fabrication of a semiconductor device in accordance with some embodiments.

The following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, the formation of a first feature on or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, wherein the additional feature is the second feature. It may also include embodiments that may be formed between the first and second features so that the first and second features cannot be in direct contact. Also, this disclosure may repeat reference numbers and/or letters in the various examples. This repetition is for the sake of simplicity and clarity, and does not necessarily dictate a relationship between the various embodiments and/or configurations being discussed.

Also, spatially relative terms such as “under”, “below”, “under”, “above”, “on top”, etc. refer to one element or feature and another element(s) as shown in the drawings. or may be used herein for ease of description to describe a relationship between feature(s). Spatially relative terms are intended to encompass different orientations of a device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and spatially relative descriptors used herein may likewise be interpreted correspondingly.

According to some embodiments, power rail contacts for the nano-FET layer are buried under the isolation region surrounding the nano-FET. The source/drain contacts can be used to couple the source/drain regions of the nano-FET to both the interconnects on the top and the power rail contacts on the bottom. Thus, the source/drain regions can be attached to the rear power rail, and the metal-semiconductor alloy region need not be formed on the rear surface of the power rail contacts.

1 shows an illustration of a simplified nano-FET in accordance with some embodiments. 1 is a cut-away three-dimensional view with some features of a nano-FET omitted for clarity of explanation. In the illustrated embodiment, the nano-FET is a forksheet FET. Nano-FETs also include nanosheet field-effect transistors (NSFETs), nanowire field-effect transistors (NWFETs), and gate-all-around field effect transistors (NWFETs). -effect transistor; GAAFET) or the like.

Nano-FETs include nanostructures 56 over a substrate 50 , such as over fins 54 extending from the substrate 50 . Nanostructure 56 is a semiconductor layer that acts as a channel region for the nano-FET. An isolation region 78 , such as a shallow trench isolation (STI) region, is disposed over the substrate 50 and adjacent the fin 54 . Although isolation region 78 is described/illustrated as separate from substrate 50 , the term “substrate” as used herein refers to substrate 50 alone or a combination of substrate 50 and isolation region 78 . can do. Further, while the fin 52 is shown as being of a single continuous material with the substrate 50 , the fin 52 and/or the substrate 50 may include a single material or multiple materials. In this regard, fin 54 refers to the portion extending over and from between neighboring isolation regions 78 .

A gate structure 120 surrounds the nanostructure 56 and is disposed over the fin 54 . The gate structure 120 includes a gate dielectric 122 and a gate electrode 124 . The gate dielectric 122 is along the top surface, sidewalls, and bottom surface of the nanostructure 56 , and may extend along the sidewalls of the fin 54 and/or over the top surface of the fin 54 . The gate electrode 124 is on the gate dielectric 122 . Epitaxial source/drain regions 106 are disposed on opposite sides of gate spacers 106 . In an embodiment in which a plurality of transistors are formed, the epitaxial source/drain region 106 may be shared among the various transistors. One or more interlayer dielectric (ILD) layers (discussed in greater detail below) overly and/or through epitaxial source/drain regions 106 and/or gate structures 120, therethrough, epitaxial source/drain regions 106 and A contact (discussed in more detail below) to the gate electrode 124 is formed.

The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N includes, for example, an n-type device, such as an NMOS transistor (eg, an n-type nano-FET), and the p-type region 50P includes, for example, a PMOS transistor (eg, a PMOS transistor). , p-type devices such as p-type nano-FETs). In the illustrated embodiment, the nano-FET is a forksheet FET. In a fork seat FET, both the n-type and p-type devices are integrated into the same fork seat structure. Dielectric wall 68 provides semiconductor fins 54, nanostructures 56 and epitaxial source/drain regions 106 for n-type devices, and semiconductor fins 54, nanostructures 56 for p-type devices. ) and epitaxial source/drain regions 106 . Gate structures 120 extend along three sides of each nanostructure 56 . Forksheet FETs allow n-type and p-type devices to be formed close to each other, and the gate structures 120 of the devices can be physically and electrically coupled to each other, reducing the amount of gate contacts used in CMOS processes. Dielectric fins 84 are formed over isolation regions 78 at cell boundaries, separating adjacent forksheet FETs.

Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Additionally, some embodiments contemplate aspects for use in planar devices, such as planar FETs, or in fin field effect transistors (FinFETs).

Also, Fig. 1 shows a reference cross section used in the following drawings. Cross-section A-A is along the longitudinal axis of nanostructure 56 and along the direction of current flow, for example, between epitaxial source/drain regions 106 . Section B-B is perpendicular to section A-A and is along the longitudinal axis of gate structure 120 . Section C-C is perpendicular to section A-A and extends through epitaxial source/drain region 106 . Subsequent drawings refer to these reference sections for clarity.

2 - 23C are cross-sectional views of intermediate steps in the fabrication of a semiconductor device in accordance with some embodiments. Specifically, fabrication of the device layer of a nano-FET is described. 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 and 15 are cross-sectional views taken along the reference section BB of FIG. 1 except that four pins are shown; am. 16A, 17A, 18A, 19A, 20A, 21A, 22A, and 23A are cross-sectional views taken along reference section A-A of FIG. 1 , except that two gate structures are shown; 16b, 17b, 18b, 19b, 20b, 21b, 22b, and 23b are cross-sectional views taken along the reference section B-B of FIG. 1 , except that four pins are shown. 16c, 17c, 18c, 19c, 20c, 21c, 22c and 23c are cross-sectional views taken along the reference section C-C of FIG. 1 except that four pins are shown.

In Figure 2, a substrate 50 is provided to form a nano-FET. Substrate 50 is a semiconductor, such as a bulk semiconductor, semiconductor-on-insulator (SOI) substrate, etc., which may or may not be doped (eg, with p-type or n-type dopant). It may be a substrate. The substrate 50 may be, for example, a wafer, such as a silicon wafer. In the illustrated embodiment, the substrate 50 is an SOI substrate. In general, the SOI substrate is a semiconductor layer 50A formed on an insulator layer 50B. The insulator layer 50B may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. An insulator layer 50B is provided on the substrate core 50C, which is typically a silicon substrate or a glass substrate. Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material (eg, semiconductor layer 50A) of substrate 50 is silicon; germanium; compound semiconductors comprising silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide; alloy semiconductors comprising silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and/or gallium indium arsenide phosphide; or a combination thereof.

The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N may be, for example, for forming an n-type device, such as an NMOS transistor (eg, an n-type nano-FET), and the p-type region 50P is, for example, a PMOS transistor. (eg, p-type nano-FETs) for forming p-type devices. As discussed in greater detail below, although one n-type region 50N and one p-type region 50P are shown, the substrate 50 may include any desired amount of such region.

The substrate 50 may be lightly doped with p-type impurities or n-type impurities. An anti-punch-through (APT) implantation may be performed on the upper portion of the substrate 50 to form an APT region. During the APT implantation, dopants may be implanted into the n-type region 50N and the p-type region 50P. The dopant may have a conductivity type opposite to that of the source/drain regions to be subsequently formed in each of the n-type region 50N and the p-type region 50P. The APT region may extend below the subsequently formed source/drain region in the nano-FET, which will be formed in a subsequent process. The APT region may be used to reduce leakage from the source/drain region to the substrate 50 . In some embodiments, the doping concentration of the APT region may range from about 10 ¹⁸ cm ⁻³ to about 10 ¹⁹ cm ⁻³ .

In FIG. 3 , a multilayer stack 52 is formed over a substrate 50 . Multilayer stack 52 includes alternating first semiconductor layers 52A and second semiconductor layers 52B. The first semiconductor layer 52A is formed of a first semiconductor material, and the second semiconductor layer 52B is formed of a second semiconductor material. Each of the semiconductor materials may be selected from among the candidate semiconductor materials of the substrate 50 . In the illustrated embodiment, the multilayer stack 52 includes four layers each of a first semiconductor layer 52A and a second semiconductor layer 52B. It should be understood that the multilayer stack 52 may include any number of first semiconductor layers 52A and second semiconductor layers 52B. For example, the multilayer stack 52 may include about 3 to about 8 layers each of the first semiconductor layer 52A and the second semiconductor layer 52B.

In the illustrated embodiment, the second semiconductor layer 52B will be used to form the channel region for the nano-FET in both the n-type region 50N and the p-type region 50P. The first semiconductor layer 52A is a sacrificial layer (or dummy layer), which is removed in subsequent processing to expose the top and bottom surfaces of the second semiconductor layer 52B in both regions. The second semiconductor material of the second semiconductor layer 52B is a material suitable for both n-type and p-type nano-FETs such as silicon, and the first semiconductor material of the first semiconductor layer 52A is a second semiconductor material such as silicon germanium. A material with high etch selectivity from etching of the material.

In another embodiment, the first semiconductor layer 52A will be used to form a channel region for the nano-FET in one region (eg, p-type region 50P), and the second semiconductor layer 52B ) will be used to form the channel region for the nano-FET in another region (eg, n-type region 50N). The first semiconductor material of the first semiconductor layer 52A is silicon germanium (eg, Si _x Ge _1-x and x may be in the range of 0 to 1), pure or substantially pure germanium, may be suitable for a p-type nano-FET such as a group III-V compound semiconductor, a group II-VI compound semiconductor, and the like, and the second semiconductor layer ( The second semiconductor material of 52B) may be suitable for an n-type nano-FET such as, for example, silicon, silicon carbide, group III-V compound semiconductor, group II-VI compound semiconductor, and the like. Since the first semiconductor material and the second semiconductor material may have high etch selectivity from etching each other, the first semiconductor layer 52A may be removed without removing the second semiconductor layer 52B in the n-type region 50N. Alternatively, the second semiconductor layer 52B may be removed from the p-type region 50P without removing the first semiconductor layer 52A.

Each layer of the multilayer stack 52 is grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), chemical vapor deposition (CVD) or deposited by a process such as atomic layer deposition (ALD), or the like. Each layer may be formed with a small thickness, such as, for example, a thickness in the range of about 5 nm to about 30 nm. In some embodiments, one group of layers (eg, second semiconductor layer 52B) is formed thinner than another group of layers (eg, first semiconductor layer 52A). For example, in some embodiments in which the first semiconductor layer 52A is a sacrificial layer (or dummy layer) and the second semiconductor layer 52B is used to form the channel region, the second semiconductor layer 52B is the second semiconductor layer 52B. It may be thicker than one semiconductor layer 52A. The relative thickness of the layer may be based on the desired channel height and the channel work function requirements of the resulting nano-FET.

In FIG. 4 , trenches 60 are etched in substrate 50 and multilayer stack 52 , so that fin structures 62 ( fin structures 62N in n-type region 50N and fin structures in p-type region 50P) are etched in FIG. (including 62P)). Fin structures 62 include semiconductor fins 54 and nanostructures 56, respectively. Semiconductor fins 54 are semiconductor strips patterned on substrate 50 . In an embodiment where the substrate 50 is an SOI substrate, the semiconductor fin 54 comprises the remainder of the semiconductor layer 50A. The nanostructures 56 include the remainder of the multilayer stack 52 on the semiconductor fins 54 . Specifically, the nanostructures 56 alternately include first nanostructures 56A and second nanostructures 56B. The first nanostructure 56A and the second nanostructure 56B are respectively formed of the remaining portions of the first semiconductor layer 52A and the second semiconductor layer 52B. In the illustrated embodiment, the second nanostructures 56B are each disposed between the two first nanostructures 56A. The etching may be any acceptable etching process, such as reactive ion etch (RIE), neutral beam etch (NBE), etc., or a combination thereof, having the pattern of fin structures 62 . This may be done using a mask 58 . The etching may be anisotropic.

Mask 58 may be a single layer mask, or may be a multilayer mask, such as a multilayer mask comprising a first mask layer 58A and a second mask layer 58B on the first mask layer 58A, respectively. The first mask layer 58A and the second mask layer 58B may each be formed of a dielectric material such as silicon oxide, silicon nitride, combinations thereof, etc., and may be deposited or thermally grown according to acceptable techniques. can The material of the first mask layer 58A may have high etch selectivity from etching of the material of the second mask layer 58B. For example, the first mask layer 58A may be formed of silicon oxide, and the second mask layer 58B may be formed of silicon nitride.

The fin structures 62 may be patterned by any suitable method. For example, the fin structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. In general, a double patterning process or multiple patterning process combines photolithography and a self-aligned process, e.g., having a smaller pitch than would otherwise be obtainable using a single direct photolithography process. A pattern can be created. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-aligning process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin structures 62 . In some embodiments, a mask 58 (or other layer) may remain on the fin structures 62 .

The fin structure 62 may have a width ranging from about 5 nm to about 20 nm. Fin structures 62 in n-type region 50N and p-type region 50P are shown to have substantially the same width for illustrative purposes. In some embodiments, fin structures 62 in one region (eg, n-type region 50N) are wider than fin structures 62 in another region (eg, p-type region 50P). or it may be narrow.

The fin structures 62 are formed in adjacent pairs. Each pair of fin structures 62 will be used to form a forksheet FET. One fin structure 62N of each pair will be used to form an n-type device, and the other fin structure 62P in each pair will be used to form a p-type device. Each pair of fin structures 62N and 62P is separated by a corresponding first one of the trenches 60A. A dielectric wall (discussed in more detail below) will be formed in the trench 60A between each pair of fin structures 62N, 62P, and thus different types of nano-FETs to be formed in the fin structures 62N, 62P. It will provide electrical isolation between them. The trench 60A may have a first width W _{1 in a} range of about 6 nm to about 30 nm. An adjacent pair of fin structures 62 are separated by a corresponding second trench in trenches 60B. The trench 60B may have a second width W _{2 in a} range of about 22 nm to about 46 nm. Since the width W ₂ is greater than the first width W ₁ , adjacent pairs of the fin structures 62 are further spaced apart than each pair of the fin structures 62N and 62P.

5 , a liner layer 64 is formed over the mask 58 (if present), the fin structures 62 and the substrate 50 . The liner layer 64 will be used to separate the fin structures 62 from subsequently formed contacts. The liner layer 64 may be formed of a dielectric material that may be formed by a thermal oxidation or conformal deposition process. Acceptable dielectric materials include, for example, low-k dielectric materials (eg, materials having a k-value less than about 7) such as silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, etc. ; high-k dielectric materials (eg, materials having a k-value greater than about 7) such as, for example, hafnium oxide, zirconium oxide, zirconium aluminum oxide, hafnium aluminum oxide, hafnium silicon oxide, aluminum oxide, and the like; combinations thereof; etc. Acceptable deposition processes include atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam deposition (MBD), physical vapor deposition (PVD), and the like. In some embodiments, the liner layer 64 is formed of silicon oxide by thermal oxidation. The liner layer 64 may be formed to a thickness ranging from about 1 nm to about 10 nm.

A dielectric layer 66 is then formed over the liner layer 64 . Dielectric layer 66 may be formed of a low-k dielectric material (such as selected from among candidate dielectric materials for liner layer 64 ), which may be formed by a conformal deposition process (eg, a candidate for forming liner layer 64 ). method selected from among the methods). The material of the dielectric layer 66 has a different k-value than the material of the liner layer 64 and has a high etch selectivity from etching of the material of the liner layer 64 . In some embodiments, dielectric layer 66 is formed of silicon nitride by ALD or CVD.

Since the trenches 60A and 60B have different widths, they are filled with different amounts of dielectric material. A liner layer 64 is formed along the sidewalls and bottom of the trenches 60A, 60B. Since the trench 60A has a narrower width, it is completely filled (or overfilled) by the dielectric layer 66 . However, the trench 60B is not completely filled by the dielectric layer 66 because it has a greater width. In other words, after dielectric layer 66 is deposited, trench 60A is filled (or overfilled) but some portion of trench 60B remains unfilled.

6 , dielectric layer 66 is etched back to remove a portion of dielectric layer 66 . Specifically, portions of dielectric layer 66 within trench 60B and over mask 58 (if present) or fin structures 62 are removed by etchback to reform trench 60B. . The dielectric layer 66 is etched back (eg, at a faster rate than the material(s) of the liner layer 64 ) using an acceptable etching technique, such as, for example, an etching process selective to the dielectric layer 66 . etch the material(s) of the dielectric layer 66). After etchback is complete, the remaining portion of dielectric layer 66 is in trench 60A. The remaining portion of the dielectric layer 66 forms a dielectric wall 68 that separates the fin structures 62N and 62P of each pair of fin structures 62 . Dielectric wall 68 may partially or completely fill trench 60A. The dielectric wall 68 may have a width W _{1 in a} range from about 6 nm to about 30 nm. After dielectric layer 66 is formed, forksheet structure 80 extends from substrate 50 . The forksheet structure 80 includes a dielectric wall 68 and a pair of fin structures 62 , respectively, with the dielectric wall 68 disposed between the fin structures 62 .

As noted above, one n-type region 50N and one p-type region 50P are shown, however, the substrate 50 may include any desired amount of such region. Each fork seat structure 80 is disposed at the boundary between the n-type region 50N and the p-type region 50P. Further, the fin structures 62N and 62P of each fork seat structure 80 alternate. In other words, each n-type region 50N includes a first fin structure 62N from the first fork seat structure 80 , and a second fin structure 62N from the second fork seat structure 80 . includes

In FIG. 7 , a conductive layer 72 is deposited over dielectric wall 68 and liner layer 64 . Conductive layer 72 fills trench 60B and may be formed over mask 58 (if present) or fin structure 62 . When dielectric wall 68 partially fills trench 60A, conductive layer 72 may also form in the remainder of trench 60A. Conductive layer 72 may be formed by a deposition process (eg, ALD, CVD, PVD, etc.), plating process (eg, electroplating, electroless plating, etc.), for example, tungsten (W ), ruthenium (Ru), cobalt (Co), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), nickel (Ni), these It may be formed of a metal or a metal-containing material such as an alloy of

In FIG. 8 , conductive layer 72 is etched back to remove some portions of conductive layer 72 . Specifically, portions of conductive layer 72 within trench 60A and over mask 58 (if present) or fin structures 62 are removed by etchback. Conductive layer 72 may, for example, be selective to conductive layer 72 (eg, material(s) of conductive layer 72 at a faster rate than the material(s) of liner layer 64 ). Etching) is etched back using an acceptable etching technique, such as an etching process. After the etchback is complete, the remaining portion of the conductive layer 72 is placed in the trench 60B. The portion of conductive layer 72 remaining in trench 60B forms power rail contacts 74 between forksheet structures 80 . After the power rail contact 74 _{has reached the desired height H 1} , timed etch processes may be used to stop etching the conductive layer 72 . The height H ₁ may be in the range of about 20 nm to about 60 nm. Further, the power rail contact 74 may have a width W _{4 in a} range from about 6 nm to about 30 nm.

In FIG. 9 , insulating material 76 is formed in the remainder of trench 60A adjacent to forksheet structure 80 . Insulating material 76 may be deposited in mask 58 (if present) or fin structures 62 and trenches 60A, 60B. The insulating material 76 may be, for example, an oxide such as silicon oxide, such as a nitride such as silicon nitride, or the like, or a combination thereof, such as high density plasma CVD (HDP-CVD), flowable CVD (FCVD), etc.; Or it may be formed by a combination thereof. Other insulating materials formed by any acceptable process may be used. Once the insulating material 76 is formed, an annealing process may be performed. Although insulating material 76 is illustrated as a single layer, some embodiments may use multiple layers. A removal process is then applied to insulating material 76 to remove excess material of insulating material 76 and liner layer 64 over mask 58 (if present) or fin structures 62 . In some embodiments, a planarization process may be utilized, such as, for example, chemical mechanical polish (CMP), an etchback process, combinations thereof, and the like. The planarization process exposes the mask 58 or nanostructure 56 so that after the planarization process is complete, the top surface of each of the mask 58 or nanostructure 56 , the remainder of the liner layer 64 , and the insulating material (76) becomes coplanar (within the process variation). In the illustrated embodiment, the mask 58 remains after the planarization process. In another embodiment, the mask 58 may also be removed by a planarization process.

In FIG. 10 , insulating material 76 is recessed to form STI region 78 , re-forming a portion of trench 60B. The insulating material 76 is recessed such that at least a portion of the nanostructure 56 protrudes from the STI region 78 . In the illustrated embodiment, the top surface of the STI region 78 is below the top surface of the semiconductor fin 54 . In some embodiments, the top surface of the STI region 78 is coplanar (within process variations) on or with the top surface of the semiconductor fin 54 . Further, the top surface of the STI region 78 may have a flat surface, a convex surface, a concave surface (eg, dishing), or a combination thereof, as shown. The upper surface of the STI region 78 may be formed planar, convex, and/or concave by suitable etching. STI region 78 may, for example, be selective for insulating material 76 (eg, material(s) of insulating material 54 at a faster rate than the material(s) of forksheet structure 80 ) may be recessed using an acceptable etching process, such as an etching process that selectively etches For example, oxide removal using dilute hydrofluoric (dHF) acid may be used. A time-limited etching process may be used to stop etching the insulating material 76 after the STI region 78 _{has reached the desired height H 2 .} The height H ₂ may be in the range of about 5 nm to about 20 nm. The liner layer 64 may also be recessed during recessing of the insulating material 76 . The top surfaces of the insulating material 76 and the liner layer 64 may be coplanar (within process variations) after recessing.

After the STI regions 78 are formed, the forksheet structure 80 extends from between neighboring STI regions 78 . STI regions 78 are formed over and bury power rail contacts 74 . Each liner layer 64 is disposed between the forksheet structure 80 and each STI region 78 and power rail contact 74 . It should be understood that the process described above is only one example of how the fork seat structure 80 may be formed. Other acceptable processes may also be used to form the forksheet structure 80 and the STI region 78 . The forksheet structure 80 may be processed in a manner similar to that semiconductor fins are processed in a process for forming a FinFET. Processing the fork seat structure 80 in this manner allows an n-type device and a p-type device to be integrated into the same fork seat structure 80 .

11 , channel spacers 82 are formed over and around forksheet structure 80 , for example, in portions of trench 60B. Channel spacers 82 may be formed of a semiconductor material (eg, a material selected from candidate semiconductor materials of substrate 50 ), which may be, for example, vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE). It can be grown by a process such as, for example, deposited by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), and the like. In some embodiments, the channel spacers 82 are grown by epitaxial growth, which may include growing a thin seed layer on the fin structures 62 and then growing the material of the channel spacers 82 from the seed layer. . After the fin structures 62 are formed (eg, after the trenches 60 are etched in the substrate 50 , as discussed above with respect to FIG. 4 ), a seed layer may be grown. An anisotropic etch may be performed after forming the material of the channel spacers 82 to expose the STI regions 78 . The channel spacers 82 are used as temporary spacers during processing, which will then be subsequently removed to expose portions of the nanostructures 56 that will serve as channel regions for the nano-FETs. Specifically, in the illustrated embodiment, the channel spacers 82 and first nanostructures 56A will be subsequently removed and replaced with gate structures formed around three sides of the second nanostructures 56B. Accordingly, the channel spacers 82 are formed of a material having a high etch selectivity from the etching of the material of the second nanostructures 56B. The channel spacers 82 may be formed of the same semiconductor material as the first nanostructure 56A, or may be formed of a different material.

In FIG. 12 , a dielectric fin 84 is formed between the channel spacers 82 and on the STI region 78 , for example in the remainder of the trench 60B not filled by the channel spacers 82 . . Accordingly, each trench 60B is filled by a pair of channel spacers 82 and a dielectric fin 84 , with the dielectric fin 84 being between the channel spacers 82 . The dielectric fin 84 is a low-k dielectric material (eg, a low-k dielectric material, which may be formed by a thermal oxidation or conformal deposition process (eg, a process selected from candidate methods of forming the liner layer 64 ). a material selected from candidate dielectric materials for the liner layer 64 ), a high-k dielectric material (eg, a material selected from candidate dielectric materials for the liner layer 64 ), a combination thereof, or the like. In the illustrated embodiment, each dielectric fin 84 includes a first dielectric layer 84A and a second dielectric layer 84B on the first dielectric layer 84A, the first dielectric layer 84A being silicon carbonitride, silicon It is formed of oxycarbide or silicon oxycarbide, and the second dielectric layer 84B is formed of silicon oxide. The dielectric fin 84 may have a fifth width W _{5 in a} range from about 6 nm to about 30 nm.

A removal process is then applied to the dielectric fins 84 to remove excess material(s) of the dielectric fins 84 over the channel spacers 82 . In some embodiments, a planarization process may be utilized, such as, for example, chemical mechanical polishing (CMP), an etchback process, combinations thereof, and the like. The planarization process exposes the channel spacers 82 so that the top surfaces of the channel spacers 82 and dielectric fins 84 are coplanar (within process variations) after the planarization process is complete.

In FIG. 13 , dielectric fin 84 is selectively recessed to re-form a portion of trench 60B. The dielectric fin 84 is etched selectively to the dielectric fin 84 (eg, the material(s) of the first dielectric layer 84A and the second dielectric layer 84B) to the material(s) of the channel spacer 82 . may be recessed using an acceptable etching process such as selectively etching at a higher rate).

In FIG. 14 , for example, a third dielectric layer 84C for dielectric fin 84 is selectively formed in trench 60B as on first dielectric layer 84A and second dielectric layer 84B. Third dielectric layer 84C may be formed of a high-k dielectric material (such as one selected from candidate dielectric materials for liner layer 64 ), which may be formed by a conformal deposition process (eg, to form liner layer 64 ). a method selected from among the candidate methods). A removal process is then applied to remove excess material(s) of the channel spacers 82 and the third dielectric layer 84C over the mask 58 (if present) or fin structures 62 . In some embodiments, a planarization process may be utilized, such as, for example, chemical mechanical polishing (CMP), an etchback process, combinations thereof, and the like. The planarization process exposes the mask 58 or nanostructure 56 so that the top surface of the mask 58 or nanostructure 56, the channel spacer 82 and the third dielectric layer 84C, respectively, after the planarization process is complete. to be coplanar (within process variations). In the illustrated embodiment, the mask 58 remains after the planarization process. In another embodiment, the mask 58 may also be removed by a planarization process.

In the illustrated embodiment, dielectric fin 84 has a lower portion formed of a low-k dielectric material (comprising a first dielectric layer 84A and a second dielectric layer 84B) and an upper portion formed of a high-k dielectric (the second dielectric layer 84B). 3 dielectric layer 84C). It should be understood that other types of dielectric fins 84 may be formed, such as, for example, dielectric fins 84 having more or fewer layers. In various embodiments, the dielectric fin 84 comprises a lower portion and an upper portion of a low-k dielectric material; a lower portion and an upper portion of a high-k dielectric material; a lower portion of high-k dielectric material and an upper portion of low-k dielectric material; a lower portion and/or an upper portion of a single layer; multi-layered lower portion and/or upper portion; and the like. _{The upper portion of the dielectric fin 84 may have a height H 3 in} the range of about 6 nm to about 30 nm, and the lower portion of the dielectric fin 84 may have a height H _{4 in} the range of about 27 nm to about 60 nm. and the dielectric fin 84 may have an overall height in the range of about 33 nm to about 90 nm.

In FIG. 15 , forksheet structure 80 and channel spacers 82 are recessed such that dielectric fins 84 extend between neighboring channel spacers 82 . Recessing removes mask 58 from fin structure 62 if mask 58 is still present at this processing step. Recessing may be by an acceptable etching process(s). For example, the forksheet structure 80 may be subjected to an acceptable etch process (eg, channel spacers 82 , such as selective for mask 58 , nanostructures 56 and dielectric wall 68 ) ) and selectively etching the material(s) of the mask 58 , the nanostructures 56 and the dielectric wall 68 at a faster rate than the material(s) of the dielectric fins 84 ). have. The channel spacers 82 may be subjected to an acceptable etching process (eg, at a faster rate than the material(s) of the nanostructures 56 and dielectric wall 68 , such as those selective for the channel spacers 82 ). by selectively etching the material(s) of the channel spacers 82). Recessing/trimming may remove portions of nanostructures 56 .

A dummy dielectric layer 86 is then formed over the forksheet structure 80 , the channel spacers 82 and the dielectric fins 84 . The dummy dielectric layer 86 may be silicon oxide, silicon nitride, combinations thereof, or the like, which may be deposited or thermally grown according to acceptable techniques.

16A-23C illustrate further intermediate steps in the fabrication of nano-FETs. 16A, 17A, 18A, 19A, 20A, 21A, 22A, and 23A may be applied to both the n-type region 50N and the p-type region 50P. The differences (if any) in the structure of the n-type region 50N and the p-type region 50P are described in the text accompanying each figure.

16A , 16B and 16C , a dummy gate 94 is formed over the dummy dielectric layer 86 . The dummy gate 94 may be formed by forming a dummy gate layer and patterning the dummy gate layer. A dummy gate layer 86 may be deposited over the dummy dielectric layer 86 and then planarized by, for example, CMP. The dummy gate layer may be of a conductive or non-conductive material and may be selected from the group comprising amorphous silicon, polysilicon, poly-SiGe, metallic nitride, metallic silicide, metallic oxide, and metal. . The dummy gate layer may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques for depositing selected materials. The dummy gate layer may then be patterned to form a dummy gate 94 using acceptable photolithography and etching techniques, such as, for example, a mask 96 having the pattern of the dummy gate 94 . The pattern of mask 96 is transferred to the dummy gate layer by an acceptable etching technique to form dummy gate 94 . The pattern of mask 96 may also be selectively transferred to the dummy dielectric layer by an acceptable etching technique to form dummy dielectric 92 .

Mask 96 may be a single layer mask or may be a multilayer mask, such as a multilayer mask comprising a first mask layer 96A and a second mask layer 96B, respectively. The first mask layer 96A and the second mask layer 96B may each be formed of a dielectric material such as silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. The material of the first mask layer 96A may have high etch selectivity from etching of the material of the second mask layer 96B. For example, the first mask layer 96A may be formed of silicon oxide, and the second mask layer 96B may be formed of silicon nitride.

A dummy gate 94 covers the portion of the nanostructure 56 that will be exposed in subsequent processing to form a channel region. Specifically, dummy gate 94 extends along the portion of nanostructure 56 that will be used to form channel region 88 . The pattern of mask 96 may be used to physically isolate adjacent dummy gates 94 . The dummy gate 94 may also have a longitudinal direction substantially perpendicular (within process variations) to the longitudinal direction of the semiconductor fin 54 . Mask 96 may be selectively removed after patterning by, for example, acceptable etching techniques.

A gate spacer 98 is formed over the fin structure 62 , for example, on the exposed sidewalls of the mask 96 , the dummy gate 94 and the dummy dielectric 92 . Gate spacers 98 may be formed by conformally forming an insulating material followed by etching the insulating material. The insulating material may be a low-k dielectric material (such as selected from candidate dielectric materials for liner layer 64 ), which may be a conformal deposition process (eg, selected from candidate methods of forming liner layer 64 ). method) can be deposited. The gate spacer 98 may be formed of a single layer of insulating material or multiple layers of insulating material. In some embodiments, the gate spacers 98 each include multiple layers of silicon oxycarbonitride, where each layer may have a different composition of silicon oxycarbonitride. In some embodiments, the gate spacers 98 each include a silicon oxide layer disposed between two silicon nitride layers. Other spacer structures may be formed. Etching of the insulating material may be anisotropic. For example, the etching process may be, for example, dry etching, such as RIE, NBE, or the like. After etching, the gate spacers 98 may have straight sidewalls or curved sidewalls.

Prior to the formation of the gate spacers 98, implantation for lightly doped source/drain (LDD) regions may be performed. In an embodiment with different device types, similar to implantation discussed above, a mask, eg, photoresist, may be formed over the n-type region 50N while exposing the p-type region 50P, and a suitable type (eg, p-type) impurities may be implanted into the fin structure 62 exposed in the p-type region 50P. The mask may then be removed. A mask, eg, photoresist, may then be formed over p-type region 50P, exposing n-type region 50N, with exposed fin 66 structures 55 in n-type region 50N. An appropriate type of impurity (eg, n-type) may be implanted into it. The mask may then be removed. The n-type impurity may be any one of the aforementioned n-type impurities, and the p-type impurity may be any one of the aforementioned p-type impurities. The lightly doped source/drain regions may have an impurity concentration ranging ^{from about 10 15} cm ⁻³ to about 10 ¹⁹ cm ^{−3 .} Annealing can be used to repair implant damage and activate implanted impurities. During implantation, the channel region 88 remains covered by the dummy gate 94 such that the channel region 88 is substantially free from impurities implanted into the LDD region.

Note that the above disclosure generally describes a process for forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, different orders of steps may be used, and the like (eg, additional spacers may be formed and removed, etc.). Moreover, n-type and p-type devices can be formed using different structures and steps.

Then, after the gate spacers 98 are formed, source/drain recesses 102 are formed in the fin structures 62 and the channel spacers 82 . In the illustrated embodiment, source/drain recesses 102 extend through nanostructures 56 and channel spacers 82 to expose semiconductor fins 54 and STI regions 78 . The source/drain recesses 102 may also extend into the semiconductor fins 54 . That is, the source/drain recesses 102 may be formed only in the nanostructure 56 or may be formed to extend into the semiconductor fin 54 . In various embodiments, the source/drain recesses 102 in the fin structure 62 may extend to a top surface of the semiconductor fin 54 without etching the semiconductor fin 54 ; The semiconductor fin 54 may be etched such that the bottom surface of the source/drain recess 102 in the fin structure 62 is disposed below the top surface of the STI region 78 , and the like. The source/drain recesses 102 are formed by an acceptable etching process (eg, of the dielectric wall 68 and the dielectric fin 84 , such as selective for the fin structures 62 and the channel spacers 82 ). selectively etching the material(s) of the semiconductor fins 54 , the nanostructures 56 and the channel spacers 82 at a faster rate than the material(s)). The dielectric walls 68 and dielectric fins 84 thus remain after the source/drain recesses 102 are formed. Gate spacers 98 and mask 96 collectively mask portions of fin structures 62 and channel spacers 82 during the etching process used to form source/drain recesses 102 . A time-limited etching process may be used to stop etching the source/drain recesses 102 after the source/drain recesses 102 have reached a desired depth.

The inner spacers 104 are optionally formed on the sidewalls of the remainder of the first nanostructures 56A, eg, sidewalls exposed by the source/drain recesses 102 . As discussed in more detail below, source/drain regions will then be formed in the source/drain recesses 102 and the first nanostructures 56A will subsequently be replaced with corresponding gate structures. The inner spacers 104 act as isolation features between the subsequently formed source/drain regions and the subsequently formed gate structures. In addition, the inner spacers 104 may be used to prevent damage to the source/drain regions subsequently formed by a subsequent etching process, such as an etching process used to subsequently form the gate structure.

As an example for forming the inner spacers 104 , the source/drain recesses 102 may be enlarged. Specifically, the portion of the sidewall of the first nanostructure 56A exposed by the source/drain recess 102 may be recessed. Although the sidewalls of the first nanostructure 56A are shown as straight, the sidewalls may be concave or convex. The sidewalls may be subjected to an acceptable etching process such as selective for the material of the first nanostructure 56A (eg, the first nanostructure 56B and the first nanostructure 56B at a faster rate than the material(s) of the semiconductor fin 54 ). by selectively etching the material of the nanostructures 56A). The etching may be isotropic. For example, when the semiconductor fin 54 and the second nanostructure 56B are formed of silicon and the first nanostructure 56A is formed of silicon germanium, the etching process is tetramethylammonium hydroxide (TMAH), ammonium hydroxide It may be wet etching using (NH ₄ OH) or the like. In another embodiment, the etching process may be dry etching using a fluorine-based gas such as hydrogen fluoride (HF) gas. In some embodiments, the same etching process may be performed continuously to form the source/drain recesses 102 and recess the sidewalls of the first nanostructures 56A. In some embodiments, the etching process used to recess the sidewalls may also trim (eg, reduce the thickness) the etched portion of the second nanostructures 56B. The inner spacers 104 may then be formed by conformally forming an insulating material followed by etching the insulating material. The insulating material may be formed of a low-k dielectric material (such as selected from among the candidate dielectric materials for the liner layer 64 ), which is a conformal deposition process (eg, candidate methods of forming the liner layer 64 ). may be deposited by a method selected from among Etching of the insulating material may be anisotropic. For example, the etching process may be, for example, dry etching such as RIE, NBE, or the like. Although the outer sidewalls of the inner spacer 104 are shown recessed from the sidewalls of the gate spacer 98 , the outer sidewalls of the inner spacer 104 extend beyond or flush with the sidewalls of the gate spacer 98 . there may be In other words, the inner spacer 104 may partially fill, completely fill, or overfill the sidewall recesses. Moreover, although the sidewalls of the inner spacer 104 are shown as concave, the sidewalls of the inner spacer 104 may be straight or convex.

17A , 17B and 17C , an epitaxial source/drain region 106 is formed in the source/drain recess 102 . Epitaxial source/drain regions 70 are formed in source/drain recesses 102 such that each dummy gate 94 is disposed between respective neighboring pairs of epitaxial source/drain regions 106 . In some embodiments, the gate spacers 98 and inner spacers 104 are separated from the epitaxial source by an appropriate lateral distance such that the epitaxial source/drain regions 106 do not short the subsequently formed gate of the nano-FET. /used to isolate dummy gate 94 and first nanostructure 56A from drain region 106, respectively. Epitaxial source/drain regions 106 may be formed in contact with inner spacers 104 (if present) and may extend beyond sidewalls of second nanostructures 56B. The epitaxial source/drain region 106 may improve performance by applying a stress to the second nanostructure 56B.

The epitaxial source/drain region 106 in the n-type region 50N may be formed by masking the p-type region 50P. Then, an epitaxial source/drain region 106 is epitaxially grown in the source/drain recess 102 of the n-type region 50N. The epitaxial source/drain regions 106 may include any acceptable material suitable for an n-type nano-FET. For example, epitaxial source/drain regions 106 of n-type region 50N are tensioned relative to channel region 88, such as, for example, silicon, silicon carbide, silicon carbide doped with phosphorus, silicon phosphide, etc. It may contain a material which applies a deformation|transformation. The epitaxial source/drain regions 106 in the n-type region 50N may have a surface raised from each surface of the fin structure 62 and may have facets.

The epitaxial source/drain region 106 in the p-type region 50P may be formed by masking the n-type region 50N. Then, the epitaxial source/drain region 106 is epitaxially grown in the source/drain recess 102 in the p-type region 50P. The epitaxial source/drain regions 106 may include any acceptable material suitable for a p-type nano-FET. For example, the epitaxial source/drain region 106 of the p-type region 50P may include a material that exerts a compressive strain on the channel region 88, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, or the like. can The epitaxial source/drain regions 106 in the p-type region 50N may have surfaces raised from the respective surfaces of the fin structures 62 and may have facets.

Epitaxial source/drain regions 106 , second nanostructures 56B, and/or fins 54 form source/drain regions similar to the process previously discussed for forming lightly doped source/drain regions. can be implanted with a dopant to do so, followed by annealing. The source/drain regions may have an impurity concentration ranging ^{from about 10 19} cm ⁻³ to about 10 ²¹ cm ^{−3 .} The n-type and/or p-type impurities for the source/drain regions may be any of the impurities described above. In some embodiments, epitaxial source/drain regions 106 may be doped in situ during growth.

As a result of the epitaxial process used to form the epitaxial source/drain region 106 , the upper surface of the epitaxial source/drain region 106 is facet that extends laterally outward beyond the surface of the fin structure 62 . has Adjacent epitaxial source/drain regions 106 remain separated by dielectric walls 68 or dielectric fins 84 after the epitaxial process is complete, preventing merging of epitaxial source/drain regions 106 . . Thus, the epitaxial source/drain regions 106 each have a straight bottom surface (contacting the semiconductor fin 54), a straight sidewall (contacting the dielectric wall 68), and a faceted side surface (contacting the dielectric fin 84), respectively. facing) and a facet top surface (facing the substrate 50). In addition, physical separation between the epitaxial source/drain region 106 and the dielectric fin 84 may be maintained to form a contact between the sidewall of the epitaxial source/drain region 106 and the power rail contact 74 . . In some embodiments, the epitaxial source/drain region 106 may be grown along the <010> direction, such that a lower portion of the source/drain recess 102 is interposed between the epitaxial source/drain regions 106 . remains and a dielectric fin 84 is formed. In some embodiments, a post-growth etchback is performed to reform the lower portion of the source/drain recesses 102 that separate the epitaxial source/drain regions 106 from the dielectric fins 84 . For example, the width of the epitaxial source/drain region 106 may be etched to reduce its width by an amount in the range of about 2 nm to about 20 nm, thus the lower portion of the source/drain recess 102 . reshape

The epitaxial source/drain regions 106 may include one or more layers of semiconductor material. For example, the epitaxial source/drain region 106 may include a first layer of semiconductor material 106A and a second layer of semiconductor material 106B. Any number of layers of semiconductor material may be used for epitaxial source/drain regions 106 . Each of the first semiconductor material layer 106A and the second semiconductor material layer 106B may be formed of a different semiconductor material and/or may be doped with different dopant concentrations. In some embodiments, the first semiconductor material layer 106A may have a smaller dopant concentration than the second semiconductor material layer 106B. In embodiments where epitaxial source/drain regions 106 include two layers of semiconductor material, first layer of semiconductor material 106A may be grown from fin structure 62 and second layer of semiconductor material 106B Silver may be grown from the first semiconductor material layer 106A.

18A , 18B and 18C , a dielectric layer 110 is formed in a lower portion of the source/drain recess 102 . Each dielectric layer 110 is formed between an epitaxial source/drain region 106 and a corresponding adjacent dielectric fin 84 . The dielectric layer 110 is a low-k dielectric material (eg, a liner), which may be formed by a thermal oxidation or conformal deposition process (eg, a method selected from candidate methods of forming the liner layer 64 ). a material selected from candidate dielectric materials for layer 64 ), a high-k dielectric material (eg, a material selected from candidate dielectric materials for liner layer 64 ), combinations thereof, or the like. A removal process, such as an etchback process, is then applied to the dielectric layer 110 to remove excess material in the dielectric layer 110 outside of the lower portion of the source/drain recess 102 , eg, epitaxial source/drain. Remove the portion above area 106 .

A first ILD 114 is then formed over the dielectric layer 110 , the epitaxial source/drain regions 106 and the dielectric fin 84 . The first ILD 114 is over the dielectric layer 110 , epitaxial source/drain regions 106 , gate spacers 98 , mask 96 (if present) or dummy gate 94 and dielectric fins 84 . It may be formed by depositing a dielectric material and then planarizing the dielectric material. Acceptable dielectric materials include, for example, oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), undoped silicate glass (USG), and the like; nitrides such as silicon nitride; and the like. Other insulating materials may be used. Deposition may be by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. Other acceptable processes may be used to form the dielectric material. Planarization may be accomplished by any suitable method, such as CMP, an etchback process, combinations thereof, and the like. The planarization process makes the top surface of the first ILD 114 level with the top surface of the mask 96 (if present) or dummy gate 94 . The planarization process may also remove the mask and portions of the gate spacers 98 along the sidewalls of the mask 96 . After the planarization process, the top surface of the first ILD 114 , gate spacer 98 , mask 96 (if present) or dummy gate 94 is coplanar (within process variations). Thus, the top surface of the mask 96 (if present) or dummy gate 94 is exposed through the first ILD 114 . In the illustrated embodiment, the mask 96 may be maintained and the planarization process level the top surface of the first ILD 114 with the top surface of the mask 96 .

In some embodiments, a contact etch stop layer (CESL) 112 includes a first ILD 114 and a dielectric layer 110 , an epitaxial source/drain region 106 , a gate spacer 98 , a dielectric fin 84 , and It is disposed between the dielectric walls 68 . The CESL 112 may include a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, etc. that has high etch selectivity from etching of the first ILD 114 and the dielectric layer 110 .

As discussed in more detail below, a portion of dielectric layer 110 (eg, in the cross-section of FIG. 18C ) is the contact between the sidewall of epitaxial source/drain region 106 and power rail contact 74 . will be replaced by Forming the dielectric layer 110 adjacent the epitaxial source/drain region 106 reduces manufacturing costs compared to forming the CESL 112 and the first ILD 114 adjacent the epitaxial source/drain region 106 . can increase However, the inclusion of dielectric layer 110 allows better control of the etching process that will be used to expose the top surface of power rail contact 74 . Accordingly, the manufacturing yield can be increased, and the overall manufacturing cost can be reduced by more than the cost of forming the dielectric layer 110 .

19A , 19B and 19C , mask 96 (if present), dummy gate 94 , dummy dielectric 92 , channel spacer 82 and first nanostructure 56A are removed and gate structure 120 . ) is replaced by The gate structure 120 includes a gate dielectric 122 and a gate electrode 124 on the gate dielectric 122 . Gate structure 120 may also be referred to as a “gate stack”.

Mask 96 (if present) and dummy gate 94 are removed in an etch process to form a recess. A portion of the dummy dielectric 92 in the recess may also be removed. In some embodiments, the dummy gate 94 is removed by an anisotropic dry etch process. For example, the etching process may include a dry etching process using reactive gas(es) that selectively etch the dummy gate 94 at a faster rate than the first ILD layer 114 or the gate spacers 98 . can During removal, dummy dielectric 92 may be used as an etch stop layer when dummy gate 94 is etched. The dummy gate dielectric 92 may then be removed after removal of the dummy gate 94 . Each recess exposes and/or overlies a portion of the second nanostructure 56B that acts as a channel region 88 . A portion of the second nanostructure 56B that will act as a channel region is disposed between neighboring pairs of epitaxial source/drain regions 106 .

Then, the remaining portions of the channel spacers 82 and the first nanostructures 56A are removed to expand the recesses. The remaining portions of the channel spacers 82 and the first nanostructures 56A combine the material(s) of the channel spacers 82 and the first nanostructures 56 with the second nanostructures 56B, the semiconductor fins 54 . , STI regions 78 , dielectric fins 84 , and material(s) of dielectric wall 68 may be removed by an acceptable etching process that selectively etches at a faster rate than the material(s). The etching may be isotropic. For example, when semiconductor fin 54 and second nanostructure 56B are formed of silicon and channel spacer 82 and first nanostructure 56A are formed of silicon germanium, the etching process is tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NHOH), etc. may be wet etching.

The exposed portions of the second nanostructures 56B and the semiconductor fins 54 are optionally trimmed. The trimming reduces the thickness of the exposed portion of the second nanostructure 56B. _{For example, the trimming may reduce the second thickness T 2} (see FIG. 3 ) of the second nanostructure 56B by an amount in the range of about 40% to about 70%, and also the exposure of the semiconductor fin 54 . The width of the part can be reduced. The trimming may be performed simultaneously with the formation of the recess, or may be performed after the recess is formed. For example, the exposed portions of the second nanostructures 56 and the semiconductor fins 54 may have a higher velocity than the material of the inner spacers 104 , the gate spacers 98 , the dielectric fins 84 , and the dielectric walls 68 . The furnace may be trimmed by an acceptable etching process that selectively etches the material(s) of the second nanostructures 56 and semiconductor fins 54 . The etching may be isotropic. For example, if the semiconductor fin 54 and the second nanostructure 56B are formed of silicon and the channel spacers 82 and the first nanostructure 56A are formed of silicon germanium, the trimming process is diluted ammonium hydroxide. - It may be a wet etching using a hydrogen peroxide mixture (APM), a sulfuric acid-hydrogen peroxide mixture (SPM), or the like.

A gate dielectric 122 and a gate electrode 124 are formed for a replacement gate. A gate dielectric 122 is conformally deposited in the recess, such as, for example, on the top surface and sidewalls of the semiconductor fin 54 and on the top surface, sidewalls, and bottom surfaces of the second nanostructure 56B. . A gate dielectric 122 may also be deposited on the top surface of the STI region 78 and on the sidewalls of the dielectric fin 84 and dielectric wall 68 .

The gate dielectric 122 includes, for example, one or more dielectric layers such as oxides, metal oxides, metal silicates, etc., or combinations thereof. In some embodiments, the gate dielectric 122 includes silicon oxide, silicon nitride, or multiple layers thereof. In some embodiments, the gate dielectric 122 comprises a high-k dielectric material, and in these embodiments, the gate dielectric 100 may have a k value greater than about 7.0, and may be a metal oxide or hafnium, aluminum, zirconium. , silicates of lanthanum, manganese, barium, titanium, lead, and combinations thereof. The gate dielectric 122 may be multi-layered. For example, in some embodiments, the gate dielectric 122 may include an interfacial layer 122A of silicon oxide formed by thermal or chemical oxidation, respectively, and a metal oxide layer 122b over the interfacial layer. A method of forming the gate dielectric layer 122 may include molecular-beam deposition (MBD), ALD, PECVD, or the like.

A gate dielectric 124 is each deposited over the gate dielectric 122 and fills the remainder of the recess. The gate electrode 124 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although a single layer gate electrode 114 is shown, the gate electrode 124 may include any number of liner layers, any number of work function tuning layers, and filler materials. Any combination of layers that make up the gate electrode 124 may be deposited in the region between each second nanostructure 56B and between the semiconductor fin 54 and the second nanostructure 56B. A method of forming the gate electrode 124 may include ALD, PECVD, or the like.

After filling of the recesses, a planarization process, such as, for example, CMP, may be performed to remove excess portions of gate dielectric 122 and gate electrode 124 , which excess portions are first ILD 114 . and over the top surface of the gate spacer 98 . A recess process, such as an etchback, may then be performed to recess the top surface of the gate dielectric 122 and the gate electrode 124 from the top surface of the dielectric fin 84 . Timed etch processes may be used to stop etching the gate dielectric 122 and gate electrode 124 so that the top surface of the gate electrode 124 is desired for the top second nanostructure 56B. Let it have a height (H ₅ ). The height (H ₅ ) may be in the range of about 6 nm to about 30 nm. Thus, the remaining portions of the material of gate dielectric 122 and gate electrode 124 form a replacement gate structure for the resulting nano-FET.

An etch stop layer 126 is then deposited over the recessed gate structure 120 . Etch stop layer 126 may be formed of a conductive material, such as tungsten, ruthenium, cobalt, copper, molybdenum, nickel, combinations thereof, etc., having a different etch rate than a subsequently formed gate mask that may be deposited by ALD, CVD, PVD, etc. may include In some embodiments, etch stop layer 126 is formed of tungsten, such as fluorine-free tungsten, deposited by a selective deposition process, such as a selective CVD process. Because the etch stop layer 126 is formed of a conductive material, it can serve to stop the etch and can also be used to adjust the contact resistance for the gate structure 120 .

Formation of gate dielectric 122 in region 50N and region 50P may occur simultaneously such that gate dielectric 122 in each region is formed of the same material, and formation of gate electrode 124 in each region It may occur simultaneously so that the gate electrode 124 of the is formed of the same material. In some embodiments, the gate dielectric 122 in each region may be formed by separate processes such that the gate dielectric 122 may be of different materials, and/or the gate electrode 124 in each region may be formed by separate processes. It may be formed by processes such that the gate electrode 124 may be of different materials. Various masking steps may be used to mask and expose the appropriate area when using separate processes. For example, in the illustrated embodiment, gate electrodes 124 of different materials are formed in region 50N and region 50P.

As shown in FIG. 19B , the gate electrode 124 around the channel region 88 of the same forksheet structure 80 may be physically and electrically coupled. This combination can be advantageous in some CMOS processes. For example, when an inverter, a gate, a memory, etc. are formed using a nano-FET, the amount of gate contacts can be reduced by directly connecting the gate electrode 124 . The gate electrode 124 around the channel region 88 of the adjacent forksheet structure 80 is physically and electrically separated by a dielectric fin 84 .

20A , 20B and 20C , a gate mask 128 is formed over each gate structure 120 , eg, on each etch stop layer 126 . Accordingly, each gate mask 128 is disposed between opposing portions of the gate spacers 98 . In some embodiments, forming the gate mask 128 includes forming a dielectric material over the recessed gate structure 120 and then performing a planarization process to remove excess portions of the dielectric material extending over the first ILD 114 . includes doing The dielectric material (eg, a material selected from among the candidate dielectric materials for the liner layer 64 ) may be a low-k dielectric material, which is a conformal deposition process (eg, a candidate method of forming the liner layer 64 ). can be deposited by a method selected from among

A second ILD 132 is then deposited over the gate mask 128 , the first ILD 114 and the gate spacers 98 . The second ILD 132 may be formed of a material selected from the same group of candidate materials of the first ILD 114 and deposited using a method selected from the same group of candidate methods for depositing the first ILD 114 . can be The first ILD 114 and the second ILD 132 may be formed of the same material, or may include different materials. After formation, the second ILD 132 may be planarized by, for example, CMP.

In some embodiments, the etch stop layer 130 is formed between the second ILD 132 and each of the gate mask 128 , the first ILD 114 , and the gate spacers 98 . The etch stop layer 130 may include a dielectric material, eg, silicon nitride, silicon oxide, silicon oxynitride, etc., having a different etch rate than the material of the second ILD layer 132 .

21A , 21B and 21C , the source/drain contact openings 134 are the second ILD 132 , the etch stop layer 130 , the first ILD 114 , the CESL 112 , the dielectric layer 110 and the STI region. (78) is formed. Source/drain contact openings 134 expose facet top and side surfaces of epitaxial source/drain regions 106 . The source/drain contact openings 134 may also expose a top surface of the power rail contacts 74 and expose portions of sidewalls of the semiconductor fins 54 . The source/drain contact openings 134 may be formed using acceptable photolithography and etching techniques. Multiple etching steps may be used to form the source/drain contact openings 134 . As mentioned above, CESL 112 is formed of a material that has high etch selectivity from etching of dielectric layer 110 . One of the etching steps used to form the source/drain contact openings is a selective etching process for the dielectric layer 110 (eg, at a higher rate than the material(s) of the CESL 112 ). ) to etch the material(s) of). Accordingly, the aspect ratio of the lower portion of the source/drain contact openings 134 may be improved, which ensures that sufficient areas of the top surface of the power rail contacts 74 are exposed, which may reduce the contact resistance of the nano-FETs. helps to ensure Specifically, the lower portion of the source/drain contact opening 134 has a width (measured between the sidewall of the dielectric fin 84 and the side surface of the epitaxial source/drain region 106 ) in the range of about 4 nm to about 20 nm. (W ₆ ), wherein the lower portion of the source/drain contact opening 134 is in the range of about 32 nm to about 80 nm (the top surface of the power rail contact 74 and the epitaxial source/drain region 106 ) ) may have a height (H ₆₎ measured between the top surface) of, and the height (H ₆₎ a ratio of width (W ₆₎ is from about 1.6: in the range of 1: 1 to about 20.

In the illustrated embodiment, the source/drain contact openings 134 are formed in a self-aligned patterning method such that all of the first ILDs 114 are removed in the cross-section of FIG. 21A . In another embodiment, other patterning methods may be used such that a portion of the first ILD 114 remains in the cross-section of FIG. 21A .

In the embodiment illustrated in FIG. 21A , etching of the epitaxial source/drain region 106 occurs such that the source/drain contact opening 134 partially extends into the epitaxial source/drain region 106 . In another embodiment, the source/drain contact openings 134 do not extend into the epitaxial source/drain regions 106 .

22A , 22B and 22C , the metal-semiconductor alloy region 136 is the source/drain contact opening 134 as on the portion of the epitaxial source/drain region 106 exposed by the source/drain contact opening 134 . ) is formed selectively. Metal-semiconductor alloy region 136 is a silicide region formed of a metal silicide (eg, titanium silicide, cobalt silicide, nickel silicide, etc.), a metal germanide (eg, titanium germanide, cobalt germanide, nickel germanide, etc.) etc.), a silicon-germanide region formed of both metal silicide and metal germanide, and the like. The metal-semiconductor alloy region 136 may be formed by depositing metal in the source/drain contact openings 134 and then performing a thermal annealing process. The metal may be used in an epitaxial source/drain region ( 106) can be any metal capable of reacting with the semiconductor material (eg, silicon, silicon germanium, germanium, etc.). The metal may be deposited by a deposition process such as ALD, CVD, PVD, or the like, and may be deposited to a thickness ranging from about 1 nm to about 10 nm. In an embodiment, the metal-semiconductor alloy region 136 is a silicide region formed of titanium-silicon. After the thermal annealing process, a cleaning process, such as a wet cleaning, may be performed to remove any from the source/drain contact opening 134 , such as from the surfaces of the power rail contact 74 , the STI region 78 , and the semiconductor fin 54 . of residual metals can be removed.

The metal-semiconductor alloy region 136 may be formed to a desired thickness by controlling the thickness of the metal deposited to form the metal-semiconductor alloy region 136 . The metal-semiconductor alloy region 136 may have a thickness T _{1 in a} range from about 2.5 nm to about 7.5 nm. In some embodiments, the metal used to form the metal-semiconductor alloy region 136 is deposited by a uniform deposition process such as ALD such that the metal-semiconductor alloy region 136 has a uniform thickness. In some embodiments, the metal used to form the metal-semiconductor alloy region 136 is deposited by a non-uniform deposition process such as PVD such that the metal-semiconductor alloy region 136 has a non-uniform thickness. For example, the portion of the metal-semiconductor alloy region 136 on the top surface of the epitaxial source/drain region 106 is a portion of the metal-semiconductor alloy region 136 on the side surface of the epitaxial source/drain region 106 . It may have a greater thickness (T _{1 ) than the portion.} Forming the metal-semiconductor alloy region 136 on the top surface and the side surface of the epitaxial source/drain region 106 may increase the contact area to the epitaxial source/drain region 106, so that the epitaxial source /help to lower the contact resistance compared to forming the metal-semiconductor alloy region 136 on only the top surface of the drain region 106 .

23A , 23B and 23C , source/drain contacts 138 are formed in source/drain contact openings 134 . The source/drain contact openings 134 are formed with a liner such as, for example, a diffusion barrier layer, an adhesive layer, and a conductive material. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, and the like. The liner may be deposited by a conformal deposition process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. In some embodiments, the liner may include an adhesive layer and at least a portion of the adhesive layer may be treated to form a diffusion barrier layer. The conductive material may be tungsten, ruthenium, cobalt, copper, molybdenum, nickel, combinations thereof, or the like. The conductive material may be deposited by ALD, CVD, PVD, or the like. A planarization process, such as CMP, may be performed to remove excess material from the top surface of the second ILD 132 . The remaining liner and conductive material in the source/drain contact openings 134 form the source/drain contacts 138 . Source/drain contact 138 is physically and electrically coupled to power rail contact 74 and metal-semiconductor alloy region 136 (if present) or epitaxial source/drain region 106 .

Source/drain contact 138 has a lower portion (between dielectric fin 84 and epitaxial source/drain region 106) and an upper portion (above epitaxial source/drain region 106). _{The lower portion of the source/drain contact 138 has a width W 7} (measured between the sidewall of the dielectric fin 84 and the side surface of the metal-semiconductor alloy region 136 ) in the range of about 4 nm to about 20 nm. wherein the lower portion of the source/drain contact 138 is in a range of about 32 nm to about 80 nm (measured between the top surface of the power rail contact 74 and the top surface of the metal-semiconductor alloy region 136 ) ) can have a height (H _{7 ). The upper portion of the source/drain contact 138 has a height H 8} (measured between the top surface of the source/drain contact 138 and the top surface of the metal-semiconductor alloy region 136 ) ranging from about 1 nm to about 50 nm. ) can have

Source/drain contact 138 connects epitaxial source/drain region 106 to power rail contact 74 . Accordingly, there is no need for a metal-semiconductor alloy region to be formed on the power rail contact 74 . That is, all surfaces of the power rail contacts 74 are free of metal-semiconductor alloy regions. Accordingly, the manufacturing cost can be reduced.

A gate contact 140 is also formed extending through the second ILD 132 , the etch stop layer 130 , the gate mask 128 , and the etch stop layer 126 . As an example for forming the gate contact 140 , a contact opening is formed through the second ILD 132 , the etch stop layer 130 , the gate mask 128 , and the etch stop layer 126 . The contact openings may be formed using acceptable photolithography and etching techniques. A liner such as, for example, a diffusion barrier layer, an adhesive layer, and the like, and a conductive material are formed in the contact opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, and the like. The liner may be deposited by a conformal deposition process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. In some embodiments, the liner may include an adhesive layer and at least a portion of the adhesive layer may be treated to form a diffusion barrier layer. The conductive material may be tungsten, cobalt, ruthenium, aluminum, nickel, copper, a copper alloy, silver, gold, or the like. The conductive material may be deposited by ALD, CVD, PVD, or the like. A planarization process, such as CMP, may be performed to remove excess material from the top surface of the second ILD 132 . The remaining liner and conductive material in the contact opening form the gate contact 140 . The gate contact 140 is physically and electrically coupled to the gate electrode 124 . The gate contact 140 may have an overall height within a range of about 1 nm to about 50 nm.

Gate contact 140 may be formed before source/drain contact 138 , with source/drain contact 138 , or after source/drain contact 138 . After formation is complete, the top surfaces of the second ILD 132 , the source/drain contacts 138 , and the gate contacts 140 are coplanar (within process variations). In the illustrated embodiment, the source/drain contacts 138 and the gate contacts 140 are formed of different cross-sections to reduce the risk of contact shorts. In another embodiment, a portion or all of the source/drain contact 138 and the gate contact 140 may be formed of the same cross-section.

As discussed in more detail below, a first interconnect structure (eg, a front interconnect structure) will be formed over the substrate 50 . A portion or all of the substrate 50 may then be removed and replaced with a second interconnect structure (eg, a back interconnect structure). Accordingly, the device layer 150 of the active device is formed between the front and back interconnect structures. The front and back interconnect structures each include conductive features electrically connected to the nano-FETs of the device layer 150 . Conductive features (eg, metallization patterns, also referred to as interconnects) of the front surface interconnect structure are electrically connected to the front surfaces of the epitaxial source/drain regions 106 and gate electrodes 124 to provide a logic circuit, a memory circuit , will form a functional circuit such as an image sensor circuit and the like. Conductive features (eg, power rails) of the backside interconnect structure will be electrically connected to the backside of the epitaxial source/drain regions 106 to provide a reference voltage, supply voltage, etc. to the functional circuit. Although device layer 150 is described as having nano-FETs, other embodiments may include device layers having different types of transistors (eg, planar FETs, FinFETs, TFTs, etc.).

24A-29C are cross-sectional views of intermediate steps in the fabrication of a semiconductor device in accordance with some embodiments. Specifically, fabrication of the device layer of a nano-FET is described. 23A, 24A, 25A, 26A, 27A, 28A, and 29A are cross-sectional views taken along reference section A-A of FIG. 1 , except that two gate structures are shown; 23b, 24b, 25b, 26b, 27b, 28b and 29b are cross-sectional views taken along the reference section B-B of FIG. 1 except that four pins are shown; 23c, 24c, 25c, 26c, 27c, 28c and 29c are cross-sectional views taken along the reference section C-C of FIG. 1 except that four pins are shown; 23A, 24A, 25A, 26A, 27A, 28A and 29A may be applied to both the n-type region 50N and the p-type region 50P. The differences (if any) in the structure of the n-type region 50N and the p-type region 50P are described in the text accompanying each figure.

24A , 24B and 24C , interconnect structure 160 is formed on device layer 150 , eg, on second ILD 132 . The interconnect structure 160 connects the front side of the substrate 50/device layer 150 (eg, the side of the substrate 50 over which the device layer 150 is formed, eg, the semiconductor layer 50A). side), so it may also be referred to as a front interconnect structure.

Interconnect structure 160 may include one or more layers of conductive features 162 formed in one or more stacked dielectric layers 164 . Each of the dielectric layers 164 may include a dielectric material, such as a low-k dielectric material, an extra low-k (ELK) dielectric material, or the like. Dielectric layer 164 may be deposited using a suitable process, such as CVD, ALD, PVD, PECVD, or the like.

Conductive features 162 may include conductive lines and conductive vias interconnecting layers of conductive lines. Conductive vias may extend through each of the dielectric layers 164 to provide vertical connections between the layers of conductive lines. Conductive features 162 may be formed through any acceptable process. For example, the conductive features 162 may be formed through a damascene process, such as a single damascene process, a dual damascene process, or the like. In a damascene process, each dielectric layer 164 is patterned using a combination of photolithography and etching techniques to form trenches corresponding to a desired pattern of conductive features 162 . An optional diffusion barrier and/or optional adhesive layer may be deposited and the trench may then be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, or other substitutes, and suitable materials for the conductive material include tungsten, ruthenium, cobalt, copper, molybdenum, nickel, combinations thereof. etc. In an embodiment, the conductive features 162 may be formed by depositing a seed layer of copper or copper alloy and filling the trench by electroplating. A chemical mechanical planarization (CMP) process or the like may be used to remove excess conductive material from the surface of each dielectric layer 164 and planarize the surface for subsequent processing.

In the example shown, five layers of conductive feature 162 and dielectric layer 164 are illustrated. However, it should be understood that interconnect structure 160 may include any number of conductive features disposed in any number of dielectric layers. Conductive features 162 of interconnect structure 160 are electrically connected to gate contacts 140 and source/drain contacts 138 to form functional circuitry. That is, conductive feature 162 interconnects epitaxial source/drain region 106 and gate electrode 124 . In some embodiments, functional circuitry formed by interconnect structure 160 may include logic circuitry, memory circuitry, image sensor circuitry, and the like. The second ILD 132 , the source/drain contacts 138 , and the gate contact 140 are also to be considered part of the interconnect structure 160 , such as part of the first level conductive feature of the interconnect structure 160 . can

The carrier substrate 166 is then bonded to the top surface of the interconnect structure 160 by bonding the layer 168 (eg, including bonding layers 168A, 168B). The carrier substrate 166 may be a glass carrier substrate, a ceramic carrier substrate, a semiconductor substrate (eg, a silicon substrate), a wafer (eg, a silicon wafer), or the like. The carrier substrate 166 may provide structural support during subsequent processing steps and in the finished device. The carrier substrate 166 is substantially free of any active or passive devices.

In various embodiments, carrier substrate 166 may be bonded to interconnect structure 160 using a suitable technique, such as dielectric to dielectric bonding, or the like. Dielectric to dielectric bonding may include depositing bonding layers 168A and 168B on interconnect structure 160 and carrier substrate 166, respectively. In some embodiments, bonding layer 168A includes silicon oxide (eg, high density plasma (HDP) oxide, etc.) deposited by CVD, ALD, PVD, or the like. Bonding layer 168B may likewise be an oxide layer formed prior to bonding using, for example, CVD, ALD, PVD, thermal oxidation, or the like. Other suitable materials may be used for bonding layers 168A, 168B.

The dielectric to dielectric bonding process may further include applying a surface treatment to one or more of the bonding layers 168 . The surface treatment may include plasma treatment. Plasma treatment may be performed in a vacuum environment. After plasma treatment, the surface treatment may further include a cleaning process (eg, rinsing with deionized water or the like) that may be applied to one or more bonding layers 168 . The carrier substrate 166 is then aligned with the interconnect structure 160 , the two being pressed against each other to initiate pre-bonding of the carrier substrate 166 to the interconnect structure 160 . The pre-bonding may be performed at room temperature (eg, within the range of about 20° C. to about 25° C.). After the pre-bonding, an annealing process may be applied, for example, by heating the interconnect structure 160 and carrier substrate 166 to a temperature of about 170°C.

25A , 25B and 25C , the intermediate structure is turned over with the back side of the substrate 50 facing upward. The back side of the substrate 50 means the side opposite to the front side of the substrate 50 on which the device layer 150 is formed. Substrate 50 is then thinned to remove (or at least reduce its thickness) backside portions of substrate 50, such as insulator layer 50B and substrate core 50C. The thinning process may include a planarization process (eg, mechanical grinding, chemical mechanical polishing (CMP), etc.), an etchback process, combinations thereof, and the like. The thinning process exposes the surface of the liner layer 64 and semiconductor fin 54 at the backside of the device layer 150 .

26A , 26B and 26C , semiconductor fin 54 is removed to form recess 142 . Each recess 142 is disposed between the dielectric wall 68 and the power rail contact 74 . The semiconductor fin 54 may be formed using an acceptable photolithography and etching technique, such as an etching process selective to the semiconductor fin 54 (eg, the material of the liner layer 64 and epitaxial source/drain regions 106 ). etching the material of the semiconductor fin 54 at a higher rate). During removal, an underlying layer of epitaxial source/drain region 106 (eg, first layer of semiconductor material 106A) may be used as an etch stop layer when semiconductor fin 54 is etched. An underlying layer of epitaxial source/drain region 106 (eg, first layer of semiconductor material 106A) may be removed (or not removed) during removal of semiconductor fin 54 .

27A , 27B and 27C , a dielectric fin 144 is formed in the recess 142 as on the epitaxial source/drain region 106 . Dielectric fin 144 replaces semiconductor fin 54, which may help reduce parasitic capacitance and/or leakage current of the resulting nano-FET, thereby improving its performance. The dielectric fins 144 are formed of a low-k dielectric material (eg, by a thermal oxidation or conformal deposition process (eg, a method selected from candidate methods of forming the liner layer 64 ). a material selected from candidate dielectric materials for the liner layer 64 ), a high-k dielectric material (eg, a material selected from candidate dielectric materials for the liner layer 64 ), a combination thereof, or the like. In the illustrated embodiment, the dielectric fin 144 includes a first dielectric layer 144A and a second dielectric layer 144B on the first dielectric layer 144A, the first dielectric layer 144A being formed of silicon nitride and a second The dielectric layer 144B is formed of silicon oxide. Forming the first dielectric layer 144A (eg, nitride) is the epitaxial source/drain region 106 and gate structure 120 during formation of the second dielectric layer 144B (eg, oxide). It can help prevent oxidation.

After the material(s) of the dielectric fins 144 are deposited, to remove excess material(s) of the dielectric fins 144 and the liner layer 64 over the power rail contacts 74 and the dielectric walls 68 . A removal process is applied. In some embodiments, a planarization process may be utilized, such as, for example, chemical mechanical polishing (CMP), an etchback process, combinations thereof, and the like. The planarization process exposes the power rail contacts 74 and dielectric walls 68 so that the top surfaces of the power rail contacts 74, dielectric walls 68, liner layer 64, and dielectric fins 144 are finished with the planarization process. After (within process variation) it becomes coplanar. After the planarization process, the first dielectric layer 144A may have a thickness ranging from about 2 nm to about 10 nm, the second dielectric layer 144B may have a height ranging from about 8 nm to about 70 nm, and the dielectric fin 144 may be about The total height may be in the range of 24 nm to about 80 nm, and the height H ₁ of the power rail contact 74 may be in the range of about 20 nm to about 60 nm.

Burying the power rail contacts 74 under the STI region 78 allows them to be exposed through a planarization process, eliminating the need to etch the contact openings to the backside of the power rail contacts 74 . Accordingly, the overlay processing window for backside processing can be widened. Further, since the power rail contact 74 is already connected to the epitaxial source/drain region 106 in the processing step, there is no need for a metal-semiconductor alloy region to be formed on the backside of the power rail contact 74 . Therefore, the contact resistance for the nano-FET can be improved.

28A , 28B and 28C , interconnect structure 170 is formed on the backside of device layer 150 , such as over power rail contacts 74 , dielectric walls 68 and dielectric fins 144 , for example. The interconnect structure 170 may also be referred to as a backside interconnect structure because it is formed on the backside of the device layer 150 . The components of interconnect structure 170 may be similar to interconnect structure 160 . For example, interconnect structure 170 may include a similar material to interconnect structure 160 and may be formed using a similar process. In particular, interconnect structure 170 may include stacked layers of conductive features 172 formed in stacked dielectric layers 174 . Conductive features 172 may include routing lines (eg, for routing to and from subsequently formed contact pads and external connections). The conductive features 172 may further include conductive vias extending from the dielectric layer 174 to provide vertical interconnections between the stacked layers of conductive lines. After formation, the conductive features 172 may have a thickness in the range of about 1 nm to about 50 nm. Power rail contacts 74 connect conductive features 172 of interconnect structure 170 to transistors in device layer 150 and conductive features 162 of interconnect structure 160 .

Part or all of the conductive features 172 are power rail lines, which are conductive lines that electrically connect the epitaxial source/drain regions 106 to a reference voltage, supply voltage, or the like. For example, power rail line 172P may be a first level conductive line of interconnect structure 160 . By placing the power rail line 172P on the back side of the device layer 150 rather than the front side of the device layer 150 , an advantage may be achieved. For example, the gate density of the nano-FET and/or the interconnect density of the interconnect structure 160 may be increased. In addition, the rear surface of the device layer 150 may accommodate a wider power rail to reduce resistance and increase power transfer efficiency to the nano-FET. For example, the width of the conductive feature 172 may be at least twice the width of the first level conductive line (eg, the first conductive line 162A) of the interconnect structure 160 .

In some embodiments, conductive features of interconnect structure 170 may be patterned to include one or more embedded passive devices, such as resistors, capacitors, inductors, and the like. Embedded passive devices may be integrated with conductive features 172 (eg, power rail lines 172P) to provide circuitry (eg, power circuitry) to the backside of device layer 150 .

29A , 29B , and 29C , a passivation layer 182 , UBM 184 , and external connections 186 are formed over interconnect structure 170 . The passivation layer 182 may include, for example, a polymer such as polyimide, polybenzoxazole (PBO), or a benzocyclobutene (BCB)-based polymer. Alternatively, passivation layer 182 may include a non-organic dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or the like. The material of passivation layer 182 may be deposited by, for example, CVD, PVD, ALD, or the like.

UBM 184 is formed through passivation layer 182 to conductive features 172 of interconnect structure 170 and external connections 186 are formed on UBM 146 . The UBM 184 may include one or more layers of copper, nickel, gold, etc. formed by a plating process or the like. An external connection 186 (eg, a solder ball) is formed on the UBM 184 . Forming the external connection 186 may include placing a solder ball on an exposed portion of the UBM 184 and then reflowing the solder ball. In an alternative embodiment, the formation of the external connections 186 includes performing a plating step to form a solder region over the top conductive feature 172 and then reflowing the solder region. In another embodiment, the external contacts 186 are metal contacts having substantially vertical sidewalls, such as micro bumps, for example. UBM 184 and external connections 186 may be used to provide input/output connections to other electrical components such as other device dies, redistribution structures, printed circuit boards (PCBs), motherboards, and the like. UBM 184 and external connections 186 may also be referred to as backside input/output pads, which may provide signal, reference voltage, supply voltage, and/or ground connections to the nano-FETs of device layer 150 .

Embodiments may achieve advantages. Burying the power rail contact 74 under the STI region 78 allows the backside thereof to be exposed through a planarization process, eliminating the need to etch the contact opening into the backside of the power rail contact 74 . Also, because the power rail contact 74 is connected to the epitaxial source/drain region 106 by the source/drain contact 138 , a metal-semiconductor alloy region will be formed on the backside of the power rail contact 74 . no need. Therefore, the contact resistance for the nano-FET can be improved.

In an embodiment, a method includes forming a forksheet structure over a substrate; forming a power rail contact adjacent the forksheet structure; forming an isolation region on the power rail contact, the forksheet structure projecting from the isolation region; growing a first source/drain region in the forksheet structure; depositing an interlayer dielectric (ILD) over the first source/drain regions; and forming a source/drain contact through the ILD and the isolation region, the source/drain contact being connected to the first source/drain region and the power rail contact.

In some embodiments of the method, the forksheet structure includes first nanostructures, second nanostructures, and a dielectric wall between the first nanostructures and the second nanostructures, and wherein the first source/drain regions include the first nanostructures. wherein the method further comprises growing a second source/drain region in the forksheet structure, wherein the second source/drain region is adjacent to the second nanostructure, and wherein the dielectric wall comprises the first source/drain region and the disposed between the second source/drain regions. In some embodiments, the method includes forming a first gate structure around the first nanostructure; and forming a second gate structure around the second nanostructure, wherein the second gate structure is connected to the first gate structure. In some embodiments of the method, the first nanostructures, the second nanostructures and the dielectric wall have longitudinal axes parallel to the first direction, the dielectric wall having the first source/drain regions and the second source/drain regions in the second direction disposed between the regions, wherein the first direction is perpendicular to the second direction. In some embodiments of the method, forming the power rail contact comprises depositing a conductive layer on and adjacent the forksheet structure; and removing a portion of the conductive layer on the forksheet structure, wherein the power rail contact includes a portion of the conductive layer remaining adjacent the forksheet structure. In some embodiments of the method, forming the isolation region comprises depositing a dielectric layer over the forksheet structure and the power rail contact; and removing a portion of the dielectric layer on the forksheet structure, wherein the isolation region includes a portion of the dielectric layer remaining on the power rail contact. In some embodiments of the method, forming the fork seat structure includes: forming a first fin structure and a second fin structure extending from the substrate; depositing a dielectric layer over and between the first and second fin structures; and removing the portion of the dielectric layer over the first fin structure and the second fin structure to form a dielectric wall including a portion of the dielectric layer remaining between the first fin structure and the second fin structure. In some embodiments, the method includes forming a dielectric fin on the isolation region, the first source/drain region being separated from the dielectric fin after growing the first source/drain region; and after growing the first source/drain regions, depositing a dielectric layer between the dielectric fin and the first source/drain regions, wherein the ILD is deposited over the dielectric layer. In some embodiments of the method, forming the source/drain contacts comprises: etching an opening through the ILD, the dielectric layer and the isolation region, a portion of the opening in the ILD exposing a top surface of the first source/drain region wherein portions of the openings in the dielectric layer expose side surfaces of the first source/drain regions, and portions of the openings in the isolation regions expose power rail contacts; forming a metal-semiconductor alloy region on the first source/drain region and within the opening, a portion of the metal-semiconductor alloy region on a top surface of the first source/drain region having a first thickness, wherein the first source/drain region has a first thickness. the portion of the metal-semiconductor alloy region on the side surface of the region has a second thickness, the first thickness being greater than or equal to the second thickness; and forming source/drain contacts on the metal-semiconductor alloy region and the portion of the power rail contact exposed by the opening.

In an embodiment, a device comprises: a power rail contact; an isolation region on the power rail contact; a first dielectric fin on the isolation region; a second dielectric pin adjacent the isolation region and the power rail contact; a first source/drain region on the second dielectric fin; and a source/drain contact between the first source/drain region and the first dielectric fin, the source/drain contact comprising a top surface of the first source/drain region, a side surface of the first source/drain region, and a power rail contact the top surface of the contact.

In some embodiments, the device further includes a liner layer disposed between the first dielectric fin and each of the isolation region and the power rail contact. In some embodiments, the device further comprises a metal-semiconductor alloy region between the source/drain contact and the first source/drain region, wherein the portion of the metal-semiconductor alloy region on a top surface of the first source/drain region comprises a second 1 thickness, the portion of the metal-semiconductor alloy region on the side surface of the first source/drain regions has a second thickness, the first thickness being greater than or equal to the second thickness. In some embodiments of the device, the first thickness and the second thickness are in a range of 2.5 nm to 7.5 nm. In some embodiments of the device, the back surface of the power rail contact and the second dielectric fin are coplanar. In some embodiments, the device comprises: a second dielectric layer on the back surface of the power rail contact and the first dielectric fin; and a power rail line in the second dielectric layer, the power rail line connected to the power rail contact. In some embodiments of the device, the surface of the power rail contact is free of metal-semiconductor alloy regions. In some embodiments, the device comprises: a dielectric layer laterally disposed between the first dielectric fin and the first source/drain regions, the source/drain contacts extending therethrough; and an interlayer dielectric (ILD) on the dielectric layer, the first dielectric fin, and the second dielectric fin, the source/drain contacts extending through the ILD.

In an embodiment, a device includes a first interconnect structure comprising a metallization pattern; a second interconnect structure comprising a power rail line; a device layer comprising a device layer between the first interconnect structure and the second interconnect structure, the device layer comprising: a transistor comprising source/drain regions; a power rail contact connected to the power rail line; and a source/drain contact connected to the power rail contact, the source/drain region, and the metallization pattern.

In some embodiments of the device, the device layer further includes an isolation region that isolates the transistor from other transistors of the device layer, and the power rail contacts are embedded in the isolation region. In some embodiments of the device, the source/drain region has a faceted top surface and a faceted side surface, and the source/drain contacts extend along the faceted top surface and the faceted side surface.

The foregoing description sets forth features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Moreover, those skilled in the art should appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure.

Example

One. In the method,

forming a forksheet structure on the substrate;

forming power rail contacts adjacent the fork seat structure;

forming an isolation region over the power rail contact, wherein the forksheet structure protrudes from the isolation region;

growing a first source/drain region in the forksheet structure;

depositing an interlayer dielectric (ILD) over the first source/drain regions; and

forming source/drain contacts through the ILD and the isolation region;

wherein the source/drain contact is connected to the first source/drain region and the power rail contact.

2. The method of claim 1,

wherein the forksheet structure includes first nanostructures, second nanostructures, and a dielectric wall between the first nanostructures and the second nanostructures, the first source/drain regions adjacent the first nanostructures; , the method is

growing a second source/drain region in the forksheet structure, wherein the second source/drain region is adjacent the second nanostructure, and the dielectric wall comprises the first source/drain region and the second nanostructure. 2 , disposed between the source/drain regions.

3. 3. The method of claim 2,

forming a first gate structure around the first nanostructure; and

forming a second gate structure around the second nanostructure;

further comprising, wherein the second gate structure is connected to the first gate structure.

4. 3. The method of claim 2,

wherein the first nanostructures, the second nanostructures and the dielectric wall have longitudinal axes parallel to a first direction, and wherein the dielectric wall is between the first source/drain region and the second source/drain region in a second direction. and wherein the first direction is perpendicular to the second direction.

5. The method of claim 1 , wherein forming the power rail contact comprises:

depositing a conductive layer on and adjacent the forksheet structure; and

removing a portion of the conductive layer on the fork seat structure;

wherein the power rail contact comprises a portion of the conductive layer remaining adjacent the forksheet structure.

6. The method of claim 1 , wherein forming the isolation region comprises:

depositing a dielectric layer over the forksheet structure and the power rail contact; and

removing a portion of the dielectric layer on the forksheet structure;

and wherein the isolation region comprises a portion of the dielectric layer remaining on the power rail contact.

7. The method of claim 1, wherein the forming of the fork seat structure comprises:

forming a first fin structure and a second fin structure extending from the substrate;

depositing a dielectric layer over and between the first fin structure and the second fin structure; and

removing a portion of the dielectric layer over the first fin structure and the second fin structure to form a dielectric wall comprising a portion of the dielectric layer remaining between the first fin structure and the second fin structure;

A method comprising:

8. The method of claim 1,

forming a dielectric fin on the isolation region, the first source/drain region being separated from the dielectric fin after growing the first source/drain region; and

after growing the first source/drain regions, depositing a dielectric layer between the dielectric fin and the first source/drain regions, wherein the ILD is deposited on the dielectric layer.

A method further comprising:

9. The method of claim 8, wherein the forming of the source/drain contact comprises:

etching an opening through the ILD, the dielectric layer and the isolation region, wherein a portion of the opening in the ILD exposes a top surface of the first source/drain region, and wherein a portion of the opening in the dielectric layer comprises the second 1 expose a side surface of a source/drain region, and a portion of the opening in the isolation region exposes the power rail contact;

forming a metal-semiconductor alloy region on the first source/drain region and within the opening, wherein a portion of the metal-semiconductor alloy region on a top surface of the first source/drain region has a first thickness; 1 the portion of the metal-semiconductor alloy region on the side surface of the source/drain regions has a second thickness, the first thickness being at least a second thickness; and

forming the source/drain contacts on the metal-semiconductor alloy region and the portion of the power rail contact exposed by the opening;

A method comprising:

10. In the device,

power rail contacts;

an isolation region on the power rail contact;

a first dielectric fin on the isolation region;

a second dielectric fin adjacent the isolation region and the power rail contact;

a first source/drain region on the second dielectric fin; and

a source/drain contact between the first source/drain region and the first dielectric fin, a top surface of the first source/drain region, a side surface of the first source/drain region, and a top of the power rail contact the source/drain contact in contact with the surface

A device comprising a.

11. 11. The method of claim 10,

and a liner layer disposed between a first dielectric fin and each of the isolation region and the power rail contact.

12. 11. The method of claim 10,

a metal-semiconductor alloy region between the source/drain contact and the first source/drain region, wherein a portion of the metal-semiconductor alloy region on a top surface of the first source/drain region has a first thickness , wherein the portion of the metal-semiconductor alloy region on the side surface of the first source/drain region has a second thickness, the first thickness being at least the second thickness.

13. 13. The method of claim 12,

wherein the first thickness and the second thickness are in the range of 2.5 nm to 7.5 nm.

14. 11. The method of claim 10,

and the back surface of the power rail contact and the second dielectric fin are coplanar.

15. 15. The method of claim 14,

a second dielectric layer on the back surface of the power rail contact and the first dielectric fin; and

a power rail line in the second dielectric layer, the power rail line connected to the power rail contact

A device further comprising a.

16. 15. The method of claim 14,

wherein the surface of the power rail contact is free of metal-semiconductor alloy regions.

17. 11. The method of claim 10,

a dielectric layer laterally disposed between the first dielectric fin and the first source/drain regions, the source/drain contacts extending therethrough; and

an interlayer dielectric (ILD) on the dielectric layer, the first dielectric fin, and the second dielectric fin, the source/drain contacts extending through the ILD;

Further comprising, the device.

18. In the device,

a first interconnect structure comprising metallization patterns;

a second interconnect structure comprising a power rail line;

a device layer between the first interconnect structure and the second interconnect structure

comprising, the device layer comprising:

a transistor comprising source/drain regions;

a power rail contact connected to the power rail line; and

A source/drain contact connected to the power rail contact, the source/drain region, and the metallization pattern.

A device comprising a.

19. 19. The method of claim 18, wherein the device layer comprises:

and an isolation region isolating the transistor from other transistors in the device layer, wherein the power rail contact is buried in the isolation region.

20. 19. The method of claim 18,

wherein the source/drain region has a faceted top surface and a faceted side surface, and wherein the source/drain contacts extend along the faceted top surface and the faceted side surface.

Claims (10)

In the method,
forming a forksheet structure on the substrate;
forming power rail contacts adjacent the fork seat structure;
forming an isolation region over the power rail contact, wherein the forksheet structure protrudes from the isolation region;
growing a first source/drain region in the forksheet structure;
depositing an interlayer dielectric (ILD) over the first source/drain regions; and
forming source/drain contacts through the ILD and the isolation region;
wherein the source/drain contact is connected to the first source/drain region and the power rail contact. According to claim 1,
wherein the forksheet structure includes first nanostructures, second nanostructures, and a dielectric wall between the first nanostructures and the second nanostructures, the first source/drain regions adjacent the first nanostructures; , the method is
growing a second source/drain region in the forksheet structure, wherein the second source/drain region is adjacent the second nanostructure, and the dielectric wall comprises the first source/drain region and the disposed between the second source/drain regions. 3. The method of claim 2,
forming a first gate structure around the first nanostructure; and
forming a second gate structure around the second nanostructure;
further comprising, wherein the second gate structure is connected to the first gate structure. 3. The method of claim 2,
wherein the first nanostructures, the second nanostructures and the dielectric wall have longitudinal axes parallel to a first direction, and wherein the dielectric wall is between the first source/drain region and the second source/drain region in a second direction. and wherein the first direction is perpendicular to the second direction. The method of claim 1 , wherein forming the power rail contact comprises:
depositing a conductive layer on and adjacent the forksheet structure; and
removing a portion of the conductive layer on the fork seat structure;
wherein the power rail contact comprises a portion of the conductive layer remaining adjacent the forksheet structure. The method of claim 1 , wherein forming the isolation region comprises:
depositing a dielectric layer over the forksheet structure and the power rail contact; and
removing a portion of the dielectric layer on the forksheet structure;
and wherein the isolation region comprises a portion of the dielectric layer remaining on the power rail contact. The method of claim 1, wherein the forming of the fork seat structure comprises:
forming a first fin structure and a second fin structure extending from the substrate;
depositing a dielectric layer over and between the first and second fin structures; and
removing a portion of the dielectric layer over the first fin structure and the second fin structure to form a dielectric wall comprising a portion of the dielectric layer remaining between the first fin structure and the second fin structure;
A method comprising: According to claim 1,
forming a dielectric fin on the isolation region, the first source/drain region being separated from the dielectric fin after growing the first source/drain region; and
after growing the first source/drain regions, depositing a dielectric layer between the dielectric fin and the first source/drain regions, wherein the ILD is deposited on the dielectric layer.
A method further comprising: In the device,
power rail contacts;
an isolation region on the power rail contact;
a first dielectric fin on the isolation region;
a second dielectric fin adjacent the isolation region and the power rail contact;
a first source/drain region on the second dielectric fin; and
a source/drain contact between the first source/drain region and the first dielectric fin, a top surface of the first source/drain region, a side surface of the first source/drain region, and a top of the power rail contact the source/drain contact in contact with the surface
A device comprising a. In the device,
a first interconnect structure comprising metallization patterns;
a second interconnect structure comprising a power rail line;
a device layer between the first interconnect structure and the second interconnect structure
comprising, the device layer comprising:
a transistor comprising source/drain regions;
a power rail contact connected to the power rail line; and
a source/drain contact connected to the power rail contact, the source/drain region, and the metallization pattern
A device comprising a.

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