CN113363215A

CN113363215A - Semiconductor device and method of forming the same

Info

Publication number: CN113363215A
Application number: CN202110578143.0A
Authority: CN
Inventors: 苏焕杰; 庄正吉; 张尚文; 邱奕勋; 王培宇; 蔡庆威; 王志豪
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2020-05-27
Filing date: 2021-05-26
Publication date: 2021-09-07
Also published as: DE102020134570A1; TW202145365A; KR102515314B1; TWI782473B; KR20210147861A

Abstract

Embodiments of the invention disclose a semiconductor device and a method of forming the same. In one embodiment, a semiconductor device includes: a power rail contact; an isolation region on the power rail contact; a first dielectric fin on the isolation region; a second dielectric fin adjacent the isolation region and the power rail contact; a first source/drain region on the second dielectric fin; a source/drain contact between the first source/drain region and the first dielectric fin, the source/drain contact connected to the first source/drain region and the power rail contact.

Description

Semiconductor device and method of forming the same

Technical Field

Embodiments of the invention relate to semiconductor devices and methods of forming the same.

Background

Semiconductor devices are used in various electronic applications such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are generally manufactured by: insulating or dielectric layers of materials, conductive layers, and semiconductor layers are sequentially deposited on a semiconductor substrate and patterned using photolithography on the various material layers to form circuit components and elements thereon.

The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuing to reduce the minimum component size, which allows more components to be integrated into a given area. However, as the minimum component size decreases, other problems arise that should be addressed.

Disclosure of Invention

According to an aspect of an embodiment of the present invention, there is provided a method of forming a semiconductor device, including: forming a fork plate structure above the substrate; forming a power rail contact adjacent the fork strap structure; forming an isolation region on the power rail contact, the prong structure protruding from the isolation region; growing a first source/drain region in the fork plate structure; depositing an interlayer dielectric (ILD) over the first source/drain region; and forming a source/drain contact through the ILD and the isolation region, the source/drain contact connected to the first source/drain region and the power rail contact.

According to another aspect of an embodiment of the present invention, there is provided a semiconductor device including: a power rail contact; an isolation region on the power rail contact; a first dielectric fin on the isolation region; a second dielectric fin adjacent the isolation region and the power rail contact; a first source/drain region on the second dielectric fin; and a source/drain contact between the first source/drain region and the first dielectric fin, the source/drain contact contacting a top surface of the first source/drain region, a side surface of the first source/drain region, and a top surface of the power rail contact.

According to still another aspect of an embodiment of the present invention, there is provided a semiconductor device including: a first interconnect structure comprising a metallization pattern; a second interconnect structure including power traces; a device layer between the first interconnect structure and the second interconnect structure, the device layer comprising: a transistor including source/drain regions; a power rail contact connected to the power rail; and a source/drain contact connected to the power rail contact, the source/drain region, and the metallization pattern.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1 illustrates an example of a nanostructured field effect transistor (nano-FET) in a three-dimensional view according to some embodiments.

Fig. 2-23C are cross-sectional views of intermediate stages in the manufacture of semiconductor devices according to some embodiments.

Fig. 24A-29C are various views of other intermediate stages in the manufacture of a semiconductor device, according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, for ease of description, spaced relationship terms such as "below …," "below …," "lower," "above …," "upper," etc. may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures. The term spaced relationship is intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relationship descriptors used herein interpreted accordingly as such.

According to some embodiments, power rail contacts for layers of a nanofet are buried under an isolation region surrounding the nanofet. Source/drain contacts can be used to couple source/drain regions of the nanofet to the upper interconnect and the lower power rail contact. Thus, the source/drain regions can be attached to the backside power rail and do not require the formation of a metal-semiconductor alloy on the backside of the power rail contacts.

FIG. 1 illustrates an example of a simplified nano-FET according to some embodiments. Fig. 1 is a cut three-dimensional view with some components of the nanofet omitted for clarity. In the illustrated embodiment, the nanofets are fork plate FETs. The nanofet may be a nanosheet field effect transistor (NSFET), nanowire field effect transistor (NWFET), wrap-around gate field effect transistor (GAAFET), or the like.

The nanofet includes nanostructures 56 over the substrate 50, for example over fins 54 extending from the substrate 50. The nanostructures 56 are semiconductor layers that serve as channel regions for the nanofets. An isolation region 78, such as a Shallow Trench Isolation (STI) region, is disposed over the substrate 50 and adjacent to the fin 54. Although isolation regions 78 are described/illustrated as being separate from substrate 50, as used herein, "substrate" may refer to substrate 50 alone or a combination of substrate 50 and isolation regions 78. Additionally, although the fin 54 is shown as a single, continuous material with the substrate 50, the fin 54 and/or the substrate 50 may comprise a single material or multiple materials. In this context, fin 54 refers to the portion that extends over and between adjacent isolation regions 78.

Gate structure 120 is wrapped around nanostructures 56 and disposed over fins 54. Gate structure 120 includes a gate dielectric 122 and a gate electrode 124. The gate dielectric 122 is along the top, sidewalls, and bottom surfaces of the nanostructures 56, and may extend along the sidewalls and/or top surface of the fins 54. A gate electrode 124 is on the gate dielectric 122. Epitaxial source/drain regions 106 are disposed on opposite sides of gate structure 120. In embodiments where multiple transistors are formed, the epitaxial source/drain regions 106 may be shared between the various transistors. One or more interlayer dielectric (ILD) layers (discussed in more detail below) are formed over the epitaxial source/drain regions 106 and/or the gate structure 120 through the ILD layers (discussed in more detail below) to make contact with the drain regions 106 and the gate electrode 124.

Substrate 50 has an N-type region 50N and a P-type region 50P. N-type region 50N comprises an N-type device, such as an NMOS transistor, e.g., an N-type nano-FET, and P-type region 50P comprises a P-type device, such as a PMOS transistor, e.g., a P-type nano-FET. In the illustrated embodiment, the nanofets are fork plate FETs. In a cross-plate FET, both the n-type and p-type devices are integrated in the same cross-plate structure. Dielectric walls 68 separate semiconductor fin 54, nanostructure 56 of the n-type device, and epitaxial source/drain regions 106 from semiconductor fin 54, nanostructure 56, and epitaxial source/drain regions 106 of the p-type device. Gate structure 120 extends along three sides of each nanostructure 56. The cross-plate FET allows the n-type and p-type devices to be formed close to each other and allows the gate structure 120 of the device to be physically and electrically coupled to the other, thereby reducing the number of gate contacts used in the CMOS process. Dielectric fins 84 are formed over the isolation regions 78 at the cell boundaries, separating adjacent fork plate FETs.

Some embodiments discussed herein are discussed in the context of a nanofet formed using a gate-last process. In other embodiments, a gate first process may be used. Also, some embodiments contemplate aspects for use in planar devices such as planar FETs or fin field effect transistors (finfets).

Fig. 1 further illustrates a reference cross-section used in subsequent figures. Cross section a-a is along the longitudinal axis of the nanostructure 56 and, for example, in the direction of current flow between the epitaxial source/drain regions 106. Section B-B is perpendicular to section a-a and along the longitudinal axis of the gate structure, and section C-C is perpendicular to section a-a and extends through the epitaxial source/drain region 106. For clarity, the subsequent figures refer to these reference sections.

Fig. 2-23C are cross-sectional views of intermediate stages in the manufacture of semiconductor devices according to some embodiments. In particular, fabrication of a device layer of a nanofet is shown. Fig. 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 and 15 are cross-sectional views taken along a reference section B-B in fig. 1, but in which four fins are shown. Fig. 16A, 17A, 18A, 19A, 20A, 21A, 22A, and 23A are sectional views shown along a reference section a-a in fig. 1, except that two gate structures are shown. Fig. 16B, 17B, 18B, 19B, 20B, 21B, 22B, and 23B are sectional views shown along a reference section B-B in fig. 1, except that four fins are shown. Fig. 16C, 17C, 18C, 19C, 20C, 21C, 22C, and 23C are sectional views shown along a reference section C-C in fig. 1, except that four fins are shown.

In fig. 2, a substrate 50 for forming a nanofet is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. Substrate 50 may be a wafer, such as a silicon wafer. In the illustrated embodiment, the substrate 50 is an SOI substrate. Typically, the SOI substrate is a semiconductor layer 50A formed on an insulator layer 50B. The insulator layer 50B may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. Insulator layer 50B is disposed on substrate core 50C, which is typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of substrate 50 (e.g., semiconductor layer 50A) may include silicon; for example, silicon germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, and/or gallium indium phosphide; or a combination thereof.

Substrate 50 has an N-type region 50N and a P-type region 50P. N-type region 50N may be used to form an N-type device, such as an NMOS transistor, e.g., an N-type nanofet, and P-type region 50P may be used to form a P-type device, such as a PMOS transistor, e.g., a P-type nanofet. As discussed in more detail below, although one N-type region 50N and one P-type region 50P are shown, substrate 50 may include any desired number of such regions.

The substrate 50 may be lightly doped with p-type or n-type impurities. An anti-punch-through (APT) implant may be performed on an upper portion of the substrate 50 to form an APT region. During the APT implant, dopants may be implanted into the N-type region 50N and the P-type region 50P. The dopant may have a conductivity type opposite to that of the source/drain regions to be subsequently formed in each of the N-type region 50N and the P-type region 50P. The APT region may extend under source/drain regions subsequently formed in a nano-FET formed in a subsequent process. APT regions may be used to reduce leakage from the source/drain regions to the substrate 50. In some embodiments, the doping concentration in the APT region may be about 10¹⁸cm^-3To about 10¹⁹cm^-3Within the range of (1).

In fig. 3, a multi-layer stack 52 is formed over a substrate 50. The multilayer stack 52 includes alternating first and

second semiconductor layers

52A and 52B. The first semiconductor layer 52A is formed of a first semiconductor material, and the second semiconductor layer 52B is formed of a second semiconductor material. The semiconductor materials may each be selected from candidate semiconductor materials for substrate 50. In the illustrated embodiment, the multilayer stack 52 includes four layers of each of the first semiconductor layer 52A and the second semiconductor layer 52B. It should be understood that the multi-layer stack 52 may include any number of first and second semiconductor layers 52A, 52B. For example, the multilayer stack 52 may include about three to about eight layers of each of the first semiconductor layer 52A and the second semiconductor layer 52B.

In the embodiment shown, the second semiconductor layer 52B will be used to form a channel region for the nanofet in both the N-type region 50N and the P-type region 50P. The first semiconductor layer 52A is a sacrificial layer (or dummy layer) which will be removed in a subsequent process to expose the top and bottom surfaces of the second semiconductor layer 52B in both regions. The second semiconductor material of the second semiconductor layer 52B is a material suitable for n-type and p-type nano-FETs, such as silicon, and the material of the first semiconductor layer 52A has a high etch selectivity with respect to etching of the second semiconductor material, such as silicon germanium.

In another embodiment, the first semiconductor layer 52A will be used to form a channel region for the nanofet in one region (e.g., P-type region 50P) and the second semiconductor layer 52B will be used to form a channel region for the nanofet in another region (e.g., N-type region 50N). The first semiconductor material of the first semiconductor layer 52A may be suitable for a p-type nanofet, such as silicon germanium (e.g., Si)_xGe_1-xWhere x may be in the range of 0 to 1), pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, and the like. The second semiconductor material of the second semiconductor layer 52B may be suitable for n-type nano-FETs such as silicon, silicon carbide, III-V compound semiconductors, II-VI compound semiconductors, and the like. The etching of the first semiconductor material and the second semiconductor material with respect to each other may have a high etching selectivity, so that the first semiconductor layer 52A may be removed without removing the second semiconductor layer 52B in the N-type region 50N, and the semiconductor layer 52B may be removed without removing the first semiconductor layer 52A in the P-type region 50P.

Each layer of the multi-layer stack 52 may be grown by a process such as Vapor Phase Epitaxy (VPE) or Molecular Beam Epitaxy (MBE), deposited by a process such as Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD), or the like. Each layer may be formed to a small thickness, for example, a thickness in the range of about 5nm to about 30 nm. In some embodiments, one set of layers (e.g., the second semiconductor layer 52B) is formed thinner than the other set of layers (e.g., the first semiconductor layer 52A). For example, in some embodiments in which the first semiconductor layer 52A is a sacrificial layer (or dummy layer) and the second semiconductor layer 52B is used to form a channel region, the second semiconductor layer 52B may be thicker than the first semiconductor layer 52A. The relative thicknesses of the layers may be based on the desired channel height and channel work function requirements of the resulting nanofet.

In fig. 4, trenches 60 are etched in substrate 50 and multilayer stack 52 to form fin structures 62 (including fin structure 62N in N-type region 50N and fin structure 62P in P-type region 50P). Fin structures 62 each include a semiconductor fin 54 and a nanostructure 56. The semiconductor fins 54 are semiconductor strips patterned in the substrate 50. In embodiments where the substrate 50 is an SOI substrate, the semiconductor fin 54 comprises a remaining portion of the semiconductor layer 50A. The nanostructures 56 comprise the remaining portion of the multi-layer stack 52 on the semiconductor fin 54. In particular, the nanostructures 56 include alternating first nanostructures 56A and second nanostructures 56B. The first nanostructures 56A and the second nanostructures 56B are formed from the remaining portions of the first semiconductor layer 52A and the second semiconductor layer 52B, respectively. In the illustrated embodiment, the second nanostructures 56B are respectively disposed between two first nanostructures 56A. The etch may be any acceptable etch process, such as Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), or the like, or combinations thereof, and may be performed using mask 58 having the pattern of fin structure 62. The etching may be anisotropic.

Mask 58 may be a single layer mask or may be a multi-layer mask, such as a multi-layer mask that includes a first masking layer 58A and a second masking layer 58B on first masking layer 58A, respectively. First masking layer 58A and second masking layer 58B may each be formed of a dielectric material such as silicon oxide, silicon nitride, combinations thereof, and the like, and may be deposited or thermally grown according to acceptable techniques. The material of the first mask layer 58A may have a high etch selectivity compared to the etching of the material of the second mask layer 58B. For example, the first mask layer 58A may be formed of silicon oxide, and the second mask layer 58B may be formed of silicon nitride.

Fin structure 62 may be patterned by any suitable method. For example, fin structure 62 may be patterned using one or more photolithography processes, including a double patterning process or a multiple patterning process. Typically, double patterning or multiple patterning processes combine lithographic and self-aligned processes, allowing for the generation of patterns with, for example, pitches smaller than those obtainable using single pass direct lithography. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers may then be used to pattern fin structure 62. In some embodiments, mask 58 (or other layer) may remain on fin structure 62.

Fin structure 62 may have a width in a range of about 5nm to about 20 nm. For illustrative purposes, fin structures 62 in N-type region 50N and P-type region 50P are shown to have substantially equal widths. In some embodiments, fin structures 62 in one region (e.g., N-type region 50N) may be wider or narrower than fin structures 62 in another region (e.g., P-type region 50P).

Fin structures 62 are formed as adjacent pairs. Each pair of fin structures 62 will be used to form a fork plate FET. One fin structure 62N of each pair will be used to form an N-type device and the other fin structure 62P of each pair will be used to form a P-type device. Each pair of

fin structures

62N, 62P is separated by a respective first trench 60A. A dielectric wall (discussed in more detail below) will be formed in the trench 60A between each pair of

fin structures

62N, 62P to provide electrical isolation between the different types of nanofets to be formed in the

fin structures

62N, 62P. The trench 60A may have a first width W in the range of about 6nm to about 30nm₁. Adjacent pairs of fin structures 62 are separated by respective second trenches 60B. The trench 60B may have a second width W in the range of about 22nm to about 46nm₂. Width W₂Is greater than the first width W₁Such that adjacent pairs of fin structures 62 are spaced apart from each pair of

fin structures

62N, 62P.

In fig. 5, liner layer 64 is formed over mask 58 (if present), fin structure 62, and substrate 50. Liner 64 will serve to separate fin structure 62 from subsequently formed contacts. Liner 64 may be formed of a dielectric material, which may be formed by a thermal oxidation or conformal deposition process. Acceptable dielectric materials include low-k dielectric materials (e.g., those having k values less than about 7), such as silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbide, and the like; high-k dielectric materials (e.g., dielectric materials having a k value greater than about 7), such as hafnium oxide, zirconium oxide, aluminum zirconium oxide, hafnium aluminum oxide, hafnium silicon oxide, aluminum oxide, and the like; combinations thereof; and so on. Acceptable deposition processes include Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), Molecular Beam Deposition (MBD), Physical Vapor Deposition (PVD), and the like. In some embodiments, liner 64 is formed from silicon oxide by thermal oxidation. The liner 64 may be formed to a thickness in the range of about 1nm to about 10 nm.

A dielectric layer 66 is then formed on the liner layer 64. Dielectric layer 66 may be formed of a low-k dielectric material (e.g., one selected from the candidate dielectric materials for liner layer 64) that may be deposited by a conformal deposition process, such as one selected from the candidate methods of forming liner layer 64. The material of the dielectric layer 66 has a different k value than the material of the pad layer 64 and has a high etch selectivity compared to the etching of the material of the pad layer 64. In some embodiments, the dielectric layer 66 is formed of silicon nitride by ALD or CVD.

Because the

trenches

60A, 60B have different widths, they are filled with different amounts of dielectric material. Liner 64 is formed along the sidewalls and bottom of

trenches

60A, 60B. Because trenches 60A have a narrower width, they are completely filled (or overfilled) with dielectric layer 66. However, because trenches 60B have a larger width, they are not completely filled by dielectric layer 66. After depositing dielectric layer 66, trench 60A is filled (or overfilled), but some portions of trench 60B remain unfilled.

In fig. 6, the dielectric layer 66 is etched back to remove portions of the dielectric layer 66. Specifically, portions of dielectric layer 66 in trenches 60B and over mask 58 (if present) or fin structure 62 are removed. By the etch back, the trench 60B is newly formed. Acceptable etch techniques are used, such as with an etch process that is selective to dielectric layer 66 (e.g., to be more selective than the material of liner 64)The material of the dielectric layer 66 is etched at a fast rate), the thickness of the dielectric layer 66 is etched back and forth. After the etch back is complete, the remaining portion of the dielectric layer 66 is in the trench 60A. The remaining portion of dielectric layer 66 forms dielectric walls 68, which dielectric walls 68

separate fin structures

62N, 62P of each pair of fin structures 62. The dielectric wall 68 may partially or completely fill the trench 60A. The dielectric wall 68 may have a width W in the range of about 6nm to about 30nm₃. After the dielectric layer 66 is formed, the prong plate structure 80 extends from the substrate 50. Fork plate structures 80 each include a dielectric wall 68 and a pair of fin structures 62, with dielectric wall 68 disposed between fin structures 62.

As noted above, although one N-type region 50N and one P-type region 50P are shown, substrate 50 may include any desired number of such regions. Each prong structure 80 is disposed at the boundary of the N-type region 50N and the P-type region 50P. Further, the

fin structures

62N, 62P of each prong structure 80 alternate. In other words, each N-type region 50N includes a first fin structure 62N from the first prong structure 80 and includes a second fin structure 62N from the second prong structure 80.

In fig. 7, a conductive layer 72 is deposited over the dielectric wall 68 and the liner layer 64. Conductive layer 72 fills trench 60B and may also be formed on mask 58 (if present) or fin structure 62. Dielectric wall 68 partially fills trench 60A and conductive layer 72 may also be formed in the remaining portion of trench 60A. The conductive layer 72 may be formed of a metal or a metal-containing material, which may be formed by a deposition process (e.g., ALD, CVD, PVD, etc.), a plating process (e.g., electroplating, electroless plating, etc.), such as tungsten (W), ruthenium (Ru), cobalt (Co), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), nickel (Ni), an alloy thereof, or the like.

In fig. 8, the conductive layer 72 is etched back to remove portions of the conductive layer 72. Specifically, a portion of conductive layer 72 in trench 60A and over mask 58 (if present) or fin structure 62 is removed by an etch-back. The thickness of conductive layer 72 is etched back and forth using an acceptable etching technique, such as with an etching process that is selective to conductive layer 72 (e.g., etching the material of conductive layer 72 at a faster rate than the material of conductive layer 72). After etching backThereafter, the remaining portion of conductive layer 72 is disposed in trench 60B. The portion of conductive layer 72 remaining in trench 60B forms a power rail contact 74 between prong structures 80. To a desired height H at the power rail contact 74₁Thereafter, a timed etch process may be used to stop etching of conductive layer 72. Height H₁And may range from about 20nm to about 60 nm. Further, the power rail contact 74 may have a width W in the range of about 6nm to about 30nm₄。

In fig. 9, insulative material 76 is formed in the remaining portions of trench 60A, adjacent to prong structure 80. Insulating material 76 may be deposited over mask 58 (if present) or fin structure 62 and in

trenches

60A, 60B. The insulating material 76 may be an oxide such as silicon oxide, a nitride such as silicon nitride, or the like, or combinations thereof, and may be formed by high density plasma CVD (HDP-CVD), flowable CVD (fcvd), or the like, or combinations thereof. Other insulating materials formed by any acceptable process may be used. Once the insulating material 76 is formed, an annealing process may be performed. Although insulating material 76 is shown as a single layer, some embodiments may utilize multiple layers. A removal process is then applied to insulative material 76 to remove excess material of liner 64 and insulative material 76 over mask 58 (if present) or fin structure 62. In some embodiments, a planarization process, such as a chemical process, may utilize a mechanical polishing (CMP), an etch-back process, combinations thereof, and the like. The planarization process exposes the mask 58 or the nanostructures 56 such that the top surface of the mask 58 or the nanostructures 56, the rest of the liner 64, and the insulating material 76, respectively, are coplanar (within process variations) after the planarization process. In the embodiment shown, the mask 58 remains after the planarization process. In another embodiment, the mask 58 may also be removed by a planarization process.

In fig. 10, insulative material 76 is recessed to form STI regions 78, thereby reforming portions of trenches 60B. Insulating material 76 is recessed such that at least a portion of nanostructures 56 protrude from STI regions 78. In the embodiment shown, the top surface of STI region 78 is below the top surface of semiconductor fin 54. The top surface of the STI region 78 is above or with the top surface of the semiconductor fin 54The top surfaces of the fins 54 are coplanar (within process variations). Further, the top surface of the STI region 78 may have a flat surface, a convex surface, a concave surface (e.g., a recess), or a combination thereof as shown. The top surface of STI regions 78 may be formed flat, convex, and/or concave by appropriate etching. STI regions 78 may be recessed using an acceptable etch process, such as an etch process that is selective to insulative material 76 (e.g., selectively etches the material of insulative material 76 at a faster rate than the material of insulative material 76). For example, oxide removal using, for example, dilute hydrofluoric acid (dHF) acid may be used. To a desired height H in the STI region 78₂Thereafter, a timed etch process may be used to stop the etching of insulating material 76. Height H₂And may range from about 5nm to about 20 nm. The liner layer 64 may also be recessed during recessing of the insulating material 76. After recessing, the top surfaces of insulating material 76 and pad layer 64 may be coplanar (varying across the process).

After forming the STI regions 78, a prong structure 80 extends from between adjacent STI regions 78. STI regions 78 are formed over the power rail contacts 74 and are buried over the power rail contacts 74. Each liner 64 is disposed between an STI region 78 and a power rail contact 74. It should be understood that the above-described process is merely one example of how the fork plate structure 80 may be formed. Other acceptable processes may also be used to form the fork plate structure 80 and STI regions 78. The fork plate structure 80 may be processed in a similar manner as the semiconductor fin will be processed in the process of forming the FinFET. Processing the fork plate structure 80 in this manner allows both n-type devices and p-type devices to be integrated into the same fork plate structure 80.

In fig. 11, channel spacers 82 are formed over and around the fork plate structure 80, for example in portions of the trenches 60B. The channel spacers 82 may be formed of a semiconductor material, such as one selected from the candidate semiconductor materials of the substrate 50, which may be grown by a process such as Vapor Phase Epitaxy (VPE) or Molecular Beam Epitaxy (MBE), deposited by a process such as Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD). In some embodiments, the channel spacers 82 are grown by epitaxial growth, which may include growing a thin seed layer on the fin structure 62, and then growing the material of the channel spacers 82 from the seed layer. The seed layer may be grown after forming fin structures 62 (e.g., after etching trenches 60 in substrate 50, as discussed above with respect to fig. 4). An anisotropic etch may be performed after the material forming the channel spacers 82, thereby exposing the STI regions 78. The channel spacers 82 act as temporary spacers during processing and will be subsequently removed to expose the portions of the nanostructures 56 that will serve as the channel regions of the nanofets. Specifically, in the illustrated embodiment, the channel spacers 82 and the first nanostructures 56A will be subsequently removed and replaced by gate structures formed around three sides of the second nanostructures 56B. Thus, the channel spacer 82 is formed of a material having a high etch selectivity compared to the etching of the material of the second nanostructure 56B. The channel spacer 82 may be formed of the same semiconductor material as the first nanostructure 56A, or may be formed of a different material.

In fig. 12, dielectric fins 84 are formed between the channel spacers 82 and on the STI regions 78, e.g., in the remaining portions of the trenches 60B not filled by the channel spacers 82. Thus, each trench 60B is filled with a pair of channel spacers 82 and a dielectric fin 84, the dielectric fin 84 being located between the channel spacers 82. The dielectric fin 84 may be formed of a low-k dielectric material (e.g., one selected from the candidate dielectric materials forming the liner 64), a high-k dielectric material (e.g., one selected from the candidate dielectric materials of the liner 64), combinations thereof, or the like, which may be formed by a thermal oxidation or conformal deposition process (e.g., one selected from the candidate methods of the liner 64). In the illustrated embodiment, each dielectric fin 84 includes a first dielectric layer 84A and a second dielectric layer 84B on the first dielectric layer 84A, wherein the first dielectric layer 84A is formed of silicon carbonitride, silicon oxycarbide, or silicon oxycarbide and the second dielectric layer 84B is formed of silicon oxide. The dielectric fin 84 may have a width W in a range of about 6nm to about 30nm₅。

A removal process is then applied to dielectric fin 84 to remove excess material of dielectric fin 84 above channel spacers 82. In some embodiments, a planarization process is performed, which may utilize, for example, Chemical Mechanical Polishing (CMP), etch back, combinations thereof, and the like. The planarization process exposes the channel spacers 82 so that the top surfaces of the channel spacers 82 and the dielectric fin 84 are coplanar (within process variations) after the planarization process is complete.

In fig. 13, dielectric fin 84 is optionally recessed to reform a portion of trench 60B. The dielectric fin 84 may be recessed using an acceptable etch process, such as an etch process that is selective to the dielectric fin 84 (e.g., selectively etching the material of the first and second

dielectric layers

84A, 84B at a faster rate than the material of the channel spacer 82).

In fig. 14, a third dielectric layer 84C for the dielectric fin 84 is optionally formed in the trench 60B, such as on the first and second

dielectric layers

84A and 84B. The third dielectric layer 84C may be formed of a high-k dielectric material (such as one selected from the candidate dielectric materials for the liner 64) that may be deposited by a conformal deposition process (such as one selected from the candidate formation methods for the liner 64). A removal process is then applied to remove excess material of third dielectric layer 84C and channel spacers 82 over mask 58 (if present) or fin structure 62. In some embodiments, a planarization process such as chemical mechanical planarization may use polishing (CMP), an etch back process, combinations thereof, and the like. The planarization process exposes the mask 58 or nanostructures 56 such that the top surfaces of the mask 58 or nanostructures 56, the channel spacers 82, and the third dielectric layer 84C are coplanar (within process variations) after the planarization process is performed. In the embodiment shown, mask 58 remains after the planarization process. In another embodiment, the mask 58 may also be removed by a planarization process.

In the embodiment shown, the dielectric fin 84 has a lower portion (comprising first dielectric layer 84A and second dielectric layer 84B) formed of a low-k dielectric material and an upper portion (comprising third dielectric layer 84C) formed of a high-k dielectric material. It should be understood that other types of dielectric fins 84 may be formed, such as dielectric fins 84 having more or fewer layers. In various embodiments, the dielectric fin 84 may include lower and upper portions of a low-k dielectric material; of high-k dielectric materialsA lower portion and an upper portion; a lower portion of a high-k dielectric material and an upper portion of a low-k dielectric material; a single-layer lower and/or upper portion; a multi-layer lower and/or upper portion; and so on. The upper portion of the dielectric fin 84 may have a height H in the range of about 6nm to about 30nm₃The lower portion of the dielectric fin 84 may have a height H in the range of about 27nm to about 60nm₄The total height of the dielectric fin 84 may be in the range of about 33nm to about 90 nm.

In fig. 15, the fork plate structures 80 and channel spacers 82 are recessed such that dielectric fins 84 extend from between adjacent channel spacers 82. If the mask is still present in this step, the recess removes the mask 58 from the fin structure 62. The recessing may be performed by an acceptable etching process. For example, the prong structure 80 may be a recess using an acceptable etch process, such as an etch process that is selective to the mask 58, the nanostructures 56, and the dielectric wall 68 (e.g., selectively etching the material of the mask 58). The nanostructures 56 and dielectric walls 68 grow at a faster rate than the material of the channel spacers 82 and dielectric fins 84. The channel spacers 82 may optionally be trimmed using an acceptable etch process, such as an etch process that is selective to the channel spacers 82 (e.g., the material of the channel spacers 82 is selectively etched at a faster rate than the material of the nanostructures 56 and the dielectric walls 68). Recessing/trimming may remove some of the nanostructures 56.

A dummy dielectric layer 86 is then formed over the fork plate structure 80, the channel spacers 82, and the dielectric fin 84. The dummy dielectric layer 86 may be formed of silicon oxide, silicon nitride, combinations thereof, and the like, which may be deposited or thermally grown according to acceptable techniques.

Fig. 16A-23C illustrate other intermediate stages in the fabrication of a nanofet. Fig. 16A, 17A, 18A, 19A, 20A, 21A, 22A, and 23A may be applied to the N-type region 50N and the P-type region 50P. The structural differences (if any) between the N-type region 50N and the P-type region 50P are described in the text accompanying each figure.

In fig. 16A, 16B, and 16C, a dummy gate 94 is formed on the dummy dielectric layer 86. Dummy gate 94 may be formed by forming a dummy gate layer and patterning the dummy gate layer. A dummy gate layer may be deposited over dummy dielectric layer 86 and then planarized, for example by CMP. The dummy gate layer may be a conductive material or a non-conductive material and may be selected from the group consisting of amorphous silicon, polysilicon (polysilicon), poly-silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer may be deposited by Physical Vapor Deposition (PVD), CVD, sputter deposition, or other techniques for depositing selected materials. The dummy gate layer may then be patterned to form dummy gate 94 using acceptable photolithography and etching techniques, for example, using mask 96 with the pattern of dummy gate 94. The pattern of mask 96 is transferred to the dummy gate layer by an acceptable etching technique. To form dummy gate 94. The pattern of mask 96 may be further transferred to dummy dielectric layer 86 by an acceptable etch technique to form dummy dielectric 92.

Mask 96 may be a single layer mask or may be a multi-layer mask, such as a multi-layer mask that includes first and second mask layers 96A and 96B, respectively. First masking layer 96A and second masking layer 96B may each be formed of a dielectric material such as silicon oxide, silicon nitride, combinations thereof, and the like, and may be deposited or thermally grown according to acceptable techniques. The material of the first mask layer 96A may have a high etching selectivity compared to the material of the second mask layer 96B. For example, the first mask layer 96A may be formed of silicon oxide, and the second mask layer 96B may be formed of silicon nitride.

Dummy gate 94 covers the portion of nanostructure 56 that will be exposed in subsequent processing to form the channel region. In particular, dummy gate 94 extends along a portion of nanostructure 56 that will be used to form channel region 88. The pattern of mask 96 may be used to physically separate adjacent dummy gates 94. Dummy gate 94 may also have a length direction. The mask 96 is substantially perpendicular to the length direction of the semiconductor fin 54 (within process variations). The mask 96 may optionally be removed after patterning, for example by an acceptable etching technique.

Gate spacers 98 are then formed over fin structure 62, e.g., on exposed sidewalls of mask 96, dummy gate 94, and dummy dielectric 92. The gate spacers 98 may be formed by conformally forming an insulating material and then etching it. The insulating material may be formed of a low-k dielectric material (e.g., one selected from the candidate dielectric materials for liner layer 64) that may be deposited by a conformal deposition process, such as one selected from the candidate methods of forming liner layer 64. The gate spacer 98 may be formed of a single layer of insulating material or multiple layers of insulating material. In some embodiments, the gate spacers 98 each comprise multiple layers of silicon carbonitride, where each layer may have a different composition than silicon carbonitride. In some embodiments, the gate spacers 98 each comprise a silicon oxide layer disposed between two layers of silicon nitride. Other spacer structures may be formed. The etching of the insulating material may be anisotropic. For example, the etching process may be a dry etch, such as RIE, NBE, or the like. After etching, the gate spacers 98 may have straight sidewalls or curved sidewalls.

An implant of lightly doped source/drain (LDD) regions may be performed prior to forming the gate spacers 98. In embodiments with different device types, similar to the implantation described above, a mask (e.g., photoresist) may be formed over the N-type region 50N while exposing the P-type region 50P, and an appropriate type (e.g., P-type) impurity may be implanted into the fin structure 62 exposed in the P-type region 50P. The mask may then be removed. Subsequently, a mask, such as photoresist, may be formed over the P-type region 50P while exposing the N-type region 50N, and an appropriate type of impurity (e.g., N-type) may be implanted into the fin structure 62 exposed in the N-type region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities previously discussed, and the p-type impurity may be any of the p-type impurities previously discussed. The impurity concentration of the lightly doped source/drain region may be about 10¹⁵cm^-3To about 10¹⁹cm^-3Within the range of (1). Annealing may be used to repair implant damage and activate implanted impurities. During the implantation, the channel region 88 remains covered by the dummy gate 94, so that the channel region 88 remains substantially free of impurities implanted in the LDD region.

Note that the above disclosure generally describes the process of forming the spacers and LDD regions. Other processes and sequences may be used. For example, fewer or more spacers may be utilized, a different order of steps may be utilized (e.g., additional spacers may be formed and removed, etc.). In addition, different structures and steps may be used to form the n-type and p-type devices.

After forming gate spacers 98, source/drain recesses 102 are then formed in fin structure 62 and channel spacers 82. In the embodiment shown, source/drain recesses 102 extend through nanostructures 56 and channel spacers 82. The source/drain recesses 102 may also extend into the semiconductor fin 54. In other words, source/drain recesses 102 may be formed only in nanostructures 56 or may also be formed to extend into semiconductor fin 54 and STI region 78. In various embodiments, source/drain recesses 102 in fin structure 62 may extend to the top surface of semiconductor fin 54 without etching semiconductor fin 54; or it may extend into the semiconductor fin 54. Semiconductor fin 54 may be etched such that a bottom surface of source/drain recesses 102 in fin structure 62 is disposed below a top surface of STI region 78. Acceptable etch processes may be used to form source/drain recesses 102, such as etch processes that are selective to fin structure 62 and channel spacers 82 (e.g., the material of semiconductor fin 54, nanostructures 56, and channel spacers 82 is selectively etched at a faster rate than the material of dielectric walls 68 and dielectric fin 84). Thus, after the formation of source/drain recesses 102, dielectric walls 68 and dielectric fin 84 remain. Gate spacers 98 and mask 96 collectively mask portions of fin structure 62 and channel spacers 82 during the etch process used to form source/drain recesses 102. After the source/drain recesses 102 reach a desired depth, a timed etch process may be used to stop the etching of the source/drains.

The interior spacers 104 are optionally formed on sidewalls of the remaining portions of the first nanostructures 56A, e.g., those sidewalls exposed by the source/drain recesses 102. As will be discussed in more detail below, source/drain regions will be subsequently formed therein. The source/drain recesses 102 and the first nanostructures 56A will then be replaced by corresponding gate structures. The inner spacers 104 serve as isolation features between subsequently formed source/drain regions and subsequently formed gate structures. In addition, the inner spacers 104 may serve to prevent damage to subsequently formed source/drain regions by a subsequent etching process, such as an etching process used to subsequently form a gate structure.

As an example of forming the inner spacer 104, the source/drain recess 102 may be extended. In particular, portions of the sidewalls of the first nanostructure 56A exposed by the source/drain recesses 102 may be recessed. Although the sidewalls of the first nanostructures 56A are shown as being straight, the sidewalls may be concave or convex. The sidewalls may be recessed by an acceptable etch process, such as an etch process that is selective to the material of the first nanostructures 56A (e.g., selectively etches the material of the first nanostructures 56A at a faster rate than the material of the second nanostructures 56A). The etching may be isotropic. For example, when the semiconductor fin 54 and the second nanostructure 56B are formed of silicon and the first nanostructure 56A is formed of silicon germanium, the etching process may be to use tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH)₄OH), and the like. In another embodiment, the etching process may be a dry etch using a fluorine-based gas such as Hydrogen Fluoride (HF). In some embodiments, the same etch process may be performed sequentially to both form source/drain recesses 102 and recess sidewalls of first nanostructure 56A. In some embodiments, the etching process used to recess the sidewalls may also trim (e.g., reduce the thickness of) the etched portions of the second nanostructures 56B. The inner spacers 104 may then be formed by conformally forming an insulating material and then etching the insulating material. The insulating material may be formed of a low-k dielectric material (e.g., one selected from the candidate dielectric materials for liner layer 64) that may be deposited by a conformal deposition process, such as one selected from the candidate methods of forming liner layer 64. The etching of the insulating material may be anisotropic. For example, the etching process may be a dry etch, such as RIE, NBE, or the like. Although the outer sidewalls of the inner spacers 104 are illustrated as being recessed from the sidewalls of the gate spacers 98, the outer sidewalls of the inner spacers 104 may extend beyond or be flush with the sidewalls of the gate spacers 98. Thus, the interior spacer 104 may be partially filledCompletely filling or overfilling the sidewall recess. Also, although the sidewalls of the interior spacer 104 are shown as being concave, the sidewalls of the interior spacer 104 may be straight or convex.

In fig. 17A, 17B, and 17C, epitaxial source/drain regions 106 are formed in the source/drain recesses 102. Epitaxial source/drain regions 106 are formed in source/drain recesses 102 such that each dummy gate 94 is disposed between a respective adjacent pair of epitaxial source/drain regions 106. In some embodiments, gate spacers 98 and interior spacers 104 are used to separate dummy gate 94 and first nanostructure 56A, respectively, from epitaxial source/drain regions 106 by an appropriate lateral distance so that epitaxial source/drain regions 106 do not short the gates of subsequently formed nanofets. The epitaxial source/drain regions 106 may be formed in contact with the interior spacers 104 (if present) and may extend beyond the sidewalls of the second nanostructures 56B. The epitaxial source/drain regions 106 may exert stress on the second nanostructures 56B, thereby improving performance.

Epitaxial source/drain regions 106 in N-type region 50N may be formed by masking P-type region 50P. Epitaxial source/drain regions 106 are then epitaxially grown in source/drain recesses 102 in N-type region 50N. Epitaxial source/drain regions 106 may comprise any acceptable material suitable for an n-type nanofet. For example, the epitaxial source/drain regions 106 in the N-type region 50N may comprise a material that exerts a tensile strain on the channel region 88, such as silicon, silicon carbide, phosphorus doped silicon carbide, silicon phosphide, or the like. Epitaxial source/drain regions 106 in N-type region 50N may have surfaces that are raised from the respective surfaces of fin structure 62 and may have facets.

Epitaxial source/drain regions 106 in P-type region 50P may be formed by masking N-type region 50N. Epitaxial source/drain regions 106 are then epitaxially grown in source/drain recesses 102 in P-type region 50P. Epitaxial source/drain regions 106 may comprise any acceptable material suitable for a p-type nanofet. For example, epitaxial source/drain regions 106 in P-type region 50P may comprise a material that exerts a compressive strain on channel region 88, such as silicon germanium, boron-doped silicon germanium, germanium tin, or the like. Epitaxial source/drain regions 106 in P-type region 50P may have surfaces that protrude from the respective surfaces of fin structure 62 and may have facets.

Epitaxial source/drain regions 106, second nanostructures 56B, and/or fins 54 may be implanted with dopants to form source/drain regions, similar to the processes previously discussed for forming lightly doped source/drain regions, followed by a doping anneal. The impurity concentration of the source/drain region may be about 10¹⁹cm^-3To about 10²¹cm^-3Within the range of (1). The n-type and/or p-type impurities for the source/drain regions may be any of the impurities previously discussed. In some embodiments, the epitaxial source/drain regions 106 may be doped in-situ during growth.

As a result of the epitaxial process used to form epitaxial source/drain regions 106, the upper surface of epitaxial source/drain regions 106 has facets that extend laterally outward beyond the surface of fin structure 62. After the epitaxial process is completed, adjacent epitaxial source/drain regions 106 are kept separated by dielectric wall 68 or dielectric fin 84, thereby avoiding merging of epitaxial source/drain regions 106. Thus, the epitaxial source/drain regions 106 each have a straight bottom surface (contacting the semiconductor fin 54), straight sidewalls (contacting the dielectric walls 68), faceted side surfaces (facing the dielectric fin 84), and faceted top surfaces (facing away from the counter substrate 50). In addition, physical isolation between the epitaxial source/drain regions 106 and the dielectric fin 84 is maintained so that contact between the sidewalls of the epitaxial source/drain regions 106 and the power rail contacts 74 may be formed. In some embodiments, the epitaxial source/drain regions 106 may be grown along the <010> direction such that a lower portion of the source/drain recesses 102 remains between the epitaxial source/drain regions 106 and forms the dielectric fin 84. In some embodiments, a post-growth etch back is performed to reform a lower portion of the source/drain recess 102 separating the epitaxial source/drain regions 106 from the dielectric fin 84. For example, the width of the epitaxial source/drain regions 106 may be etched to reduce their width by an amount in the range of about 2nm to about 20nm, thereby reforming the lower portions of the source/drain recesses 102.

Epitaxial source/drain regions 106 may include one or more layers of semiconductor material. For example, the epitaxial source/drain regions 106 may include a first layer of semiconductor material 106A and a second layer of semiconductor material 106B. Any number of layers of semiconductor material may be used for epitaxial source/drain regions 106. Each of the first semiconductor material layer 106A and the second semiconductor material layer 106B may be formed of a different semiconductor material and/or may be doped to a different dopant concentration. In some embodiments, the first semiconductor material layer 106A may have a dopant concentration less than the second semiconductor material layer 106B. In embodiments where the epitaxial source/drain regions 106 include two layers of semiconductor material, a first layer of semiconductor material 106A may be grown from the fin structure 62 and a second layer of semiconductor material 106B may be grown from the first layer of semiconductor material 106A.

In fig. 18A, 18B, and 18C, a dielectric layer 110 is formed in the lower portion of the source/drain recess 102. Each dielectric layer 110 is formed between an epitaxial source/drain region 106 and a respective adjacent dielectric fin 84. The dielectric layer 110 may be formed of a low-k dielectric material (e.g., one selected from the candidate dielectric materials for forming the liner 64), a high-k dielectric material (e.g., one selected from the candidate dielectric materials for the liner 64), combinations thereof, or the like, which may be formed by a thermal oxidation or conformal deposition process (e.g., one selected from the candidate methods for the liner 64). A removal process, such as an etch-back process, is then applied to the dielectric layer 110 to remove excess material of the dielectric layer 110 outside of the lower portions of the source/drain recesses 102, e.g., those portions above the epitaxial source/drain regions 106.

A first ILD114 is then formed over the dielectric layer 110, the epitaxial source/drain regions 106, and the dielectric fin 84. The first ILD114, gate spacer 98, mask 96 (if present) or dummy gate 94, and dielectric fin 84 may be formed by depositing a dielectric material on dielectric layer 110, epitaxial source/drains 106, and then planarizing the dielectric material. Acceptable dielectric materials may include oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), Undoped Silicate Glass (USG), and the like; nitrides, such as silicon nitride; and so on. Other insulating materials may be used. Deposition may be by any suitable method, such as CVD, plasma enhanced CVD (pecvd), or FCVD. Other acceptable processes may be used to form the dielectric material. The planarization may be performed by any suitable method, such as CMP, an etch back process, a combination thereof, and the like. The planarization process flushes the top surface of the first ILD114 with the top surface of the mask 96 (if present) or dummy gate 94. The planarization process may also remove portions of the mask 96 and gate spacers 98 along the sidewalls of the mask. After the planarization process, the top surfaces of the first ILD114, gate spacer 98 and mask 96 (if present) or dummy gate 94 are coplanar (within process variations). Thus, the top surfaces of mask 96 (if present) or dummy gate 94 are exposed through first ILD 114. In the illustrated embodiment, the mask 96 remains and the planarization process flushes the top surface of the first ILD114 with the top surface of the mask 96.

In some embodiments, a Contact Etch Stop Layer (CESL)112 is disposed between the first ILD114 and the dielectric layer 110, the epitaxial source/drain regions 106, the gate spacers 98, the dielectric fins 84, and the dielectric walls 68. The CESL 112 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, having a high etch selectivity compared to the etching of the first ILD114 and the dielectric layer 110.

As will be discussed in more detail below, portions of the dielectric layer 110 (e.g., those in the cross-section of fig. 18C) will be replaced by contacts between the sidewalls of the epitaxial source/drain regions 106 and the power rail contacts 74. Forming the dielectric layer 110 proximate the epitaxial source/drain regions 106 may increase manufacturing costs as compared to forming the CESL 112 and the first ILD114 proximate the epitaxial source/drain regions 106. However, the inclusion of dielectric layer 110 may allow for a better controlled etch process that will be used to expose the top surface of power rail contact 74. Accordingly, the manufacturing yield may be improved, and the overall manufacturing cost may be reduced compared to the cost of forming the dielectric layer 110.

In fig. 19A, 19B, and 19C, mask 96 (if present), dummy gate 94, dummy dielectric 92, channel spacer 82, and first nanostructure 56A are removed and replaced with gate structure 120. The gate structure 120 includes a gate dielectric 122 and a gate electrode 124 located on the gate dielectric 122. The gate structure 120 may also be referred to as a "gate stack".

The mask 96 (if present) and the dummy gate 94 are removed in an etching process, thereby forming a recess. Portions of the dummy dielectric 92 in the recesses may also be removed. In some embodiments, dummy gate 94 is removed by an anisotropic dry etch process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 94 at a faster rate than the first ILD114 or the gate spacer 98. During removal, dummy dielectric 92 may act as an etch stop when dummy gate 94 is etched. The dummy dielectric 92 may then be removed after removing the dummy gate 94. Each recess exposes and/or covers a portion of the second nanostructure 56B that serves as the channel region 88. The portion of the second nanostructure 56B that serves as the channel region 88 is disposed between an adjacent pair of epitaxial source/drain regions 106.

The channel spacers 82 and the remaining portions of the first nanostructures 56A are then removed to enlarge the recesses. The channel spacer 82 and the remaining portions of the first nanostructures 56A may be removed by an acceptable etch process that selectively etches the channel spacer 82 and the materials of the first nanostructures 56A, the second nanostructures 56B, the semiconductor fin 54, the STI region 78, the dielectric fin 84, and the dielectric wall 68 at a faster rate than the channel spacer 82 and the first nanostructures 56A. The etching may be isotropic. For example, when the semiconductor fin 54 and the second nanostructure 56B are formed of silicon and the channel spacer 82 and the first nanostructure 56A are formed of silicon germanium, the etching process may be to use tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH)₄OH) and the like.

The second nanostructure 56B and the exposed portion of the semiconductor fin 54 are optionally trimmed. The trimming reduces the thickness of the exposed portions of the second nanostructures 56B. For example, the trimming may modify the second thickness T of the second nanostructure 56B₂(see fig. 3) by an amount in the range of about 40% to about 70%, and may also reduce the width of the exposed portion of the semiconductor fin 54. Trimming may be performed simultaneously with the formation of the recess, or may be performed after the formation of the recess. For example, a second nano-junctionExposed portions of the structures 56B and the semiconductor fins 54 may be trimmed by an acceptable etch process that selectively etches the material of the second nanostructures 56B and the semiconductor fins 54, the interior spacers 104, the gate spacers 98, the dielectric fins 84, and the dielectric walls 68 at a faster rate than the material of the second nanostructures 56B and the semiconductor fins 54. The etching may be isotropic. For example, when the semiconductor fin 54 and the second nanostructure 56B are formed of silicon and the channel spacer 82 and the first nanostructure 56A are formed of silicon germanium, the trimming process may be wet etching using a dilute ammonium hydroxide-hydrogen peroxide mixture (APM), sulfuric acid-hydrogen peroxide mixture (SPM), or the like.

A gate dielectric 122 and a gate electrode 124 are formed for the replacement gate. A gate dielectric 122 is conformally deposited in the recess, for example on the top surface and sidewalls of the semiconductor fin 54 and on the top surface, sidewalls, and bottom surface of the second nanostructure 56B. Gate dielectric 122 may also be deposited on the top surface of STI regions 78 and on the sidewalls of dielectric fins 84 and dielectric walls 68.

The gate dielectric 122 includes one or more dielectric layers such as an oxide, a metal silicate, the like, or combinations thereof. In some embodiments, the gate dielectric 122 comprises silicon oxide, silicon nitride, or multilayers thereof. In some embodiments, the gate dielectric 122 comprises a high-k dielectric material, and in such embodiments, the gate dielectric 122 may have a k value greater than about 7.0, and may comprise a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The gate dielectric 122 may be multilayered. For example, in some embodiments, the gate dielectrics 122 may each include an interfacial layer 122A of silicon oxide formed by thermal or chemical oxidation and a metal oxide layer 122B over the interfacial layer. Methods of forming the gate dielectric 122 may include Molecular Beam Deposition (MBD), ALD, PECVD, and the like.

Gate electrodes 124 are deposited over gate dielectric 122 and fill the remaining portions of the recesses, respectively. Gate electrode 124 can include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multilayers thereof. For example, although a single layer gate electrode 124 is shown, the gate electrode 124 may include any number of liner layers, any number of work function adjusting layers, and fill materials. Any combination of the layers making up the gate electrode 124 may be deposited between each second nanostructure 56B and in the region between the semiconductor fin 54 and the second nanostructure 56B. The formation method of the gate electrode 124 may include ALD, PECVD, and the like.

After filling the recesses, a planarization process such as CMP may be performed to remove excess portions of the material of the gate dielectric 122 and the gate electrode 124 over the top surfaces of the first ILD114 and the gate spacer 98. A recess process, such as an etch back, may then be performed to recess the top surfaces of gate dielectric 122 and gate electrode 124 from the top surface of dielectric fin 84. Timed etch may use various processes to stop etching of gate dielectric 122 and gate electrode 124 such that the top surface of gate electrode 124 has a desired height H relative to the topmost second nanostructure 56B₅. Height H₅And may range from about 6nm to about 30 nm. The remaining portions of the material of gate dielectric 122 and gate electrode 124 thus form replacement gate structure 120 of the resulting nanofet.

An etch stop layer 126 is then deposited over the recessed gate structure 120. The etch stop layer 126 may comprise a conductive material deposited by ALD, CVD, PVD, etc., such as tungsten, ruthenium, cobalt, copper, molybdenum, nickel, combinations thereof, etc., having an etch rate different from that of a subsequently formed gate mask. In some embodiments, the etch stop layer 126 is formed of tungsten (e.g., fluorine-free tungsten) deposited by a selective deposition process (e.g., a selective CVD process). Because the etch stop layer 126 is formed of a conductive material, it may function to stop etching and may also be used to adjust the contact resistance to the gate structure 120.

The formation of gate dielectric 122 in region 50N and region 50P may occur simultaneously such that gate dielectric 122 in each region is formed of the same material, and the formation of gate electrode 124 may occur simultaneously such that gate electrode 124 in each region is formed of the same material. In some embodiments, the gate dielectric 122 in each region may be formed by a different process such that the gate dielectric 122 may be a different material, and/or the gate electrode 124 in each region may be formed by a different process such that the gate electrode 124 may be a different material. When different processes are used, various masking steps may be used to mask and expose the appropriate regions. For example, in the illustrated embodiment, gate electrodes 124 of different materials are formed in region 50N and region 50P.

As shown in fig. 19B, the gate electrodes 124 around the channel regions 88 of the same prong structure 80 may be physically and electrically coupled. Such coupling may be advantageous in some CMOS processes. For example, when a nanofet is used to form an inverter, gate, memory, etc., directly connecting gate electrode 124 may allow for a reduction in the number of gate contacts. Gate electrodes 124 around channel regions 88 of adjacent fork plate structures 80 are physically and electrically isolated by dielectric fins 84.

In fig. 20A, 20B, and 20C, a gate mask 128 is formed on each gate structure 120, for example, on each etch stop layer 126. Thus, each gate mask 128 is disposed between opposing portions of the gate spacers 98. Forming the gate mask 128 includes forming a dielectric material over the recessed gate structure 120 and then performing a planarization process to remove excess portions of the dielectric material extending over the first ILD 114. The dielectric material may be formed of a low-k dielectric material (e.g., one selected from the candidate dielectric materials for liner layer 64) that may be deposited by a conformal deposition process, such as one selected from the candidate methods of forming liner layer 64.

A second ILD132 is then deposited over the gate mask 128, the first ILD114 and the gate spacers 98. The second ILD132 may be formed of a material selected from the same set of candidate materials for the first ILD114 and may be deposited using a method selected from the same set of candidate methods for depositing the first ILD 114. The first ILD114 and the second ILD132 may be formed of the same material or may comprise different materials. After formation, the second ILD132 may be planarized, for example by CMP.

In some embodiments, an etch stop layer 130 is formed between the second ILD132 and each of the gate mask 128, first ILD114, and gate spacer 98. The etch stop layer 130 may comprise a dielectric material (e.g., silicon nitride, silicon oxide, silicon oxynitride, etc.) having a different etch rate than the material of the second ILD 132.

In fig. 21A, 21B, and 21C, source/drain contact openings 134 are formed in the second ILD132, etch stop layer 130, first ILD114, CESL 112, dielectric layer 110, and STI regions 78. Source/drain contact openings 134 expose multiple top and side surfaces of epitaxial source/drain regions 106. The source/drain contact openings 134 also expose a top surface of the power rail contact 74 and may expose portions of the semiconductor fin 54. Acceptable photolithography and etching techniques may be used to form the source/drain contact openings 134. Multiple etching steps may be used to form the source/drain contact openings 134. As described above, the CESL 112 is formed of a material having high etch selectivity to etch the dielectric layer 110. One of the etch steps to form the source/drain contact openings is an etch process that is selective to the dielectric layer 110 (e.g., etches the material of the dielectric layer 110 at a faster rate than the material of the CESL 112). Thus, the aspect ratio of the lower portion of the source/drain contact opening 134 may be improved, helping to ensure that a sufficient area of the top surface of the power rail contact 74 is exposed, which may reduce the contact resistance of the nanofet. Specifically, the width W of the lower portion of the source/drain contact opening 134₆In the range of about 4nm to about 20nm (measured between the sidewalls of the dielectric fin 84 and the side surfaces of the epitaxial source/drain regions 106), the lower portion of the source/drain contact openings 134 may have a height H in the range of about 32nm to about 80nm₆Height H (measured between the top surface of power rail contact 74 and the top surface of epitaxial source/drain region 106)₆And width W₆In a ratio of about 1.6: 1 to about 20: 1, in the above range.

In the illustrated embodiment, the source/drain contact openings 134 are formed in a self-aligned patterning process such that all of the first ILD114 is removed in the cross-section of fig. 21A. In another embodiment, other patterning methods may be used such that some of the first ILD114 remains in the cross-section of fig. 21A.

In the embodiment shown in fig. 21A, the etching of the epitaxial source/drain regions 106 occurs such that the source/drain contact openings 134 extend partially into the epitaxial source/drain regions 106. In another embodiment, the source/drain contact openings 134 do not extend into the epitaxial source/drain regions 106.

In fig. 22A, 22B, and 22C, metal-semiconductor alloy regions 136 are optionally formed in the source/drain contact openings 134, such as on portions of the epitaxial source/drain regions 106 exposed by the source/drain contact openings 134. Metal-semiconductor alloy regions 136 may be silicide regions formed from metal silicides (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), germanide regions formed from metal germanides (e.g., titanium germanide, germanium cobaltate, germanium nickelate, etc.), silicon germanium regions formed from both metal silicides and metal germanides, and so forth. The metal semiconductor alloy regions 136 may be formed by depositing a metal in the source/drain contact openings 134 and then performing a thermal annealing process. The metal may be any metal capable of reacting with the semiconductor material (e.g., silicon germanium, etc.) of epitaxial source/drain regions 106 to form a low resistance metal semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. The metal may be deposited to a thickness in the range of about 1nm to about 10nm by a deposition process such as ALD, CVD, PVD, and the like. In one embodiment, metal-semiconductor alloy regions 136 are silicide regions formed of titanium-silicon. After the thermal annealing process, a cleaning process, such as a wet clean, may be performed to remove any remaining metal from the source/drain contact openings 134 (such as from the surfaces of the power rail contacts 74, the STI regions 78, and the semiconductor fins 54).

Metal-semiconductor alloy region 136 may be formed to a desired thickness by controlling the thickness of the deposited metal to form metal-semiconductor alloy region 136. Thickness T of metal-semiconductor alloy region 136₁And may range from about 2.5nm to about 7.5 nm. In some embodiments, the metal used to form metal-semiconductor alloy region 136 is deposited by a uniform deposition process, such as ALD, such that metal-semiconductor alloy region 136 has a uniform thicknessUniform thickness. In some embodiments, the metal used to form metal-semiconductor alloy region 136 is deposited by a non-uniform deposition process, such as PVD, such that metal-semiconductor alloy region 136 has a non-uniform thickness. For example, the portion of the metal semiconductor alloy region 136 on the top surface of the epitaxial source/drain region 106 may have a greater thickness T than the portion of the metal semiconductor alloy region 136 on the side surface of the epitaxial source₁. Forming metal-semiconductor alloy regions 136 on the top and side surfaces of epitaxial source/drain regions 106 may increase the contact area with epitaxial source/drain regions 106, thereby reducing the contact resistance as compared to forming metal-semiconductor alloy regions 136 only on the top surfaces of epitaxial source/drain regions 106.

In fig. 23A, 23B, and 23C, source/drain contacts 138 are formed in the source/drain contact openings 134. A liner material such as a diffusion barrier layer, an adhesion layer, etc., and a conductive material are formed in the source/drain contact openings 134. The liner may comprise titanium, titanium nitride, tantalum nitride, and the like. The liner may be deposited by a conformal deposition process, such as Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), and the like. In some embodiments, the liner may include an adhesive layer, and at least a portion of the adhesive layer may be treated to form the diffusion barrier layer. The conductive material may be tungsten, ruthenium, cobalt, copper, molybdenum, nickel, combinations thereof, and the like. The conductive material may be deposited by ALD, CVD, PVD, or the like. A planarization process such as CMP may be performed to remove excess material from the top surface of second ILD 132. The remaining liner and conductive material in the source/drain contact openings 134 form source/drain contacts 138. The drain contact 138 is physically and electrically coupled to the power rail contact 74 and the metal-semiconductor alloy region 136 (if present) or the epitaxial source/drain region 106.

The source/drain contact 138 has a lower portion (between the dielectric fin 84 and the epitaxial source/drain region 106) and an upper portion (above the epitaxial source/drain region 106). The lower portion of the source/drain contact 138 may have a width W in the range of about 4nm to about 20nm₇(measured between the sidewalls of the dielectric fin 84 and the side surfaces of the metal-semiconductor alloy region 136). Source electrodeHeight H of lower portion of drain contact 138₇(measured between the top surface of power rail contact 74 and the top surface of metal semiconductor alloy region 136) is in the range of about 32nm to about 200 nm. Height H of upper portion of nano source/drain contact 138₈(measured between the top surface of source/drain contacts 138 and the top surface of metal semiconductor alloy region 136) may be in the range of about 1nm to about 50 nm.

Source/drain contacts 138 connect the epitaxial source/drain regions 106 to the power rail contacts 74. Thus, there is no need to form a metal semiconductor alloy region on the power rail contact 74. In other words, all surfaces of the power rail contact 74 are free of metal-semiconductor alloy regions. The manufacturing cost can be reduced.

A gate contact 140 is also formed that extends through the second ILD132, etch stop layer 130, gate mask 128 and etch stop layer 126. As an example of forming the gate contact 140, a contact opening is formed through the second ILD132, etch stop layer 130, gate mask 128, and etch stop layer 126. The contact openings may be formed using acceptable photolithography and etching techniques. A liner such as a diffusion barrier layer, an adhesion layer, etc., and a conductive material are formed in the contact opening. The liner may comprise titanium, titanium nitride, tantalum nitride, and the like. The liner may be deposited by a conformal deposition process, such as Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), and the like. In some embodiments, the liner may include an adhesive layer, and at least a portion of the adhesive layer may be treated to form the diffusion barrier layer. The conductive material may be tungsten, cobalt, ruthenium, aluminum, nickel, copper alloys, silver, gold, or the like. The conductive material may be deposited by ALD, CVD, PVD, or the like. A planarization process such as CMP may be performed to remove excess material from the top surface of second ILD 132. The remaining liner and the conductive material in the contact opening form a gate contact 140. Gate contact 140 is physically and electrically coupled to gate electrode 124. The gate contact 140 may have an overall height in the range of about 1nm to about 50 nm.

The gate contact 140 may be formed before, after, or after the source/drain contact 138. After formation is complete, the top surfaces of the second ILD132, source/drain contacts 138 and gate contact 140 are coplanar (internal). In the illustrated embodiment, the source/drain contacts 138 and the gate contact 140 are formed in different cross-sections, thereby reducing the risk of shorting the contacts. In another embodiment, some/all of the source/drain contacts 138 and the gate contact 140 may be formed in the same cross-section.

As will be discussed in more detail below, a first interconnect structure (e.g., a front-side interconnect structure) will be formed over the substrate 50. Some or all of substrate 50 will then be removed and replaced with a second interconnect structure (e.g., a backside interconnect structure). Thus, a device layer 150 of active devices is formed between the front-side interconnect structure and the back-side interconnect structure. Both the front-side and backside interconnect structures include conductive features of the nanofets electrically connected to device layer 150. The conductive components (e.g., metallization patterns, also referred to as interconnects) of the front-side interconnect structure will be electrically connected to the front-side of the epitaxial source/drain regions 106 and the gate electrodes 124 to form functional circuitry, such as logic circuitry, memory circuitry, image sensor circuitry, and the like. Conductive members (e.g., power rails) of the backside interconnect structure will be electrically connected to the backside of the epitaxial source/drain regions 106 to provide reference voltages, power supply voltages, etc. to the functional circuitry. Although the device layer 150 is described as having nanofets, other embodiments may include the device layer 150 having different types of transistors (e.g., planar FETs, finfets, TFTs, etc.).

Fig. 24A-29C are cross-sectional views of intermediate stages in the manufacture of semiconductor devices according to some embodiments. In particular, fabrication of a device layer of a nanofet is shown. Fig. 23A, fig. 24A, fig. 25A, fig. 26A, fig. 27A, fig. 28A, and fig. 29A are sectional views shown along a reference section a-a in fig. 1, except that two gate structures are shown. Fig. 23B, 24B, 25B, 26B, 27B, 28B, and 29B are sectional views shown along a reference section B-B in fig. 1, except that four fins are shown. Fig. 23C, 24C, 25C, 26C, 27C, 28C, and 29C are sectional views shown along a reference section C-C in fig. 1, except that four fins are shown. Fig. 23A, fig. 24A, fig. 25A, fig. 26A, fig. 27A, fig. 28A, and fig. 29A may be applied to the N-type region 50N and the P-type region 50P. The structural differences (if any) between the N-type region 50N and the P-type region 50P are described in the text accompanying each figure.

In fig. 24A, 24B, and 24C, an interconnect structure 160 is formed on the device layer 150, e.g., on the second ILD 132. Interconnect structure 160 may also be referred to as a frontside interconnect structure because it is formed on the front side of substrate 50/device layer 150 (e.g., the side of substrate 50 on which device layer 150 is formed, such as the side having semiconductor layer 50A).

The interconnect structure 160 may include one or more layers of conductive features 162 formed in one or more stacked dielectric layers 164. Each dielectric layer 164 may include a dielectric material, such as a low-k dielectric material, an additional low-k dielectric, an (ELK) dielectric material, and so forth. The dielectric layer 164 may be deposited using a suitable process such as CVD, ALD, PVD, PECVD, etc.

The conductive features 162 may include conductive lines and conductive vias interconnecting the conductive layers. Conductive vias may extend through the respective dielectric layers 164 to provide vertical connections between the wire layers. The conductive features 162 may be formed by any acceptable process. For example, the conductive features 162 may be formed by a damascene process, such as a single damascene process, a dual damascene process, and the like. In a damascene process, the respective dielectric layer 164 is patterned using a combination of photolithography and etching techniques to form trenches corresponding to the desired pattern of conductive features 162. An optional diffusion barrier layer and/or an optional adhesion layer may be deposited and the trench may then be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum nitride, titanium oxide, and the like, and suitable materials for the conductive material include tungsten, ruthenium, cobalt, copper, molybdenum, nickel, combinations thereof, and the like. In one embodiment, the conductive features 162 may be formed by depositing a seed layer of copper or copper alloy and filling the trenches by electroplating. A Chemical Mechanical Planarization (CMP) process or the like may be used to remove excess conductive material from the surface of the respective dielectric layer 164 and planarize the surface for subsequent processing.

In the example shown, five layers of conductive features 162 and dielectric layers 164 are shown. However, it should be understood that interconnect structure 160 may include any number of conductive features disposed in any number of dielectric layers. The conductive members 162 of the interconnect structure 160 are electrically connected to the gate contact 140 and the source/drain contacts 138 to form a functional circuit. In other words, the conductive features 162 interconnect the epitaxial source/drain regions 106 and the gate electrode 124. In some embodiments, the functional circuitry formed by interconnect structure 160 may include logic circuitry, memory circuitry, image sensor circuitry, and the like. The second ILD132, source/drain contacts 138, and gate contacts 140 may also be considered part of the interconnect structure 160, such as part of the first level conductive features of the interconnect structure 160.

The carrier substrate 166 is then bonded to the top surface of the interconnect structure 160 by a bonding layer 168 (e.g., including

bonding layers

168A, 168B). The carrier substrate 166 may be a glass carrier substrate, a ceramic carrier substrate, a semiconductor substrate (e.g., a silicon substrate), a wafer (e.g., a silicon wafer), or the like. The carrier substrate 166 may provide structural support during subsequent processing steps as well as in the completed device. The carrier substrate 166 is substantially free of any active or passive components.

In various embodiments, the carrier substrate 166 may be bonded to the interconnect structure 160 using a suitable technique, such as dielectric-to-dielectric bonding. Dielectric-to-dielectric bonding may include depositing

bonding layers

168A, 168B on the interconnect structure 160 and the carrier substrate 166, respectively. In some embodiments, the bonding layer 168A includes silicon oxide (e.g., High Density Plasma (HDP) oxide, etc.) deposited by CVD, ALD, PVD, etc. The bonding layer 168B may also be an oxide layer formed prior to bonding using, for example, CVD, ALD, PVD, thermal oxidation, or the like. Other suitable materials may also be used for the bonding layers 168A, 168B.

The dielectric-to-dielectric bonding process may further include surface treating one or more bonding layers 168. The surface treatment may comprise a plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may further include a cleaning process (e.g., rinsing with deionized water, etc.) that may be applied to the one or more bonding layers 168. The carrier substrate 166 is then aligned with the interconnect structure 160 and the two are pressed against each other to initiate pre-bonding of the carrier substrate 166 to the interconnect structure 160. The pre-bond may be at room temperature (e.g., in the range of about 20 ℃ to about 25 ℃). After pre-bonding, an annealing process may be applied by, for example, heating the interconnect structure 160 and the carrier substrate 166 to a temperature of about 170 ℃.

In fig. 25A, 25B, and 25C, the intermediate structure is flipped so that the backside of the substrate 50 faces upward. The backside of the substrate 50 refers to the side of the substrate 50 opposite the front side on which the device layers 150 are formed. The substrate 50 is then thinned to remove (or at least reduce the thickness of) backside portions of the substrate 50, such as the insulator layer 50B and the substrate core 50C. The thinning process may include a planarization process (e.g., mechanical grinding, Chemical Mechanical Polishing (CMP), etc.), an etch-back process, combinations thereof, and the like. The thinning process exposes the liner 64 and the surface of the semiconductor fin 54 at the backside of the device layer 150.

In fig. 26A, 26B, and 26C, the semiconductor fin 54 is removed to form the recess 142. Each recess 142 is disposed between the dielectric wall 68 and the power rail contact 74. The semiconductor fins 54 may be removed using acceptable photolithography and etching techniques. For example, an etch process is utilized that is selective to the semiconductor fin 54 (e.g., the material of the semiconductor fin 54 is etched at a faster rate than the material of the liner 64 and the epitaxial source/drain regions 106). During the removal, the underlying layer of the epitaxial source/drain regions 106 (e.g., the first semiconductor material layer 106A) may serve as an etch stop layer when the semiconductor fin 54 is etched. The underlying layer of the epitaxial source/drain regions 106 (e.g., the first layer of semiconductor material 106A) may be removed (or may not be removed) during the removal of the semiconductor fin 54.

In fig. 27A, 27B, and 27C, a dielectric fin 144 is formed in the recess 142, e.g., on the epitaxial source/drain regions 106. Dielectric fin 144 replaces semiconductor fin 54, which may help reduce parasitic capacitance and/or leakage current of the resulting nanofet, thereby improving its performance. The dielectric fin 144 may be formed of a low-k dielectric material (e.g., one selected from the candidate dielectric materials forming the liner 64), a high-k dielectric material (e.g., one selected from the candidate dielectric materials of the liner 64), combinations thereof, or the like, which may be formed by a thermal oxidation or conformal deposition process (e.g., one selected from the candidate methods of the liner 64). In the illustrated embodiment, the dielectric fin 144 includes a first dielectric layer 144A and a second dielectric layer 144B on the first dielectric layer 144A, wherein the first dielectric layer 144A is formed of silicon nitride and the second dielectric layer 144B is formed of silicon oxide. Forming the first dielectric layer 144A (e.g., nitride) may help avoid oxidation of the epitaxial source/drain regions 106 and the gate structure 120 during formation of the second dielectric layer 144B (e.g., oxide).

After depositing the material of the dielectric fin 144, a removal process is applied to remove excess material of the dielectric fin 144 and the liner 64 over the power rail contact 74 and the dielectric wall 68. In an embodiment, a planarization process such as Chemical Mechanical Polishing (CMP), an etch back process, a combination thereof, or the like may be utilized. The planarization process exposes the power rail contact 74 and the dielectric wall 68 such that the top surfaces of the power rail contact 74, the dielectric wall 68, the liner layer 64, and the dielectric fin 144 are coplanar (within process variations) after the planarization process is complete. After the planarization process, the thickness of the first dielectric fin may be in a range of about 2nm to about 10nm, and the height of the second dielectric layer 144B may be in a range of about 8nm to about 70 nm. The overall height of the dielectric fin 144 may be in the range of about 24nm to about 80nm, and the height H1 of the power rail contact 74 may be in the range of about 20nm to about 60 nm.

Burying the power rail contacts 74 under the STI regions 78 may expose them through a planarization process, thereby avoiding the need to etch contact openings at the backside of the power rail contacts 74. The overlay process window for backside processing may thus be widened. Furthermore, because the power rail contacts 74 are already connected to the epitaxial source/drain regions 106 in this processing step, there is no need to form metal semiconductor alloy regions on the backside of the power rail contacts 74. Contact resistance to the nano-FET can be improved.

In fig. 28A, 28B, and 28C, an interconnect structure 170 is formed at the backside of the device layer 150, e.g., on the power rail contacts 74, the dielectric walls 68, and the dielectric fins 144. Interconnect structure 170 may also be referred to as a backside interconnect structure because it is formed on the backside of device layer 150. The components of interconnect structure 170 may be similar to interconnect structure 160. For example, interconnect structure 170 may comprise a similar material as interconnect structure 160 and may be formed using a similar process as interconnect structure 160. In particular, the interconnect structure 170 may include stacked layers of conductive features 172 formed in stacked dielectric layers 174. The conductive members 172 may include wiring (e.g., for routing to subsequently formed contact pads and external connectors). The conductive features 172 may further include conductive vias extending in the dielectric layer 174 to provide vertical interconnects between the stacked layers of conductive lines. After formation, the conductive features 172 may have a thickness in a range of about 1nm to about 50 nm. The power rail contact 74 connects the conductive member 172 of the interconnect structure 170 to the transistor of the device layer 150 and the conductive member 162 of the interconnect structure 160.

Some or all of the conductive features 172 are power traces 172P, which are wires that electrically connect the epitaxial source/drain regions 106 to a reference voltage, a power supply voltage, or the like. For example, power rail 172P can be a first level conductor of interconnect structure 160. Advantages may be realized by placing power trace 172P on the back side of device layer 150 rather than the front side of device layer 150. For example, the gate density of the nanofets and/or the interconnect density of the interconnect structures 160 may be increased. In addition, the backside of device layer 150 can accommodate wider power rails, thereby reducing resistance and improving power transfer efficiency to the nanofets. For example, the width of the conductive feature 172 may be at least twice the width of the first level conductive line (e.g., conductive line 162A) of the interconnect structure 160.

In some embodiments, the conductive components of the interconnect structure 170 may be patterned to include one or more embedded passive devices, such as resistors, capacitors, inductors, and the like. Embedded passive devices may be integrated with conductive features 172 (e.g., power traces 172P) to provide circuitry (e.g., power circuitry) on the backside of device layer 150.

In fig. 29A, 29B, and 29C, a passivation layer 182, a UBM184, and an external connector 186 are formed over the interconnect structure 170. The passivation layer 182 may include a polymer such as polyimide, Polybenzoxazole (PBO), benzocyclobutene (BCB), a base polymer, or the like. Alternatively, the passivation layer 182 may include an inorganic dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or the like. The material of the passivation layer 182 may be deposited by, for example, CVD, PVD, ALD, and the like.

A UBM184 is formed through the passivation layer 182 to the conductive feature 172 of the interconnect structure 170, and an external connector 186 is formed on the UBM 184. UBM184 may include one or more layers of copper, nickel, gold, or be formed by a plating process, etc. External connectors 186 (e.g., solder balls) are formed on UBM 184. The formation of the external connectors 186 may include placing solder balls on the exposed portions of the UBM184 and then reflowing the solder balls. In an alternative embodiment, the formation of the external connectors 186 includes performing a plating step to form a solder region over the topmost conductive member 172 and then reflowing the solder region. In another embodiment, the external connectors 186 are metal connectors having substantially vertical sidewalls, such as micro-bumps. UBM184 and external connector 186 may be used to provide input/output connections to other electrical components, such as other device dies, redistribution structures, Printed Circuit Boards (PCBs), motherboards, and the like. UBM184 and external connector 186, which may also be referred to as backside input/output pads, may provide signal, reference, supply, and/or ground connections to the nanofets of device layer 150.

Embodiments may realize advantages. Burying the power rail contacts 74 under the STI regions 78 may expose their backside through a planarization process, thereby avoiding the need to etch contact holes to the backside of the power rail contacts 74. Furthermore, since the power rail contact 74 is connected to the epitaxial source/drain regions 106 through the source/drain contacts 138, there is no need to form a metal-semiconductor alloy region on the backside of the power rail contact 74. Therefore, the contact resistance to the nano FET can be improved.

In one embodiment, a method comprises: forming a fork plate structure above the substrate; forming a power rail contact adjacent to the prong structure; forming an isolation region on the power rail contact, the prong plate structure protruding from the isolation region; growing a first source/drain region in the fork plate structure; depositing an interlayer dielectric (ILD) on the first source/drain region; and forming a source/drain contact through the ILD and the isolation region, the source/drain contact connected to the first source/drain region and the power rail contact.

In some embodiments of the method, the prong plate structure includes a first nanostructure, a second nanostructure, and a dielectric wall between the first nanostructure and the second nanostructure, the first source/drain region abutting the first nanostructure, the method further comprising: a second source/drain region is grown in the fork plate structure, the second source/drain region abutting the second nanostructure, and a dielectric wall disposed between the first source/drain region and the second source/drain region. In some embodiments, the method further comprises: a first gate structure is formed around the first nanostructure. A second gate structure is formed around the second nanostructure, the second gate structure being connected to the first gate structure. In some embodiments of the method, the first nanostructure, the second nanostructure, and the dielectric wall have parallel longitudinal axes in a first direction, and the dielectric wall is disposed between the first source/drain region and the second source/drain region in a second direction, the first direction being perpendicular to the second direction. In some embodiments of the method, forming the power rail contact comprises: a conductive layer is deposited on and adjacent to the fork plate structure. Portions of the conductive layer on the prong plate structure are removed and the power rail contact includes portions of the conductive layer remaining adjacent to the prong plate structure. In some embodiments of the method, forming the isolation region comprises: a dielectric layer is deposited over the prong plate structure and the power rail contacts. Portions of the dielectric layer over the fork plate structure are removed, and the isolation region includes portions of the dielectric layer that remain over the power rails. In some embodiments of the method, forming the fork plate structure comprises: forming a first fin structure and a second fin structure extending from a substrate; depositing a dielectric layer over and between the first and second fin structures; portions of the dielectric layer over the first fin structure and the second fin structure are removed to form a dielectric wall, the dielectric wall including portions of the dielectric layer remaining between the first fin structure and the second fin structure. In some embodiments, the method further comprises: forming a dielectric fin on the isolation region, after growing the first source/drain region, separating the first source/drain region from the dielectric fin; after growing the first source/drain region, a dielectric layer is deposited between the dielectric fin and the first source/drain region, and an ILD is deposited on the dielectric layer. In some embodiments of the method, forming the source/drain contact comprises: etching an opening through the ILD, the dielectric layer, and the isolation region, a portion of the opening in the ILD exposing a top surface of the first source/drain region, a portion of the opening in the dielectric layer exposing the first source/drain region and the sides, a portion of the opening in the isolation region exposing the power rail contact; forming a metal-semiconductor alloy region on the first source/drain region and in the opening, a portion of the metal-semiconductor alloy region on a top surface of the first source/drain region having a first thickness, a portion of the metal-semiconductor alloy region on a side of the first source/drain region having a second thickness, the first thickness being greater than or equal to the second thickness; source/drain contacts are formed on the metal semiconductor alloy region and portions of the power rail contacts are exposed at the openings.

In one embodiment, a device comprises: a power rail contact; an isolation region on the power rail contact; a first dielectric fin on the isolation region; a second dielectric fin adjacent the isolation region and the power rail contact; a first source/drain region on the second dielectric fin; a source/drain contact between the first source/drain region and the first dielectric fin, the source/drain contact contacting a top surface of the first source/drain region, a side of the first source/drain region, and a top surface of the power rail contact.

In some embodiments, the device further comprises: a liner layer disposed between each of the first dielectric fin and the isolation region and the power rail contact. In some embodiments, the device further comprises: a metal semiconductor alloy region between the source/drain contact and the first source/drain region, a portion of the metal semiconductor alloy region on a top surface of the first source/drain region having a first thickness, and a portion of the metal semiconductor alloy region on a side of the first source/drain region having a second thickness, the first thickness being greater than or equal to the second thickness. In some embodiments of the device, the first thickness and the second thickness are in a range of 2.5nm to 7.5 nm. In some embodiments of the device, the power rail contact and the backside of the second dielectric fin are coplanar. In some embodiments, the device further comprises: a second dielectric layer on the power rail contact and the backside of the first dielectric fin; a power trace in the second dielectric layer, the power trace connected to the power trace contact. In some embodiments of the device, the surface of the power rail contact is free of the metal-semiconductor alloy region. In some embodiments, the device further comprises: a dielectric layer laterally disposed between the first dielectric fin and the first source/drain region, the source/drain contact extending through the dielectric layer; an inter-layer dielectric layer (ILD) on the dielectric layer, the first dielectric fin, and the second dielectric fin, the source/drain contact extending through the ILD.

In one embodiment, a device comprises: a first interconnect structure comprising a metallization pattern; a second interconnect structure including power traces; a device layer between the first interconnect structure and the second interconnect structure, the device layer comprising: a transistor including source/drain regions; a power rail contact connected to the power rail; a source/drain contact connected to the power rail contact, the source/drain region, and the metallization pattern.

In some embodiments of the device, the device layer further comprises: an isolation region to isolate the transistor from other transistors of the device layer, the power rail contact being buried in the isolation region. In some embodiments of the device, the source/drain region has a faceted top surface and faceted sides, and the source/drain contact extends along the faceted top surface and the faceted sides.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of forming a semiconductor device, comprising:

forming a fork plate structure above the substrate;

forming a power rail contact adjacent to the prong structure;

forming an isolation region on the power rail contact, the prong plate structure protruding from the isolation region;

growing a first source/drain region in the fork plate structure;

depositing an interlayer dielectric (ILD) on the first source/drain region; and

forming a source/drain contact through the ILD and the isolation region, the source/drain contact connected to the first source/drain region and the power rail contact.

2. The method of claim 1, wherein the prong plate structure includes a first nanostructure, a second nanostructure, and a dielectric wall between the first nanostructure and the second nanostructure, the first source/drain region abutting the first nanostructure, the method further comprising:

growing a second source/drain region in the fork plate structure, the second source/drain region abutting the second nanostructure, the dielectric wall disposed between the first source/drain region and the second source/drain region.

3. The method of claim 2, further comprising:

forming a first gate structure around the first nanostructure; and

forming a second gate structure around the second nanostructure, the second gate structure being connected to the first gate structure.

4. The method of claim 2, wherein the first nanostructure, the second nanostructure, and the dielectric wall have parallel longitudinal axes in a first direction, and the dielectric wall is disposed between the first source/drain region and the second source/drain region in a second direction, the first direction being perpendicular to the second direction.

5. The method of claim 1, wherein forming the power rail contact comprises:

depositing a conductive layer on and adjacent to the fork plate structure; and

removing portions of the conductive layer on the prong structure, the power rail contact including portions of the conductive layer remaining adjacent to the prong structure.

6. The method of claim 1, wherein forming the isolation region comprises:

depositing a dielectric layer on the prong plate structure and the power rail contact; and

removing portions of the dielectric layer on the fork plate structure, the isolation region including portions of the dielectric layer remaining on a power rail.

7. The method of claim 1, wherein forming the fork plate structure comprises:

forming a first fin structure and a second fin structure extending from the substrate;

depositing a dielectric layer over and between the first and second fin structures; and

removing portions of the dielectric layer over the first fin structure and the second fin structure to form a dielectric wall, the dielectric wall including portions of the dielectric layer remaining between the first fin structure and the second fin structure.

8. The method of claim 1, further comprising:

forming a dielectric fin on the isolation region, after growing the first source/drain region, separating the first source/drain region from the dielectric fin; and

after growing the first source/drain region, depositing a dielectric layer between the dielectric fin and the first source/drain region, the ILD being deposited on the dielectric layer.

9. A semiconductor device, comprising:

a power rail contact;

an isolation region on the power rail contact;

a first dielectric fin on the isolation region;

a second dielectric fin adjacent to the isolation region and the power rail contact;

a first source/drain region on the second dielectric fin; and

a source/drain contact between the first source/drain region and the first dielectric fin, the source/drain contact contacting a top surface of the first source/drain region, a side surface of the first source/drain region, and a top surface of the power rail contact.

10. A semiconductor device, comprising:

a first interconnect structure comprising a metallization pattern;

a second interconnect structure including power traces;

a device layer between the first interconnect structure and the second interconnect structure, the device layer comprising:

a transistor including source/drain regions;

a power rail contact connected to the power rail; and

a source/drain contact connected to the power rail contact, the source/drain region, and the metallization pattern.