KR20210145497A - Micro-nano-fin light-emitting diodes electrode assembly and method for manufacturing thereof - Google Patents

Abstract

The present invention relates to an LED electrode assembly, and more particularly, to a micro-nanopin LED electrode assembly and a method for manufacturing the same. According to the present invention, a micro-nanopin LED electrode assembly includes: a lower electrode line; a plurality of micro-nanopin LED devices; and an upper electrode line. An object of the present invention is to provide an electrode assembly using a micro-nanopin LED that has improved luminance and maintains high efficiency by increasing a light emitting area, and a method for manufacturing the same.

Description

Micro-nano-fin light-emitting diodes electrode assembly and method for manufacturing thereof

The present invention relates to an LED electrode assembly, and more particularly, to a micro-nanopin LED electrode assembly and a manufacturing method thereof.

Micro LED and nano LED can realize excellent color and high efficiency, and because they are eco-friendly materials, they are used as core materials for various light sources and displays. In line with these market conditions, research to develop a new nanorod LED structure or a shell-coated nanocable LED by a new manufacturing process is in progress. In addition, research on a protective film material to achieve high efficiency and high stability of the protective film covering the outer surface of the nanorods, or research and development of a ligand material advantageous for the subsequent process is in progress.

In line with such research in the field of materials, display TVs using red, green, and blue micro-LEDs have recently been commercialized. Display and various light sources using micro-LED have high performance characteristics, theoretical lifespan and very long and high efficiency. The electrode assembly implemented by placing it with pick place technology is a real high-resolution commercial display from smartphones to TVs, or light sources with various sizes, shapes, and brightness due to the limitations of process technology in consideration of high unit cost, high process defect rate, and low productivity. It is difficult to manufacture. In addition, it is more difficult to individually place nano-LEDs, which are smaller than micro-LEDs, on an electrode with the same pick and place technology as micro-LEDs.

In order to overcome this difficulty, the present inventor's Patent Publication No. 10-1490758 discloses a nanorod-type LED mixed solution is dropped on an electrode and an electric field is formed between two different electrodes to form a nanorod. Disclosed is a miniature LED electrode assembly manufactured through a method of self-aligning type LED elements on an electrode. However, the nanorod LED used has a problem in that a large number of LEDs must be mounted in order to achieve the desired efficiency because the light extraction area is small and the efficiency is not good, and the problem that the nanorod LED itself has a high possibility of defects there is

Specifically, for nanorod-type LED devices, it is known that an LED wafer is manufactured by a top-down method by mixing a nano-pattern process and dry etching/Ÿ‡ etching, or growing directly on a substrate by a bottom-up method. . In these nanorod-type LEDs, the long axis of the LED coincides with the stacking direction of each layer in the stacking direction, that is, in the p-GaN/InGaN multiple quantum well (MQW)/n-GaN stacked structure, so the light emitting area is narrow, and the light emitting area is relatively narrow. As a result, surface defects have a significant impact on efficiency degradation, and it is difficult to optimize the crystal-hole recombination rate.

Therefore, the LED electrode assembly using a new LED material that can be easily arranged using an electric field, has a large luminous area, minimizes or prevents reduction in efficiency due to surface defects, and has an optimized electron-hole recombination rate. There is an urgent need for development.

Registered Patent Publication No. 10-1490758

The present invention has been devised to solve the above problems, and an object of the present invention is to provide an electrode assembly using a micro-nanopin LED having improved luminance and maintaining high efficiency by increasing a light emitting area and a method for manufacturing the same.

In addition, it is possible to prevent a decrease in efficiency due to surface defects by greatly reducing the area of the photoactive layer exposed on the surface while increasing the light emitting area, thereby stably emitting light with high luminance. but has a different purpose.

In addition, the decrease in electron-hole recombination efficiency due to the non-uniformity of electron and hole velocities and the decrease in luminous efficiency due to this decrease, and the area of the photoactive layer exposed to the surface is greatly reduced while increasing the luminous area, thereby preventing the decrease in efficiency due to surface defects. It is another object to provide an electrode assembly using a micro-nanopin LED device and a method for manufacturing the same.

Furthermore, it is possible to more easily self-align the device on the electrode by an electric field without fear of an electrical short circuit, and to provide an electrode assembly using a micro-nanopin LED device with improved electrode arrangement design and electrode implementation easiness and a manufacturing method thereof It has another purpose.

In order to solve the above problems, the present invention (1) has a plane having a length and width of nano or micro size on a lower electrode line including a plurality of lower electrodes spaced apart in the horizontal direction at a predetermined interval, A plurality of micro-nanopin LED devices in which a first conductive semiconductor layer, a photoactive layer, a second conductive semiconductor layer, and a polarization inducing layer are sequentially stacked in the thickness direction as a rod-shaped device having a thickness perpendicular to the plane smaller than the length. A step of introducing a solution containing It provides a method of manufacturing a micro-nanopin LED device electrode assembly comprising the steps of self-aligning so as to be self-aligned, and (3) forming an upper electrode line on a plurality of self-aligned micro-nanopin LED devices.

According to an embodiment of the present invention, the predetermined interval may be smaller than the micro-nano pin LED element length.

In addition, between the steps (2) and (3), (4) the side of the first conductive semiconductor layer or the polarization inducing layer of each micro-nano fin LED device in contact with the at least two lower electrodes and the at least two Forming a conductive metal layer connecting the lower electrodes, and (5) forming an insulating layer on the lower electrode line by not covering the upper surface of the self-aligned plurality of micro-nano pin LED devices. can

In addition, the micro-nanopin LED device may have a length of 1000 to 10000 nm and a thickness of 100 to 3000 nm.

In addition, the width of the micro-nanopin LED device may be greater than or equal to the thickness.

In addition, the ratio of the length to the thickness of the micro-nanopin LED device may be 3:1 or more.

In addition, the micro-nano-fin LED device may further include a protective film formed on the side surface of the device to cover the exposed surface of the photoactive layer.

In addition, the polarization inducing layer consists of a first polarization inducing layer and a second polarization inducing layer disposed adjacent to each other in the longitudinal direction of the device, and the first polarization inducing layer and the second polarization inducing layer have different electrical polarities. can In this case, for example, the first polarization inducing layer may be ITO, and the second polarization inducing layer may be a metal or a semiconductor.

In addition, the present invention has a lower electrode line including a plurality of lower electrodes spaced apart in the horizontal direction at a predetermined interval, a plane having a length and width of nano or micro size, and a thickness perpendicular to the plane is smaller than the length. As a rod-type device, a first conductive semiconductor layer, a photoactive layer, a second conductive semiconductor layer, and a polarization inducing layer are sequentially stacked in the thickness direction, and at least two lower electrodes adjacent to the first conductive semiconductor layer or the polarization inducing layer; Provided is a micro-nanopin LED device electrode assembly comprising a plurality of micro-nanopin LED devices disposed to be in contact with each other, and an upper electrode line disposed on the plurality of micro-nanopin LED devices.

According to an embodiment of the present invention, one of the first conductive semiconductor layer and the second conductive semiconductor layer includes a p-type GaN semiconductor layer, the other includes an n-type GaN semiconductor layer, and the p-type GaN The thickness of the semiconductor layer may be 10 to 350 nm, the thickness of the n-type GaN semiconductor layer may be 100 to 3000 nm, and the thickness of the photoactive layer may be 30 to 200 nm.

In addition, a protrusion having a predetermined width and thickness may be formed on the lower surface of the first conductive semiconductor layer of the micro-nanopin LED device in the longitudinal direction of the device.

In addition, the width of the protrusion may be formed to have a length of 50% or less compared to the width of the micro-nanopin LED device.

In addition, the emission area of the micro-nanopin LED device may exceed twice the area of the vertical cross-section of the micro-nanopin LED device.

Hereinafter, the terms used in the present invention are defined.

In the description of an embodiment according to the present invention, each layer, region, pattern or substrate, “on”, “top”, “top”, “under”, “below” of each layer, region, pattern ", "in the case of being described as being formed under "," "on", "upper", "upper", "under", "lower", "lower" refers to "directly" and " includes all meanings of "indirectly".

The micro-nano pin LED electrode assembly according to the present invention is advantageous in achieving high luminance and light efficiency by increasing the light emitting area of the device compared to the electrode assembly using the conventional rod-type LED device. In addition, while increasing the light emitting area of the device, the area of the photoactive layer exposed on the surface can be greatly reduced to prevent or minimize the decrease in efficiency due to surface defects, so that it is possible to realize an electrode assembly with excellent quality. Furthermore, the reduction in electron-hole recombination efficiency due to the non-uniformity of the electron and hole velocities of the used LED device and the reduction in luminous efficiency due to this are minimized, and since it is very suitable for the method of self-aligning the device on the electrode by an electric field, the electrode assembly Since it can be implemented more easily, it can be widely applied to various lighting, light sources, displays, and the like.

1 and 2 are views of a micro-nanopin LED electrode assembly according to an embodiment of the present invention, FIG. 1 is a plan view of the micro-nanopin LED electrode assembly, and FIG. It is a cross section.
3 to 5 are a perspective view of a micro-nanopin LED device included in an embodiment of the present invention, a cross-sectional view taken along the boundary line XX' of FIG. 3, and a cross-sectional view taken along the boundary line YY' of FIG. 3 .
6A and 6B are schematic views of a first rod-type device in which a first conductive semiconductor layer, a photoactive layer, and a second conductive semiconductor layer are stacked in the thickness direction, respectively, and a first conductive semiconductor layer, a photoactive layer, and a second conductive semiconductor layer in the longitudinal direction; It is a schematic diagram of a second rod-type device in which layers are stacked.
7 is a schematic diagram of a micro-nanopin LED device manufacturing process included in an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail so that those of ordinary skill in the art to which the present invention pertains can easily implement them. The present invention may be embodied in many different forms and is not limited to the embodiments described herein.

1 and 2, the micro-nanopin LED electrode assembly 1000 according to an embodiment of the present invention is a lower portion including a plurality of electrodes 211, 212, 213, 214 spaced apart in the horizontal direction at a predetermined interval. An electrode line 200, a plurality of micro-nano-pin LED devices 100 and 101 disposed on the lower electrode line 200, and an upper electrode line 300 disposed in contact with upper portions of the micro-nano-pin LED devices 100 and 101 ) is implemented including

First, before the detailed description of each configuration, the electrode lines for self-aligning the micro-nanopin LED device and emitting light will be described.

The micro-nano-pin LED electrode assembly 1000 includes an upper electrode line 300 and a lower electrode line 200 disposed to face the upper and lower portions with the micro-nano-pin LED devices 100 and 101 interposed therebetween. Since the upper electrode line 300 and the lower electrode line 200 are not arranged in a horizontal direction, two types of electrodes implemented to have an ultra-small thickness and width are horizontally arranged in micro or nano units within a plane of a limited area. By breaking away from the complicated electrode line of the electrode assembly by the conventional electric field induction arranged to have a gap, the electrode design can be very simple and can be implemented more easily.

Specifically, the electrode assembly implemented by self-aligning elements through conventional electric field induction uses horizontally spaced electrodes as assembly electrodes to mount a rod-type micro LED element on the assembly electrode, The same electrode, that is, the assembly electrode as it is, is used as the driving electrode, whereas the lower electrode line 200 provided in the embodiment of the present invention functions as an assembly electrode, but the first conductive semiconductor is formed on the lower electrode line 200 . Since only the surface of the layer or the surface of the second conductive semiconductor layer is in contact, the micro-nanopin LED devices 100 and 101 cannot emit light with only the lower electrode line 200, which is different from the conventional electrode assembly through electric field induction. . This distinction causes a significant difference in the degree of freedom of electrode design and the ease of electrode design.

In other words, when the assembled electrode and the driving electrode are used as the same electrode, the rod-type micro LED element can be mounted as many as possible in the plane of a limited area, and at the same time, different voltages are applied at intervals of micro-nano size. It was not easy in the design or implementation of the electrode structure because it had to be implemented. However, since the same type of power (for example, (+) or (-) power) is applied to the lower electrode line 200 included in the present invention when driving, an electrical short between the lower electrodes 211, 212, 213 and 214 in the lower electrode line 200 is There is little concern. In addition, in the prior art, both ends of each rod-type ultra-small LED element had to correspond one-to-one to the adjacent electrodes, respectively, so that light could be emitted without an electrical short circuit. Accordingly, if each rod-type micro LED element is disposed across three or four adjacent electrodes, the photoactive layer of the rod-type micro LED element inevitably comes into contact with the electrode, and as a result, a short circuit occurs. Therefore, there was a difficulty in designing the electrode. However, in the micro-nanopin LED devices 100 and 101 included in the present invention, the surface of the first conductive semiconductor layer or the second conductive semiconductor layer is in contact with the lower electrode line, so it spans several adjacent lower electrodes 211, 212, 213, 214. Even when disposed, an electrical short does not occur, which has an advantage in that the lower electrode line 200 can be designed more easily.

In addition, the upper electrode line 300 is arranged as shown in FIGS. 1 and 2 so that electrical contact is possible on the upper surfaces of the micro-nanopin LED devices 100 and 101 , so the design or implementation of the electrode is very easy. There is one advantage. In particular, although FIG. 1 shows that the upper electrode line 300 is divided into the first upper electrode 301 and the second upper electrode 302 to be implemented, all micro-nanopin LED devices arranged with only one upper electrode Since it can be implemented to contact the upper surface of the electrode, there is an advantage that the electrode can be very simplified compared to the prior art.

The lower electrode line 200 is an assembly electrode for self-aligning the micro-nanopin LED devices 100 and 101 so that the upper or lower surfaces of the micro-nanopin LED devices 100 and 101 in the thickness direction are in contact with each other, and at the same time, an upper part to be described later. It functions as one of the driving electrodes provided for emitting light to the micro-nanopin LED devices 100 and 101 together with the electrode line 300 .

In addition, the lower electrode line 200 is implemented to include a plurality of lower electrodes 211 , 212 , 213 , and 214 spaced apart in the horizontal direction at a predetermined interval. The number and spacing of the lower electrodes 211 , 212 , 213 , and 214 may include the electrodes 211 , 212 , 213 , and 214 at an appropriately set number and spacing in consideration of the function as an assembly electrode and the length of the device.

In addition, as long as the plurality of lower electrodes 211 , 212 , 213 , and 214 included in the lower electrode line 200 are arranged to be spaced apart in the horizontal direction, there is no limitation on specific electrode arrangement. It may have a structure in which it is arranged.

On the other hand, the distance between the adjacent electrodes 211 and 212 may be smaller than the length of the micro-nanopin LED device 100. If the distance between the two adjacent electrodes is equal to or wider than the length of the micro-nanopin LED device, the micro- The nanopin LED device can be self-aligned in a form sandwiched between two adjacent electrodes. can't

In addition, when the upper electrode line 300 is designed to be in electrical contact with the upper portions of the micro-nanopin LED devices 100 and 101 mounted on the lower electrode line 200 , the number, arrangement, shape, etc. are not limited. However, as shown in FIG. 1 , if the lower electrode lines 200 are arranged side by side in one direction, the upper electrode lines 300 may be arranged to be perpendicular to the one direction, and such an electrode arrangement is an electrode widely used in a display or the like in the prior art. As the arrangement, there is an advantage that the electrode arrangement and control technology of the conventional display field can be used as it is.

Meanwhile, FIG. 1 shows only the first upper electrode 301 and the second upper electrode 302 so that the upper electrode line 300 including them covers only some elements, but this is omitted for ease of description. As a result, it is revealed that there is an unillustrated upper electrode disposed on top of the micro-nanopin LED device.

The lower electrode line 200 and the upper electrode line 300 may have the material, shape, width, and thickness of an electrode used in a typical LED electrode assembly, and can be manufactured using a known method, so the present invention is specifically does not limit this to For example, the electrode may be aluminum, chromium, gold, silver, copper, graphene, ITO, or an alloy thereof, and may have a width of 2 to 50 μm and a thickness of 0.1 to 100 μm. It may be appropriately changed in consideration of the size and the like.

Next, the micro-nanopin LED devices 100 and 101 disposed between the above-described lower electrode line 200 and the upper electrode line 300 will be described.

3 to 5, the micro-nanopin LED device 100 according to an embodiment of the present invention has a length in an X-axis direction and a width in the Y-axis direction with respect to the mutually perpendicular X, Y, and Z axes. , when the Z-axis direction is the thickness, the length becomes the long axis, and the length at which the thickness becomes the short axis is a rod-shaped device larger than the thickness, and the first conductive semiconductor layer 10, the photoactive layer 20, the second It is a device in which the second conductive semiconductor layer 30 and the polarization inducing layer 40 are sequentially stacked.

More specifically, the micro-nanopin LED device 100 has a predetermined shape in an X-Y plane consisting of a length and a width, a direction perpendicular to the plane becomes a thickness direction, and each layer is stacked in the thickness direction. The micro-nanofin LED device having such a structure has an advantage in that it can secure a wider light emitting area due to the flat surface of the length and width even if the thickness of the photoactive layer 20 in the portion exposed to the side is thin. In addition, due to this, the light emitting area of the micro-nanopin LED device 100 according to an embodiment of the present invention may have a wide light emitting area exceeding twice the longitudinal cross-sectional area of the micro-nanopin LED device. Here, the longitudinal cross-section is a cross-section parallel to the X-axis direction, which is the longitudinal direction, and in the case of an element having a constant width, it may be the X-Y plane.

Specifically, referring to FIGS. 6A and 6B , both the first rod-type device 1 shown in FIG. 6A and the second rod-type device 1 ′ shown in FIG. 6B include the first conductive semiconductor layer 2 ), the photoactive layer 3 and the second conductive semiconductor layer 4 are stacked, the length (ℓ) and the thickness (m) are the same, and the thickness (h) of the photoactive layer is also the same rod-type device. . However, in the first rod-shaped element 1, the first conductive semiconductor layer 2, the photoactive layer 3, and the second conductive semiconductor layer 4 are stacked in the thickness direction, whereas the second rod-shaped element 1' ) is structurally different in that each layer is stacked in the longitudinal direction.

However, the two devices 1 and 1' have a large difference in the emission area. For example, the length (ℓ) is 4500 nm, the thickness (m) is 600 nm, and the thickness (h) of the photoactive layer 3 is 100 nm. Assuming that , the ratio of the surface area of the photoactive layer 3 of the first rod-type device 1 and the surface area of the photoactive layer 3 of the second rod-type device 1 ′ corresponding to the emission area is 6.42 μm ² : 0.6597 With μm ² , the light emitting area of the micro-nanofin LED device 1 is 9.84 times larger. In addition, the ratio of the surface area of the photoactive layer 3 exposed to the outside in the light emission area of the total photoactive layer is similar to that of the first rod-shaped element 1 and the second rod-shaped element 1', but the increased photoactive layer ( Since the absolute value of the unexposed surface area of 3) is much larger, the effect of the exposed surface area on excitons is much reduced. Therefore, the micro-nanofin LED device 1 has a higher surface defect than the horizontally arranged rod-type device 1 ′. Since the effect on the horizontal array element 1' is much smaller, it can be evaluated that the micro-nanopin LED element 1 is significantly superior to the horizontal array rod-type element 1' in terms of luminous efficiency and luminance. In addition, in the case of the second rod-type device 1', the wafer on which the conductive semiconductor layer and the photoactive layer are stacked in the thickness direction is etched in the thickness direction. As a result, the long device length corresponds to the wafer thickness and increases the device length. In order to do this, an increase in the etched depth is unavoidable. The greater the etch depth, the higher the probability of occurrence of defects on the device surface. As a result, the area of the photoactive layer exposed in the second rod-type device 1 ′ is equal to that of the first rod-type device 1 . Even if it is small, the possibility of occurrence of surface defects is greater, and ultimately, the first rod-type device 1 can be significantly superior in luminous efficiency and luminance when the reduction in luminous efficiency due to the increase in the possibility of surface defects is taken into consideration.

Further, the movement distance of the holes injected from any one of the first conductive semiconductor layer 2 and the second conductive semiconductor layer 4 and the electrons injected from the other is the first rod-type element 1 and the second rod-type element Short compared to (1'), which reduces the probability of electrons and/or holes being captured by defects on the wall during electron and/or hole movement, thereby minimizing luminescence loss, and emitting light due to electron-hole velocity imbalance It can also be advantageous to minimize losses. In addition, in the case of the second rod-type element 1', a strong optical path behavior occurs due to the circular rod-shaped structure, so the path of light generated by electron-holes resonates in the longitudinal direction, so that light is emitted from both ends in the longitudinal direction. On the other hand, in the case of the first rod-type device 1, the first rod-type device 1 emits light from the upper surface and the lower surface, so there is an advantage of expressing excellent front emission efficiency.

The micro-nano-fin LED device 100 of the present invention has the conductive semiconductor layers 10 and 30 and the photoactive layer 20 stacked in the thickness direction like the first rod-type device 1 described above, and the length is greater than the thickness. Even if the area of the photoactive layer 20 exposed at the same time as having a more improved light emitting area by implementing it longer is slightly increased, the depth of etching is shallow because the thickness is smaller than the length of the rod, so the exposed surface of the photoactive layer 20 is defective Since the possibility of this occurrence can be reduced, it is advantageous to minimize or prevent a decrease in luminous efficiency due to a defect.

Although the plane is shown as a rectangle in FIG. 3, it is not limited thereto, and it turns out that it can be employed without limitation, from a general rectangular shape such as a rhombus, a parallelogram, and a trapezoid to an oval.

The micro-nanopin LED devices 100 and 101 according to an embodiment of the present invention have a length and a width of micro or nano units, for example, the device may have a length of 1000 to 10000 nm, and a width of 100 to 3000 may be in nm. In addition, the thickness may be 100 ~ 3000 nm. The length and width may have different standards depending on the shape of the plane. For example, if the plane is a rhombus or a parallelogram, one of the two diagonals may be the length and the other may be the width, and in the case of a trapezoid, the height, the upper side And a long side of the base may be a length, and a short side perpendicular to the long side may be a width. Alternatively, when the shape of the plane is an ellipse, the major axis of the ellipse may be the length and the minor axis may be the width.

At this time, the ratio of the length to the thickness of the micro-nanopin LED devices 100 and 101 may be greater than 3:1, more preferably, more than 6:1, which makes it easier to connect the lower electrode through the electric field. It has the advantage of being able to self-align. If the length and thickness ratio of the micro-nanopin LED device 100 is reduced to less than 3:1, it may be difficult to self-align the device on the electrode through an electric field, and the device is not fixed on the lower electrode. There is a risk of causing an electrical contact short circuit caused by a process defect. However, the ratio of the length to the thickness may be 15:1 or less, and through this, it may be advantageous to achieve the object of the present invention, such as optimization of a turning force that becomes self-aligned through an electric field.

In addition, the ratio of the length to the width in the plane may also be greater, preferably 3:1 or more, more preferably 6:1 or more, so that it can be more easily self-aligned to the lower electrode through an electric field there is an advantage However, the ratio of the length to the width may be 15:1 or less, which may be advantageous for optimization of the turning force that is self-aligned through the electric field.

In addition, the width of the micro-nanopin LED devices 100 and 101 may be greater than or equal to the thickness. Through this, when the micro-nanopin LED devices 100 and 101 are aligned on the lower electrode line using an electric field, the There is an advantage that alignment can be minimized or prevented. If the micro-nanopin LED device is aligned on its side, the side photoactive layer exposed in the device on the electrode is achieved even if alignment and mounting are achieved in which one end and the other end contact the two adjacent lower electrodes 211/212 and 213/214, respectively. There is a fear that the device may not emit light due to an electrical short that occurs due to contact.

In addition, the micro-nanopin LED devices 100 and 101 may be devices having different sizes at both ends in the longitudinal direction, for example, a rod-type device having a rectangular plane with an equilateral trapezoid having a length greater than an upper side and a lower side. , depending on the difference in length between the upper and lower sides, a difference between positive and negative charges accumulated at both ends of the device in the longitudinal direction may occur as a result.

In addition, a protrusion 11 having a predetermined width and thickness may be formed on the lower surface of the first conductive semiconductor layer 10 of the micro-nanopin LED devices 100 and 101 in the longitudinal direction of the device. The protrusion 11 will be described in detail in the description of the manufacturing method to be described later, but after etching the wafer in the thickness direction, in order to remove the etched LED part on the wafer, from both sides of the lower end of the etched LED part to the central part inward It may be generated as a result of etching in the horizontal direction. The protrusion 11 may help to improve the extraction of the top emission of the micro-nanopin LED device 100 . In addition, when the micro-nanopin LED device 100 is self-aligned on the lower electrode line, the protrusion 11 has a polarization inducing layer 40 that is opposite to one surface of the device on which the protrusion 11 is formed is the lower electrode. It can help control the alignment to be positioned on line 200 . Furthermore, the polarization inducing layer is positioned on the lower electrode line 200, and the upper electrode line 300 is formed on one surface of the device on which the protrusion 11 is formed, and the protrusion 11 is formed with the upper electrode line 300 and As the contact area is increased, it may be advantageous to improve the mechanical coupling force between the upper electrode line 300 and the micro-nanopin LED device 100 .

At this time, the width of the protrusion 11 may be formed to be 50% or less, more preferably, 30% or less of the width of the micro-nanopin LED device 100, through which the micro-nanopins etched on the LED wafer Separation of the LED element portion may be easier. If a protrusion is formed exceeding 50% of the width of the micro-nanopin LED device 100, it may not be easy to separate the micro-nanopin LED device portion etched on the LED wafer, and Separation may occur, which may lower mass productivity, and there is a risk that the uniformity of the micro-nanopin LED devices produced in plurality may be lowered. Meanwhile, the width of the protrusion 11 may be formed to be 10% or more of the width of the micro-nanopin LED device 100 . If the width of the protrusion is formed to be less than 10% of the width of the micro-nanopin LED device 100, the separation on the LED wafer may be easy, but during side etching (FIG. 7(g), FIG. 7(i)) Reference) Due to excessive etching, there is a risk that even a portion of the first conductive semiconductor layer that should not be etched may be etched, and the effect according to the above-described protrusion 11 may not be exhibited. In addition, there is a risk that the device may be damaged by the wet etching solution, and the micro-nanopin LED device dispersed in the high-risk etching solution having a strong basic property needs to be cleaned separately from the wet etching solution. On the other hand, the thickness of the protrusion 11 may have a thickness of 10 to 30% of the thickness of the first conductive semiconductor layer, and through this, the first conductive semiconductor layer may be formed to a desired thickness and quality, as described above. It may be more advantageous to express the effect through the protrusion 11 . Here, the thickness of the first conductive semiconductor layer means a thickness based on the lower surface of the first conductive semiconductor layer on which the protrusion is not formed.

As a specific example, the width of the protrusion 11 may be 50 to 300 nm, and the thickness may be 50 to 400 nm.

Hereinafter, each layer included in the micro-nanopin LED devices 100 and 101 will be described.

The micro-nanopin LED devices 100 and 101 include a first conductive semiconductor layer 10 and a second conductive semiconductor layer 30 . The conductive semiconductor layer used may be used without limitation if it is a conductive semiconductor layer employed in general LED devices used for lighting, displays, and the like. According to a preferred embodiment of the present invention, any one of the first conductive semiconductor layer 10 and the second conductive semiconductor layer 30 includes at least one n-type semiconductor layer, and the other conductive semiconductor layer is a p-type semiconductor. It may include at least one layer.

When the first conductive semiconductor layer 10 includes an n-type semiconductor layer, the n-type semiconductor layer is InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1) For example, any one or more of a semiconductor material having a composition formula of InAlGaN, GaN, AlGaN, InGaN, AlN, InN, etc. may be selected, and a first conductive dopant (eg, Si, Ge, Sn, etc.) may be doped. According to a preferred embodiment of the present invention, the thickness of the first conductive semiconductor layer 10 may be 1.5 to 5 μm, but is not limited thereto.

When the second conductive semiconductor layer 30 includes a p-type semiconductor layer, the p-type semiconductor layer is InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1) For example, any one or more of a semiconductor material having a composition formula of InAlGaN, GaN, AlGaN, InGaN, AlN, InN, etc. may be selected, and a second conductive dopant (eg, Mg) may be doped. According to a preferred embodiment of the present invention, the thickness of the second conductive semiconductor layer 30 may be 0.01 to 0.30 μm, but is not limited thereto.

According to an embodiment of the present invention, one of the first conductive semiconductor layer 10 and the second conductive semiconductor layer 30 includes a p-type GaN semiconductor layer, and the other includes an n-type GaN semiconductor layer. and the p-type GaN semiconductor layer may have a thickness of 10 to 350 nm, and the n-type GaN semiconductor layer may have a thickness of 100 to 3000 nm, through which holes injected into the p-type GaN semiconductor layer and the n-type GaN semiconductor layer are injected The moving distance of the electrons is shorter compared to the rod-type device in which the semiconductor layer and the photoactive layer are stacked in the longitudinal direction as shown in FIG. It is possible to minimize emission loss, and it may be advantageous to minimize emission loss due to electron-hole velocity imbalance as well.

Next, the photoactive layer 20 is formed on the first conductive semiconductor layer 10 and may have a single or multiple quantum well structure. The photoactive layer 20 may be used without limitation if it is a photoactive layer included in a typical LED device used for lighting, display, and the like. A cladding layer (not shown) doped with a conductive dopant may be formed above and/or below the photoactive layer 20 , and the clad layer doped with the conductive dopant may be implemented as an AlGaN layer or an InAlGaN layer. In addition, a material such as AlGaN or AlInGaN may be used as the photoactive layer 20 . In the photoactive layer 20, when an electric field is applied to the device, electrons and holes that move from the conductive semiconductor layer positioned above and below the photoactive layer to the photoactive layer generate electron-hole pairs in the photoactive layer. will glow due to According to a preferred embodiment of the present invention, the thickness of the photoactive layer 20 may be 30 ~ 300 nm, but is not limited thereto.

Next, the polarization inducing layer 40 formed on the second conductive semiconductor layer 30 described above is a layer that facilitates self-alignment by an electric field by allowing both ends to have different electrical polarities in the longitudinal direction of the device. When using a material such as , metal, etc., it can function as an electrode layer by increasing conductivity. The polarization inducing layer 40 may have a first polarization inducing layer 41 disposed at one end along the device longitudinal direction, and a second polarization inducing layer 42 disposed at the other end thereof, and the first polarization inducing layer 40 may be disposed at the other end thereof. The layer 41 and the second polarization inducing layer 42 may have different electrical polarities. For example, the first polarization inducing layer 41 may be ITO, and the second polarization inducing layer 42 may be a metal or a semiconductor. In addition, the thickness of the polarization inducing layer 40 may be 50 ~ 500 nm, but is not limited thereto. The first polarization inducing layer 41 and the second polarization inducing layer 42 may be disposed in the same area by dividing the upper surface of the second conductive semiconductor layer 30 in two, but is not limited thereto. Either one of the inducing layer 41 and the second polarization inducing layer 42 may be disposed to have a larger area.

The first conductive semiconductor layer 10, the photoactive layer 20, the second conductive semiconductor layer 30, and the polarization inducing layer 40 described above may be included as minimum components of the LED device, and on each layer It may further include another phosphor layer, an active layer, a semiconductor layer, a hole blocking layer and/or an electrode layer below.

Meanwhile, according to an embodiment of the present invention, a protective film 50 formed on the side of the micro-nanopin LED device 100 to cover the exposed surface of the photoactive layer 20 may be further included. The protective film 50 is a film for protecting the exposed surface of the photoactive layer 20 , and covers at least all of the exposed surface of the photoactive layer 20 , for example, both sides of the micro-nanopin LED device 100 . And, it is possible to cover both the front end surface and the rear end surface. The protective film 50 is preferably silicon nitride (Si ₃ N ₄ ), silicon dioxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), yttrium oxide (Y ₂ O ₃ ) and titanium dioxide (TiO ₂ ), aluminum nitride (AlN), and gallium nitride (GaN) may include any one or more, more preferably made of the above components, but may be transparent, but However, the present invention is not limited thereto. According to a preferred embodiment of the present invention, the thickness of the protective film 50 may be 5 nm to 100 nm, but is not limited thereto.

The above-described micro-nanopin LED devices 100 and 101 may be manufactured by a manufacturing method described later, but is not limited thereto. Specifically, the micro-nanopin LED devices 100 and 101 are (A) preparing an LED wafer in which a first conductive semiconductor layer, a photoactive layer and a second conductive semiconductor layer are sequentially stacked on a substrate, (B) the LED wafer Forming a polarization inducing layer patterned so that regions having different electrical polarities are adjacent to each other on the second conductive semiconductor layer of etching the LED wafer in the thickness direction so that the thickness perpendicular to the plane is smaller than the length to form a plurality of micro-nanopin LED pillars, and (D) separating the plurality of micro-nanopin LED pillars from the substrate It can be carried out including the step of making.

Referring to FIG. 7 , first, as step (A) of the present invention, a first conductive semiconductor layer 10 , a photoactive layer 20 and a second conductive semiconductor layer 30 are sequentially formed on a substrate (not shown). A step of preparing the stacked LED wafer 51 is performed.

Since the description of each layer provided in the LED wafer 51 is the same as that described above, a detailed description thereof will be omitted, and will be mainly described with reference to parts not described.

First, the thickness of the first conductive semiconductor 10 in the LED wafer 51 may be thicker than the thickness of the first conductive semiconductor layer 10 in the micro-nanopin LED device 100 described above. In addition, each layer in the LED wafer 51 may have a c-plane crystal structure.

The LED wafer 51 may have undergone a cleaning process, and the present invention is not particularly limited thereto since a cleaning process and a conventional wafer cleaning solution and cleaning process may be appropriately employed. The cleaning solution may be, for example, isopropyl alcohol, acetone and hydrochloric acid, but is not limited thereto.

Next, as the step (B) of the present invention, as shown in FIGS. 7 (b) and (c1) / (c2), the polarization inducing layer 40 on the second conductive semiconductor layer 30 of the LED wafer 51 performing the steps to form The polarization inducing layer 40 may be specifically patterned so that regions having different electrical polarities are adjacent to each other on the second conductive semiconductor layer of the LED wafer. More specifically, step (B) includes B-1) forming the first polarization inducing layer 41 on the second conductive semiconductor layer 30 as shown in FIG. 7(b), B-2) The first A step of etching the polarization inducing layer 41 in the thickness direction along a predetermined pattern and B-3) as shown in FIGS. 7(c1) and 7(c2), a second polarization-inducing layer 42 on the etched part It may be carried out including the step of forming a.

First, as a step B-1), a step of forming the first polarization inducing layer 41 on the second conductive semiconductor layer 30 is performed. The first polarization inducing layer 41 may be a conventional electrode layer formed on a semiconductor layer, and may be, for example, Cr, Ti, Ni, Au, ITO, etc., preferably ITO in terms of transparency. The first polarization inducing layer 41 may be formed through a conventional method of forming an electrode, and may be formed by, for example, deposition through sputtering. For example, when ITO is used, it may be deposited to a thickness of about 150 nm, and may be further subjected to a rapid thermal annealing process after the deposition process. Since it can be appropriately adjusted in consideration of the thickness and material of the layer 41, the present invention is not particularly limited thereto.

Next, as a step B-2), a step of etching the first polarization inducing layer 41 in a thickness direction according to a predetermined pattern is performed. This step is a step of preparing a point where the second polarization inducing layer 42 to be described later is to be formed, taking into account the area ratio and arrangement of the first polarization inducing layer 41 and the second polarization inducing layer 42 in the device. Thus, the pattern can be formed. For example, the pattern may be formed such that the first polarization-inducing layer 41 and the second polarization-inducing layer 42 are alternately arranged side by side, as can be seen in FIG. 7(d) . Since the pattern can be formed by appropriately applying a conventional photolithography method or a nanoimprinting method, a detailed description thereof will be omitted in the present invention.

The etching may be performed by employing an appropriate known etching method in consideration of the selected material of the first polarization inducing layer 41 . For example, when the first polarization inducing layer 41 is ITO, it may be etched through wet etching. At this time, the etched thickness may be etched up to the upper surface of the second conductive semiconductor layer 30 , that is, all of the ITO may be etched in the thickness direction, but is not limited thereto. Specifically, only a portion of the ITO is etched in the thickness direction, and the second polarization inducing layer 42 may be formed on the etched portion of the intaglio, in this case the first polarization inducing layer 41 and the second polarization inducing layer 42 which are ITO. ), it is pointed out that one end of the upper layer of the device may be formed with a stacked two-layer structure.

Next, as a step B-3), a step of forming the second polarization inducing layer 42 on the etched intaglio portion may be performed. The second polarization-inducing layer 42 is a material having a different electrical polarity from that of the selected first polarization-inducing layer 41, and can be used without limitation in the case of a material used in a conventional LED, and may be, for example, a metal or a semiconductor. , specifically nickel or chromium. As the method for forming these, a known method may be appropriately employed according to a material such as vapor deposition, and the present invention is not particularly limited thereto.

Next, in the step (C) of the present invention, each device has a plane having a length and width of nano or micro size, and the LED wafer 51 is formed in the thickness direction so that the thickness perpendicular to the plane is smaller than the length. Etching to form a plurality of micro-nanopin LED pillars 52 is performed.

Specifically, in step (C), 3-1) forming a mask pattern layer 61 on the upper surface of the polarization inducing layer 40 so that each element is a plane having a predetermined shape having a length and width of nano or micro size 7(d)), C-2) forming a plurality of micro-nanopin LED pillars 52 by etching the first conductive semiconductor layer 10 to a partial thickness in the thickness direction along the pattern ( 7(e)), C-3) forming an insulating film 62 to cover the exposed side of the micro-nanofin LED pillar 52 (FIG. 7(f)), C-4) adjacent The insulating film 62 formed on the first conductive semiconductor layer 10 so that the top surface (A in FIG. 7(f)) of the first conductive semiconductor layer 10 between the micro-nanopin LED pillars 52 is exposed. Removing a part (FIG. 7(g)), C-5) The first conductive semiconductor layer 10 is further added in the thickness direction through the exposed upper portion of the first conductive semiconductor layer (A in FIG. 7(g)) A step of etching to form a portion of the first conductive semiconductor layer (B in FIG. 7(h)), the side of which is exposed by a predetermined thickness, below the first conductive semiconductor layer of the micro-nanofin LED pillar on which the insulating film 62 is formed (FIG. 7(h)), C-6) etching the portion of the first conductive semiconductor layer with side surfaces exposed (FIG. 7(h) B) from both sides toward the center (FIG. 7(i)), and C -7) removing the mask pattern layer 61 disposed on the polarization inducing layer 40 and the insulating film 62 covering the side surfaces (FIG. 7(j)).

First, as step C-1), forming a mask pattern layer 61 on the upper surface of the polarization inducing layer 40 so that each device has a predetermined shape having a length and width of nano or micro size (FIG. 5(d)).

The mask pattern layer 61 is a layer patterned to have a desired planar shape of the implemented LED device, and may be formed of a known method and material used for etching an LED wafer. The mask pattern layer 61 may be, for example, a SiO ₂ hard mask pattern layer. Briefly describing a method of forming it, forming an unpatterned SiO ₂ hard mask layer on the polarization inducing layer 40, the Forming a metal layer on the SiO ₂ hard mask layer, forming a predetermined pattern on the metal _{layer, etching the metal layer and the SiO 2} hard mask layer along the pattern, and removing the metal layer. can be formed.

The mask layer is a layer from which the mask pattern layer 61 is derived. For example, SiO ₂ may be formed through deposition. The thickness of the mask layer may be formed to be 0.5 ~ 3㎛, for example, may be formed of 1.2㎛. In addition, the metal layer may be, for example, an aluminum layer, and the aluminum layer may be formed through deposition. The predetermined pattern formed on the formed metal layer is for realizing the pattern of the mask pattern layer, and may be a pattern formed by a conventional method. For example, the pattern may be formed through photolithography using a photosensitive material or may be a pattern formed through a known nanoimprinting method, laser interference lithography, electron beam lithography, or the like. Thereafter, the metal layer and the SiO ₂ hard mask layer are etched along the formed pattern. For example, the metal layer is an inductively coupled plasma (ICP), SiO ₂ hard mask layer or an imprinted polymer layer is RIE. It can be etched using a dry etching method such as (reactive ion etching).

Next, the etched SiO ₂ metal layer present on the hard mask layer, other photosensitive material layers, or a step of removing the remaining polymer layer according to the imprint method may be performed. The removal may be performed through a conventional wet etching or dry etching method depending on the material, and detailed description thereof will be omitted in the present invention.

FIG. 7(d) is _{a plan view in which a SiO 2} hard mask layer 61 is patterned on the polarization inducing layer 40, followed by a C-2) step along the pattern as shown in FIG. 7(e), the LED wafer 51 ) by etching the first conductive semiconductor layer 10 to a partial thickness in the thickness direction to form a plurality of micro-nanofin LED pillars 52 . The etching may be performed through a conventional dry etching method such as ICP.

After that, in step C-3), as shown in FIG. 7(f) , a step of forming an insulating film 62 to cover the exposed side surface of the micro-nanopin LED pillar 52 may be performed. The insulating film 62 coated on the side surface may be formed through vapor deposition, and the material thereof may be, for example, SiO ₂ , but is not limited thereto. The insulating film 62 functions as a side mask layer, and specifically, in the process of etching the first conductive semiconductor layer portion (B) to separate the micro-nano-fin LED pillar 52 as shown in FIG. 7(i). The micro-nanopin LED pillar 52 remains on the side and functions to prevent damage due to the etching process. The insulating film 62 may have a thickness of 100 to 600 nm, but is not limited thereto.

Next, as step C-4), as shown in FIG. 7(g), the upper surface of the first conductive semiconductor layer 10 (A in FIG. 7(g)) between the adjacent micro-nanopin LED pillars 52 is exposed. A step of removing a portion of the insulating film 62 formed on the first conductive semiconductor layer 10 may be performed. The removal of the insulating film 62 may be performed through an appropriate etching method in consideration of the material, and the _{insulating film 62 of SiO 2} may be removed through dry etching such as RIE.

Next, in step C-5), the first conductive semiconductor layer 10 is further etched in the thickness direction through the exposed upper portion of the first conductive semiconductor layer (A in FIG. 7G) as shown in FIG. 7(h). to form a portion of the first conductive semiconductor layer (B in FIG. 7(h)) with the side exposed by a predetermined thickness below the first conductive semiconductor layer of the micro-nanofin LED pillar on which the insulating film 62 is formed. carry out As described above, the exposed portion B of the first conductive semiconductor layer 10 is a portion on which side etching is performed in a direction parallel to the substrate in a step to be described later. The process of further etching the first conductive semiconductor layer 10 in the thickness direction may be performed by, for example, a dry etching method such as ICP.

Thereafter, in step C-6), as shown in FIG. 7(i), a step of side-etching the portion of the first conductive semiconductor layer (B of FIG. . The side etching may be performed through wet etching. For example, the wet etching may be performed at a temperature of 60 to 100° C. using a tetramethylammonium hydroxide (TMAH) solution.

Thereafter, after wet etching in the lateral direction is performed, in step C-7), as shown in FIG. 7( j ), the mask pattern layer 61 disposed on the polarization inducing layer 40 and the insulating film 62 covering the side surfaces can be performed to remove the Both the material of the mask pattern layer 61 and the insulating film 62 disposed thereon _{may be SiO 2} , and may be removed by wet etching. For example, the wet etching may be performed using a buffer oxide etchant (BOE).

According to an embodiment of the present invention, as the step (E) between the steps (C) and (D) described above, as shown in FIG. The step of forming may be further performed. The protective film 50 may be formed by, for example, deposition, and may have a thickness of 10 to 100 nm, for example 40 nm, and the material may be, for example, alumina. When using alumina, an ALD (atomic layer deposition) method may be used as an example of the deposition. In addition, in order to form the deposited protective film 50 only on the side surfaces of a plurality of micro-nanopin LED pillars, the protective film 50 positioned on the remaining portions except for the side surfaces is etched, for example, removed by dry etching through ICP. can be On the other hand, although FIG. 7(l) shows that the protective film 50 surrounds the entire side surface, the protective film 50 may not be formed on all or part of the remaining portions except for the photoactive layer on the side surface. make it clear

Next, as a step (D) according to the present invention, as shown in FIG. 7(m), a step of separating the plurality of micro-nanopin LED pillars 50 from the substrate is performed. The separation may be cut using a cutting mechanism or detachment using an adhesive film, and the present invention is not particularly limited thereto.

On the other hand, the micro-nanopin LED devices 100 and 101 are one surface in the thickness direction in which each layer is stacked on the two adjacent electrodes 211/212 and 213/214 of the lower electrode line 200 as shown in FIG. 2 . One surface of the device on the polarization inducing layer side may be in contact with the middle, and the first conductive semiconductor layer 10 opposite to the opposite surface of one surface of the device in contact with the lower electrode line 200 is in contact with the upper electrode line 300 . can do. In this case, due to the protrusion formed on one surface of the first conductive semiconductor layer 10 , the polarization inducing layer 40 may be disposed to contact the lower electrode line 200 with a higher probability.

In addition, in the lower electrode line 200, the micro-nanopin LED element is arranged on the unit electrode area, that is, on the lower electrode line 200, and then the upper electrode line 300 is arranged on the micro-nanofin LED element to be independent. The area of the region capable of being driven by the polarizer is preferably 1 μm ² to 100 cm ² , and more preferably 10 μm ² to 100 mm ² , but the area of the unit electrode is not limited to the above area. .

According to an embodiment of the present invention, as shown in FIG. 2 , as shown in FIG. 2 , the micro-nanopin LED elements 100 and 101 are in contact with the lower electrode line 200 in order to reduce the contact resistance between them. One micro-nanopin LED device (100, 101) may further include a conductive metal layer (500) connecting between the first polarization inducing layer (40) and the lower electrode line (200). The conductive metal layer 500 may be a conductive metal layer such as silver, aluminum, or gold, and may be formed, for example, to have a thickness of about 10 nm.

In addition, the self-aligned micro-nanopin on the lower electrode line 200 is insulated in the space between the first conductive semiconductor layer 10 and the upper electrode line 300 corresponding to the upper surfaces of the LED devices 100 and 101 and in electrical contact. A layer 600 may be further included. The insulating layer 600 prevents electrical contact between the two electrode lines 200 and 300 facing vertically, and performs a function of more easily implementing the upper electrode line 300 . The insulating layer 600 may be used without limitation in the case of a material performing a normal insulating function. Preferably, it may be a transparent material, and for example, SiO ₂ , SiN _x, Al ₂ O, HfO ₂ , ZrO _{2 It} may be a layer formed of an insulating material.

The micro-nanopin LED electrode assembly 1000 according to an embodiment of the present invention described above is (1) a lower electrode line 200 including a plurality of lower electrodes 211 , 212 , 213 , 214 spaced in a horizontal direction at a predetermined interval. A first conductive semiconductor layer 10 and a photoactive layer 20 in the thickness direction as a rod-shaped device having a plane having a length and width of nano or micro size, and having a thickness perpendicular to the plane smaller than the length. , the second conductive semiconductor layer 30 and the polarization inducing layer 40 are sequentially stacked micro-injecting a solution containing a plurality of nano-fin LED devices 100 and 101, (2) the lower electrode line 200 ) by applying an assembly voltage to the micro-in the solution at least two lower electrodes 211/212,213/214 to which the first conductive semiconductor layer 10 or polarization inducing layer 40 of the micro-nanopin LED devices 100 and 101 are adjacent. ), and (3) self-aligning a plurality of micro-nano-fin LED devices 100 and 101 to form an upper electrode line 300 on the LED device.

First, as step (1), a plurality of micro-nanopin LED devices 100 and 101 on a lower electrode line 200 including a plurality of lower electrodes 211 , 212 , 213 , 214 spaced apart in the horizontal direction at a predetermined interval. Steps to insert

A solution containing a plurality of micro-nanopin LED devices 100 and 101 is a solvent that functions to disperse a plurality of micro-nanopin LED devices 100 and 101 and the device and move the device on the electrode of the lower electrode line. may include In this case, the solution may be in the form of ink or paste, and the solution may be injected onto the lower electrode line 200 using an inkjet. On the other hand, although step (1) has been described as a case in which the device is put into a solution phase mixed with a solvent, a case in which the device is first put on the lower electrode line and then the solvent is added and consequently the solution is also included.

The solvent may be any one or more selected from the group consisting of acetone, water, alcohol and toluene, and more preferably acetone. However, the type of solvent is not limited to the above description, and any solvent that can evaporate well without physically and chemically affecting the micro-nanopin LED device may be used without limitation. Preferably, the micro-nanopin LED device may be added in an amount of 0.001 to 100 parts by weight based on 100 parts by weight of the solvent. If the amount is less than 0.001 parts by weight, the number of micro-nanopin LED elements connected to the lower electrode may be small, making it difficult for the micro-nanopin LED electrode assembly to function normally. To overcome this, the solution must be added dropwise several times. There may be a problem, and when it exceeds 100 parts by weight, there may be a problem that the alignment of individual micro-nanopin LED devices may be disturbed.

Next, as the step (2), the first conductive semiconductor layer 10 or the polarization inducing layer 40 of the micro-nanopin LED devices 100 and 101 in the solution by applying an assembly voltage to the lower electrode line 200 . A step of self-aligning the at least two adjacent lower electrodes 211/212 and 213/214 to be in contact with each other is performed.

In step (2), charges are induced in the micro-nanopin LED device by induction of an electric field formed by the potential difference between the lower electrodes 211/212 and 213/214 adjacent to the micro-nanopin LED device, and the micro-nanopin LED device is induced. In the longitudinal direction of the LED device, it is a step of inducing different charges toward both ends around the center of the device in the longitudinal direction to self-align the LED device. , or power may be applied to form a potential difference between a first group of two or more adjacent lower electrodes and a second group of two or more adjacent lower electrodes adjacent to the first group. At this time, the intensity, type, etc. of the applied assembly voltage are inserted into Korean Patent Application Nos. 10-2013-0080412, 10-2016-0092737, 10-2016-0073572, etc. by the inventor of the present invention as reference. can be

Next, as step (3) of the present invention, (3) a step of forming the upper electrode line 300 on a plurality of self-aligned micro-nanopin LED devices 100 and 101 is performed. The upper electrode line 300 may be implemented by depositing an electrode material after patterning the electrode line using known photolithography or by dry and/or wet etching after depositing the electrode material. At this time, since the electrode material is the same as the description of the electrode material of the lower electrode line described above, it will be omitted below.

On the other hand, as a step (4) between steps (2) and (3) described above, each of the micro-nanopin LED devices 100 and 101 in contact with the lower electrode line 200 includes the polarization inducing layer 40 and the lower part. On the lower electrode line 200 by not covering the upper surfaces of the self-aligned micro-nanopin LED devices 100 and 101 as a step and (5) step of forming the metal layer 500 for current connecting the electrode line 200 . The method may further include forming the insulating layer 600 .

The conduction-only metal layer 500 may be manufactured by patterning a line on which the current-conducting metal layer is to be deposited by applying a photolithography process using a photosensitive material and then depositing the current-conducting metal layer, or by etching the deposited metal layer after patterning. have. The process may be performed by appropriately employing a known method, and Korean Patent Application No. 10-2016-0181410 by the inventor of the present invention may be incorporated as a reference.

After forming the conductive metal layer 500, the self-aligned micro-nanopin LED devices 100 and 101 do not cover the upper surface of the upper surface to form the insulating layer 600 on the lower electrode line 200 may be performed. . The insulating layer 600 may be formed through the deposition of a known insulating material, for example, an _{insulating material such as SiO 2} , SiN _{x is} deposited through a PECVD method, or an insulating material such as AlN or GaN is used by the MOCVD method. Alternatively, an insulating material such as Al ₂ O, HfO ₂ , or ZrO ₂ may be deposited through an ALD method. On the other hand, the insulating layer 600 may be formed to a level that does not cover the upper surfaces of the self-aligned micro-nanofin LED devices 100 and 101. To this end, an insulating layer is formed through deposition to a thickness that does not cover the upper surfaces. Alternatively, after deposition to cover the upper surface, dry etching may be performed until the upper surface of the device is exposed.

As described above, the LED electrode assembly using the micro-nanopin LED device can be used without limitation in various electrical and electronic components, electrical and electronic devices using LEDs, for example, lighting, displays, medical devices, beauty devices, and the like.

Although one embodiment of the present invention has been described above, the spirit of the present invention is not limited to the embodiments presented herein, and those skilled in the art who understand the spirit of the present invention can add components within the scope of the same spirit. , changes, deletions, additions, etc. may easily suggest other embodiments, but this will also fall within the scope of the present invention.

100,101: micro-nanopin LED element 10: first conductive semiconductor layer
20: photoactive layer 20: second conductive semiconductor layer
40: polarization inducing layer 50: protective film
211,212,213,214: lower electrode 200: lower electrode line
301,302: upper electrode 300: upper electrode line

Claims (14)

(1) On a lower electrode line including a plurality of lower electrodes spaced apart in the horizontal direction at a predetermined interval, a plane having a length and width of nano or micro size is provided, and the thickness perpendicular to the plane is greater than the length Injecting a solution containing a plurality of micro-nanopin LED devices in which a first conductive semiconductor layer, a photoactive layer, a second conductive semiconductor layer, and a polarization inducing layer are sequentially stacked in a thickness direction as a small rod-type device;
(2) applying an assembly voltage to the lower electrode line to self-align the first conductive semiconductor layer or the polarization inducing layer of the micro-nanopin LED device in the solution so that it contacts at least two adjacent lower electrodes; and
(3) forming an upper electrode line on a plurality of self-aligned micro-nanopin LED devices; micro-nanopin LED device electrode assembly manufacturing method comprising a. According to claim 1,
The predetermined interval is a micro-nano pin LED device electrode assembly manufacturing method, characterized in that smaller than the length of the micro-nano pin LED device. The method according to claim 1, wherein between steps (2) and (3)
(4) forming a conductive metal layer connecting between the at least two lower electrodes and the side of the first conductive semiconductor layer or polarization inducing layer of each micro-nano pin LED device in contact with the at least two lower electrodes; and
(5) forming an insulating layer on the lower electrode line by not covering the upper surface of the self-aligned plurality of micro-nano pin LED devices; Micro-nano pin LED device electrode assembly manufacturing method further comprising a . According to claim 1,
The micro-nano-fin LED device has a length of 1000 to 10000 nm, and a thickness of 100 to 3000 nm, a method of manufacturing a micro-nano-fin LED device electrode assembly. According to claim 1,
The micro-nano-pin LED device has a width greater than or equal to the thickness, characterized in that the micro-nano-pin LED device electrode assembly manufacturing method. According to claim 1,
The micro-nano-fin LED device electrode assembly manufacturing method, characterized in that the ratio of the length to the thickness of the micro-nano-fin LED device is 3:1 or more. According to claim 1,
The micro-nano-fin LED device is a micro-nano-fin LED device electrode assembly manufacturing method, characterized in that it further comprises a protective film formed on the side of the device to cover the exposed surface of the photoactive layer. According to claim 1,
The polarization inducing layer consists of a first polarization inducing layer and a second polarization inducing layer disposed adjacent to each other in the longitudinal direction of the device, and the first polarization inducing layer and the second polarization inducing layer have different electrical polarities. Micro-nanopin LED electrode assembly manufacturing method. 9. The method of claim 8,
The first polarization inducing layer is ITO, and the second polarization inducing layer is a micro-nano pin LED electrode assembly manufacturing method, characterized in that it is a metal or a semiconductor. a lower electrode line including a plurality of lower electrodes spaced apart in a horizontal direction at predetermined intervals;
A rod-shaped device having a nano or micro-sized length and width, and having a thickness perpendicular to the plane smaller than the length, in the thickness direction a first conductive semiconductor layer, a photoactive layer, a second conductive semiconductor layer, and polarization induction a plurality of micro-nanopin LED devices in which the layers are sequentially stacked and the first conductive semiconductor layer or the polarization inducing layer is in contact with at least two adjacent lower electrodes; and
A micro-nano-pin LED device electrode assembly comprising a; an upper electrode line disposed on the plurality of micro-nano-pin LED devices. 11. The method of claim 10,
One of the first conductive semiconductor layer and the second conductive semiconductor layer includes a p-type GaN semiconductor layer, and the other includes an n-type GaN semiconductor layer,
The p-type GaN semiconductor layer has a thickness of 10 to 350 nm, the n-type GaN semiconductor layer has a thickness of 100 to 3000 nm, and the photoactive layer has a thickness of 30 to 200 nm. Micro-nanofin LED device electrode assembly. 11. The method of claim 10,
The micro-nanopin LED device electrode assembly, characterized in that the lower surface of the first conductive semiconductor layer of the micro-nanopin LED device has a protrusion having a predetermined width and thickness formed in the longitudinal direction of the device. 13. The method of claim 12,
The width of the protrusion is micro-nanopin LED device electrode assembly, characterized in that it is formed to have a length of 50% or less compared to the width of the micro-nanopin LED device. 11. The method of claim 10,
The micro-nanopin LED device has a light emitting area that exceeds twice the longitudinal cross-sectional area of the micro-nanopin LED device.

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