KR20210134523A - Semiconductor devices - Google Patents

Abstract

A semiconductor device according to an embodiment of the present invention may include: a substrate having a first region and a second region; and a first string selection gate electrode and a second string select gate electrode that are disposed at the same height level on a stacked structure including interlayer insulating layers and gate electrodes that are alternately and repeatedly stacked on the substrate, wherein the gate electrodes include a lower gate electrode, a first lower selection gate electrode and a second lower selection gate electrode disposed at the same height level on the lower gate electrode, memory cell gate electrodes stacked on the first and second lower selection gate electrodes to be spaced apart from each other in a first direction perpendicular to the upper surface of the substrate, and the memory cell gate electrodes; main separation structures penetrating the gate electrodes, extended in a second direction perpendicular to the first direction, and spaced apart from each other in the first direction and a third direction perpendicular to the second direction, in the first region and the second region; an auxiliary separation structure penetrating the gate electrodes between the main isolation structures and extended in the second direction in the second region; a first lower isolation structure between the first lower selection gate electrode and the second lower selection gate electrode in the first region; and vertical memory structures penetrating the stack structure in the first region. The interlayer insulating layers may include a first material. The first lower separation structure includes a second material different from the first material. The auxiliary separation structure may include a portion passing between the first and second lower selection gate electrodes. An objective of the present invention is to provide the semiconductor device with improved electrical characteristics.

Description

semiconductor device

The present invention relates to a semiconductor device.

In an electronic system requiring data storage, a semiconductor device capable of storing high-capacity data is required. Accordingly, a method for increasing the data storage capacity of a semiconductor device is being studied. For example, as a method for increasing the data storage capacity of a semiconductor device, a semiconductor device including memory cells arranged three-dimensionally instead of two-dimensionally arranged memory cells has been proposed.

One of the technical problems to be achieved by the technical idea of the present invention is to provide a semiconductor device with improved electrical characteristics.

A semiconductor device according to example embodiments may include a substrate having a first region and a second region; A stacked structure including interlayer insulating layers and gate electrodes alternately and repeatedly stacked on the substrate, wherein the gate electrodes are a lower gate electrode, a first lower select gate electrode and a second lower select gate electrode disposed at the same height level on the lower gate electrode a lower selection gate electrode, memory cell gate electrodes spaced apart from each other and stacked on the first and second lower selection gate electrodes in a first direction perpendicular to the top surface of the substrate, and the same on the memory cell gate electrodes a first string select gate electrode and a second string select gate electrode disposed at a height level; In the first region and the second region, penetrating the gate electrodes, extending in a second direction perpendicular to the first direction, and spaced apart from each other along the first direction and a third direction perpendicular to the second direction main separation structures disposed; an auxiliary isolation structure extending in the second direction through the gate electrodes between the main isolation structures in the second region; a first lower isolation structure on the first region between the first lower select gate electrode and the second lower select gate electrode; and vertical memory structures penetrating the stack structure on the first region. The interlayer insulating layers may include a first material, the first lower isolation structure may include a second material different from the first material, and the auxiliary isolation structure may be disposed between the first and second lower selection gate electrodes. It may include passing parts.

A semiconductor device according to example embodiments may include a substrate having a first region and a second region; A stacked structure including interlayer insulating layers and gate electrodes alternately and repeatedly stacked on the substrate, a first lower selection gate electrode and a second lower selection gate electrode disposed at the same height level, the first and Memory cell gate electrodes stacked apart from each other in a first direction perpendicular to the top surface of the substrate on the second lower selection gate electrodes, and a first string selection disposed at the same height level on the memory cell gate electrodes a gate electrode and a second string select gate electrode; an auxiliary isolation structure penetrating the gate electrodes and extending in a second direction perpendicular to the first direction on the second region; a first lower isolation structure on the first region between the first lower select gate electrode and the second lower select gate electrode; a second lower isolation structure disposed in the second region, between the first lower selection gate electrode and the second lower selection gate electrode, and between the first lower isolation structure and the auxiliary isolation structure; and vertical memory structures penetrating the stack structure on the first region. In the second region, the gate electrodes include gate pads arranged in a stepped shape, the interlayer insulating layers include a first material, and the first lower isolation structure includes a second material different from the first material. In addition, the auxiliary isolation structure may include a portion passing between the first and second lower selection gate electrodes.

By separating the lower select gate without cutting the lower select gate, a semiconductor device having improved electrical characteristics may be provided. By splitting the lower selection line into units of the string selection line, deterioration of operating characteristics and performance of a cell may be suppressed.

The various and beneficial advantages and effects of the present invention are not limited to the above, and will be more easily understood in the course of describing specific embodiments of the present invention.

1A and 1B are plan views illustrating semiconductor devices according to example embodiments.
2A to 2D are cross-sectional views illustrating semiconductor devices according to example embodiments.
3 is an enlarged view illustrating a semiconductor device according to example embodiments.
4A to 7D are cross-sectional views illustrating a manufacturing process of a semiconductor device according to example embodiments.
8 is a diagram schematically illustrating a data storage system including a semiconductor device according to example embodiments.
9 is a perspective view schematically illustrating a data storage system including a semiconductor device according to an exemplary embodiment.
10 is a cross-sectional view schematically illustrating a semiconductor package according to an exemplary embodiment.

Hereinafter, terms such as "upper", "middle" and "lower" are replaced with other terms, for example, "first", "second" and "third" to describe the elements of the specification. may also be used to Terms such as “first”, “second” and “third” may be used to describe various components, but the components are not limited by the terms, and “first component” means “ second component”.

An example of a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1A, 1B, 2A, 2B, 2C, 2D, and 3 .

1A is a plan view illustrating an example of a semiconductor device 1 according to an embodiment of the present invention, and FIG. 1B is a plan view illustrating an example of the semiconductor device 1 according to an embodiment of the present invention with lower selection gate electrodes It is a floor plan shown at the level. 2A to 2D are cross-sectional views illustrating cross-sections taken along lines II', II-II', III-III' and IV-IV' of FIG. 1, respectively. 3 is an enlarged cross-sectional view of an area indicated by 'A' of FIG. 2A.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1A to 3 , a semiconductor device 1 according to an exemplary embodiment includes a substrate 3 including a first region R1 and a second region R2, and a peripheral circuit structure on the substrate 3 ( 6), the plate pattern 21 on the peripheral circuit structure 6 , the stacked structure 30 disposed on the plate pattern 21 , a vertical memory penetrating at least the stacked structure 30 and contacting the plate pattern 21 . The structures 50m and at least the vertical dummy structures 50d penetrating through the stacked structure 30 and contacting the plate pattern 21 may be included.

The substrate 3 may include a first region R1 and a second region R2 . The first region R1 may be a memory cell array region, and the second region R2 may be a step region, an extension region, or a contact region. The substrate 3 may be a semiconductor substrate including a material having semiconductor properties (e.g., silicon). For example, the substrate 3 may be a silicon substrate.

A peripheral circuit structure 6 may be disposed on the substrate 3 . The peripheral circuit structure 6 includes a peripheral circuit 12 on the substrate 3 , a peripheral wiring structure 15 electrically connected to the peripheral circuit 12 on the substrate 3 , and a peripheral circuit 12 on the substrate 3 . ) and a lower insulating structure 18 covering the peripheral wiring structure 15 .

The peripheral circuit 12 includes source/drain regions 12b disposed in an active region 9a defined by an isolation region 9s on the substrate 3, and an active region between the source/drain regions 12b. a peripheral transistor comprising a peripheral gate dielectric layer 12c and a peripheral gate electrode 12a sequentially disposed on 9a, and a peripheral spacer layer 12d disposed on both sidewalls of the peripheral gate electrode 12a; can

The peripheral wiring structure 15 may include peripheral wiring lines 151 and peripheral contact plugs 15v electrically connecting the peripheral wiring lines.

The lower insulating structure 18 may be disposed on the substrate 3 to cover the peripheral circuit 12 and the peripheral wiring structure 15 . The lower insulating structure 18 may include one insulating layer or a plurality of insulating layers, and may include, for example, one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a low dielectric layer.

The plate pattern 21 may be disposed on the peripheral circuit structure 6 . The plate pattern 21 may include a doped silicon layer, for example, a doped polysilicon layer. At least a portion of the plate pattern 21 may be a common source in the flash memory device.

The plate pattern 21 may include a lower layer 21a, an intermediate layer 21b disposed on the lower layer 21a, and an upper layer 21c disposed on the intermediate layer 21b. The lower layer 21a, the middle layer 21b, and the upper layer 21c may include a doped polysilicon layer, for example, a polysilicon layer having an N-type conductivity. The lower layer 21a may have a thickness greater than that of the middle layer 21b and the upper layer 21c. A region formed of N-type polysilicon in the plate pattern 21 may be a common source of the flash memory device.

The stacked structure 30 may be disposed on the plate pattern 21 . The multilayer structure 30 may be disposed on the first region R1 and may extend from the first region R1 onto the second region R2 .

The stacked structure 30 may include gate electrodes 39 and interlayer insulating layers 33 that are alternately and repeatedly stacked in a vertical direction (Z) perpendicular to the upper surface of the substrate 3 . The stacked structure 30 may further include a dielectric layer ( 41 of FIG. 3 ) covering an upper surface and a lower surface of each of the gate electrodes 39 , and covering some side surfaces of each of the gate electrodes 39 .

In the second region R2 , the gate electrodes 39 may include gate pads arranged in a step shape.

The gate electrodes 39 may include a conductive material. For example, the gate electrodes 39 include at least one of doped polysilicon, metal nitride (eg, TiN, etc.), metal-semiconductor compound (eg, TiSi, NiSi, etc.), and metal (eg, W, etc.). can do. The dielectric layer 41 may include silicon oxide or a high dielectric (e.g., AlO, etc.). The interlayer insulating layers 33 may include silicon oxide. The plurality of interlayer insulating layers 33 may have different thicknesses. In an exemplary embodiment, the interlayer insulating layer 33 disposed on the lower selection gate electrode 39L2 may have a greater thickness than other interlayer insulating layers.

The gate electrodes 39 may include a plurality of lower gate electrodes 39L and a plurality of upper gate electrodes 39U disposed on the plurality of lower gate electrodes 39L. When the semiconductor device 1 is a flash memory device, at least one of the plurality of lower gate electrodes 39L may be a lower selection gate electrode. At least one of the plurality of upper gate electrodes 39U may be a string selection gate electrode. A plurality of gate electrodes between the lower selection gate electrode and the string selection gate electrode may be memory cell gate electrodes, for example, word lines.

In an illustrative example, referring to FIGS. 2A to 2D , the lowermost gate electrode 39L1 of the plurality of lower gate electrodes 39L is a lower erase control gate electrode, and is disposed on the upper end adjacent to the lowermost gate electrode 39L1 . The electrode 39L2 may be lower selection gate electrodes. Among the plurality of upper gate electrodes 39U, the uppermost gate electrode 39U5 and the lower electrode 39U4 adjacent thereto may be string selection gate electrodes. The electrodes 39L3, 39L4, 39L5, 39U1, 39U2, and 39U3 disposed between the lower select gate electrodes and the string select gate electrodes may be memory cell gate electrodes, for example, word lines. The number and stacking order of the lower erase gate electrode, the lower selection gate electrodes, the memory cell gate electrode, and the string selection gate electrodes are not limited thereto, and may be changed according to the total number of stacked gate electrodes.

The lower selection gate electrodes 39L2 may be formed in plurality to be separated from each other. In an exemplary embodiment, the lower selection gate electrodes 39L2 may include first to fourth lower selection gate electrodes G1 , G2 , G3 , and G4 disposed at the same height level.

The string select gate electrodes 39U4 and 39U5 include a plurality of string select gate electrodes separated from each other at the same height level, for example, first to fourth string select gate electrodes S1 , S2 , S3 , and S4 . can do.

The separation structure of the first to fourth lower selection gate electrodes G1, G2, G3, and G4 and the first to fourth string selection gate electrodes S1, S2, S3, and S4 will be described with reference to separation structures to be described later. to explain

The separation structure may be disposed to penetrate at least a portion of the stacked structure 30 . The separation structures may include primary separation structures 42M, first and second auxiliary separation structures 42S1 , 42S2 , first and second lower separation structures 48C and 48E and an upper separation structure 45 . can In one example, each of the main isolation structures 42M and the first and second auxiliary isolation structures 42S1 and 42S2 may include an insulating material. In another example, each of the main isolation structures 42M and the first and second auxiliary isolation structures 42S1 and 42S2 may include a conductive pattern and an insulating spacer on a side surface of the conductive pattern.

The main isolation structures 42M may be disposed to pass through the gate electrodes 39 in the first region R1 and the second region R2 . There may be a plurality of main separation structures 42M, and may be disposed parallel to each other. Each of the main isolation structures 42M may extend along a first horizontal direction X parallel to the upper surface of the substrate 3 . The first horizontal direction X may be a direction from the first area R1 to the second area R2 . The main isolation structures 42M may penetrate the stack structure 30 , the upper layer 21c , and the middle layer 21b to contact the lower layer 21a . The main isolation structures 42M may extend in the vertical direction Z to pass through the stack structure 30 , and may separate the gate electrodes 39 in the second horizontal direction Y. The second horizontal direction Y may be parallel to the upper surface of the substrate 3 and may be perpendicular to the first horizontal direction X. The plurality of main separation structures 42M may be disposed to be spaced apart from each other in the second horizontal direction Y.

The first and second auxiliary isolation structures 42S1 and 42S2 may be disposed between the main isolation structures 42M to pass through the gate electrodes 39 .

The second auxiliary isolation structure 42S may extend from the first area R1 into the second area R2 in the first horizontal direction X between the main isolation structures 42M. The second auxiliary separation structure 42S2 may include portions spaced apart from each other in the first horizontal direction X in the second region R2 .

In the semiconductor device 1 according to an exemplary embodiment, a third lower isolation structure 48M is disposed between portions of the second auxiliary isolation structure 42S2 spaced apart from each other at the same height level as the lower selection gate electrodes 39L2. may further include. The third lower isolation structure 48M may selectively separate the lower selection gate electrodes 39L2. The third lower isolation structure 48M may include the same material as the interlayer insulating layers 33 .

As shown in FIG. 1B , at the same height level as the lower selection gate electrodes 39L2 , the second auxiliary isolation structure 42S2 and the third lower isolation structure 48M are formed in a fourth direction along the second horizontal direction Y, respectively. It may have a width d4 and a fifth width d5. The fourth width d4 and the fifth width d5 may be different from each other, for example, the fourth width d4 may be smaller than the fifth width d5.

The first auxiliary separation structures 42S1 may be disposed between the second auxiliary separation structures 42S2 and the main separation structures 42M. The first auxiliary separation structure 42S1 may be disposed in the second region R2 and may extend in the first horizontal direction X. The first and second auxiliary separation structures 42S1 and 42S2 may extend in the vertical direction Z to pass through the stack structure 30 . The first and second lower isolation structures 48C and 48E are disposed at substantially the same height level as the lower select gate electrode 39L2 among the gate electrodes 39 to separate the lower select gate electrodes 39L2. can

The first lower isolation structure 48C may extend in the first horizontal direction X from the first region R1 to separate the lower selection gate electrodes 39L2 . For example, the first lower isolation structure 48C may extend in the first horizontal direction (X) between the lower selection gate electrodes 39L2 . The first lower isolation structure 48C may include a material different from that of the interlayer insulating layer 33 . For example, the first lower isolation structure 48C may include silicon nitride, and the interlayer insulating layer 33 may include silicon oxide.

The second lower isolation structure 48E may be disposed at a boundary between the first region R1 and the second region R2 or within the second region R2 . The second lower isolation structure 48E may be disposed between the first lower isolation structure 48C and the first auxiliary isolation structure 42S1 . In the plan view of FIG. 1B , one side of the second lower separation structure 48E is in contact with one side of the first lower separation structure 48C, and the other side of the second lower separation structure 48E is the first auxiliary separation structure. It may be in contact with one side of (42S1).

The second lower isolation structure 48E may include a material different from that of the first lower isolation structure 48C. In an illustrative example, the first lower isolation structure 48C may include silicon nitride, and the second lower isolation structure 48E may include silicon oxide. In an illustrative example, the second lower isolation structure 48E may be integrally formed with the adjacent interlayer insulating layer 33 disposed thereon, and may include the same material as the interlayer insulating layer 33 .

At an upper portion of the second lower isolation structure 48E, at least a portion of the interlayer insulating layer 33 and the gate electrode 39 may be recessed toward the center of the second lower isolation structure 48E. As they move away from the second lower isolation structure 48E, the interlayer insulating layers 33 and the gate electrodes 39 may have a depression in which the curvature is relieved or may not have a depression. In an illustrative example, according to a process of forming the second lower isolation structure 48E, a depression may not be formed, and the interlayer insulating layer 33 on the second lower isolation structure 48E may have a flat top surface.

The first and second lower isolation structures 48C and 48E, the third lower isolation structure 48M and the lower select gate electrodes 39L2 are formed on the lowermost gate electrode 39L1, for example, the lower erase control gate electrode. can be placed.

Referring to FIG. 1B , each of the first lower isolation structure 48C, the second lower isolation structure 48E, and the third main isolation structure 42M3 has a first width d1 in the second horizontal direction Y. , a second width d2 and a third width d3. The first to third widths d1, d2, and d3 may have different sizes. In an illustrative example, the second width d2 may be greater than the third width d3 , and the third width d3 may be greater than the first width d1 .

The upper isolation structure 45 may separate the string selection gate electrodes 39U4 and 39U5 from among the plurality of gate electrodes 39 of the stacked structure 30 . The upper separation structure 45 may be disposed at a position spaced apart from the first lower separation structure 48C and the second lower separation structure 48E in the vertical direction (Z). The upper isolation structure 45 may overlap the first lower isolation structure 48C and the second lower isolation structure 48E. The upper isolation structure 45 may separate the string selection gate electrodes 39U4 and 39U5 in a portion of the first region R1 and the second region R2 . Referring to FIG. 1A , one side of the upper separation structure 45 may contact one side of the first auxiliary separation structure 42S1 .

A plurality of gate electrodes 39 may be separated by separation structures.

In an exemplary embodiment, the lower selection gate electrodes 39L2 may include first to fourth lower selection gate electrodes G1 , G2 , G3 , and G4 separated along the second horizontal direction Y .

Between the first lower selection gate electrode G1 and the second lower selection gate electrode G2 and between the third lower selection gate electrode G3 and the fourth lower selection gate electrode G4, a first lower isolation structure ( 48C), the second lower separation structure 48E, and the first auxiliary separation structure 42S1 may be continuously disposed along the first horizontal direction X. The first lower isolation structure 48C may be disposed at substantially the same level as the lower selection gate electrode 39L2 in the first region R1 to selectively separate the lower selection gate electrode 39L2 . The second lower isolation structure 48E may be disposed at substantially the same level as the lower selection gate electrode 39L2 in the second region R2 to selectively separate the lower selection gate electrode 39L2. The first auxiliary isolation structure 42S1 is disposed to extend in the vertical direction Z from the second region R2 to separate the gate electrodes 39 including the lower selection gate electrode 39L2 .

A second auxiliary isolation structure 42S2 and a third lower isolation structure 48M3 may be disposed between the second lower selection gate electrode G2 and the third lower selection gate electrode G3 . The second auxiliary separation structure 42S extends from the first region R1 in the first horizontal direction X into the second region R2, and in the second region R2 in the first horizontal direction X may be disposed to be spaced apart from each other along the The second auxiliary isolation structure 42S2 is disposed to extend in the vertical direction Z in the first and second regions R1 and R2 to separate the gate electrodes 39 including the lower selection gate electrode 39L2. can do. The third lower isolation structure 48M3 is disposed at substantially the same height level as the lower select gate electrode 39L2 between the spaced apart regions of the second auxiliary isolation structure 42S to selectively select the lower select gate electrode 39L2. can be separated.

In an exemplary embodiment, the string selection gate electrodes 39U4 and 39U5 may include first to fourth string selection gate electrodes S1 , S2 , S3 , and S4 separated along the second horizontal direction Y, respectively. can

An upper isolation structure 45 is provided between the first string selection gate electrode S1 and the second string selection gate electrode S2 and between the third string selection gate electrode S3 and the fourth string selection gate electrode S4 . And the first auxiliary separation structure 42S1 may be continuously disposed along the first horizontal direction (X). The upper isolation structure 45 extends in the first horizontal direction X from the first region R1 to a portion of the second region R2, and is vertical to at least separate the string selection gate electrodes 39U4 and 39U5. It may extend in the direction Z. The first auxiliary isolation structure 42S1 may be disposed to extend in the vertical direction Z from the second region R2 to separate the gate electrodes 39 including the string selection gate electrodes 39U4 and 39U5 . .

A second auxiliary isolation structure 42S2 may be disposed between the second string selection gate electrode S2 and the third lower selection gate electrode G3 . The second auxiliary separation structure 42S extends from the first region R1 in the first horizontal direction X into the second region R2, and in the second region R2 in the first horizontal direction X may be disposed to be spaced apart from each other along the The second auxiliary isolation structure 42S2 is disposed to extend in the vertical direction Z in the first and second regions R1 and R2, and includes the gate electrodes 39 including the string selection gate electrodes 39U4 and 39U5. ) can be separated.

In an exemplary embodiment, the number of string select gate electrodes 39U4 and 39U5 positioned at the same height level may be the same as the number of lower select gate electrodes 39L2 positioned at the same height level. By disposing the lower select gate electrodes in the same number as the string select gate electrodes, one lower select gate electrode may control one string select gate electrode. Thereby, it is possible to suppress deterioration of the operating characteristics and performance of the cell. 1A and 1B , each of the string select gate electrodes 39U4 and 39U5 and the lower select gate electrodes 39L2 is divided into four electrodes. However, the number of separated electrodes is limited thereto. doesn't happen

The vertical memory structures 50m and the vertical dummy structures 50d may be disposed to pass through the stack structure 30 in the first region R1 .

Referring to FIG. 3 , the vertical memory structure 50m includes an insulating core region 56m, a pad pattern 58m on the insulating core region 56m, a side surface of the insulating core region 56m, and a side surface of the pad pattern 58m. a dielectric structure 52m and a channel layer 54m between the insulative core region 56m and the dielectric structure 52m and between the insulative core region 56m and the pad pattern 58m.

The pad pattern 58m may be disposed at a higher level than the uppermost gate electrode 39U5 of the gate electrodes 39 .

The pad pattern 58m may include doped silicon, for example, polysilicon having an N-type conductivity. The channel layer 54m may contact the pad pattern 58m. The channel layer 54m may be formed of a silicon layer. The dielectric structure 52m may include a first dielectric layer 52a, an information storage layer 52d, and a second dielectric layer 52b. The information storage layer 52d may be interposed between the first dielectric layer 52a and the second dielectric layer 52b. The first dielectric layer 52a may include silicon oxide and/or a high dielectric. The information storage layer 52d may include a material capable of storing information in a memory device, for example, silicon nitride capable of trapping a charge. The second dielectric layer 52b may be a tunnel dielectric layer in contact with the channel layer 54m. The second dielectric layer 52b may be silicon oxide or silicon oxide doped with impurities.

The gate electrodes 39 may include a plurality of lower gate electrodes 39L and a plurality of upper gate electrodes 39U disposed on the plurality of lower gate electrodes 39l.

The vertical memory structure 50m includes a lower vertical portion 50L penetrating through the plurality of lower gate electrodes 39L, an upper vertical portion 50U penetrating the plurality of upper gate electrodes 39U, and a lower vertical portion ( 50L) and a width change portion 50V between the upper vertical portion 50U.

The width-variable portion 50V may be disposed between an uppermost lower gate electrode of the plurality of lower gate electrodes 39L and a lowermost upper gate electrode of the plurality of upper gate electrodes 39u.

The width-variable portion 50V may have a side surface that extends while being bent from a side surface of the lower vertical portion 50L and a side surface of the upper vertical portion 50U. The width-variable portion 50V may have a lateral inclination different from that of the lower vertical portion 50L and the lateral inclination of the upper vertical portion 50U. Accordingly, the width change portion 50V may be referred to as a slope change portion or a bent portion.

The interlayer insulating layer 33 positioned between the uppermost lower gate electrode of the plurality of lower gate electrodes 39L and the lowermost upper gate electrode of the plurality of upper gate electrodes 39U includes the first layer 33_1 and A second layer 33_2 on the first layer 33_1 may be included.

In the plate pattern 21 , the intermediate layer 21b penetrates the dielectric structure 52m and may contact the channel layer 54m. The dielectric structure 52m may be separated into an upper dielectric structure 52mU and a lower dielectric structure 52mL by an intermediate layer 21b.

The vertical dummy structures 50d may be dummy structures electrically insulated from the bit line 78b. The vertical dummy structures 50d may serve as supports for preventing the stacked structure 30 from collapsing or deforming. The vertical dummy structures 50d may have the same cross-sectional structure as the vertical memory structure 50m and may be formed of the same material.

Referring to FIG. 2A , the vertical dummy structures 50d may penetrate the first lower separation structure 48C, and the upper separation structure 45 may penetrate the upper portions of the vertical dummy structures 50d.

The bit line 78b and the bit line connection plug 75b may be disposed at a higher level than the stack structure 30 . The bit line 78b and the bit line connection plug 75b may be disposed through the capping insulating structure 40 disposed on the stack structure 30 . The bit line 78b may have a line shape extending in the second horizontal direction (Y). A bit line connection plug 75b may be disposed between the vertical memory structure 50m and the bit line 78b to electrically connect the vertical memory structure 50m and the bit line 78b. The bit line connection plugs 75b may include a first plug 75_1 and a second plug 75_2 that are sequentially stacked.

Hereinafter, an exemplary method of forming a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 4A to 7D .

4A, 5A, 6A, and 7A are cross-sectional views illustrating cross-sections taken along line I-I' of FIGS. 1A and 1B, and FIGS. 4B, 5B, 6B and 7B are FIGS. 1A and 1B. It is a cross-sectional view showing cross-sections taken along line II-II' of 1b, and FIGS. 4c, 5c, 6c and 7c are cross-sectional views showing cross-sections taken along line III-III' of FIGS. 1a and 1b 4D, 5D, 6D, and 7D are cross-sectional views illustrating cross-sections taken along line IV-IV' of FIGS. 1A and 1B.

4A to 4D , the peripheral circuit 12 and the peripheral wiring structure 15 may be formed on the substrate 3 .

A device isolation region 9s may be formed in the substrate 3 , and a peripheral gate dielectric layer 12c and a peripheral gate electrode 12a may be sequentially formed. The device isolation region 9s may be formed by, for example, a shallow trench isolation (STI) process. A peripheral spacer layer 12d and a peripheral source/drain region 12b may be formed on both sidewalls of the peripheral gate dielectric layer 12c and the peripheral gate electrode 12a.

The lower insulating structure 18 may be formed to cover the peripheral circuit 12 .

A lower layer 21a covering the lower insulating structure 18 may be formed on the substrate 3 . A preliminary intermediate layer 21p extending from the first region R1 to a portion of the second region R2 may be formed on the lower layer 21a. An upper layer 21c covering the lower layer 21a and the preliminary intermediate layer 21p may be formed. The lower layer 21a and the upper layer 21c may include a doped polysilicon layer, for example, a polysilicon layer having an N-type conductivity. The preliminary intermediate layer 21p may include a plurality of layers stacked one by one or sequentially. For example, the preliminary intermediate layer 21p may include a silicon oxide layer, a silicon nitride layer and a silicon oxide layer stacked one after another.

5A to 5D , a preliminary stacked structure 30p in which a plurality of interlayer insulating layers 33 and a plurality of sacrificial layers 36l and 36h are alternately stacked on the upper layer 21c may be formed. have. The plurality of sacrificial layers 36l and 36h may be formed of a material that can be selectively etched by having high etch selectivity with respect to the plurality of interlayer insulating layers 33 . The etch selectivity may be quantitatively expressed through a ratio of the etch rates of the sacrificial layers 36l and 36h to the etch rates of the interlayer insulating layers 33 . The interlayer insulating layers 33 may include, for example, at least one of silicon oxide and silicon nitride. The sacrificial layers 36l and 36h may include, for example, at least one of silicon, silicon oxide, silicon carbide, and silicon nitride. In one embodiment, the interlayer insulating layers 33 may include silicon oxide, and the sacrificial layers 36l and 36h may include silicon nitride.

Among the plurality of sacrificial layers 36l and 36h , the sacrificial layer 36l to be replaced with the lower selection gate electrode ( 39L2 in FIGS. 2A to 2D ) may have lower etch selectivity than other sacrificial layers 36h . The etch selectivity may be controlled by a component of the sacrificial layer, a deposition method of the sacrificial layer, and the like. In an illustrative example, when the sacrificial layers 36h and 36l include silicon nitride, the sacrificial layer 36l contains a lower concentration of nitrogen compared to the sacrificial layer 36h, compared to the sacrificial layer 36h. It may have low etch selectivity.

At least a portion of the sacrificial layer 36l of the second region R2 may be cut to form a cut region. In an exemplary embodiment, the cut region may be formed in a central portion of the sacrificial layer 36l in the second horizontal direction Y, and may partially extend from the second region R2 in the first horizontal direction X. . The second lower isolation structure 48E may be formed by filling the cut region with an insulating material. In an illustrative example, the second lower isolation structure 48E may be integrally formed with the interlayer insulating layer 33 adjacent thereto. The second lower isolation structure 48E may include, for example, silicon oxide. At an upper portion of the second lower isolation structure 48E, at least a portion of the interlayer insulating layer 33 and the gate electrode 39 may be depressed toward the center of the second lower isolation structure 48E. As they move away from the second lower isolation structure 48E, the interlayer insulating layers 33 and the gate electrodes 39 may have a depression in which the curvature is relieved or may not have a depression.

6A to 6D , vertical memory structures 50m and vertical dummy structures 50d passing through the preliminary stacked structure 30p may be formed.

The vertical memory structures 50m and the vertical dummy structures 50d may be formed by filling channel holes formed by anisotropically etching the sacrificial layers 36l and 36h and the interlayer insulating layers 33 using a mask layer. . Sidewalls of the vertical memory structures 50m and the vertical dummy structures 50d may or may not be perpendicular to the top surface of the lower layer 21a. The vertical memory structures 50m and the vertical dummy structures 50d may be formed to penetrate the upper layer 21c and the preliminary intermediate layer 21p to recess a portion of the lower layer 21a. Some of the vertical dummy structures 50d may be formed to penetrate the first lower separation structure 48C. By sequentially forming the dielectric structure 52m, the channel layer 54m, and the insulating core region 56m in the channel hole, vertical memory structures 50m and vertical dummy structures 50d may be formed.

Next, referring to FIGS. 7A to 7D , an upper insulating layer 34 covering the interlayer insulating layers 33 may be formed on the interlayer insulating layers 33 . One or a plurality of interlayer insulating layers 33 positioned thereon and an upper isolation structure 45 penetrating the upper insulating layer 34 may be formed. The upper separation structure 45 may be formed through at least a portion of an upper portion of the vertical dummy structure 50d. The upper isolation structure 45 may be formed of silicon oxide. The formation order of the upper isolation structure 45 and the vertical memory structures 50d may be changed. For example, after forming the upper isolation structure 45 , it is also possible to form the vertical memory structures 50d extending in the vertical direction Z under the upper isolation structure 45 .

Isolation trenches TR passing through the preliminary stacked structure 30p may be formed in regions corresponding to the main isolation structure 42M and the first and second auxiliary isolation structures 42S1 and 42S2 . The isolation trenches TR may be formed to penetrate the upper layer 21c. By performing an etch-back process in the isolation trenches TR, the preliminary intermediate layer 21p of the first region R1 may be selectively removed, and a portion of the exposed dielectric structure 52m may be removed together. . An intermediate layer 21b may be formed in a region from which the preliminary intermediate layer 21p is removed. The intermediate layer 21b may be formed of a polysilicon layer having an N-type conductivity.

The sacrificial layers 36l and 36h may be selectively removed through the isolation trenches TR to form a tunnel portion TL. While all of the sacrificial layers 36h having a relatively high etch selectivity are removed, a portion of the sacrificial layer 36l having a relatively low etch selectivity is not removed and remains. In the illustrative example, the sacrificial layer 36l may start to be removed from both sides and remain in the central portion. The remaining sacrificial layer may be referred to as a first lower isolation structure 48C.

The first lower isolation structure 48C may be formed adjacent to the second lower isolation structure 48E. The first lower isolation structure 48C extends in the first horizontal direction X in the first region R1 , and the second lower isolation structure 48E is formed between the first and second regions R1 and R2 . It may extend along the first horizontal direction X into the second region R2 from the boundary. The first and second lower isolation structures 48C may separate the lower selection gate electrode 39L2 of FIGS. 2A to 2D along the second horizontal direction Y to be formed by a process to be described later.

The first lower isolation structure 48C is a portion where the sacrificial layer 36l remains, and may be formed of the same material as the sacrificial layer 36l. In an illustrative example, the first lower isolation structure 48C may include silicon nitride. The second lower isolation structure 48E may include a material different from that of the first lower isolation structure 48C. In an illustrative example, the second lower isolation structure 48E may be integrally formed with the neighboring interlayer insulating layer 33 and may include the same material as the neighboring interlayer insulating layer 33 . For example, the second lower isolation structure 48E may include silicon oxide.

Next, referring to FIGS. 2A to 2D , the gate electrodes 39 may be formed by filling the tunnel portion TL formed by removing the sacrificial layers 36l and 36h with a conductive material. The preliminary stacked structure 30p may be formed of a stacked structure 30 including gate electrodes 39 and interlayer insulating layers 33 .

In an exemplary embodiment, before forming the gate electrodes 39 in the tunnel portions TL, a dielectric layer may be conformally formed. Forming the gate electrodes 39 in the tunnel portions TL may include forming conductive material layers in the tunnel portions TL and etching the conductive material layers.

The isolation trenches TR may be filled with silicon oxide to form a main isolation structure 42M and first and second auxiliary isolation structures 42S1 and 42S2 .

Next, a data storage system including a semiconductor device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 8 and 9 and 10 , respectively.

8 is a diagram schematically illustrating a data storage system including a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 8 , a data storage system 1000 according to an exemplary embodiment of the present invention includes a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100 to control the semiconductor device 1100 . may include. The data storage system 1000 may be a storage device including the semiconductor device 1100 or an electronic device including the storage device. For example, the data storage system 1000 may be a solid state drive device (SSD) including the semiconductor device 1100 , a universal serial bus (USB), a computing system, a medical device, or a communication device.

In an embodiment, the data storage system 1000 may be an electronic system that stores data.

The semiconductor device 1100 may be the semiconductor device according to the embodiment described above with reference to FIGS. 1 to 3 . The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F.

The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110 , a page buffer 1120 , and a logic circuit 1130 . For example, the first structure 1100F may include a peripheral circuit structure ( 6 in FIGS. 2A to 2D ) including the aforementioned peripheral circuit ( 12 in FIGS. 2A to 2D ). The peripheral circuit ( 12 of FIGS. 2A to 2D ) may be a transistor constituting a peripheral circuit structure including the decoder circuit 1110 , the page buffer 1120 , and the logic circuit 1130 .

The second structure 1100S includes a bit line BL, a common source line CSL, word lines WL, first and second gate upper lines UL1 and UL2, and first and second gate lower lines. It may be a memory structure including the memory cells LL1 and LL2 and the memory cell strings CSTR between the bit line BL and the common source line CSL.

In the second structure 1100S, each of the memory cell strings CSTR includes lower transistors LT1 and LT2 adjacent to the common source line CSL and upper transistors UT1 adjacent to the bit line BL. UT2) and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may be variously modified according to embodiments.

In example embodiments, the upper transistors UT1 and UT2 may include a string select transistor, and the lower transistors LT1 and LT2 may include a ground select transistor. The gate lower lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word lines WL may be gate electrodes of the memory cell transistors MCT, and the gate upper lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

The above-described gate electrodes (39 of FIGS. 2A to 2D ) may constitute the gate lower lines LL1 and LL2 , the word lines WL and the gate upper lines UL1 and UL2 .

In example embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string select transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the lower erase control transistor UT1 uses a gate induced drain leakage (GIDL) phenomenon to erase data stored in the memory cell transistors MCT. can be used for

The common source line CSL, the first and second gate lower lines LL1 and LL2, the word lines WL, and the first and second gate upper lines UL1 and UL2 form the first structure ( It may be electrically connected to the decoder circuit 1110 through first connection wires 1115 extending from the inside 1100F to the second structure 1100S.

At least a portion of the aforementioned plate pattern ( 21 in FIGS. 2A to 2D ) may be a common source line CSL. The bit lines BL may be electrically connected to the page buffer 1120 through second connection lines 1125 extending from the first structure 1100F to the second structure 1100S. The bit lines BL may be the bit lines 78b described above.

In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by the logic circuit 1130 .

The semiconductor device 1000 may further include an input/output pad 1101 .

The semiconductor device 1000 may communicate with the controller 1200 through the input/output pad 1101 electrically connected to the logic circuit 1130 . The input/output pad 1101 may be electrically connected to the logic circuit 1130 through an input/output connection line 1135 extending from the first structure 1100F to the second structure 1100S. Accordingly, the controller 1200 may be electrically connected to the semiconductor device 1000 through the input/output pad 1101 , and may control the semiconductor device 1000 .

The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . In some embodiments, the data storage system 1000 may include a plurality of semiconductor devices 1100 , and in this case, the controller 1200 may control the plurality of semiconductor devices 1000 .

The processor 1210 may control the overall operation of the data storage system 1000 including the controller 1200 . The processor 1210 may operate according to a predetermined firmware, and may access the semiconductor device 1100 by controlling the NAND controller 1220 . The NAND controller 1220 may include a NAND interface 1221 that handles communication with the semiconductor device 1100 . Through the NAND interface 1221 , a control command for controlling the semiconductor device 1100 , data to be written to the memory cell transistors MCT of the semiconductor device 1100 , and the memory cell transistors of the semiconductor device 1100 ( Data to be read from the MCT) may be transmitted. The host interface 1230 may provide a communication function between the data storage system 1000 and an external host. When receiving a control command from an external host through the host interface 1230 , the processor 1210 may control the semiconductor device 1100 in response to the control command.

9 is a perspective view schematically illustrating a data storage system including a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 9 , a data storage system 2000 according to an exemplary embodiment of the present invention includes a main board 2001 , a controller 2002 mounted on the main board 2001 , one or more semiconductor packages 2003 , and DRAM 2004 . The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 by wiring patterns 2005 formed on the main board 2001 .

The main board 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary according to a communication interface between the data storage system 2000 and an external host. In example embodiments, the data storage system 2000 includes an M-Phy for Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), Universal Flash Storage (UFS), etc. can communicate with an external host according to any one of the interfaces of In example embodiments, the data storage system 2000 may operate by power supplied from an external host through the connector 2006 . The data storage system 2000 may further include a power management integrated circuit (PMIC) for distributing power supplied from an external host to the controller 2002 and the semiconductor package 2003 .

The controller 2002 may write data to or read data from the semiconductor package 2003 , and may improve the operating speed of the data storage system 2000 .

The DRAM 2004 may be a buffer memory for mitigating a speed difference between the semiconductor package 2003 as a data storage space and an external host. The DRAM 2004 included in the data storage system 2000 may operate as a kind of cache memory, and may provide a space for temporarily storing data in a control operation for the semiconductor package 2003 . When the data storage system 2000 includes the DRAM 2004 , the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to the NAND controller for controlling the semiconductor package 2003 .

The semiconductor package 2003 may include first and second semiconductor packages 2003a and 2003b spaced apart from each other. Each of the first and second semiconductor packages 2003a and 2003b may be a semiconductor package including a plurality of semiconductor chips 2200 . Each of the semiconductor chips 2200 may include the semiconductor device according to the embodiment described above with reference to FIGS. 1 to 3 .

Each of the first and second semiconductor packages 2003a and 2003b includes the package substrate 2100 , the semiconductor chips 2200 on the package substrate 2100 , and adhesive layers 2300 disposed on lower surfaces of the semiconductor chips 2200 , respectively. ), a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100. may include

The package substrate 2100 may be a printed circuit board including package upper pads 2130 . Each of the semiconductor chips 2200 may include an input/output pad 2210 .

In example embodiments, the connection structure 2400 may be a bonding wire electrically connecting the input/output pad 2210 and the package upper pads 2130 . Accordingly, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other by a bonding wire method, and may be electrically connected to the package upper pads 2130 of the package substrate 2100 and can be electrically connected. According to embodiments, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be formed through a through-electrode (TSV) instead of the bonding wire-type connection structure 2400 . It may be electrically connected to each other by a connection structure comprising a.

In example embodiments, the controller 2002 and the semiconductor chips 2200 may be included in one package. For example, the controller 2002 and the semiconductor chips 2200 are mounted on a separate interposer substrate different from the main substrate 2001, and the controller 2002 and the semiconductor chips 2200 are formed by wiring formed on the interposer substrate. These may be connected to each other.

10 is a cross-sectional view schematically illustrating a semiconductor package according to an exemplary embodiment of the present invention. FIG. 10 illustrates an exemplary embodiment of the semiconductor package 2003 of FIG. 9 , and conceptually shows a region cut along the cutting line VI-VI' of the semiconductor package 2003 of FIG. 10 .

Referring to FIG. 10 , in the semiconductor package 2003 , the package substrate 2100 may be a printed circuit board. The package substrate 2100 is disposed on or exposed through the package substrate body 2120 , the package upper pads 2130 disposed on the upper surface of the package substrate body 2120 , and the lower surface of the package substrate body 2120 . It may include lower pads 2125 to be formed, and internal wirings 2135 electrically connecting the upper pads 2130 and the lower pads 2125 in the package substrate body 2120 . The upper pads 2130 may be electrically connected to the connection structures 2400 . The lower pads 2125 may be connected to the wiring patterns 2005 of the main board 2010 of the electronic system 2000 as shown in FIG. 9 through conductive connectors 2800 .

Each of the semiconductor chips 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 that are sequentially stacked on the semiconductor substrate 3010 . The first structure 3100 may include a peripheral circuit region including peripheral interconnections 3110 . The second structure 3200 includes a common source line 3205 , a gate stack structure 3210 on the common source line 3205 , and memory channel structures 3220 and isolation structures 3230 passing through the gate stack structure 3210 . ), bit lines 3240 electrically connected to the memory channel structures 3220 , and gate connection wirings electrically connected to the word lines (WL of FIG. 8 ) of the gate stack structure 3210 . have. The first structure 3100 may include the first structure 1100F of FIG. 8 , and the second structure 3200 may include the second structure 1100S of FIG. 8 . For example, in FIG. 10 , a partially enlarged area indicated by reference numeral 1 may represent the cross-sectional structure of FIG. 2D . Accordingly, each of the semiconductor chips 2200 may include the semiconductor device 1 according to the embodiment described above with reference to FIGS. 1 to 3 .

Each of the semiconductor chips 2200 may include a through wiring 3245 electrically connected to the peripheral wirings 3110 of the first structure 3100 and extending into the second structure 3200 . The through wiring 3245 may pass through the gate stacked structure 3210 and may be further disposed outside the gate stacked structure 3210 .

Each of the semiconductor chips 2200 is electrically connected to the peripheral wirings 3110 of the first structure 3100 and electrically connected to the input/output connection wiring 3265 and the input/output connection wiring 3265 extending into the second structure 3200 . It may further include an input/output pad 2210 connected to .

As described above, embodiments of the present invention have been described with reference to the accompanying drawings, but those of ordinary skill in the art to which the present invention pertains can implement the present invention in other specific forms without changing the technical spirit or essential features. You can understand that there is Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

The present invention is not limited by the above-described embodiments and the accompanying drawings, but is intended to be limited by the appended claims. Therefore, various types of substitution, modification and change will be possible by those skilled in the art within the scope not departing from the technical spirit of the present invention described in the claims, and it is also said that it falls within the scope of the present invention. something to do.

Semiconductor device: 1 Semiconductor substrate: 3
Peripheral circuit structure: 6 Peripheral circuit: 12
Peripheral wiring structure: 15 Lower insulation structure: 18
Plate pattern: 21 Bottom layer: 21a
Middle layer: 21b Preliminary middle layer: 21p
Top layer: 21c Laminate structure: 30
Preliminary Laminate: 30p Interlayer Insulation Layer: 33
Gate electrodes: 39 Dielectric layer: 41
Sacrificial Layer: 36 Vertical Memory Structure: 50m
Vertical dummy structure: 50d Bitline: 78b
Bitline Connection Plug: 75b Main Separation Structure: 42M
First auxiliary separation structure: 42S1 Second auxiliary separation structure: 42S2
First lower separating structure: 48C Second lower separating structure: 48E
Third lower separation structure: 48M Upper separation structure: 45
First region: R1 Second region: R2

Claims (10)

a substrate having a first region and a second region;
A stacked structure including interlayer insulating layers and gate electrodes alternately and repeatedly stacked on the substrate, wherein the gate electrodes are a lower gate electrode, a first lower select gate electrode and a second lower select gate electrode disposed at the same height level on the lower gate electrode a lower selection gate electrode, memory cell gate electrodes spaced apart from each other and stacked on the first and second lower selection gate electrodes in a first direction perpendicular to the top surface of the substrate, and the same on the memory cell gate electrodes a first string select gate electrode and a second string select gate electrode disposed at a height level;
In the first region and the second region, penetrating the gate electrodes, extending in a second direction perpendicular to the first direction, and spaced apart from each other along the first direction and a third direction perpendicular to the second direction main separation structures disposed;
an auxiliary isolation structure extending in the second direction through the gate electrodes between the main isolation structures in the second region;
a first lower isolation structure on the first region between the first lower select gate electrode and the second lower select gate electrode; and
including vertical memory structures penetrating the stack structure on the first region,
the interlayer insulating layers include a first material,
The first lower separation structure includes a second material different from the first material,
The auxiliary isolation structure includes a portion passing between the first and second lower selection gate electrodes.
According to claim 1,
a second lower isolation structure disposed between the first lower selection gate electrode and the second lower selection gate electrode and between the first lower isolation structure and the auxiliary isolation structure in the second region;
The second lower isolation structure includes the first material.
3. The method of claim 2,
The first lower separation structure has a first width along the third direction,
The second lower separation structure has a second width along the third direction,
The second width is greater than the first width.
4. The method of claim 3,
The auxiliary separation structure has a third width along the third direction,
The third width is greater than the first width and smaller than the second width.
According to claim 1,
and an upper isolation structure on the memory cell gate electrodes, in contact with the auxiliary isolation structure, and disposed between the first string select gate electrode and the second string select gate electrode.
6. The method of claim 5,
The upper isolation structure overlaps the first lower isolation structure.
According to claim 1,
The first material comprises silicon oxide,
The second material comprises silicon nitride.
a substrate having a first region and a second region;
A stacked structure including interlayer insulating layers and gate electrodes alternately and repeatedly stacked on the substrate, a first lower selection gate electrode and a second lower selection gate electrode disposed at the same height level, the first and Memory cell gate electrodes stacked apart from each other in a first direction perpendicular to the top surface of the substrate on the second lower selection gate electrodes, and a first string selection disposed at the same height level on the memory cell gate electrodes a gate electrode and a second string select gate electrode;
an auxiliary isolation structure penetrating the gate electrodes and extending in a second direction perpendicular to the first direction on the second region;
a first lower isolation structure on the first region between the first lower select gate electrode and the second lower select gate electrode;
a second lower isolation structure disposed in the second region, between the first lower selection gate electrode and the second lower selection gate electrode, and between the first lower isolation structure and the auxiliary isolation structure; and
on the first region, including vertical memory structures penetrating the stacked structure;
On the second region, the gate electrodes include gate pads arranged in a step shape,
the interlayer insulating layers include a first material,
The first lower separation structure includes a second material different from the first material,
The auxiliary isolation structure includes a portion passing between the first and second lower selection gate electrodes.
9. The method of claim 8,
The first and second lower select gate electrodes are ground select gate electrodes.
9. The method of claim 8,
the gate electrodes further include an erase control gate electrode;
The first lower selection gate electrode, the second lower selection gate electrode, the first lower isolation structure, and the second lower isolation structure are disposed on the erase control gate electrode.

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