KR20210130608A - Light emitting display device and manufacturing method thereof - Google Patents

Abstract

In accordance with one embodiment, a light emitting display device comprises: a substrate including a display region and a non-display region surrounding the display region; a lower pad electrode positioned on the substrate in the non-display region; a lower planarization layer covering the lower pad electrode; and an upper pad electrode positioned on the lower pad electrode in the non-display region, and overlapping at least a part of the lower planarization layer. The lower planarization layer includes an opening through which an upper surface of the lower pad electrode is exposed. The lower pad electrode and the upper pad electrode are connected to each other by the opening. The lower planarization layer includes: an exposure part through which an upper surface of the lower planarization layer is exposed; and an overlapping part overlapping at least a part of the upper pad electrode. The height of the upper surface of the exposure part is higher than the height of the upper surface of the planarization part. In accordance with the present invention, the metal layer of a pad electrode can be protected.

Description

Light emitting display device and manufacturing method thereof

The present disclosure relates to a light emitting display device and a method for manufacturing the same.

A light emitting display device is a self-luminous display device that displays an image with a light emitting diode (LED) emitting light.

Unlike a liquid crystal display (LCD), a light emitting display device does not require a separate light source, and thus a thickness and weight can be relatively reduced. In addition, since the light emitting display device exhibits high quality characteristics such as low power consumption, high luminance, and high response speed, it is attracting attention as a next-generation display device for portable electronic devices.

The embodiments are for reducing damage to the pad electrode of the non-display area that may occur in a subsequent process such as a process of forming a color filter.

According to an exemplary embodiment, a light emitting display device includes: a substrate including a display area and a non-display area surrounding the display area; a lower pad electrode positioned on the substrate in the non-display area; a lower planarization layer covering a portion of the lower pad electrode; and an upper pad electrode positioned on the lower pad electrode and overlapping at least a portion of the lower planarization layer, wherein the lower planarization layer includes an opening through which a top surface of the lower pad electrode is exposed, and the A lower pad electrode and the upper pad electrode are connected to each other, and the lower planarization layer includes an exposed portion exposing an upper surface of the lower planarization layer and an overlapping portion overlapping at least partially overlapping the upper pad electrode, wherein the upper surface of the exposed portion has a height of the upper pad electrode. It is lower than the height of the upper surface of the overlapping part.

The upper pad electrode includes an upper layer including titanium (Ti), an intermediate layer including aluminum (Al), and a lower layer including titanium (Ti), and the lower pad electrode includes an upper layer including titanium (Ti), aluminum It may include an intermediate layer containing (Al) and titanium (Ti).

The lower planarization layer may include at least one material selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin.

a semiconductor layer positioned on the substrate in the display area; a gate insulating film covering the semiconductor layer; a gate electrode positioned on the gate insulating layer; an interlayer insulating film covering the gate electrode; and a source electrode and a drain electrode positioned on the interlayer insulating layer and connected to the semiconductor layer, wherein the lower pad electrode may be positioned on the same layer as the source electrode and the drain electrode.

a pixel electrode positioned on the lower planarization layer; a light emitting layer positioned on the pixel electrode; and a common electrode positioned on the emission layer, wherein the lower planarization layer covers the source electrode and the drain electrode, and includes a via hole, through which the drain electrode and the pixel electrode may be connected.

an encapsulation layer covering the common electrode in the display area; a sensing insulating layer positioned on the encapsulation layer; a plurality of sensing electrodes positioned on the sensing insulating layer; and an inorganic protective layer covering the plurality of sensing electrodes, wherein the plurality of sensing electrodes may be located on the same layer as the upper pad electrode.

The method may further include a buffer layer positioned between the encapsulation layer and the sensing insulating layer and between the lower pad electrode and the upper pad electrode, wherein the lower pad electrode and the upper pad electrode may be electrically connected to each other.

According to an exemplary embodiment, a light emitting display device includes: a substrate including a display area and a non-display area surrounding the display area; a first lower pad electrode and a second lower pad electrode spaced apart from each other in the non-display area; a first lower planarization layer and a second lower planarization layer at least partially overlapping the first lower pad electrode and the second lower pad electrode, respectively; a first upper pad electrode overlapping the first lower pad electrode and the first lower planarization layer, and a second upper pad electrode overlapping the second lower pad electrode and the second lower planarization layer; and a light blocking member positioned to at least partially overlap between the first upper pad electrode and the second upper pad electrode positioned on the same layer.

An upper surface of the light blocking member may be positioned higher than upper surfaces of the first upper pad electrode and the second upper pad electrode.

The first upper pad electrode and the second upper pad electrode include an upper layer including titanium (Ti), an intermediate layer including aluminum (Al), and a lower layer including titanium (Ti), and the first lower pad electrode , and the second lower pad electrode may include an upper layer including titanium (Ti), an intermediate layer including aluminum (Al), and a lower layer including titanium (Ti).

A distance from one end of the first lower pad electrode to one end of the second lower pad electrode may be 10 μm to 20 μm.

A distance from one end of the first upper pad electrode to one end of the second upper pad electrode may be 10 μm or less.

a semiconductor layer positioned on the substrate in the display area; a gate insulating film covering the semiconductor layer; a gate electrode positioned on the gate insulating layer; an interlayer insulating film covering the gate electrode; and a source electrode and a drain electrode positioned on the interlayer insulating layer and connected to the semiconductor layer, wherein the lower pad electrode may be positioned on the same layer as the source electrode and the drain electrode.

a pixel electrode positioned on the lower planarization layer; a light emitting layer positioned on the pixel electrode; a common electrode positioned on the light emitting layer; an encapsulation layer positioned on the common electrode; and a plurality of sensing electrodes positioned on the sensing insulating layer, wherein in the display area, the sensing insulating layer is positioned on the encapsulation layer, the lower planarization layer covers the source electrode and the drain electrode, and The plurality of sensing electrodes may be positioned on the same layer as the upper pad electrode.

and a buffer layer positioned between the encapsulation layer and the sensing insulating layer, between the first lower pad electrode and the first upper pad electrode, and between the second lower pad electrode and the second upper pad electrode. and the first lower pad electrode and the first upper pad electrode, and the second lower pad electrode and the second upper pad electrode may be electrically connected to each other.

According to an exemplary embodiment, a method of manufacturing a light emitting display device includes: stacking a gate insulating layer and an interlayer insulating layer on a substrate including a display area and a non-display area; forming a source electrode and a drain electrode on the interlayer insulating layer in the display area, and forming a lower pad electrode on the interlayer insulating layer in the non-display area; forming a lower planarization layer on the source electrode, the drain electrode, and the lower pad electrode; forming a sensing electrode on the lower planarization layer in the display area, on the sensing insulating layer, and forming an upper pad electrode on the lower planarization layer in the non-display area; forming an inorganic protective layer to cover the sensing electrode and the upper pad electrode; forming a light blocking member and a color filter on the inorganic passivation layer in the display area, and forming an upper planarization layer on the color filter; and etching the inorganic passivation layer to partially expose a top surface of the lower planarization layer in the non-display area.

The inorganic passivation layer may be etched by a dry etching process.

The exposed upper surface of the lower planarization layer may have a lower height than the upper surface overlapping the upper pad electrode.

According to an exemplary embodiment, a method of manufacturing a light emitting display device includes: stacking a gate insulating layer and an interlayer insulating layer on a substrate including a display area and a non-display area; forming a source electrode and a drain electrode on the interlayer insulating layer in the display area, and forming a first lower pad electrode and a second lower pad electrode on the interlayer insulating layer in the non-display area; forming a lower planarization layer on the source electrode, the drain electrode, the first lower pad electrode, and the second lower pad electrode; forming a sensing electrode on the lower planarization layer in the display area and on the sensing insulating layer, and forming a first upper pad electrode and a second upper pad electrode on the lower planarization layer in the non-display area; and forming a light blocking member and a color filter on the sensing electrode in the display area, and forming the light blocking member to partially overlap the first upper pad electrode and the second upper pad electrode in the non-display area. .

In the non-display area, the light blocking member may be formed between the first upper pad electrode and the second upper pad electrode.

According to an exemplary embodiment, a light emitting display device includes: a substrate including a display area and a non-display area surrounding the display area; a pad inorganic insulating layer positioned on the substrate in the non-display area; a pad electrode positioned on the pad inorganic insulating layer; an inorganic protective layer positioned on the pad electrode or the pad inorganic insulating layer; and an upper planarization layer positioned on the inorganic passivation layer, wherein one end of the upper planarization layer coincides with one end of the inorganic passivation layer.

One end of the lower surface of the upper planarization layer may coincide with one end of the upper surface of the inorganic passivation layer.

The inorganic passivation layer may be positioned to partially overlap the pad electrode, and a top surface of the pad electrode may be partially exposed.

The inorganic passivation layer may be positioned on the pad inorganic insulating layer, and one end of the inorganic passivation layer may be spaced apart from both ends of the pad electrode.

The upper planarization layer may include an organic insulating material.

According to an exemplary embodiment, a light emitting display device includes: a substrate including a display area and a non-display area surrounding the display area; an interlayer insulating film positioned on the substrate; a lower pad electrode positioned on the interlayer insulating layer in the non-display area; a buffer layer covering a portion of the lower pad electrode; and an upper pad electrode positioned on the lower pad electrode and overlapping at least a portion of the buffer layer, wherein a thickness of a portion of the buffer layer not overlapping with the upper pad electrode is greater than a thickness of a portion overlapping with the upper pad electrode thin.

The upper pad electrode includes an upper layer including titanium (Ti), an intermediate layer including aluminum (Al), and a lower layer including titanium (Ti), and the lower pad electrode includes an upper layer including titanium (Ti), aluminum It may include an intermediate layer including (Al) and a lower layer including titanium (Ti).

a semiconductor layer positioned on the substrate in the display area; a gate insulating film covering the semiconductor layer; a gate electrode positioned on the gate insulating layer; an interlayer insulating film covering the gate electrode; a source electrode and a drain electrode positioned on the interlayer insulating layer and connected to the semiconductor layer; and a lower planarization layer covering the source electrode and the drain electrode, wherein the lower pad electrode may be positioned on the same layer as the source electrode and the drain electrode.

a pixel electrode positioned on the lower planarization layer; a light emitting layer positioned on the pixel electrode; and a common electrode positioned on the emission layer, wherein the lower planarization layer covers the source electrode and the drain electrode, and includes a via hole, through which the drain electrode and the pixel electrode may be connected.

an encapsulation layer covering the common electrode in the display area; a sensing insulating layer positioned on the encapsulation layer; a plurality of sensing electrodes positioned on the sensing insulating layer; and an inorganic protective layer covering the plurality of sensing electrodes, wherein the plurality of sensing electrodes are positioned on the same layer as the upper pad electrode, and the buffer layer is positioned between the encapsulation layer and the sensing insulating layer, The lower pad electrode and the upper pad electrode may be electrically connected.

According to embodiments, when forming the pad electrode in the non-display area, after depositing an inorganic protective layer on the pad electrode, a subsequent process is performed to prevent damage to the pad electrode that may occur in a subsequent process, such as a color filter forming process. can reduce

In addition, since the metal layer of the pad electrode can be protected, the performance of the pad electrode can also be maintained.

According to embodiments, since the end of the pad electrode may be protected by the light blocking member, damage to the pad electrode that may occur in the process of forming the pad electrode and forming the color filter may be reduced.

1 is a schematic plan view of a light emitting display device according to an exemplary embodiment.
2 is a plan view of a portion including a sensing unit in a light emitting display device according to an exemplary embodiment.
3 is a cross-sectional view illustrating a portion of a display area in a light emitting display device according to an exemplary embodiment.
4 is an enlarged image of part A of FIG. 3 .
5 is a partial view of a pad part in the light emitting display device according to an exemplary embodiment.
FIG. 6 is a cross-sectional view taken along line VI-VI' in FIG. 5 .
FIG. 7 is a detailed view of part B in FIG. 6 .
8 to 11 schematically illustrate a method of manufacturing a pad in a method of manufacturing a light emitting display device according to an exemplary embodiment.
12 is a cross-sectional view illustrating a portion of a display area in a light emitting display device according to an exemplary embodiment.
13 is a cross-sectional view illustrating a portion of a pad in a light emitting display device according to an exemplary embodiment.
14 is a cutaway image of a portion of a pad in the light emitting display device according to an exemplary embodiment.
15 is a cutaway image of a portion of a pad in a light emitting display device according to a comparative example.
16 and 17 are cross-sectional views illustrating a portion of a pad in a light emitting display device according to an exemplary embodiment.
18 is a cross-sectional view illustrating a portion of a pad in a light emitting display device according to an exemplary embodiment.
19 is a cross-sectional view illustrating a portion of a pad in a light emitting display device according to an exemplary embodiment.
20 to 23 schematically illustrate a method of manufacturing a pad in a method of manufacturing a light emitting display device according to an exemplary embodiment.
24 is a cross-sectional view illustrating a portion of a pad in a light emitting display device according to an exemplary embodiment.
25 and 26 are cross-sectional views illustrating a portion of a display area in a light emitting display device according to an exemplary embodiment.
27 illustrates a portion of a substrate including a pad portion in the light emitting display device according to an exemplary embodiment.
28 is a cross-sectional view taken along the line XXI-XXI' in FIG. 27 .
29 and 30 show another embodiment of FIG. 28 .

Hereinafter, with reference to the accompanying drawings, various embodiments of the present invention will be described in detail so that those of ordinary skill in the art can easily implement them. The present invention may be embodied in many different forms and is not limited to the embodiments described herein.

In order to clearly explain the present invention, parts irrelevant to the description are omitted, and the same reference numerals are given to the same or similar elements throughout the specification.

In addition, since the size and thickness of each component shown in the drawings are arbitrarily indicated for convenience of description, the present invention is not necessarily limited to the illustrated bar. In order to clearly express various layers and regions in the drawings, the thicknesses are enlarged. And in the drawings, for convenience of description, the thickness of some layers and regions are exaggerated.

Also, when a part of a layer, film, region, plate, etc. is said to be “on” or “on” another part, it includes not only cases where it is “directly on” another part, but also cases where another part is in between. . Conversely, when we say that a part is "just above" another part, we mean that there is no other part in the middle. In addition, to be "on" or "on" the reference portion is to be located above or below the reference portion, and does not necessarily mean to be located "on" or "on" the opposite direction of gravity. .

In addition, throughout the specification, when a part "includes" a certain component, this means that other components may be further included, rather than excluding other components, unless otherwise stated.

In addition, throughout the specification, when referring to "planar", it means when the target part is viewed from above, and "in cross-section" means when viewed from the side when a cross-section of the target part is vertically cut.

Throughout the specification, when it is said "connected", it does not mean only when two or more components are directly connected, but when two or more components are indirectly connected through another component, when physically connected In the case of being electrically connected, as well as being referred to by different names according to location or function, it may include that each part that is substantially integral with each other is connected to each other.

Hereinafter, a light emitting display device and a manufacturing method thereof will be described in detail with reference to the drawings.

1 is a schematic plan view of a light emitting display device according to an exemplary embodiment, and FIG. 2 is a plan view of a light emitting display device including a sensing unit according to an exemplary embodiment.

Referring to FIG. 1 , a light emitting display device according to an exemplary embodiment includes a substrate 100 and a pad unit 30 .

The substrate 100 includes a display area DA and a non-display area NA. The display area DA is an area in which pixels including light emitting diodes and transistors are formed to display an image, and the non-display area NA is an area in which an image is not displayed and surrounds the display area DA, and This area includes the pad part 30 in which the pad PAD to which the driving signal is applied is formed.

A plurality of pixels (not shown) including a transistor, a light emitting diode, and the like are formed in the display area DA.

In the non-display area NA, a driving voltage line (not shown), a driving low voltage line (not shown), and the pad unit 30 for transmitting driving signals such as voltages and signals to the pixels formed in the display area DA are formed. do.

A sensing area TA including sensing electrodes 520 and 540 of FIG. 2 may be further formed on the display area DA to recognize a touch, and a signal to the sensing electrode is provided in the non-display area NA. A plurality of sensing wires ( 512 and 522 in FIG. 2 ) for applying ? may be additionally formed. The plurality of sensing wires 512 and 522 and the sensing electrodes 520 and 540 that may be connected to the plurality of sensing wires 512 and 522 will be described with reference to FIG. 2 .

The pad unit 30 is positioned at a portion of the non-display area NA and includes a plurality of pads PAD. The plurality of pads PAD may apply signals to a plurality of voltage lines (not shown) connected to the display area DA, a plurality of sensing wires ( 512 and 522 of FIG. 2 ), and the like. A flexible printed circuit board (not shown) may be attached to the non-display area NA. The flexible printed circuit board FPCB may be electrically connected to the pad unit 30 to transmit a driving signal for driving a pixel or the like to the pad unit 30 from the outside. The flexible printed circuit board (FPCB) and the pad part 30 may be electrically connected by an anisotropic conductive film. In addition, it may additionally include a driving integrated circuit (Integrated Chip, not shown), and a driving signal output from the driving integrated circuit may be supplied to each pixel through the plurality of pads PAD of the pad unit 30 .

Referring to FIG. 2 , the substrate 100 includes a sensing area TA in which a plurality of sensing electrodes 520 and 540 are formed on the display area DA and a peripheral area PA surrounding the sensing area TA. include more According to an exemplary embodiment, the sensing area TA may include the display area DA of FIG. 1 or may further include a part of the non-display area NA, and the peripheral area PA may be a ratio of the display area DA of FIG. 1 . The display area NA may be a non-display area NA except for the detection area.

The sensing area TA includes a plurality of sensing electrodes 520 and 540 . The plurality of sensing electrodes 520 and 540 may include a plurality of first sensing electrodes 520 and a plurality of second sensing electrodes 540 .

The first sensing electrode 520 and the second sensing electrode 540 are electrically separated from each other. According to an embodiment, the first sensing electrode 520 may be a sensing input (Tx) electrode, and the second sensing electrode 540 may be a sensing output (Rx) electrode. Also, the first sensing electrode 520 may be a sensing output (Rx) electrode, and the second sensing electrode 540 may be a sensing input (Tx) electrode.

The plurality of first sensing electrodes 520 and the plurality of second sensing electrodes 540 may be alternately distributed so as not to overlap each other in the sensing area TA and disposed in a mesh shape. A plurality of first sensing electrodes 520 may be respectively disposed in a column direction and a row direction, and a plurality of second sensing electrodes 540 may also be disposed in plurality in a column direction and a row direction.

The first sensing electrode 520 and the second sensing electrode 540 are positioned on the same layer, but may be positioned on different layers. The first sensing electrode 520 and the second sensing electrode 540 may have a diamond shape, but are not limited thereto, and may have a polygonal shape such as a square or a hexagon, a circular shape, or an oval shape. It can be implemented in various shapes, such as having The first sensing electrode 520 and the second sensing electrode 540 may be formed of a transparent conductor or an opaque conductor, and each of the sensing electrodes 520 and 540 may have a plurality of openings. The openings formed in the sensing electrodes 520 and 540 serve to allow light emitted from the light emitting diode to be emitted to the front without interference.

The plurality of first sensing electrodes 520 are electrically connected to each other by a first sensing electrode connection part 521 (also referred to as a bridge), and the plurality of second sensing electrodes 540 are connected to the second sensing electrode connection part 541 . are electrically connected to each other. When the plurality of first sensing electrodes 520 are connected in a first direction, the plurality of second sensing electrodes 540 may be connected in a second direction crossing the same. When the first sensing electrode 520 and the second sensing electrode 540 are positioned on the same layer, one of the first sensing electrode connection part 521 and the second sensing electrode connection part 541 is the first sensing electrode 520 . and the second sensing electrode 540 , and the other one is located on a different layer from the first sensing electrode 520 and the second sensing electrode 540 . As a result, the plurality of first sensing electrodes 520 and the plurality of second sensing electrodes 540 may be electrically separated. The sensing electrode connection parts located in different layers may be located in upper or lower layers of the first sensing electrode 520 and the second sensing electrode 540 , and in the embodiment to be described below, the lower layer, that is, a layer closer to the substrate. An embodiment in which the sensing electrode connection part is located in the

A plurality of sensing wires 512 and 522 respectively connected to the plurality of first sensing electrodes 520 and the plurality of second sensing electrodes 540 are positioned in the peripheral area PA. The first sensing wiring 512 may be connected to a plurality of second sensing electrodes 540 arranged in a row direction, and the second sensing wiring 522 may be connected to a plurality of first sensing electrodes 520 arranged in a column direction. can be connected According to an exemplary embodiment, the first sensing line 512 and the second sensing line 522 may be electrically connected to some of the pads PAD included in the pad unit 30 of FIG. 1 .

FIG. 2 illustrates a mutual-cap type sensing unit for sensing a touch using two sensing electrodes 520 and 540 . However, according to an embodiment, the sensing unit may be formed as a self-cap type sensing unit that senses a touch using only one sensing electrode.

Hereinafter, with reference to FIGS. 3 and 4 , when the light emitting display device includes the sensing area TA, the configuration of the light emitting display device will be described based on a cross-sectional view in the display area DA.

3 is a cross-sectional view illustrating a portion of a display area of a light emitting display device according to an exemplary embodiment, and FIG. 4 is an enlarged image of portion A of FIG. 3 .

Referring to FIG. 3 , the display area DA of the light emitting display device according to an exemplary embodiment includes a substrate 100 , a semiconductor layer 131 , a gate electrode 124 , a source electrode 173 , and a drain electrode 175 . A transistor (TFT) including a gate insulating layer 120 , an interlayer insulating layer 160 , a lower planarization layer 180 , a pixel electrode 191 , an emission layer 350 , a barrier rib 370 , a common electrode 270 , and an encapsulation layer (400). Here, the pixel electrode 191 , the emission layer 350 , and the common electrode 270 constitute the light emitting device LED. In addition, the light emitting display device further includes a sensing area TA positioned above the display area DA, wherein the sensing area TA includes a sensing insulating layer 510 , a plurality of sensing electrodes 520 and 540 , and sensing. It includes an electrode connection part 541 and an inorganic protective layer 505 . In addition, the light blocking member 220 , the color filter layers 230R, 230G, and 230B, and the upper planarization layer 550 are further provided on the sensing area TA.

The substrate 100 may include a material that does not bend due to rigid characteristics, such as glass, or a flexible material that can be bent, such as plastic or polyimide. Although not shown in FIG. 3 , a buffer layer (not shown) or a barrier layer (not shown) for leveling the surface of the substrate 100 and blocking the penetration of impurity elements may be positioned on the substrate 100 .

A semiconductor layer 131 is positioned on the substrate 100 . The semiconductor layer 131 may be formed of an oxide semiconductor, amorphous silicon, polycrystalline silicon, or the like, and may include a channel region, a source region, and a drain region that are classified according to whether or not doped with impurities, and the source region and the drain region are a conductor. It may have a conductive characteristic corresponding to .

The gate insulating layer 120 is positioned on the substrate 100 to cover the semiconductor layer 131 and the substrate 100 . The gate insulating layer 120 may be an inorganic insulating layer including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiONx), or the like.

A gate electrode 124 is positioned on the gate insulating layer 120 . The gate electrode 124 may include a metal or a metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), silver (Ag), chromium (Cr), tantalum (Ta), or titanium (Ti). and may be composed of a single layer or multiple layers. A region of the semiconductor layer 131 that overlaps with the gate electrode 124 in plan may be a channel region.

The interlayer insulating layer 160 is positioned on the substrate 100 to cover the gate electrode 124 and the gate insulating layer 120 . The interlayer insulating layer 160 may include an inorganic insulating layer including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiONx), or the like.

The source electrode 173 and the drain electrode 175 are positioned on the interlayer insulating layer 160 . The source electrode 173 and the drain electrode 175 are respectively connected to the source region and the drain region of the semiconductor layer 131 by openings formed in the interlayer insulating layer 160 and the gate insulating layer 120 . Accordingly, the aforementioned semiconductor layer 131 , the gate electrode 124 , the source electrode 173 , and the drain electrode 175 constitute one transistor TFT. In some embodiments, the transistor TFT may include only the source region and the drain region of the semiconductor layer 131 instead of the source electrode 173 and the drain electrode 175 .

The source electrode 173 and the drain electrode 175 are aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), and molybdenum (Mo). ), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta), etc. may include a metal or a metal alloy, and may be composed of a single layer or multiple layers. The source electrode 173 and the drain electrode 175 according to an embodiment may include a triple layer including an upper layer, an intermediate layer, and a lower layer, the upper and lower layers may include titanium (Ti), and the intermediate layer may include aluminum. (Al) may be included.

A lower planarization layer 180 is positioned on the source electrode 173 and the drain electrode 175 . The lower planarization layer 180 is positioned on the substrate 100 to cover the source electrode 173 , the drain electrode 175 , and the interlayer insulating layer 160 . The lower planarization layer 180 is for planarizing the surface of the substrate 100 provided with the transistor TFT, and the lower planarization layer 180 may be an organic insulating layer, and may include polyimide, polyamide, acrylic resin, or benzocyclone. It may include one or more materials selected from the group consisting of butenes and phenolic resins.

A pixel electrode 191 is positioned on the lower planarization layer 180 . The pixel electrode 191 is also referred to as an anode electrode, and may be formed of a single layer including a transparent conductive oxide film and a metal material or a multilayer including the same. The transparent conductive oxide film may include Indium Tin Oxide (ITO), poly-ITO, Indium Zinc Oxide (IZO), Indium Gallium Zinc Oxide (IGZO), Indium Tin Zinc Oxide (ITZO), and the like, and the metal material is It may include silver (Ag), molybdenum (Mo), copper (Cu), gold (Au), and aluminum (Al).

The lower planarization layer 180 includes a via hole 81 or an opening for exposing the drain electrode 175 , and the drain electrode 175 and the pixel electrode 191 through the via hole 81 of the lower planarization layer 180 . ) can be physically and electrically connected. Accordingly, the pixel electrode 191 may receive an output current to be transferred from the drain electrode 175 to the emission layer 350 .

A barrier rib 370 is positioned on the lower planarization layer 180 . The barrier rib 370 is also referred to as a pixel defining layer (PDL) and includes a pixel opening 351 through which a portion of the upper surface of the pixel electrode 191 is exposed. The pixel opening 351 of the barrier rib 370 may partition a formation position of the emission layer 350 so that the emission layer 350 may be located in a portion exposed on the upper surface of the pixel electrode 191 . The partition wall 370 may be an organic insulating layer including at least one material selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin. Also, according to an embodiment, the barrier rib 370 may be formed of a black pixel defined layer (PDL) having a black color.

The emission layer 350 is positioned in the pixel opening 351 partitioned by the partition wall 370 . The emission layer 350 may include an organic material that emits red, green, and blue light. The emission layer 350 emitting red, green, and blue light may include a low molecular weight or high molecular weight organic material. Although the light emitting layer 350 is illustrated as a single layer in FIG. 3 , in reality, auxiliary layers such as an electron injection layer, an electron transport layer, a hole transport layer, and a hole injection layer may be included above and below the light emitting layer 350 , and the light emitting layer A hole injection layer and a hole transport layer may be positioned under the 350 , and an electron transport layer and an electron injection layer may be positioned on the light emitting layer 350 .

A common electrode 270 is positioned on the barrier rib 370 and the emission layer 350 . The common electrode 270 is also referred to as a cathode electrode, and includes indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), and the like, and is formed of a transparent conductive layer. can be Also, the common electrode 270 may have a translucent characteristic, and in this case, a microcavity may be formed together with the pixel electrode 191 . According to the microcavity structure, light of a specific wavelength is emitted upward by the spacing and characteristics between the electrodes, and as a result, red, green, or blue can be displayed.

An encapsulation layer 400 is positioned on the common electrode 270 . The encapsulation layer 400 includes at least one inorganic layer and at least one organic layer, and in this embodiment includes a first inorganic encapsulation layer 410 , an organic encapsulation layer 420 , and a second inorganic encapsulation layer 430 . do. The first inorganic encapsulation layer 410 , the organic encapsulation layer 420 , and the second inorganic encapsulation layer 430 may be positioned in portions of the display area DA and the non-display area NA, and in some embodiments, The organic encapsulation layer 420 is formed around the display area DA, and the first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 may be formed up to the non-display area NA. The encapsulation layer 400 is to protect the light emitting device (LED) from moisture or oxygen that may be introduced from the outside, and one end of the first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 is directly It can be formed to be in contact. Also, according to an embodiment, the encapsulation layer 400 may include a structure in which an inorganic layer and an organic layer are sequentially further stacked.

A sensing insulating layer 510 , a plurality of sensing electrodes 520 and 540 , a sensing electrode connection unit 541 , and an inorganic protective layer 505 are positioned on the encapsulation layer 400 .

In an embodiment, the sensing insulating layer 510 , the sensing electrode connection part 541 , and the plurality of sensing electrodes 520 and 540 may constitute a sensing sensor, and the sensing sensor is a resistive type, capacitive It may be classified into a capacitive type, an electro-magnetic type, an optical type, and the like. The detection sensor according to an embodiment uses a capacitive sensor. A buffer layer (refer to 501 of FIG. 12 ) including an inorganic material may be positioned between the sensing electrode connection part 541 , the sensing insulating layer 510 , and the encapsulation layer 400 .

A sensing electrode connection part 541 is formed on the encapsulation layer 400 , and a sensing insulating layer 510 covering it is positioned on the sealing layer 400 . The sensing insulating layer 510 may be an inorganic insulating layer, and may include an organic material according to an embodiment. The inorganic material included in the inorganic insulating layer may be at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, or silicon oxynitride. have. The organic material may be at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, and perylene resin.

A plurality of sensing electrodes 520 and 540 are positioned on the sensing insulating layer 510 , and the first sensing electrode 520 and the second sensing electrode 540 are electrically insulated. The sensing insulating layer 510 includes an opening exposing the upper surface of the sensing electrode connection part 541 , and the sensing electrode connection part 541 is connected to the second sensing electrode 540 through the opening of the sensing insulating layer 510 . Two adjacent second sensing electrodes 540 are electrically connected. Meanwhile, the first sensing electrode connection part 521 connecting the first sensing electrode 520 is formed on the same layer as the first sensing electrode 520 and the second sensing electrode 540 .

The plurality of sensing electrodes 520 and 540 may include a conductive material having good conductivity. For example, the plurality of sensing electrodes 520 and 540 may include aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), and molybdenum. It may include a metal or a metal alloy such as (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta), and may be composed of a single layer or multiple layers. In this case, the plurality of sensing electrodes 520 and 540 may include openings to allow light emitted from the light emitting diodes to be emitted upward without interference. According to an embodiment, the plurality of sensing electrodes 520 and 540 may be configured as a triple layer including an upper layer, an intermediate layer, and a lower layer, the upper and lower layers may include titanium (Ti), and the middle layer may include aluminum (Al). may include.

An inorganic passivation layer 505 covering the plurality of sensing electrodes 520 and 540 and the sensing insulating layer 510 is positioned on the plurality of sensing electrodes 520 and 540 . The inorganic passivation layer 505 is also formed on the pad electrode to prevent damage applied to the pad electrode in a subsequent process (eg, a color filter process, etc.) during the process of forming the pad electrode. The inorganic passivation layer 505 and the pad electrode will be described in detail below with reference to FIG. 5 .

Referring to FIG. 4 , a cross-sectional structure of the first sensing electrode 520 among the plurality of sensing electrodes 520 and 540 is illustrated in detail.

According to an embodiment, the first sensing electrode 520 positioned on the sensing insulating layer 510 includes an upper layer 520a, an intermediate layer 520b, and a lower layer 520c. According to an exemplary embodiment, the upper layer 520a and the lower layer 520c of the first sensing electrode 520 include titanium (Ti), and the middle layer 520b includes aluminum (Al). The thickness d2 of the upper layer 520a may be 48.19 nm, the thickness d3 of the middle layer 520b may be 302.9 nm, and the thickness d4 of the lower layer 520c may be 48.19 nm.

An inorganic passivation layer 505 is positioned on the sensing insulating layer 510 and the first sensing electrode 520 , and the thickness d1 of the inorganic passivation layer 505 may be 82.62 nm. The inorganic passivation layer 505 may remain without being etched in the display area DA and/or the sensing area TA, but in the non-display area NA and/or the peripheral area PA, which will be described later, by a dry etching process The inorganic protective layer 505 may be removed.

A light blocking member 220 and color filter layers 230R, 230G, and 230B are positioned on the inorganic passivation layer 505 .

The light blocking member 220 may be positioned to overlap the sensing electrodes 520 and 540 in plan view, and may be positioned so as not to overlap the light emitting layer 350 in plan view. This is to prevent the light emitting layer 350 capable of displaying an image from being covered by the light blocking member 220 and the sensing electrodes 520 and 540 .

The color filter layers 230R, 230G, and 230B are positioned on the inorganic passivation layer 505 and the light blocking member 220 . The color filter layers 230R, 230G, and 230B include a red color filter 230R that transmits red light, a green color filter 230G that transmits green light, and a blue color filter that transmits blue light. A filter 230B is included. Each of the color filters 230R, 230G, and 230B may be positioned to overlap the light emitting layer 350 of the light emitting device in plan view. The emission layer 350 overlapping the red color filter 230R may emit red light, the emission layer 350 overlapping the green color filter 230G may emit green light, and overlapping the blue color filter 230B. The light emitting layer 350 may emit blue light. The light blocking member 220 may be positioned between each of the color filters 230R, 230G, and 230B. According to an embodiment, the color filter layers 230R, 230G, and 230B may be replaced with a color conversion layer or may further include a color conversion layer. The color conversion layer may include quantum dots.

An upper planarization layer 550 covering the color filter layers 230R, 230G, and 230B is positioned on the color filter layers 230R, 230G, and 230B. The upper planarization layer 550 is for planarizing the upper surface of the light emitting display device, and the upper planarization layer 550 includes one or more materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin. It may be an organic insulating layer including.

Hereinafter, with reference to FIGS. 5 to 7 , the pad part 30 of the light emitting display device will be described with a focus on a cross-sectional view in the non-display area NA of the light emitting display device.

5 is a partial view of a pad part in the light emitting display device according to an exemplary embodiment, FIG. 6 is a cross-sectional view taken along line VI-VI' in FIG. 5 , and FIG. 7 is a detailed view of part B in FIG. 6 .

The pad part 30 shown in FIG. 5 may correspond to the pad part 30 of FIG. 1 , and the stacking order of the light emitting display devices shown in FIGS. 6 and 7 may correspond to the light emitting display device of FIG. 3 . .

5 to 7 , the pad PAD includes lower pad electrodes 170 and 171 and upper pad electrodes 530 and 531 .

The lower pad electrodes 170 and 171 are positioned on the interlayer insulating layer 160 . The lower pad electrodes 170 and 171 include a first lower pad electrode 170 and a second lower pad electrode 171 that are spaced apart from each other. The lower pad electrodes 170 and 171 may be positioned on the same layer as the source electrode 173 and the drain electrode 175 of FIG. 3 and may be formed of the same material and by the same process. The lower pad electrodes 170 and 171 include aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), molybdenum (Mo), and tungsten. (W), titanium (Ti), chromium (Cr), may include a metal or a metal alloy such as tantalum (Ta), may be composed of a single layer or multiple layers.

In an embodiment, the lower pad electrodes 170 and 171 may be formed of a triple layer. Also, in an embodiment, one end of the lower pad electrodes 170 and 171 may include a tapered shape.

7 shows the lower pad electrodes 170 and 171 having a triple layer including an upper layer 170a, an intermediate layer 170b, and a lower layer 170c. The upper and lower layers 170a and 170c of the lower pad electrodes 170 and 171 may include titanium (Ti), and the intermediate layer 170b may include aluminum (Al).

A lower planarization layer 180 is positioned on the lower pad electrodes 170 and 171 to cover the lower pad electrodes 170 and 171 and the substrate 100 . The lower planarization layer 180 includes an opening 51 to expose at least a portion of upper surfaces of the lower pad electrodes 170 and 171 , and the first lower pad electrode 170 and the second lower pad electrode 171 are spaced apart from each other. ) has a structure in which the lower planarization layer 180 is located. The lower planarization layer 180 may be an organic insulating layer, and may include one or more materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin. In some embodiments, other organic or inorganic insulating layers positioned above the source electrode 173 and the drain electrode 175 may be used instead of the lower planarization layer 180 . An example may be the sensing insulating layer 510 .

Upper pad electrodes 530 and 531 are positioned on the lower pad electrodes 170 and 171 . In addition, the upper pad electrodes 530 and 531 are formed in the opening 51 of the lower planarization layer 180 and overlap at least a portion of the upper surface of the lower planarization layer 180 . The upper pad electrodes 530 and 531 include a first upper pad electrode 530 and a second upper pad electrode 531 that are spaced apart from each other.

The upper pad electrodes 530 and 531 may be disposed on the same layer as the plurality of sensing electrodes 520 and 540 of FIG. 3 and may be formed of the same material and by the same process. The upper pad electrodes 530 and 531 include aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), molybdenum (Mo), and tungsten. (W), titanium (Ti), chromium (Cr), may include a metal or a metal alloy such as tantalum (Ta), may be composed of a single layer or multiple layers.

The lower planarization layer 180 includes an opening 51 through which top surfaces of the lower pad electrodes 170 and 171 are exposed, and the upper pad electrodes 530 and 531 and The lower pad electrodes 170 and 171 may be in contact with each other and may be physically and electrically connected to each other. The upper surface of the lower planarization layer 180 may be exposed to the outside except for a portion where the upper pad electrodes 530 and 531 and the lower pad electrodes 170 and 171 contact each other.

In the embodiment of FIG. 7 , upper pad electrodes 530 and 531 formed of a triple layer including an upper layer 530a, an intermediate layer 530b, and a lower layer 530c are illustrated. The upper layer 530a and the lower layer 530c of the upper pad electrodes 530 and 531 may include titanium (Ti), and the intermediate layer 530b may include aluminum (Al).

Since FIG. 7 only shows part B of FIG. 6 , the lower planarization layer 180 shown in FIG. 7 corresponds to a portion of the lower planarization layer 180 positioned between the plurality of pad electrodes. The lower planarization layer 180 includes an exposed portion 185 through which the upper surface of the lower planarization layer 180 is exposed and an overlapping portion 186 partially overlapping with the upper pad electrodes 530 and 531 .

7 , the upper surface of the overlapping portion 186 covered by the upper pad electrodes 530 and 531 among the upper surfaces of the lower planarization layer 180 and the upper surface of the exposed exposed portion 185 have different heights from each other. can have That is, the height h1 of the upper surface of the exposed portion 185 of the lower planarization layer 180 may be lower than the height h2 of the upper surface of the overlapping portion 186 . The exposed portion 185 of the lower planarization layer 180 may be electrically connected to a pad of a flexible printed circuit board (FPCB).

The structure of the lower planarization layer 180 may be formed by a deposition process of the inorganic passivation layer 505 added to reduce damage to the upper pad electrodes 530 and 531 and a subsequent etching process.

Accordingly, in the light emitting display device according to the exemplary embodiment, the upper pad electrodes 530 and 531 are formed and the inorganic passivation layer 505 is deposited on the upper pad electrodes 530 and 531 in subsequent processes such as the color filter forming process. Damage to the upper pad electrodes 530 and 531 that may occur may be reduced.

Hereinafter, with reference to FIGS. 8 to 11 , the height of the lower planarization layer 180 of FIG. 7 may vary, and a manufacturing method for reducing damage that may occur in the upper pad electrodes 530 and 531 will be described. Let's look at it in detail.

8 to 11 schematically illustrate a method of manufacturing a pad in a method of manufacturing a light emitting display device according to an exemplary embodiment.

8 to 11 may correspond to a non-display area of the light emitting display device described with reference to FIG. 7 .

Referring to FIG. 8 , a light emitting display device in which a gate insulating layer 120 and an interlayer insulating layer 160 are sequentially stacked on a substrate 100 in a non-display area NA is provided.

Referring back to FIG. 3 , in the display area DA, the gate insulating layer 120 and the interlayer insulating layer 160 may be sequentially formed on the substrate 100 .

The lower pad electrodes 170 and 171 of the non-display area NA may be formed on the same layer as the source electrode 173 and the drain electrode 175 of the display area DA using the same material and the same method. That is, when the source electrode 173 and the drain electrode 175 are formed on the interlayer insulating layer 160 in the display area DA, the lower pad electrodes 170 and 171 are formed on the interlayer insulating layer 160 in the non-display area NA. ) can be formed. In this embodiment, the source electrode 173 , the drain electrode 175 , and the lower pad electrodes 170 and 171 may have the same triple-layer structure.

Thereafter, a lower planarization layer 180 covering the source electrode 173 , the drain electrode 175 , and the lower pad electrodes 170 and 171 is formed. An etching process may be performed to form an opening in the formed lower planarization layer 180 . and an opening formed in the lower planarization layer 180 includes an opening 51 exposing at least a portion of the lower pad electrodes 170 and 171 .

Thereafter, a process of forming the upper pad electrodes 530 and 531 may be performed on the pad portion 30 of the non-display area NA. The upper pad electrodes 530 and 531 of the non-display area NA may be formed on the same layer as the sensing electrodes 520 and 540 of the display area DA using the same material and the same process. That is, when the sensing electrodes 520 and 540 are formed in the display area DA, the upper pad electrodes 530 and 531 are formed on the lower planarization layer 180 in the pad part 30 of the non-display area NA. can do. A process of forming a plurality of layers is further included between the process of forming the lower planarization layer 180 in the display area DA and the process of forming the sensing electrodes 520 and 540 . In the pad part 30 , this process may not be performed, or may be removed by etching after it is performed.

In the non-display area NA, the lower planarization layer 180 positioned between the upper pad electrodes 530 and 531 and the lower pad electrodes 170 and 171 is the same as the lower planarization layer 180 of the display area DA. As such, it may be formed from the same material and the same process. Also, the lower planarization layer 180 may be formed over the display area DA and the non-display area NA.

As shown in FIG. 8 , the height of the upper surface of the lower planarization layer 180 positioned between the lower pad electrodes 170 and 171 may be constant until the process of forming the upper pad electrodes 530 and 531 . That is, the height h4 of the upper surface of the overlapping portion 186 of the lower planarization layer 180 overlapping the upper pad electrodes 530 and 531 and the exposed upper surface of the exposed portion 185 of the lower planarization layer 180 are high. (h3) may be the same. However, in some embodiments, when the upper pad electrodes 530 and 531 are etched, the exposed portion 185 of the lower planarization layer 180 may be partially etched to have a low height.

Referring to FIG. 9 , an inorganic passivation layer 505 is formed on the upper pad electrodes 530 and 531 and the lower planarization layer 180 to cover the upper pad electrodes 530 and 531 and the lower planarization layer 180 . The inorganic passivation layer 505 may also cover the sensing electrodes 520 and 540 of the display area DA and may be positioned over the display area DA and the non-display area NA.

Referring back to FIG. 3 , after forming the inorganic passivation layer 505 in the display area DA, a process of forming the light blocking member 220 and the color filter layer 230 on the inorganic passivation layer 505 may be performed. Thereafter, a process of forming the upper planarization layer 550 on the color filter layer 230 may be performed. However, since the light blocking member 220 , the color filter layer 230 , and the upper planarization layer 550 are not formed in the pad part 30 of the non-display area NA, the inorganic passivation layer 505 as shown in FIG. 9 . It can be left positioned on top. The inorganic passivation layer 505 protects the upper pad electrodes 530 and 531 in the process of forming and removing the light blocking member 220 , the color filter layer 230 , and the upper planarization layer 550 .

Since the upper pad electrodes 530 and 531 are electrically connected to the pads of the flexible printed circuit board (FPCB), they must be exposed to the outside. Therefore, the process of removing the inorganic passivation layer 505 should be further performed.

Referring to FIG. 10 , an etching process is performed to expose the upper pad electrodes 530 and 531 . Here, the etching process uses a dry etching process. The dry etching process may be performed in a vacuum chamber, and the inorganic passivation layer 505 may be removed using an etching gas such as _{chlorine (Cl 2} ), oxygen (O _{2 ), or argon (Ar).}

The inorganic passivation layer 505 of the non-display area NA may be removed by the dry etching process. On the other hand, in the display area DA, the layer that is protected by the upper planarization layer 550 including the organic insulating material and is positioned under the upper planarization layer 550 is not etched. Accordingly, as shown in FIGS. 3 and 4 , the inorganic passivation layer 505 may remain on the sensing electrodes 520 and 540 in the display area.

Referring to FIG. 11 , the inorganic passivation layer 505 is removed on the upper pad electrodes 530 and 531 by the dry etching process, and the lower planarization layer 180 is positioned between the lower pad electrodes 170 and 171 . top surface is exposed. A pad of a flexible printed circuit board (FPCB) is attached on the exposed upper pad electrodes 530 and 531 , and a voltage may be applied from the outside.

The exposed upper surface of the exposed portion 185 of the lower planarization layer 180 may have a different height from the upper surface of the overlapping portion 186 covered by the upper pad electrodes 530 and 531 by a dry etching process. That is, the height h1 of the exposed portion 185 of the lower planarization layer 180 may be lower than the height h2 of the overlapping portion 186 . The structure of the lower planarization layer 180 may occur in a process of removing the inorganic passivation layer 505 added to reduce damage to the upper pad electrodes 530 and 531 . In some embodiments, when etching to complete the upper pad electrodes 530 and 531 , the exposed portion 185 of the lower planarization layer 180 is etched first, and then in the process of removing the inorganic passivation layer 505 , 2 It may have a low height as it is etched by car.

Accordingly, in the light emitting display device according to an embodiment, the upper pad electrodes 530 and 531 are formed, and the inorganic passivation layer 505 is deposited on the upper pad electrodes 530 and 531 , so that an upper portion that may be generated in the color filter forming process is formed. Damage to the pad electrodes 530 and 531 may be reduced.

In the embodiment of FIG. 3 , an embodiment in which there is no buffer layer between the sensing sensor and the encapsulation layer 400 , that is, between the sensing electrode connection part 541 and the sensing insulating layer 510 and the encapsulation layer 400 has been described.

However, depending on the embodiment, the buffer layer 501 may be further included between the detection sensor and the encapsulation layer 400 , and an embodiment in which the buffer layer 501 is included will be described with reference to FIG. 12 .

12 is a cross-sectional view illustrating a portion of a display area in a light emitting display device according to an exemplary embodiment.

FIG. 12 is generally the same as that of FIG. 3 , but has a difference in that a buffer layer 501 is further formed on the encapsulation layer 400 .

The buffer layer 501 may be formed of an inorganic insulating layer, and inorganic materials included in the inorganic insulating layer include silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, and tin oxide. , it may be at least one of cerium oxide or silicon oxynitride.

A sensing insulating layer 510 , a sensing electrode connection part 541 , and a plurality of sensing electrodes 520 and 540 are formed on the buffer layer 501 .

Also in the embodiment of FIG. 12 , the source electrode 173 and the drain electrode 175 may be configured as a triple layer including an upper layer, an intermediate layer, and a lower layer, and the upper and lower layers may include titanium (Ti), and the intermediate layer is It may include aluminum (Al). In addition, the plurality of sensing electrodes 520 and 540 may be configured as a triple layer including an upper layer, an intermediate layer, and a lower layer, the upper and lower layers may include titanium (Ti), and the middle layer may include aluminum (Al). can do.

As shown in FIG. 12 , due to the buffer layer 501 formed in the display area TA, the layered structure of the pad part 30 may also be changed, which will be described with reference to FIG. 13 .

13 is a cross-sectional view illustrating a portion of a pad in a light emitting display device according to an exemplary embodiment.

The structure of FIG. 13 is different from that of FIG. 7 in that a buffer layer 501 is further included. 13 , the exposed portion of the buffer layer 501 may have a thinner thickness h5 than the portion covered by the upper pad electrodes 530 and 531 .

Such a difference in the thickness of the buffer layer 501 is generated as the upper surface of the buffer layer 501 exposed during the process of removing the inorganic passivation layer 505 formed to protect the upper pad electrodes 530 and 531 is partially etched. .

In FIG. 13 , the buffer layer 501 is positioned between the lower pad electrode 170 and the upper pad electrode 530 so that they are not electrically connected to each other. ), so that the lower pad electrode 170 and the upper pad electrode 530 are electrically connected to each other. This is because the lower pad electrode 170 and the upper pad electrode 530 must be electrically connected to each other to form the pad.

Also, in some embodiments, the height of the upper surface of the lower planarization layer 180 may be constant. That is, the height h4 of the upper surface of the overlapping portion 186 of the lower planarization layer 180 overlapping the upper pad electrodes 530 and 531 and the exposed upper surface of the exposed portion 185 of the lower planarization layer 180 are high. (h3) may be the same.

Hereinafter, with reference to FIGS. 14 and 15 , the pad structure of the embodiment according to FIG. 13 and the pad structure in the comparative example will be compared.

14 is a cut-away image of a portion of a pad in the light emitting display device according to an exemplary embodiment, and FIG. 15 is a cutaway image of a pad in the light emitting display device according to the comparative example.

14 and 15, a bright color layer is also shown on top of the upper pad electrode 530, which is a coating layer additionally coated in order to take an image as in FIGS. 14 and 15, and is actually an upper pad electrode ( 530) has a structure exposed to be electrically connected to other pads.

14 and 15 , in the light emitting display device according to the embodiment and comparative example of FIG. 13 , the interlayer insulating layer 160 , the lower pad electrode 170 , the lower planarization layer 180 , and the buffer layer ( 501 , and a portion of the upper pad electrode 530 are shown.

The lower planarization layer 180 is positioned between the adjacent lower pad electrode 170 and the adjacent upper pad electrode 530 , and each of the lower pad electrode 170 and the upper pad electrode 530 is configured as a triple layer.

The upper pad electrode 530 and the lower pad electrode 170 may be a triple layer including a titanium (Ti) layer, an aluminum (Al) layer, and a titanium (Ti) layer. It includes a layer and an aluminum (Al) layer marked in thick and dark between them.

An interlayer insulating layer 160 is positioned under the lower pad electrode 170 , and a buffer layer 501 is positioned in a portion between the lower pad electrode 170 and the upper pad electrode 530 .

The interlayer insulating layer 160 may be entirely formed in the display area DA and the non-display area NA.

Although the buffer layer 501 is illustrated as being positioned between the lower pad electrode 170 and the upper pad electrode 530 , it may be positioned only in a part of the pad, and in the portion extending to the right of FIG. 14 , the lower pad electrode 170 . ) and the upper pad electrode 530 may be in direct contact. That is, since the lower pad electrode 170 and the upper pad electrode 530 must be electrically connected, although not shown in FIGS. 14 and 15 , an opening exists in the buffer layer 501 , so that the lower pad electrode 170 and the upper pad electrode 170 and the upper pad electrode 530 are electrically connected. The pad electrode 530 is electrically connected.

Referring to FIG. 14 , it can be confirmed that the upper surface of the upper pad electrode 530 has a smooth surface, so that there is no damage to the upper pad electrode 530 according to the present embodiment. This is because the upper pad electrodes 530 and 531 are protected in a subsequent process due to the inorganic passivation layer 505 formed on the upper pad electrodes 530 and 531 . Accordingly, in an embodiment, even when the process of forming the light blocking member 220 and the color filter layer 230 is performed, the upper pad electrode 530 may be protected.

On the other hand, in the comparative example shown in FIG. 15 , unlike FIG. 14 , the inorganic passivation layer 505 formed on the upper pad electrodes 530 and 531 is not formed, so that the upper pad electrodes 530 and 531 are exposed to subsequent processes. In this state, the light blocking member 220 and the color filter layer 230 were formed on the upper pad electrodes 530 and 531 as they were.

Accordingly, in the comparative example shown in FIG. 15 , after forming the upper pad electrodes 530 and 531 in the non-display area and the sensing electrodes 520 and 540 in the display area, the light blocking member ( ) is formed on the sensing electrodes 520 and 540 . 220 ) and the upper pad electrode 530 are damaged in the process of forming the color filter layer 230 .

Referring to FIG. 15 , it can be seen that the upper surface of the upper pad electrode 530 has a non-smooth upper surface due to damage. Damage such as lifting and generation of tips may occur in the upper layer of the upper pad electrode 530 , the metal of the intermediate layer may be eroded, and the contact performance of the pad electrode may be deteriorated. For example, the upper and lower layers of the upper pad electrode 530 according to the comparative example may include titanium (Ti), and the middle layer may include aluminum (Al), and titanium (Ti) is damaged. Accordingly, aluminum (Al) may be eroded.

On the other hand, referring to FIG. 14 , in the display device according to an exemplary embodiment, since the metal layer of the upper pad electrode 530 may be protected during the process by the inorganic passivation layer 505 , the performance of the pad electrode may be maintained.

Hereinafter, a cross-sectional structure of the pad part 30 different from that of FIG. 13 in the embodiment in which the buffer layer 501 is further formed on the encapsulation layer 400 as shown in FIG. 12 will be additionally described.

16 and 17 are cross-sectional views illustrating a portion of a pad in a light emitting display device according to an exemplary embodiment.

First, FIG. 16 shows a structure in which the lower planarization layer 180 is exposed while all of the buffer layer 501 exposed between the upper pad electrodes 530 and 531 is etched, unlike in FIG. 13 . In this case, the upper surface of the lower planarization layer 180 may be additionally etched. That is, looking at portion X of FIG. 16 , the upper surface of the overlapping portion 186 covered by the upper pad electrodes 530 and 531 among the upper surfaces of the lower planarization layer 180 and the upper surface of the exposed exposed portion 185 are different from each other. can have a height. The height h1 of the upper surface of the exposed portion 185 of the lower planarization layer 180 may be lower than the height h2 of the upper surface of the overlapping portion 186 .

In the embodiment of FIG. 16 as well, since the inorganic protective layer 505 is formed on the upper pad electrodes 530 and 531, damage ( damage) can be reduced.

Meanwhile, in some embodiments, the pad part 30 may not include the lower planarization layer 180 between the plurality of pad electrodes. When the lower planarization layer 180 is positioned between the plurality of pad electrodes, it is good to eliminate the problem of being electrically shorted and connected between the adjacent pad electrodes, but the gap between the adjacent pad electrodes cannot be reduced below a certain level. there is That is, as the resolution increases, the gap between the pad part 30 and the pad electrode needs to be reduced, so that the pad part 30 not including the lower planarization layer 180 may be formed.

Hereinafter, a cross-sectional structure of the pad part that does not include the lower planarization layer 180 between the pad electrodes will be described with reference to FIG. 17 .

Referring to FIG. 17 , lower pad electrodes 170 and 171 and upper pad electrodes 530 and 531 each having a triple layer are formed on the interlayer insulating layer 160 , and the lower pad electrodes 170 and 171 and the upper pad are formed. A buffer layer 501 is formed between the electrodes 530 and 531 .

The buffer layer 501 is formed on the upper surfaces and tapered side surfaces of the lower pad electrodes 170 and 171 , and is also formed on the exposed interlayer insulating layer 160 . However, the portion formed on the exposed interlayer insulating layer 160 may have a thickness h5 thinner than that of other portions. This is because the buffer layer 501 may be partially etched while etching to remove the inorganic passivation layer 505 formed to protect the upper pad electrodes 530 and 531 from damage.

Accordingly, in the light emitting display device according to the embodiment of FIG. 17 , the upper pad electrodes 530 and 531 are formed, and the inorganic passivation layer 505 is deposited on the upper pad electrodes 530 and 531 , thereby Damage to the upper pad electrodes 530 and 531 that may occur in the process may be reduced.

In FIG. 17 as well, the buffer layer 501 is positioned between the lower pad electrode 170 and the upper pad electrode 530 so that they are not electrically connected to each other. ), so that the lower pad electrode 170 and the upper pad electrode 530 are electrically connected to each other. This is because the lower pad electrode 170 and the upper pad electrode 530 must be electrically connected to each other to form the pad.

Meanwhile, in some embodiments, the buffer layer 501 may not be positioned between the pad electrodes, unlike in FIG. 17 . That is, in the process of etching the inorganic passivation layer 505 , the buffer layer 501 exposed between the pad electrodes may be completely etched. In this case, an exposed portion of the interlayer insulating layer 160 positioned below the inorganic passivation layer 505 may be additionally etched.

Hereinafter, a cross-sectional structure of the pad part according to the embodiment of FIG. 18 will be described.

18 is a cross-sectional view illustrating a portion of a pad in a light emitting display device according to an exemplary embodiment.

In the embodiment of FIG. 18 , the lower planarization layer 180 is not included between the pad electrodes, and unlike FIG. 17 , the buffer layer 501 is not included.

In the embodiment of FIG. 18 , since the lower planarization layer 180 is not included, as in FIG. 17 , a gap between adjacent pad electrodes can be reduced. In addition, since the buffer layer 501 is not formed between the lower pad electrodes 170 and 171 and the upper pad electrodes 530 and 531 , the lower pad electrode 170 is not formed using a mask in the buffer layer 501 . , 171) and the upper pad electrodes 530 and 531 are directly connected to each other.

In the embodiment of FIG. 18 as well, a subsequent process such as a color filter forming process is performed in a state in which an inorganic protective layer 505 is deposited on the upper pad electrodes 530 and 531 to protect the upper pad electrodes 530 and 531, and the upper pad electrode is disposed on the upper pad electrode. (530, 531) damage (Damage) can be reduced.

In the process of removing the inorganic protective layer 505 , an exposed portion of the interlayer insulating layer 160 may be additionally etched.

Meanwhile, an additional insulating layer may be further formed on the exposed interlayer insulating layer 160 of FIG. 18 , and as an example, the light blocking member 220 may be positioned as shown in FIG. 19 .

A cross-sectional structure of the display area DA corresponding to the exemplary embodiment of FIG. 18 may be the same as that of FIG. 3 .

Hereinafter, a structure and a manufacturing method of a pad in the light emitting display device according to an exemplary embodiment will be described with reference to FIGS. 19 to 23 .

19 is a cross-sectional view illustrating a portion of a pad in a light emitting display device according to an exemplary embodiment, and FIGS. 20 to 23 schematically illustrate a method of manufacturing a pad in a method of manufacturing a light emitting display device according to an exemplary embodiment.

Since FIGS. 19 to 23 are similar to FIGS. 7 to 11 , differences will be mainly described below. Also, the structures shown in FIGS. 19 to 23 may correspond to the region B described with reference to FIG. 6 .

Referring to FIG. 19 , a first pad electrode and a second pad electrode spaced apart to be adjacent to each other are positioned on the interlayer insulating layer 160 . The first pad electrode includes a first lower pad electrode 170 and a first upper pad electrode 530 , and the second pad electrode includes a second lower pad electrode 171 and a second upper pad electrode 531 . do.

A distance W1 from one end of the first lower pad electrode 170 to one end of the second lower pad electrode 171 may be 10 μm to 20 μm. Specifically, it may be 15 μm.

The lower pad electrodes 170 and 171 may be formed of a triple layer. The upper and lower layers 170a and 170c of the lower pad electrodes 170 and 171 may include titanium (Ti), and the intermediate layer 170b may include aluminum (Al).

Lower planarization layers 180 and 181 are positioned on the lower pad electrodes 170 and 171 . The lower planarization layers 180 and 181 are positioned to at least partially overlap the lower pad electrodes 170 and 171 that are spaced apart from each other, respectively, and have a structure to cover one end of the lower pad electrodes 170 and 171 . The lower planarization layers 180 and 181 may include a first lower planarization layer 180 and a second lower planarization layer 181 spaced apart from each other. That is, the first lower planarization layer 180 is positioned between the first lower pad electrode 170 and the first upper pad electrode 530 , is positioned to partially cover the first lower pad electrode 170 , and the second lower part is positioned to partially cover the first lower pad electrode 170 . The planarization layer 181 is positioned between the second lower pad electrode 171 and the second upper pad electrode 531 , and is positioned to partially cover the second lower pad electrode 171 .

Upper pad electrodes 530 and 531 are positioned on the lower pad electrodes 170 and 171 and the lower planarization layers 180 and 181 . The upper pad electrodes 530 and 531 include a first upper pad electrode 530 and a second upper pad electrode 531 that are spaced apart from each other.

The upper pad electrodes 530 and 531 may be positioned to at least partially overlap the lower pad electrodes 170 and 171 and the lower planarization layers 180 and 181 . The upper layer 530a and the lower layer 530c of the upper pad electrodes 530 and 531 may include titanium (Ti), and the intermediate layer 530b may include aluminum (Al).

The upper pad electrodes 530 and 531 include a flat portion 535 in direct contact with the lower pad electrodes 170 and 171 and a convex portion 536 in direct contact with the lower planarization layers 180 and 181 .

A distance W2 from one end of the first upper pad electrode 530 to one end of the second upper pad electrode 531 may be 10 μm or less. Specifically, it may be 5 μm. As the distance between the neighboring upper pad electrodes 530 and 531 increases, the resolution of the display device may decrease. As the distance between the neighboring upper pad electrodes 530 and 531 decreases, the resolution of the display device may increase. Also, by not matching one end of the upper pad electrodes 530 and 531 with one end of the lower pad electrodes 170 and 171 , the step difference of the pad portion can be reduced.

The light blocking member 220 is positioned between the first upper pad electrode 530 and the second upper pad electrode 531 . Referring back to FIG. 5 , the light blocking member 220 is positioned between adjacent pad electrodes.

The light blocking member 220 is positioned to cover a portion of the first upper pad electrode 530 and the second upper pad electrode 531 , and the light blocking member 220 contacts one end of the upper pad electrodes 530 and 531 . can be located The upper surface of the light blocking member 220 may be positioned to be higher than the upper surface of the flat portion 535 of the upper pad electrodes 530 and 531 by about 0.7 μm (h6 of FIG. 19 ).

Accordingly, in the light emitting display device according to an exemplary embodiment, since the ends of the upper pad electrodes 530 and 531 may be protected by the light blocking member 220 , the upper pad electrodes 530 and 531 are formed, and the color filter is formed. Damage to the upper pad electrodes 530 and 531 that may occur in the process may be reduced. Therefore, in the embodiment of FIG. 19 , the inorganic passivation layer 505 may not be deposited on the upper pad electrodes 530 and 531 . However, according to an exemplary embodiment, an inorganic passivation layer 505 may be further deposited on the upper pad electrodes 530 and 531 . In this case, the inorganic passivation layer 505 is further deposited under the light blocking member 220 of FIG. 19 . can be formed.

Hereinafter, a method of manufacturing the pad structure of FIG. 19 will be sequentially described with reference to FIGS. 20 to 23 .

Referring to FIG. 20 , a gate insulating layer 120 and an interlayer insulating layer 160 are sequentially stacked on the non-display area NA of the substrate 100 .

The first lower pad electrode 170 and the second lower pad electrode 171 are spaced apart and formed on the interlayer insulating layer 160 . When the source electrode 173 and the drain electrode 175 are formed on the interlayer insulating layer 160 in the display area DA, the lower pad electrodes 170 and 171 are formed on the interlayer insulating layer 160 in the non-display area NA. can be formed

Referring to FIG. 21 , the first lower planarization layer 180 and the second lower planarization layer 181 are formed to overlap one end of the first lower pad electrode 170 and the second lower pad electrode 171 , respectively. The first lower planarization layer 180 and the second lower planarization layer 181 are formed to partially cover one end of the first lower pad electrode 170 and the second lower pad electrode 171 and the substrate 100 . A distance W1 between the first lower pad electrode 170 and the second lower pad electrode 171 adjacent to each other may be 15 μm. The distance between the first and second lower pad electrodes 170 and 171 may vary depending on the resolution of the display device.

Referring to FIG. 22 , upper pad electrodes 530 and 531 are formed on the lower pad electrodes 170 and 171 and the lower planarization layers 180 and 181 . That is, the first upper pad electrode 530 is formed to cover the first lower pad electrode 170 and the first lower planarization layer 180 , and the second upper pad electrode 531 is the second lower pad electrode 170 . , 171 ) and the second lower planarization layer 181 . When the sensing electrodes 520 and 540 are formed on the lower planarization layer 180 in the display area DA, the upper pad electrodes 530 and 531 are formed on the lower planarization layers 180 and 181 in the non-display area NA. can be formed

A distance W2 between the first upper pad electrode 530 and the second upper pad electrode 531 adjacent to each other may be 5 μm. The distance between the first and second upper pad electrodes 530 and 531 may vary depending on the resolution of the display device. Also, by not matching one end of the upper pad electrodes 530 and 531 with one end of the lower pad electrodes 170 and 171 , the step difference of the pad portion can be reduced.

Referring to FIG. 23 , the light blocking member 220 is formed between the first upper pad electrode 530 and the second upper pad electrode 531 . In the same process as the process of forming the light blocking member 220 on the sensing electrodes 520 and 540 in the display area DA, the light blocking member 220 in the non-display area NA may be formed. That is, the light blocking member 220 of the non-display area NA may be formed by the same material and the same method as the light blocking member 220 of the display area DA.

In the light blocking member 220 , the upper surface of the light blocking member 220 may be formed to be about 0.7 μm higher than the flat portion 535 of the upper pad electrodes 530 and 531 (refer to h6 of FIG. 23 ). A flexible printed circuit board (FPCB) or the like may be stably attached to the upper surface of 220 and the upper pad electrodes 530 and 531 , and a voltage may be applied to the pad electrode.

In addition, in the light emitting display device according to an embodiment, one end of the upper pad electrodes 530 and 531 may be protected by the light blocking member 220 , so the upper pad electrodes 530 and 531 are formed, and a color filter is formed. Damage to the upper pad electrodes 530 and 531 that may occur in the process may be reduced. Accordingly, depending on the embodiment, the inorganic passivation layer 505 may not be deposited on the upper pad electrodes 530 and 531 .

According to an embodiment, even when the buffer layer 501 is further included, the cross-sectional structure of the pad part 30 similar to that of FIG. 19 may be provided, which is illustrated in FIG. 24 .

24 is a cross-sectional view illustrating a portion of a pad in a light emitting display device according to an exemplary embodiment.

According to FIG. 24 , unlike the structure of FIG. 19 , the buffer layer 501 is positioned on the lower pad electrodes 170 and 171 and the lower planarization layers 180 and 181 , and the upper pad electrode 530 is disposed on the buffer layer 501 , 531) is located. The buffer layer 501 may not be positioned between the adjacent upper pad electrodes 530 and 531 . However, according to an exemplary embodiment, the buffer layer 501 may also be positioned between the adjacent upper pad electrodes 530 and 531 .

Referring to FIG. 24 , the upper surface of the light blocking member 220 may be formed to be higher than the flat portion 535 of the upper pad electrodes 530 and 531 (see h7 of FIG. 24 ). In the embodiment of FIG. 23 , the light blocking member ( When the upper surface of 220 is formed to be higher than the flat portion 535 of the upper pad electrodes 530 and 531 by about 0.7 μm, in the embodiment of FIG. 24 , it may be formed to be higher (about 0.4 to 0.6 μm) than this.

Hereinafter, a cross-sectional structure in the display area of the light emitting display device including the pad part according to FIGS. 19 to 24 will be described with reference to FIGS. 25 and 26 .

25 and 26 are cross-sectional views illustrating a portion of a display area in a light emitting display device according to an exemplary embodiment.

First, FIG. 25 is a cross-sectional structure of the display area DA corresponding to the pad structure of FIG. 19 , and FIG. 26 illustrates a cross-sectional structure of the display area DA corresponding to the pad structure of FIG. 24 .

First, referring to FIG. 25 , since FIG. 25 is similar to the light emitting display device of FIG. 3 described above, differences will be mainly described below.

Referring to FIG. 25 , unlike FIG. 3 , the inorganic passivation layer 505 is not formed. That is, in the display device according to the exemplary embodiment, the substrate 100 , the transistor TFT, the gate insulating layer 120 , the interlayer insulating layer 160 , the lower planarization layer 180 , the light emitting device (LED), and the encapsulation layer 400 . ) is included. In addition, the light emitting display device further includes a sensing insulating layer 510 , a plurality of sensing electrodes 520 and 540 , a light blocking member 220 , a color filter layer 230 , and an upper planarization layer 550 on the encapsulation layer 400 . and the inorganic protective film 505 is not formed.

The plurality of sensing electrodes 520 and 540 are positioned on the encapsulation layer 400 , and the light blocking member 220 is positioned directly on the plurality of sensing electrodes 520 and 540 without the inorganic passivation layer 505 . The light blocking member 220 may be positioned to overlap the sensing electrodes 520 and 540 , and may be positioned not to overlap the light emitting layer 350 .

Also, as illustrated in FIG. 19 , the light blocking member 220 may be positioned between the first upper pad electrode 530 and the second upper pad electrode 531 in the non-display area NA. The light blocking member 220 is positioned to cover a portion of the first upper pad electrode 530 and the second upper pad electrode 531 , and the light blocking member 220 is positioned to contact one end of the upper pad electrodes 530 and 531 . can do.

Accordingly, in the light emitting display device according to an exemplary embodiment, since the ends of the upper pad electrodes 530 and 531 may be protected by the light blocking member 220 , the upper pad electrodes 530 and 531 are formed, and the color filter is formed. Damage to the upper pad electrodes 530 and 531 that may occur in the process may be reduced.

Therefore, the inorganic passivation layer 505 is not formed in the display area DA.

Meanwhile, since the embodiment of FIG. 24 further includes a buffer layer 501 unlike the embodiment of FIG. 19 , the display area DA corresponding to the pad portion of FIG. 24 includes a buffer layer 501 as shown in FIG. 26 . can

Unlike FIG. 25 , in FIG. 26 , a buffer layer 501 is further included on the encapsulation layer 400 . In the embodiment of FIG. 26 , as shown in FIG. 25 , the light blocking member 220 is directly positioned on the plurality of sensing electrodes 520 and 540 without the inorganic passivation layer 505 . This is because the ends of the upper pad electrodes 530 and 531 in the pad part 30 may be protected by the light blocking member 220 , and thus damage to the upper pad electrodes 530 and 531 without including the inorganic protective layer 505 . (Damage) can be reduced.

Hereinafter, a configuration in a non-display area of a light emitting display device according to an exemplary embodiment will be described with reference to FIGS. 27 to 30 .

27 is a view illustrating a portion of a substrate including a pad part in a light emitting display device according to an exemplary embodiment, FIG. 28 is a cross-sectional view taken along line XXI-XXI' in FIG. 27, and FIGS. 29 and 30 are other views of FIG. Examples are shown.

The pad part 30 shown in FIG. 27 may correspond to the pad part 30 of FIG. 1 , and the stacking order of the light emitting display device shown in FIGS. 28 to 30 may be the same as that of the light emitting display device of FIG. 12 . have.

Referring to FIG. 27 , the plurality of pads PAD of the pad unit 30 are respectively connected to the plurality of connection wires 21 . The plurality of connection wires 21 may extend to the display area DA of FIG. 1 to be connected to devices, wires, and the like of the display area DA.

Referring to FIG. 28 , a buffer layer 501 is positioned on the substrate 100 . The buffer layer 501 may be collectively referred to as a pad inorganic insulating layer. A plurality of inorganic insulating layers, organic insulating layers, and a lower pad electrode may be positioned between the substrate 100 and the buffer layer 501 . Although not shown in the drawings, in more detail, a gate insulating layer ( 120 in FIG. 6 ) and an interlayer insulating layer ( 160 in FIG. 6 ) may be positioned on the substrate 100 , and a lower pad electrode ( FIG. 6 ) on the interlayer insulating layer 160 . 170) can be located. The lower pad electrode 170 may have a triple layer structure, and a buffer layer 501 may be positioned on the lower pad electrode 170 .

An upper pad electrode 532 is positioned on the buffer layer 501 . The upper pad electrode 532 overlaps the buffer layer 501 , and the upper surface of the buffer layer 501 is exposed at a portion where the buffer layer 501 does not overlap the upper pad electrode 532 . In an embodiment, the connection wiring 21 may be formed on the same layer as the upper pad electrode 532 or on the same layer as the lower pad electrode 170 . The upper pad electrode 532 may be collectively referred to as a pad electrode, and may be a triple layer including a titanium (Ti) layer, an aluminum (Al) layer, and a titanium (Ti) layer.

An inorganic passivation layer 505 is positioned on the buffer layer 501 and the upper pad electrode 532 . The inorganic passivation layer 505 is positioned to be spaced apart from one end of the upper pad electrode 532 , and the inorganic passivation layer 505 is positioned to overlap only a portion of the upper pad electrode 532 on the upper pad electrode 532 .

An upper planarization layer 550 is positioned on the inorganic passivation layer 505 . Referring back to FIG. 3 , in the display area DA, the upper planarization layer 550 is positioned on the light blocking member 220 and the color filter layer 230 , but in the non-display area NA, the upper planarization layer 550 is inorganic. It may be directly positioned on the passivation layer 505 . The upper planarization layer 550 and the inorganic passivation layer 505 include openings exposing a portion of the upper pad electrode 532 .

One end of the upper planarization layer 550 covering the inorganic passivation layer 505 coincides with one end of the inorganic passivation layer 505 . That is, one end of the lower surface of the upper planarization layer 550 covering the inorganic passivation layer 505 coincides with one end of the upper surface of the inorganic passivation layer 505 . Looking at portion Y1 , one end of the upper surface of the inorganic passivation layer 505 positioned on the upper pad electrode 532 coincides with one end of the lower surface of the upper planarization layer 550 . Looking at the Y2 portion, one end of the upper surface of the inorganic passivation layer 505 positioned on the buffer layer 501 coincides with one end of the lower surface of the upper planarization layer 550 . One end of the inorganic passivation layer 505 and one end of the upper planarization layer 550 may coincide with each other in plan view, and the opening is located in the upper planarization layer 550 and the inorganic passivation layer 505 and exposes the upper pad electrode 532 . may also coincide with each other. When the inorganic passivation layer 505 and the upper planarization layer 550 are etched with the same mask, one end of the upper surface of the inorganic passivation layer 505 and one end of the lower surface of the upper planarization layer 550 may be formed to match, but the etch rate Due to the difference in , one end of the inorganic passivation layer 505 and the upper planarization layer 550 may not completely match.

In the Y1 portion and the Y2 portion, the side surface of the inorganic protective film 505 is formed in a tapered structure obliquely in a direction perpendicular to the substrate 100 . The side surface of the inorganic passivation layer 505 is formed by a dry etching process. In the present embodiment, the light emitting display device forms the inorganic passivation layer 505 on the upper pad electrode 532 , so that after the upper pad electrode 532 is formed, color Damage to the upper pad electrode 532 that may occur in the filter forming process may be reduced.

A flexible printed circuit board (FPCB) or the like may be attached to a portion where the upper surface of the upper pad electrode 532 and the upper surface of the buffer layer 501 are exposed.

Referring to FIGS. 29 and 30 , since the stacking order of FIG. 28 is the same, differences will be mainly described.

29 , the upper pad electrode 532 entirely overlaps the buffer layer 501 . The inorganic passivation layer 505 is spaced apart from each other so as to partially overlap both ends of the upper pad electrode 532 around the exposed portion of the upper surface of the upper pad electrode 532 . An upper planarization layer 550 is positioned on the inorganic passivation layer 505 . A flexible printed circuit board (FPCB) or the like may be attached to a portion where the upper surface of the upper pad electrode 532 is exposed. The upper pad electrode 532 may extend beyond the pad part 30 to become a part of the connection wiring 21 .

Looking at the Y1 part, one end of the upper surface of the inorganic passivation layer 505 positioned on the upper pad electrode 532 coincides with one end of the lower surface of the upper planarization layer 550 , and the upper planarization layer 550 and the inorganic passivation layer 505 are aligned with each other. ), and the opening exposing the upper pad electrode 532 may also coincide with each other.

In FIG. 30 , the upper pad electrode 532 partially overlaps the buffer layer 501 . The inorganic passivation layer 505 is positioned on the buffer layer 501 to be spaced apart from both ends of the upper pad electrode 532 . One end of the inorganic passivation layer 505 is spaced apart from both ends of the upper pad electrode 532 . The connecting wire 21 that may be connected to the pad part 30 may be located on a different layer from the upper pad electrode 532 , and the upper pad electrode 532 may be connected to the connecting wire 21 through the opening of the insulating layer. have.

Looking at the Y2 portion, one end of the upper surface of the inorganic passivation layer 505 positioned on the buffer layer 501 coincides with one end of the lower surface of the upper planarization layer 550 .

In the Y1 portion and the Y2 portion, the side surface of the inorganic passivation layer 505 is formed obliquely in a direction perpendicular to the substrate 100 by a dry etching process. In the light emitting display device according to an embodiment, damage to the upper pad electrode 532 that may occur in the process of forming the color filter after the upper pad electrode 532 is formed by forming the inorganic passivation layer 505 on the upper pad electrode 532 . (Damage) can be reduced.

In addition, although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present invention as defined in the following claims are also presented. It belongs to the scope of the invention.

100: substrate 120: gate insulating film
131: semiconductor layer 124: gate electrode
173: source electrode 173: drain electrode
160: interlayer insulating film 180, 181: lower planarization layer
370: barrier rib 191: pixel electrode
350: light emitting layer 270: common electrode
400: encapsulation layer 501: buffer layer
510: sensing insulating layer 505: inorganic protective film
520, 540: sensing electrodes 521, 541: sensing electrode connection part
230R, 230G, 230B: Red, Blue, Green color filters
220: light blocking member 550: upper planarization layer
170, 171: lower pad electrode 530, 531, 532: upper pad electrode
512, 522: sensing wiring 30: pad part
21: connection wiring 81: via hole
51: opening 351: pixel opening
185: exposed portion 186: overlapped portion
535: flat portion 536: convex portion

Claims (30)

a substrate including a display area and a non-display area surrounding the display area;
a lower pad electrode positioned on the substrate in the non-display area;
a lower planarization layer covering a portion of the lower pad electrode; and
an upper pad electrode positioned on the lower pad electrode and overlapping at least a portion of the lower planarization layer;
the lower planarization layer includes an opening through which a top surface of the lower pad electrode is exposed, and the lower pad electrode and the upper pad electrode are connected to each other through the opening;
The lower planarization layer includes an exposed portion to which an upper surface of the lower planarization layer is exposed and an overlapping portion overlapping at least partially with the upper pad electrode,
A height of an upper surface of the exposed portion is lower than a height of an upper surface of the overlapping portion. In claim 1,
The upper pad electrode includes an upper layer containing titanium (Ti), an intermediate layer containing aluminum (Al), and a lower layer containing titanium (Ti),
The lower pad electrode includes an upper layer including titanium (Ti), an intermediate layer including aluminum (Al), and a lower layer including titanium (Ti). In claim 1,
The lower planarization layer includes at least one material selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin. In claim 1,
In the display area,
a semiconductor layer positioned on the substrate;
a gate insulating film covering the semiconductor layer;
a gate electrode positioned on the gate insulating layer;
an interlayer insulating film covering the gate electrode; and
It is positioned on the interlayer insulating film and includes a source electrode and a drain electrode connected to the semiconductor layer,
The lower pad electrode is positioned on the same layer as the source electrode and the drain electrode. In claim 4,
a pixel electrode positioned on the lower planarization layer;
a light emitting layer positioned on the pixel electrode; and
Further comprising a common electrode positioned on the light emitting layer,
The lower planarization layer covers the source electrode and the drain electrode, and includes a via hole, and the drain electrode and the pixel electrode are connected by the via hole. In claim 5,
In the display area,
an encapsulation layer covering the common electrode;
a sensing insulating layer positioned on the encapsulation layer;
a plurality of sensing electrodes positioned on the sensing insulating layer; and
Further comprising an inorganic protective film covering the plurality of sensing electrodes,
The plurality of sensing electrodes are positioned on the same layer as the upper pad electrode. In claim 6,
a buffer layer positioned between the encapsulation layer and the sensing insulating layer and between the lower pad electrode and the upper pad electrode;
The lower pad electrode and the upper pad electrode are electrically connected to each other. a substrate including a display area and a non-display area surrounding the display area;
a first lower pad electrode and a second lower pad electrode spaced apart from each other in the non-display area;
a first lower planarization layer and a second lower planarization layer at least partially overlapping the first lower pad electrode and the second lower pad electrode, respectively;
a first upper pad electrode overlapping the first lower pad electrode and the first lower planarization layer, and a second upper pad electrode overlapping the second lower pad electrode and the second lower planarization layer; and
and a light blocking member positioned to at least partially overlap between the first upper pad electrode and the second upper pad electrode positioned on the same layer. In claim 8,
An upper surface of the light blocking member is positioned higher than upper surfaces of the first upper pad electrode and the second upper pad electrode. In claim 8,
The first upper pad electrode and the second upper pad electrode include an upper layer containing titanium (Ti), an intermediate layer containing aluminum (Al), and a lower layer containing titanium (Ti),
wherein the first lower pad electrode and the second lower pad electrode include an upper layer including titanium (Ti), an intermediate layer including aluminum (Al), and a lower layer including titanium (Ti). In claim 10,
A distance from one end of the first lower pad electrode to one end of the second lower pad electrode is 10 μm to 20 μm. In claim 10,
A distance from one end of the first upper pad electrode to one end of the second upper pad electrode is 10 μm or less. In claim 10,
In the display area,
a semiconductor layer positioned on the substrate;
a gate insulating film covering the semiconductor layer;
a gate electrode positioned on the gate insulating layer;
an interlayer insulating film covering the gate electrode; and
and a source electrode and a drain electrode positioned on the interlayer insulating film and connected to the semiconductor layer,
The lower pad electrode is positioned on the same layer as the source electrode and the drain electrode. In claim 13,
a pixel electrode positioned on the lower planarization layer;
a light emitting layer positioned on the pixel electrode;
a common electrode positioned on the light emitting layer;
an encapsulation layer positioned on the common electrode; and
Further comprising a plurality of sensing electrodes positioned on the sensing insulating layer,
In the display area, the sensing insulating layer is located on the encapsulation layer,
The lower planarization layer covers the source electrode and the drain electrode,
The plurality of sensing electrodes are positioned on the same layer as the upper pad electrode. 15. In claim 14,
and a buffer layer positioned between the encapsulation layer and the sensing insulating layer, between the first lower pad electrode and the first upper pad electrode, and between the second lower pad electrode and the second upper pad electrode. and
The first lower pad electrode and the first upper pad electrode, and the second lower pad electrode and the second upper pad electrode are electrically connected to each other. stacking a gate insulating layer and an interlayer insulating layer on a substrate including a display area and a non-display area;
forming a source electrode and a drain electrode on the interlayer insulating layer in the display area, and forming a lower pad electrode on the interlayer insulating layer in the non-display area;
forming a lower planarization layer on the source electrode, the drain electrode, and the lower pad electrode;
forming a sensing electrode on the lower planarization layer in the display area, on the sensing insulating layer, and forming an upper pad electrode on the lower planarization layer in the non-display area;
forming an inorganic protective layer to cover the sensing electrode and the upper pad electrode;
forming a light blocking member and a color filter on the inorganic passivation layer in the display area, and forming an upper planarization layer on the color filter; and
and etching the inorganic passivation layer to partially expose a top surface of the lower planarization layer in the non-display area. 17. In claim 16,
The method of manufacturing a light emitting display device, wherein the inorganic passivation layer is etched by a dry etching process. 17. In claim 16,
The exposed upper surface of the lower planarization layer has a height lower than that of an upper surface overlapping the upper pad electrode. stacking a gate insulating layer and an interlayer insulating layer on a substrate including a display area and a non-display area;
forming a source electrode and a drain electrode on the interlayer insulating layer in the display area, and forming a first lower pad electrode and a second lower pad electrode on the interlayer insulating layer in the non-display area;
forming a lower planarization layer on the source electrode, the drain electrode, the first lower pad electrode, and the second lower pad electrode;
forming a sensing electrode on the lower planarization layer in the display area and on the sensing insulating layer, and forming a first upper pad electrode and a second upper pad electrode on the lower planarization layer in the non-display area; and
forming a light blocking member and a color filter on the sensing electrode in the display area, and forming the light blocking member to partially overlap the first upper pad electrode and the second upper pad electrode in the non-display area; A method of manufacturing a display device. In paragraph 19,
In the non-display area, the light blocking member is formed between the first upper pad electrode and the second upper pad electrode. a substrate including a display area and a non-display area surrounding the display area;
a pad inorganic insulating layer positioned on the substrate in the non-display area;
a pad electrode positioned on the pad inorganic insulating layer;
an inorganic protective layer positioned on the pad electrode or the pad inorganic insulating layer; and
an upper planarization layer positioned on the inorganic protective layer;
One end of the upper planarization layer coincides with one end of the inorganic passivation layer. In claim 21,
One end of the lower surface of the upper planarization layer coincides with one end of the upper surface of the inorganic passivation layer. In claim 21,
The inorganic protective layer is positioned to partially overlap the pad electrode,
A light emitting display device in which an upper surface of the pad electrode is partially exposed. In claim 21,
The inorganic protective layer is located on the pad inorganic insulating layer,
One end of the inorganic passivation layer is spaced apart from both ends of the pad electrode. In claim 21,
The upper planarization layer includes an organic insulating material. a substrate including a display area and a non-display area surrounding the display area;
an interlayer insulating film positioned on the substrate;
a lower pad electrode positioned on the interlayer insulating layer in the non-display area;
a buffer layer covering a portion of the lower pad electrode; and
an upper pad electrode positioned on the lower pad electrode and overlapping at least a portion of the buffer layer;
A portion of the buffer layer that does not overlap the upper pad electrode has a thickness smaller than a thickness of a portion that overlaps the upper pad electrode. In claim 26,
The upper pad electrode includes an upper layer containing titanium (Ti), an intermediate layer containing aluminum (Al), and a lower layer containing titanium (Ti),
The lower pad electrode includes an upper layer including titanium (Ti), an intermediate layer including aluminum (Al), and a lower layer including titanium (Ti). In claim 26,
In the display area,
a semiconductor layer positioned on the substrate;
a gate insulating film covering the semiconductor layer;
a gate electrode positioned on the gate insulating layer;
an interlayer insulating film covering the gate electrode;
a source electrode and a drain electrode positioned on the interlayer insulating layer and connected to the semiconductor layer; and
a lower planarization layer covering the source electrode and the drain electrode;
The lower pad electrode is positioned on the same layer as the source electrode and the drain electrode. 29. In claim 28,
a pixel electrode positioned on the lower planarization layer;
a light emitting layer positioned on the pixel electrode; and
Further comprising a common electrode positioned on the light emitting layer,
The lower planarization layer covers the source electrode and the drain electrode, and includes a via hole, and the drain electrode and the pixel electrode are connected by the via hole. 30. In claim 29,
In the display area,
an encapsulation layer covering the common electrode;
a sensing insulating layer positioned on the encapsulation layer;
a plurality of sensing electrodes positioned on the sensing insulating layer; and
Further comprising an inorganic protective film covering the plurality of sensing electrodes,
The plurality of sensing electrodes are positioned on the same layer as the upper pad electrode,
The buffer layer is positioned between the encapsulation layer and the sensing insulating layer,
The lower pad electrode and the upper pad electrode are electrically connected to each other.

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