KR20210121998A - Semiconductor device, layout design method for the same and method for fabricating the same - Google Patents

Abstract

Provided are a semiconductor device, a layout design method for the semiconductor device, and a method for fabricating the semiconductor device in which use of high level wiring is reduced and power loss and PnR resource loss are reduced. The semiconductor device includes a first cell region and a filler region that are arranged adjacent each other in a first direction. The semiconductor device includes: an active pattern extending in the first direction, inside the first cell region; a gate electrode extending in a second direction intersecting the first direction, on the active pattern; a gate contact that is connected to an upper surface of the gate electrode; a source/drain contact that is connected to a source/drain region of the active pattern, adjacent a side of the gate electrode; a connection wiring that extends in the first direction over the first cell region and connected to one of the gate contact and the source/drain contact; and a filler wiring that extends in the second direction and that is connected to the connection wiring, inside the filler region, wherein a height of an upper surface of the filler wiring is equal to or lower than a height of an upper surface of the connection wiring.

Description

A semiconductor device, a method for layout design of a semiconductor device, and a method for manufacturing a semiconductor device

The present invention relates to a semiconductor device, a method for designing a layout of a semiconductor device, and a method for manufacturing the semiconductor device. More specifically, the present invention relates to a semiconductor device including a filler region, a method for designing a layout of the semiconductor device, and a method for manufacturing the semiconductor device.

Due to characteristics such as miniaturization, multifunctionality, and/or low manufacturing cost, a semiconductor device is in the spotlight as an important element in the electronic industry. The semiconductor devices may be classified into a semiconductor memory device that stores logic data, a semiconductor logic device that processes logic data, and a hybrid semiconductor device that includes a storage element and a logic element.

BACKGROUND With the highly developed electronic industry, demands on the properties of semiconductor devices are increasingly increasing. For example, there is an increasing demand for high reliability, high speed and/or multifunctionality of semiconductor devices. In order to satisfy these required characteristics, structures in semiconductor devices are becoming increasingly complex and highly integrated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which power loss and PnR (Placment and Routing) resource loss are reduced by reducing the use of upper wiring.

Another technical problem to be solved by the present invention is to provide a layout design method for a semiconductor device in which power loss and PnR resource loss are reduced by reducing the use of upper wiring.

Another technical problem to be solved by the present invention is to provide a method of manufacturing a semiconductor device in which power loss and PnR resource loss are reduced by reducing the use of upper wiring.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

A semiconductor device according to some embodiments of the present invention is a semiconductor device including a first cell region and a filler region arranged in a first direction adjacent to each other, in the first cell region, in a first direction an active pattern extending on the active pattern, a gate electrode extending in a second direction intersecting the first direction, a gate contact connected to an upper surface of the gate electrode, a source/drain region of the active pattern on one side of the gate electrode; a connecting wiring connected to one of the gate contact and the source/drain contact and extending in a first direction over the connected source/drain contact, the first cell region and the filler region, and in the filler region, extending in a second direction, and a filler wiring connected to the connection wiring, wherein a height of an upper surface of the filler wiring is equal to or less than a height of an upper surface of the connection wiring.

According to some embodiments of the present invention, there is provided a semiconductor device including a first cell region and a second cell region arranged in a first direction, and a filler region between the first cell region and the second cell region. A semiconductor device comprising: a gate electrode extending in a second direction intersecting the first direction in a first cell region; source/drain contacts on one side of the gate electrode; extending in a first direction over a first cell region and a filler region; , a first connection line connected to the source/drain contact, a second gate electrode extending in the second direction in the second cell region, a gate contact connected to the upper surface of the second gate electrode, a filler region, and a second cell region a second connecting line extending across the first direction and connected to the gate contact, and a filler line extending in the second direction in the pillar region to connect the first connecting line and the second connecting line; The wire and the second connecting wire are disposed at the first routing level, and the filler wire is disposed at a level below the first routing level.

A semiconductor device according to some exemplary embodiments may include a first power wiring and a second power wiring extending side by side in a first direction, sequentially arranged in a first direction, and a second intersecting first direction a first cell separator, a second cell separator, and a third cell separator that extend side by side in the direction A first gate electrode extending in the second direction between the cell separation layers, a first source/drain contact connected to the first source/drain region of the first active pattern on one side of the first gate electrode, and a first source/drain contact A first connection contact connected to the upper surface of the drain contact, a first routing via connected to the upper surface of the first connection contact, a first routing wire extending in a first direction and connected to the upper surface of the first routing via, a first routing A second routing via connected to the upper surface of the wiring, extending in the second direction, a second routing wiring connected to the upper surface of the second routing via, and between the second cell separator and the third cell separator, extending in the second direction And, including a filler wire connected to the first routing wire, the height of the upper surface of the filler wire is less than or equal to the height of the upper surface of the first routing wire.

The details of other embodiments are included in the detailed description and drawings.

1 is a layout diagram illustrating a semiconductor device according to some embodiments.
2 is a plan view illustrating a semiconductor device according to some embodiments.
FIG. 3 is a cross-sectional view taken along line AA of FIG. 1 .
FIG. 4 is a cross-sectional view taken along line BB of FIG. 1 .
FIG. 5 is a cross-sectional view taken along CC of FIG. 1 .
FIG. 6 is a cross-sectional view taken along line DD of FIG. 1 .
7 and 8 are cross-sectional views illustrating semiconductor devices according to some embodiments.
9 is a layout diagram illustrating a semiconductor device according to some embodiments.
FIG. 10 is a cross-sectional view taken along line EE of FIG. 9 .
11 is a layout diagram illustrating a semiconductor device according to some embodiments.
12 is a cross-sectional view taken along line FF of FIG. 11 .
13 is an exemplary layout diagram for describing a function of a filler wiring of a semiconductor device according to some embodiments.
14 to 17 are various layout diagrams for describing semiconductor devices according to some embodiments.
18 is an exemplary layout diagram for describing a function of a filler wiring of a semiconductor device according to some embodiments.
19 to 21 are various exemplary layout diagrams for explaining functions of pillar wirings of a semiconductor device according to some embodiments.
22 is a block diagram of a computer system for performing layout design of a semiconductor device according to some embodiments.
23 is a flowchart illustrating a layout design method and a manufacturing method of a semiconductor device according to some embodiments.
24 to 27 are layout diagrams for explaining a layout design method of a semiconductor device according to some embodiments.

In the present specification, although first, second, etc. are used to describe various elements or components, these elements or components are not limited by these terms, of course. These terms are only used to distinguish one element or component from another. Therefore, it goes without saying that the first element or component mentioned below may be the second element or component within the spirit of the present invention.

Hereinafter, semiconductor devices according to some exemplary embodiments will be described with reference to FIGS. 1 to 6 .

For example, a fin-type transistor (FinFET) including a channel region having a fin-shaped pattern is illustrated, but the technical spirit of the present invention is not limited thereto. Of course, the semiconductor device according to some embodiments may include a tunneling transistor (FET), a transistor including a nanowire, a transistor including a nanosheet, or a three-dimensional (3D) transistor. . In addition, the semiconductor device according to some embodiments of the present invention may include a bipolar junction transistor, a lateral double diffusion transistor (LDMOS), or the like.

1 is a layout diagram illustrating a semiconductor device according to some embodiments.

Referring to FIG. 1 , a semiconductor device according to some embodiments includes a first cell region CR1 and a first pillar region FR1 .

A standard cell provided from a cell library may be provided in the first cell region CR1 . In FIG. 1 , a standard cell provided in the first cell region CR1 may be a NAND cell. However, this is only an example, and it goes without saying that the standard cell provided in the first cell region CR1 may be various, for example, a NOR cell, an XOR cell, or the like. The first filler region FR1 may be a dummy cell region that fills an empty space between cell regions in which standard cells are provided.

The first cell region CR1 and the first filler region FR1 may be adjacent to each other. Hereinafter, it will be described that the first cell region CR1 and the first filler region FR1 are arranged along the first direction X.

In some embodiments, the first cell region CR1 and the first filler region FR1 may include a first cell separation layer I1a, a second cell separation layer I1b, and a second cell separation layer I1b, which are sequentially arranged along the first direction X. It may be defined by the 3-cell separator I1c. For example, the first cell separator I1a, the second cell separator I1b, and the third cell separator I1c may extend side by side in a second direction Y crossing the first direction X. The first cell region CR1 may be defined between the first cell separation layer I1a and the second cell separation layer I1b. The first pillar region FR1 may be defined between the second cell separation layer I1b and the third cell separation layer I1c. The second cell separation layer I1b may separate the first cell region CR1 and the first pillar region FR1.

In some embodiments, the second cell isolation layer I1b and the third cell isolation layer I1c may be spaced apart from each other by one gate pitch (1CPP; 1 contacted poly pitch). For example, the distance at which the second cell separation layer I1b and the third cell separation layer I1c are spaced apart from each other is a distance between adjacent gate electrodes (eg, a first gate electrode G1 and a second gate electrode G2 to be described later). )) may be equal to the spaced distance. In the present specification, the term “same” means not only exactly the same thing, but also includes minute differences that may occur due to a margin on a process or the like.

In some embodiments, the second cell separator I1b and the third cell separator I1c may be adjacent cell separators. For example, another gate electrode or another cell separator may not be disposed between the second cell separator I1b and the third cell separator I1c.

In some embodiments, a distance between the second cell separator I1b and the third cell separator I1c may be less than or equal to 60 nm. For example, a distance between the second cell separator I1b and the third cell separator I1c may be 50 nm to 60 nm.

In a semiconductor device according to some embodiments, a first active region AR1 , a second active region AR2 , a first gate electrode G1 , a second gate electrode G2 , and a plurality of source/drain contacts CA11 to CA16), a plurality of gate contacts (CB11, CB12), a plurality of connection contacts (CM11 to CM17), a first power wiring (V _DD ), a second power wiring (V _SS ), a plurality of first routing wires (OW1, IW1, IW2, CW1), may include a second routing wire (DW1) and a first filler wire (FW1).

The first active area AR1 and the second active area AR2 may be spaced apart from each other and extend side by side. For example, the first active area AR1 and the second active area AR2 may extend in the first direction X, respectively. The second active area AR2 may be spaced apart from the first active area AR1 in the second direction Y. In some embodiments, the first active region AR1 and the second active region AR2 may be formed to cover the first cell region CR1 and the first pillar region FR1 , respectively.

In some embodiments, semiconductor devices (eg, transistors) of different conductivity types may be formed on the first active region AR1 and the second active region AR2 . Hereinafter, it will be described that the first active region AR1 is a PFET region and the second active region AR2 is an NFET region. However, this is only exemplary, and of course, the first active region AR1 may be an NFET region and the second active region AR2 may be a PFET region.

The first gate electrode G1 and the second gate electrode G2 may be interposed between the first cell separation layer I1a and the second cell separation layer I1b. The first gate electrode G1 and the second gate electrode G2 may cross the first active region AR1 and the second active region AR2, respectively. For example, the first gate electrode G1 and the second gate electrode G2 may extend side by side in the second direction Y.

In some embodiments, the first gate electrode G1 and the second gate electrode G2 may be spaced apart from each other by one gate pitch 1CPP. That is, the first gate electrode G1 and the second gate electrode G2 may be adjacent gate electrodes. For example, another gate electrode or another cell separation layer may not be disposed between the first gate electrode G1 and the second gate electrode G2 .

In some embodiments, the adjacent gate electrode and the cell separator (eg, the first gate electrode G1 and the first cell separator I1a, or the second gate electrode G2 and the second cell separator I1b) The spaced distance may be the same as a distance between adjacent gate electrodes (eg, the first gate electrode G1 and the second gate electrode G2).

The plurality of source/drain contacts CA11 to CA16 may be disposed on both sides of the first gate electrode G1 or the second gate electrode G2 . The plurality of source/drain contacts CA11 to CA16 may be connected to source/drain regions of the first active region AR1 or the second active region AR2 .

For example, the first source/drain contact CA11 may be formed on the first active region AR1 between the first gate electrode G1 and the first cell isolation layer I1a. The second source/drain contact CA12 may be formed on the first active region AR1 between the first gate electrode G1 and the second gate electrode G2 . The third source/drain contact CA13 may be formed on the first active region AR1 between the second gate electrode G2 and the second cell isolation layer I1b. The fourth source/drain contact CA14 may be formed on the second active region AR2 between the first gate electrode G1 and the first cell isolation layer I1a. The fifth source/drain contact CA15 may be formed on the second active region AR2 between the first gate electrode G1 and the second gate electrode G2 . The sixth source/drain contact CA16 may be formed on the second active region AR2 between the second gate electrode G2 and the second cell isolation layer I1b.

The source/drain contacts CA11 to CA16 may be formed in a middle-of-line (MOL) process step. That is, the source/drain contacts CA11 to CA16 may be formed before a back-end-of-line (BEOL) process step.

The plurality of gate contacts CB11 and CB12 may be disposed to overlap the first gate electrode G1 or the second gate electrode G2 . Here, the overlapping means overlapping in the third direction (Z) intersecting the first direction (X) and the second direction (Y). The plurality of gate contacts CB11 and CB12 may be connected to the first gate electrode G1 or the second gate electrode G2 . For example, the first gate contact CB11 may be connected to overlap the first gate electrode G1 , and the second gate contact CB12 may be connected to overlap the second gate electrode G2 .

The gate contacts CB11 and CB12 may be formed in a middle-of-line (MOL) process step. That is, the gate contacts CB11 and CB12 may be formed before a back-end-of-line (BEOL) process step.

The plurality of connection contacts CM11 to CM17 may be connected to some of the source/drain contacts CA11 to CA16 or some of the gate contacts CB11 and CB12, respectively. For example, the plurality of connection contacts CM11 to CM17 may be disposed to overlap some of the source/drain contacts CA11 to CA16 or some of the gate contacts CB11 and CB12, respectively.

For example, the first connection contact CM11 may be connected to overlap the first source/drain contact CA11 . The second connection contact CM12 may be connected to overlap the second source/drain contact CA12 . The third connection contact CM13 may be connected to overlap the third source/drain contact CA13 . The fourth connection contact CM14 may be connected to overlap the first gate contact CB11 . The fifth connection contact CM15 may be connected to overlap the second gate contact CB12 . The sixth connection contact CM16 may be connected to overlap the fourth source/drain contact CA14 . The seventh connection contact CM17 may be connected to overlap the sixth source/drain contact CA16 .

The connection contacts CM11 to CM17 may be formed in an MOL process step. That is, the connection contacts CM11 to CM17 may be formed prior to the BEOL process.

The first power line V _DD and the second power line V _SS may be spaced apart from each other and extend side by side. For example, the first power line V _DD and the second power line V _SS may each extend in the first direction (X). The second power line V _SS may be spaced apart from the first power line V _{DD in} the second direction (Y). In some embodiments, the first power line V _DD and the second power line V _SS may be formed over the first cell region CR1 and the first pillar region FR1 , respectively.

The first power line V _DD and the second power line V _SS may provide a power voltage. In some embodiments, a _{drain voltage may be applied to the first power line V DD} and a source voltage may be applied to the second power line V _SS . For example, a positive (+) voltage may be applied to the first power wiring V _DD , and a ground (GND) voltage or a negative (-) voltage _{may be applied to the second power wiring V SS .} However, the present invention is not limited thereto.

In some embodiments, the first power wiring V _DD may be connected to some of the source/drain contacts CA11 to CA16 . For example, at least a portion of _{the first connection contact CM11 may be disposed to overlap the first power line V DD} , and may be configured to connect the first connection contact CM11 and the first power line V _DD . A first routing via VA1 may be formed. Accordingly, the first source/drain contact CA11 may be connected to _{the first power line V DD .}

In some embodiments, the second power wiring V _SS may be connected to some other of the source/drain contacts CA11 to CA16 . For example, at least a portion of _{the sixth connection contact CM16 may be disposed to overlap the second power wiring V SS} , and may be configured to connect the sixth connection contact CM16 and the second power supply wiring V _SS . A first routing via VA1 may be formed. Accordingly, the fourth source/drain contact CA14 may be connected to _{the second power line V SS .}

The first power line V _DD and the second power line V _SS may be formed in a BEOL process. In some embodiments, the first power wire (V _DD ) and the second power wire (V _SS ) may be formed at the same routing level as the first routing wires (OW1, IW1, IW2, CW1) to be described later. For example, the first power line (V _DD ) and the second power line (V _SS ) may be disposed in a first routing level (M1) to be described later.

A plurality of first routing wires (OW1, IW1, IW2, CW1) are each extended in the first direction (X), some of the source / drain contacts (CA11 ~ CA16) or gate contacts (CB11, CB12) of Some of them can be connected. For example, the plurality of first routing wires (OW1, IW1, IW2, CW1) are each of the source / drain contacts (CA11 ~ CA16) or some of the gate contacts (CB11, CB12) to be arranged to overlap with some of the can

The plurality of first routing wires (OW1, IW1, IW2, CW1) may be disposed between _{the first power wire (V DD} ) and the second power wire (V _{SS ).} For example, a routing area RA may be defined between the first power line V _DD and the second power line V _{SS .} Illustratively, between the first power wiring (V _DD ) and the second power supply wiring (V _SS ), first to fourth routing regions (I to IV) that are sequentially arranged along the second direction (Y) will be formed can Each of the first routing wires (OW1, IW1, IW2, CW1) may be disposed in one of the first to fourth routing areas (I ~ IV).

For example, the first output wire (OW1) may be disposed in the first routing area (I) to overlap the second connection contact (CM12). In addition, a first routing via VA1 connecting the second connection contact CM12 and the first output line OW1 may be formed. Accordingly, the second source/drain contact CA12 may be connected to the first output line OW1 .

The first input wiring IW1 may be disposed in the second routing region II to overlap the fourth connection contact CM14. In addition, a first routing via VA1 connecting the fourth connection contact CM14 and the first input wiring IW1 may be formed. Accordingly, the first gate contact CB11 may be connected to the first input line IW1 . The first input wiring IW1 may function as an input wiring providing a first input signal to the first cell region CR1 .

The second input wiring IW2 may be disposed in the third routing region III to overlap the fifth connection contact CM15. In addition, a first routing via VA1 connecting the fifth connection contact CM15 and the second input wiring IW2 may be formed. Accordingly, the second gate contact CB12 may be connected to the second input line IW2 . The second input wire IW2 may function as an input wire that provides a second input signal to the first cell region CR1 .

The first connection wire CW1 may be disposed in the fourth routing region IV to overlap the seventh connection contact CM17. In addition, a first routing via VA1 connecting the seventh connection contact CM17 and the first connection line CW1 may be formed. Accordingly, the sixth source/drain contact CA16 may be connected to the first connection line CW1 . The first input wiring IW1 may function as an output wiring providing an output signal of the first cell region CR1 .

The first routing wires OW1, IW1, IW2, CW1 may be formed in a BEOL process step. The first routing wires (OW1, IW1, IW2, CW1) may be formed at the same routing level as each other. For example, the first routing wires (OW1, IW1, IW2, CW1) may be disposed in the first routing level (M1). In some embodiments, the first routing level (M1) may be a routing level disposed at the lowest level among the wirings formed in the BEOL process step.

The second routing wire (DW1) is extended in the second direction (Y), it may be connected to some of the first routing wires (OW1, IW1, IW2, CW1). For example, the second routing wire (DW1) may be arranged to overlap some of the first routing wires (OW1, IW1, IW2, CW1).

For example, the second routing wire (DW1) may extend in the second direction (Y) to overlap the first output wire (OW1) and the first connection wire (CW1). In addition, a second routing via (VA2) connecting the first output wiring (OW1) and the second routing wiring (DW1), and a second routing connecting the first connection wiring (CW1) and the second routing wiring (DW1) A via VA2 may be formed. Accordingly, the second source/drain contact CA12 may be connected to the sixth source/drain contact CA16 . Also, the first connection line CW1 may function as an output line providing an output signal of the first cell region CR1 .

The second routing wire (DW1) may be formed in the BEOL process step. The second routing wire (DW1) may be formed at a higher level than the first routing wires (OW1, IW1, IW2, CW1). For example, the second routing wire (DW1) may be disposed in a second routing level (M2) higher than the first routing level (M1).

The first pillar wiring FW1 may be disposed in the first pillar region FR1 . For example, the first pillar wiring FW1 may be interposed between the second cell separation layer I1b and the third cell separation layer I1c. The first pillar wiring (FW1) is extended in the second direction (Y), it may be connected to some of the first routing wiring (OW1, IW1, IW2, CW1). For example, the first pillar wiring FW1 may extend in the second direction Y to overlap the first connection wiring CW1 .

The first filler wire (FW1) may be formed at the same level as or lower than the first routing wires (OW1, IW1, IW2, CW1). For example, the first pillar wiring (FW1) may be disposed at a level below the first routing level (M1).

The first routing wires OW1 , IW1 , IW2 , and CW1 of the first cell region CR1 may be routed to other cell regions through the first filler wire FW1 . For example, the first pillar wiring (FW1) may extend in the second direction (Y) over the third routing region (III) and the fourth routing region (IV). In addition, a second connection wire (CW2) connected to the first pillar wire (FW1) in the third routing region (III) may be formed. Accordingly, the first cell region CR1 may provide an output signal to another cell region through the first filler interconnection FW1 and the second connection interconnection CW2 .

In Figure 1, the second connection wiring (CW2) is shown only disposed in the third routing region (III), but this is only exemplary. For example, the second connection wire (CW2) may be disposed in the first routing area (I) or the second routing area (II). Accordingly, the output signal of the first cell region CR1 may be provided to other cell regions through various routing regions.

In FIG. 1 , only the first filler interconnection FW1 is illustrated to be connected to the first connection interconnection CW1 of the first cell region CR1 , but this is only exemplary. For example, the first pillar wiring FW1 may be connected to the first input wiring IW1 or the second input wiring IW2 of the first cell region CR1 . In this case, the first cell region CR1 may receive an input signal from another cell region through the first pillar line FW1 and the second connection line CW2 .

In some embodiments, the second connection wire (CW2) may be formed at the same routing level as the first routing wires (OW1, IW1, IW2, CW1). For example, the second connection wire (CW2) may be disposed in the first routing level (M1).

In some embodiments, the first pillar interconnection FW1 may include a pillar contact Fa, a first pillar via Fb, and a second pillar via Fc. The pillar contact Fa may extend in the second direction Y to overlap the first connection line CW1 . The first pillar via Fb may connect the first connection line CW1 and the first pillar line FW1 . The second pillar via Fc may connect the first pillar wiring FW1 and the second connection wiring CW2 . The pillar contact Fa, the first pillar via Fb, and the second pillar via Fc will be described later in more detail in the description of FIGS. 2 to 6 .

2 is a plan view illustrating a semiconductor device according to some embodiments. 3 is a cross-sectional view taken along line A-A of FIG. 1 . 4 is a cross-sectional view taken along line B-B of FIG. 1 . FIG. 5 is a cross-sectional view taken along line C-C of FIG. 1 . 6 is a cross-sectional view taken along line D-D of FIG. 1 .

The semiconductor device illustrated in FIGS. 2 to 7 may be an example of a semiconductor device implemented using the layout diagram of FIG. 1 . For convenience of description, parts overlapping those described above with reference to FIG. 1 will be briefly described or omitted.

2 to 6 , a semiconductor device according to some embodiments may be formed on a substrate 100 .

The substrate 100 may be bulk silicon or silicon-on-insulator (SOI). Alternatively, the substrate 100 may be a silicon substrate, or other material such as silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide or It may include, but is not limited to, gallium antimonide.

The substrate 100 may include a first active region AR1 and a second active region AR2 . For convenience of description, it will be hereinafter described that the first active region AR1 is a PFET region and the second active region AR2 is an NFET region.

In some embodiments, the first active region AR1 and the second active region AR2 may be separated by the device isolation layer I2 . For example, as shown in FIGS. 4 and 5 , the device isolation layer I2 may extend in the first direction X to separate the first active region AR1 and the second active region AR2 .

A plurality of active patterns F1 to F4 may be formed on the substrate 100 . For example, first and second active patterns F1 and F2 may be formed on the first active area AR1 , and third and fourth active patterns F3 and F3 may be formed on the second active area AR2 . F4) may be formed. In some embodiments, each of the active patterns F1 to F4 may include a fin-shaped pattern protruding from the top surface of the substrate 100 .

The first to fourth active patterns F1 to F4 may be spaced apart from each other and extend side by side. For example, the first to fourth active patterns F1 to F4 may extend in the first direction X, respectively. Also, the first to fourth active patterns F1 to F4 may be arranged side by side in the second direction Y. In some embodiments, the first to fourth active patterns F1 to F4 may be formed over the first cell region CR1 and the first filler region FR1, respectively.

3 and 4 , in some embodiments, the first to third cell separation layers I1a, I1b, and I1c may cross the first to fourth active patterns F1 to F4. The first cell separator I1a and the second cell separator I1b may cross the first to fourth active patterns F1 to F4 to define a first cell region CR1. The second cell separator I1b and the third cell separator I1c may cross the first to fourth active patterns F1 to F4 to define a first filler region FR1.

A field insulating layer 105 may be formed on the substrate 100 . In some embodiments, the field insulating layer 105 may surround a portion of side surfaces of the first to fourth active patterns F1 to F4 . For example, as shown in FIGS. 4 to 6 , a portion of the first to fourth active patterns F1 to F4 may protrude above the field insulating layer 105 .

The field insulating layer 105 may include, for example, _{at least one of silicon oxide (SiO 2} ), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), or a combination thereof. It is not limited.

The first gate electrode G1 and the second gate electrode G2 may cross the first to fourth active patterns F1 to F4, respectively. The first gate electrode G1 and the second gate electrode G2 may each include a gate conductive layer 130 . The gate conductive layer 130 may include, for example, at least one of Ti, Ta, W, Al, Co, and combinations thereof, but is not limited thereto. The gate conductive layer 130 may include, for example, silicon or silicon germanium rather than a metal.

Although the gate conductive layer 130 is illustrated as a single layer, the technical spirit of the present invention is not limited thereto. Unlike the drawing, the gate conductive layer 130 may be formed by stacking a plurality of conductive materials. For example, the gate conductive layer 130 may include a work function control layer for controlling a work function, and a filling conductive layer filling a space formed by the work function control layer. The work function control layer may include, for example, at least one of TiN, TaN, TiC, TaC, TiAlC, and combinations thereof. The filling conductive layer may include, for example, W or Al. The gate conductive layer 130 may be formed through, for example, a replacement process, but is not limited thereto.

A gate dielectric layer 120 may be interposed between the first to fourth active patterns F1 to F4 and the gate conductive layer 130 . For example, the gate dielectric layer 120 may extend along sidewalls and bottom surfaces of the gate conductive layer 130 . However, the inventive concept is not limited thereto, and the gate dielectric layer 120 may extend only along the bottom surface of the gate conductive layer 130 .

In some embodiments, a portion of the gate dielectric layer 120 may be interposed between the field insulating layer 105 and the gate conductive layer 130 . For example, as shown in FIG. 5 , the gate dielectric layer 120 may further extend along the top surface of the field insulating layer 105 .

The gate dielectric layer 120 may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-k material having a dielectric constant greater than that of silicon oxide. The high-k material may include, for example, hafnium oxide, but is not limited thereto.

The gate spacer 140 may be formed on the substrate 100 and the field insulating layer 105 . The gate spacers 140 may extend along both sides of the gate conductive layer 130 . For example, the gate spacer 140 may extend in the second direction Y to cross the first to fourth active patterns F1 to F4 .

The gate spacer 140 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a combination thereof, but is not limited thereto.

The gate capping pattern 150 may extend along the top surface of the gate conductive layer 130 . For example, the gate capping pattern 150 may extend in the second direction Y to cover the upper surface of the gate conductive layer 130 .

A first source/drain region 160 may be formed on the first active region AR1 . For example, the first source/drain regions 160 may be formed in the first and second active patterns F1 and F2 on both sides of the gate conductive layer 130 . The first source/drain region 160 may be spaced apart from the gate conductive layer 130 by the gate spacer 140 .

A second source/drain region 260 may be formed on the second active region AR2 . For example, the second source/drain regions 260 may be formed in the third and fourth active patterns F3 and F4 on both sides of the gate conductive layer 130 . The second source/drain region 260 may be spaced apart from the gate conductive layer 130 by the gate spacer 140 .

The first source/drain region 160 and the second source/drain region 260 may each include an epitaxial layer formed in the first to fourth active patterns F1 to F4 .

When the semiconductor device formed in the first active region AR1 is a PFET, the first source/drain region 160 may include a p-type impurity or an impurity for preventing diffusion of the p-type impurity. For example, the first source/drain region 160 may include at least one of B, C, In, Ga, and Al, or a combination thereof.

When the semiconductor device formed in the second active region AR2 is an NFET, the second source/drain region 260 may include an n-type impurity or an impurity for preventing diffusion of the n-type impurity. For example, the second source/drain region 260 may include at least one of P, Sb, As, or a combination thereof.

Although each of the first source/drain region 160 and the second source/drain region 260 is illustrated as a single layer, the inventive concept is not limited thereto. For example, the first source/drain region 160 and the second source/drain region 260 may be formed of multiple layers each including impurities having different concentrations.

A plurality of interlayer insulating layers 110 , 210 , 314 , and 410 may be formed on the substrate 100 . For example, first to seventh interlayer insulating layers 110 , 210 , 314 , 410 , 510 , 610 , and 710 sequentially stacked on the substrate 100 may be formed.

The first to seventh interlayer insulating layers 110 , 210 , 314 , 410 , 510 , 610 and 710 have, for example, a low dielectric constant (low-k) having a dielectric constant lower than that of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxide. It may include at least one of the materials, but is not limited thereto.

In some embodiments, a liner layer 312 may be further formed between the second interlayer insulating layer 210 and the third interlayer insulating layer 314 . The liner layer 312 may prevent the second interlayer insulating layer 210 from being damaged in the process of forming the connection contacts CM11 to CM17 . The liner layer 312 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonitride, aluminum nitride (AlN), or a combination thereof, but is not limited thereto. . Although the liner layer 312 is illustrated as a single layer, the inventive concept is not limited thereto. Unlike the drawing, the liner layer 312 may be formed by stacking a plurality of insulating materials.

The first interlayer insulating layer 110 and the second interlayer insulating layer 210 include a field insulating layer 105 , a first source/drain region 160 , a second source/drain region 260 , a gate spacer 140 , and a gate capping layer. It may be formed to cover the pattern 150 . For example, the first interlayer insulating layer 110 may be formed on the top surface of the field insulating layer 105 , the top surface of the first source/drain region 160 , the top surface of the second source/drain region 260 , and the gate spacer 140 . side can be covered. The second interlayer insulating layer 210 may cover the top surface of the gate capping pattern 150 and the top surface of the first interlayer insulating layer 110 .

The source/drain contacts CA11 to CA16 pass through the first interlayer insulating layer 110 and the second interlayer insulating layer 210 to be connected to the first source/drain region 160 or the second source/drain region 260 . can be For example, the first to third source/drain contacts CA11 , CA12 , and CA13 may be connected to the first source/drain region 160 , and the fourth to sixth source/drain contacts CA14 , CA15 , CA16 may be connected to the second source/drain region 260 .

The gate contacts CB11 and CB12 may pass through the first interlayer insulating layer 110 and the second interlayer insulating layer 210 to be connected to the gate conductive layer 130 . For example, the first gate contact CB11 may be connected to the gate conductive layer 130 of the first gate electrode G1 , and the second gate contact CB12 may be connected to the gate conductive layer 130 of the second gate electrode G2 . It may be connected to the membrane 130 .

In some embodiments, top surfaces of the source/drain contacts CA11 to CA16 and top surfaces of the gate contacts CB11 and CB12 may be coplanar. For example, as shown in FIGS. 3 to 6 , the top surfaces of the source/drain contacts CA11 to CA16 and the top surfaces of the gate contacts CB11 and CB12 are coplanar with the top surface of the second interlayer insulating layer 210 . can be placed.

The connection contacts CM11 to CM17 may pass through the liner layer 312 and the third interlayer insulating layer 314 to be connected to the source/drain contacts CA11 to CA16 or the gate contacts CB11 and CB12. For example, the first connection contact CM11 may contact an upper surface of the first source/drain contact CA11 . The second connection contact CM12 may contact an upper surface of the second source/drain contact CA12 . The third connection contact CM13 may contact an upper surface of the third source/drain contact CA13 . The fourth connection contact CM14 may contact an upper surface of the first gate contact CB11 . The fifth connection contact CM15 may contact an upper surface of the second gate contact CB12 . The sixth connection contact CM16 may contact an upper surface of the fourth source/drain contact CA14 . The seventh connection contact CM17 may contact an upper surface of the sixth source/drain contact CA16 .

The connection contacts CM11 to CM17 may be disposed at the same level. In this specification, "arranged on the same level" means formed at the same height with respect to the upper surface of the substrate 100 . For example, top surfaces of the connection contacts CM11 to CM17 may be coplanar with the top surface of the third interlayer insulating layer 314 .

The first routing vias VA1 may each pass through the fourth interlayer insulating layer 410 to be connected to some of the connection contacts CM11 to CM17. For example, the first routing vias VA1 may be respectively connected to upper surfaces of some of the connection contacts CM11 to CM17.

The first routing wires (OW1, IW1, IW2, CW1) may each extend in the first direction (X). The first routing wires OW1, IW1, IW2, CW1 may be disposed at a higher level than the source/drain contacts CA11 to CA16, the gate contacts CB11, CB12, and the connection contacts CM11 to CM17. have. For example, the top surface of the first routing wires (OW1, IW1, IW2, CW1) is the top surface of the source / drain contacts (CA11 ~ CA16), the top surface of the gate contacts (CB11, CB12) and the connection contacts (CM11) ~CM17) can be formed higher than the upper surface.

In some embodiments, the first routing wires OW1 , IW1 , IW2 , and CW1 are respectively connected to the upper surface of the first routing via VA1 , and may be connected to some of the connection contacts CM11 to CM17 . For example, the first output line OW1 may be connected to the second connection contact CM12 . The first input wire IW1 may be connected to the fourth connection contact CM14 . The second input line IW2 may be connected to the fifth connection contact CM15 . The first connection line CW1 may be connected to the seventh connection contact CM17 .

The first power line V _DD and the second power line V _SS may each extend in the first direction (X). The first power wiring V _DD and the second power wiring V _SS are at a higher level than the source/drain contacts CA11 to CA16 , the gate contacts CB11 and CB12 , and the connection contacts CM11 to CM17 . can be placed. For example, the upper surface of the first power wire (V _DD ) and the upper surface of the second power wire (V _SS ) may be disposed on the same plane and the upper surface of the first routing wires (OW1, IW1, IW2, CW1).

In some embodiments, the first power wiring (V _DD ) and the second power wiring (V _SS ) are respectively connected to the upper surface of the first routing via (VA1), and to be connected to some other of the connection contacts (CM11 to CM17). can For example, the first power line V _DD may be connected to the first connection contact CM11 . The second power line V _SS may be connected to the sixth connection contact CM16 .

The second routing vias (VB1) may be connected to some of the first routing wires (OW1, IW1, IW2, CW1) through the sixth interlayer insulating film 610, respectively. For example, the second routing vias (VB1) may be respectively connected to the upper surface of some of the first routing wires (OW1, IW1, IW2, CW1).

The second routing wire (DW1) may extend in the second direction (Y). The second routing wire (DW1) may be disposed at a higher level than the first routing wires (OW1, IW1, IW2, CW1). For example, the upper surface of the second routing wire (DW1) may be formed higher than the upper surface of the first routing wires (OW1, IW1, IW2, CW1).

In some embodiments, the second routing wiring (DW1) is each connected to the upper surface of the second routing via (VA2), it may be connected to some of the first routing wiring (OW1, IW1, IW2, CW1). For example, the second routing wire (DW1) may be connected to the first output wire (OW1) and the first connection wire (CW1).

The first pillar wiring FW1 may be interposed between the second cell separation layer I1b and the third cell separation layer I1c. The first pillar wiring FW1 may extend in the second direction Y to connect the first connection wiring CW1 and the second connection wiring CW2 . The first filler wire (FW1) may be disposed at a level below the first routing wires (OW1, IW1, IW2, CW1). For example, the upper surface of the first pillar wiring (FW1) may be formed equal to or lower than the upper surface of the first routing wiring (OW1, IW1, IW2, CW1).

In some embodiments, the first pillar interconnection FW1 may include a pillar contact Fa, a first pillar via Fb, and a second pillar via Fc.

The pillar contact Fa may extend in the second direction Y to be connected to the first connection line CW1 and the second connection line CW2 . In some embodiments, the filler contact Fa may be disposed at the same level as the connection contacts CM11 to CM17. For example, as shown in FIG. 6 , the top surface of the pillar contact Fa may be coplanar with the top surface of the connection contacts CM11 to CM17 .

The first pillar via Fb may connect the first connection line CW1 and the first pillar line FW1 . For example, the first pillar via Fb may penetrate the fourth interlayer insulating layer 410 to be connected to the top surface of the pillar contact Fa, and the first connection wiring CW1 may be connected to the first pillar via Fb. may be connected to the upper surface of the

The second pillar via Fc may connect the first pillar wiring FW1 and the second connection wiring CW2 . For example, the second pillar via Fc may pass through the fourth interlayer insulating layer 410 to be connected to the top surface of the pillar contact Fa, and the second connection wiring CW2 may be connected to the second pillar via Fc. may be connected to the upper surface of the

In some embodiments, the first pillar via Fb and the second pillar via Fc may be disposed at the same level as the first routing vias VA1 . For example, the upper surface of the first pillar via Fb and the upper surface of the second pillar via Fc may be coplanar with the upper surface of the first routing vias VA1 .

In some embodiments, the source/drain contacts CA11 to CA16 and the gate contacts CB11 and CB12 may include a first barrier layer 220 and a first filling layer 222 , respectively. The first barrier layer 220 includes a top surface of the first source/drain region 160 , a top surface of the second source/drain region 260 , a side surface of the first interlayer insulating layer 110 , and a second interlayer insulating layer 210 . It may extend along the sides. The first filling layer 222 may fill a space formed by the first barrier layer 220 .

In some embodiments, the connection contacts CM11 to CM17 and the filler contact Fa may include a second barrier layer 320 and a second filling layer 322 , respectively. The second barrier layer 320 covers the top surfaces of the source/drain contacts CA11 to CA16 , the top surfaces of the gate contacts CB11 and CB12 , the side surface of the liner layer 312 , and the side surface of the third interlayer insulating layer 314 . may be extended accordingly. The second filling layer 322 may fill a space formed by the second barrier layer 320 .

In some embodiments, the first routing vias VA1 , the first pillar via Fb , and the second pillar via Fc may include a third barrier layer 420 and a third filling layer 422 , respectively. have. The third barrier layer 420 may extend along top surfaces of the connection contacts CM11 to CM17 and side surfaces of the fourth interlayer insulating layer 410 . The third filling layer 422 may fill a space formed by the third barrier layer 420 .

In some embodiments, the first routing wires (OW1, IW1, IW2, CW1), the first power wire (V _DD ), and the second power wire (V _SS ) are, respectively, the fourth barrier film 520 and the fourth filling membrane 522 . The fourth barrier layer 520 may extend along a top surface of the first routing via VA1 , a top surface of the fourth interlayer insulating layer 410 , and a side surface of the fifth interlayer insulating layer 510 . The fourth filling layer 522 may fill a space formed by the fourth barrier layer 520 .

In some embodiments, the second routing vias VA2 may include a fifth barrier layer 620 and a fifth filling layer 622 , respectively. The fifth barrier film 620 may extend along the upper surface of the first routing wires OW1 , IW1 , IW2 , CW1 and the side surface of the sixth interlayer insulating film 610 . The fifth filling layer 622 may fill a space formed by the fifth barrier layer 620 .

In some embodiments, the second routing wire (DW1) may include a sixth barrier film 720 and a sixth filling film (722). The sixth barrier layer 720 may extend along the top surface of the first routing vias VA1 , the top surface of the sixth interlayer insulating layer 610 , and the side surface of the seventh interlayer insulating layer 710 . The sixth filling layer 722 may fill a space formed by the sixth barrier layer 720 .

The first to sixth barrier layers 220 , 320 , 420 , 520 , 620 , and 720 are formed of a metal or metal for preventing diffusion of the first to sixth filling layers 222 , 322 , 422 , 522 , 622 , and 722 . Nitride may be included. For example, the first to sixth barrier layers 220 , 320 , 420 , 520 , 620 and 720 may include titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), It may include at least one of platinum (Pt), alloys thereof, and nitrides thereof, but is not limited thereto.

The first to sixth filling layers 222 , 322 , 422 , 522 , 622 , and 722 may include aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), and the like. It may include at least one of the alloys, but is not limited thereto.

First routing vias (VA1), first routing wires (OW1, IW1, IW2, CW1), first power wiring (V _DD ), second power wiring (V _SS ), second routing vias (VA2) And the second routing wiring (DW1), for example, may be formed by a single damascene (single damascene) process, but is not limited thereto. For example, first routing vias (VA1), first routing wires (OW1, IW1, IW2, CW1), first power wiring (V _DD ), second power wiring (V _SS ), second routing via Of course, the (VA2) and the second routing wiring (DW1) may be formed by, for example, a dual damascene (dual damascene) process or other wiring process.

7 and 8 are cross-sectional views illustrating semiconductor devices according to some embodiments. For convenience of description, portions overlapping those described above with reference to FIGS. 1 to 6 will be briefly described or omitted. For reference, FIG. 7 is a cross-sectional view taken along line A-A of FIG. 2 , and FIG. 8 is a cross-sectional view taken along line B-B of FIG. 2 .

7 and 8 , in the semiconductor device according to some embodiments, the first to fourth active patterns F1 to F4 include a plurality of wire patterns 114 , 116 , and 118 , respectively.

For example, the first to fourth active patterns F1 to F4 are sequentially stacked on the substrate 100 , respectively, and may include first to third wire patterns 114 , 116 , and 118 spaced apart from each other. . For example, the first wire pattern 114 may be spaced apart from the substrate 100 in the third direction Z, and may be spaced apart from the first wire pattern 114 of the second wire pattern 116 in the third direction Z. ), and the third wire pattern 118 may be spaced apart from the second wire pattern 116 in the third direction (Z).

The first to third wire patterns 114 , 116 , and 118 may each extend in the first direction (X). Also, the first to third wire patterns 114 , 116 , and 118 may pass through the first gate electrode G1 and the second gate electrode G2 , respectively. Accordingly, as shown in FIG. 8 , the first gate electrode G1 and the second gate electrode G2 may surround outer peripheral surfaces of the first to third wire patterns 114 , 116 , and 118 .

In FIG. 8 , the cross-sections of the first to third wire patterns 114 , 116 , and 118 are shown to be rectangular, respectively, but this is only exemplary. For example, the cross-sections of the first to third wire patterns 114 , 116 , and 118 may have different polygonal or circular shapes, respectively.

In some embodiments, each of the first to fourth active patterns F1 to F4 may further include a fin-shaped pattern 112 protruding from the upper surface of the substrate 100 and extending in the first direction X. The first wire pattern 114 may be disposed on, for example, the pin-shaped pattern 112 .

9 is a layout diagram illustrating a semiconductor device according to some embodiments. FIG. 10 is a cross-sectional view taken along line E-E of FIG. 9 . For convenience of description, portions overlapping those described above with reference to FIGS. 1 to 8 will be briefly described or omitted.

9 and 10 , in the semiconductor device according to some embodiments, the first pillar wiring FW1 includes the third pillar via Fd.

The third pillar via Fd may extend in the second direction Y to be connected to the first connection line CW1 and the second connection line CW2 . For example, the third pillar via Fd may be connected to a lower surface of the first connection line CW1 and a lower surface of the second connection line CW2 .

In some embodiments, the third pillar via Fd may be disposed at the same level as the first routing vias VA1 . For example, a top surface of the third pillar via Fd may be coplanar with a top surface of the first routing vias VA1 . In some embodiments, the third pillar via Fd may include a third barrier layer 420 and a third filling layer 422 .

11 is a layout diagram illustrating a semiconductor device according to some embodiments. 12 is a cross-sectional view taken along line F-F of FIG. 11 . For convenience of description, portions overlapping those described above with reference to FIGS. 1 to 10 will be briefly described or omitted.

9 and 10 , in the semiconductor device according to some embodiments, the first pillar wiring FW1 includes the pillar routing wiring Fe.

The filler routing wire (Fe) may extend in the second direction (Y) to be connected to the first connection wire (CW1) and the second connection wire (CW2). For example, the filler routing wire (Fe) may be connected to a side surface of the first connection wire (CW1) and a side surface of the second connection wire (CW2).

In some embodiments, the filler routing wire (Fe) may be disposed at the same level as the first routing wires (OW1, IW1, IW2, CW1). For example, the upper surface of the filler routing wire (Fe) may be disposed on the same surface and the upper surface of the first routing wires (OW1, IW1, IW2, CW1). In some embodiments, the filler routing wire Fe may include a fourth barrier layer 520 and a fourth filling layer 522 . In some embodiments, the filler routing wire (Fe) may be integrally formed with the first connection wire (CW1) and the second connection wire (CW2).

Hereinafter, a function of the first pillar wiring FW1 of a semiconductor device according to some exemplary embodiments will be described with reference to FIGS. 1 to 13 .

13 is an exemplary layout diagram for describing a function of a filler wiring of a semiconductor device according to some embodiments. For convenience of description, portions overlapping those described above with reference to FIGS. 1 to 12 will be briefly described or omitted.

Referring to FIG. 13 , the routing line (eg, the first connection line CW1 ) of the first cell area CR1 may be routed to another cell area through the first pillar line FW1 .

For example, the first connection wire CW1 may be connected to a routing wire (eg, the second connection wire CW2 ) of another cell region through the first filler wire FW1 . Accordingly, the first cell region CR1 may provide an output signal to or receive an input signal from another cell region through the first filler wire FW1 and the second connection wire CW2 .

As structures in semiconductor devices become more complex and highly integrated, the use of upper wiring for routing of semiconductor devices is increasing. However, excessive use of upper wiring causes power loss and loss of PnR resources, thereby degrading performance and productivity of the semiconductor device.

However, in the semiconductor device according to some embodiments, the use of the upper wiring may be reduced by using the first pillar wiring FW1 . As described above, the first filler interconnection FW1 may be formed in the first filler region FR1 that is a dummy cell region that fills an empty space between the cell regions, and thus does not require a separate space for routing the semiconductor device. . In addition, as described above, the first pillar wiring (FW1) may be disposed at a level below the first routing level (M1), so that an additional upper wiring (eg, a second routing level (M2) disposed in the second routing level (M2)) The signal of the first cell region CR1 may be routed without using the routing wire DW1). Accordingly, a semiconductor device having reduced power loss and reduced PnR resource loss may be provided.

Hereinafter, semiconductor devices according to some embodiments will be described with reference to FIGS. 1 to 27 .

14 to 17 are various layout diagrams for describing semiconductor devices according to some embodiments. 18 is an exemplary layout diagram for describing a function of a filler wiring of a semiconductor device according to some embodiments. For convenience of description, portions overlapping those described above with reference to FIGS. 1 to 13 will be briefly described or omitted.

14 to 17 , the semiconductor device according to some embodiments further includes a second cell region CR2 .

A standard cell provided from a cell library may be provided in the second cell region CR2 . 14 to 17 , the standard cell provided in the second cell region CR2 may be a NAND cell. However, this is only an example, and it goes without saying that the standard cell provided in the second cell region CR2 may be various, for example, a NOR cell or an XOR cell.

The first pillar region FR1 may be interposed between the first cell region CR1 and the second cell region CR2 . For example, the first cell area CR1 , the first pillar area FR1 , and the second cell area CR2 may be sequentially arranged in the first direction X .

In some embodiments, the second cell region CR2 may be defined by a third cell separation layer I1c and a fourth cell separation layer I1d that are arranged along the first direction X. For example, the third cell separator I1c and the fourth cell separator I1d may extend side by side in the second direction Y. The second cell region CR2 may be defined between the third cell separation layer I1c and the fourth cell separation layer I1d. The third cell separation layer I1c may separate the first pillar region FR1 and the second cell region CR2.

In the semiconductor device according to some embodiments, the third gate electrode G3 , the fourth gate electrode G4 , the seventh to twelfth source/drain contacts CA21 to CA26 , and the third and fourth gate contacts CB21 and CB22 . ), the eighth to fourteenth connection contacts (CM21 to CM27), a second output wire (OW2), a third output wire (OW3), a third input wire (IW3), and a third routing wire (DW2). have.

The third gate electrode G3 and the fourth gate electrode G4 may be disposed in the second cell region CR2 . For example, the third gate electrode G3 and the fourth gate electrode G4 may be interposed between the third cell separation layer I1c and the fourth cell separation layer I1d.

The seventh to twelfth source/drain contacts CA21 to CA26 may be disposed on both sides of the third gate electrode G3 or the fourth gate electrode G4 . The seventh to twelfth source/drain contacts CA21 to CA26 may be connected to source/drain regions of the first active region AR1 or the second active region AR2 . Since the arrangement of the seventh to twelfth source/drain contacts CA21 to CA26 may be similar to that of the first to sixth source/drain contacts CA11 to CA16, a detailed description thereof will be omitted below.

The third and fourth gate contacts CB21 and CB22 may be disposed to overlap the third gate electrode G3 or the fourth gate electrode G4 . For example, the third gate contact CB21 may be connected to overlap the third gate electrode G3 , and the fourth gate contact CB22 may be connected to overlap the fourth gate electrode G4 . Since the arrangement of the third and fourth gate contacts CB21 and CB22 may be similar to that of the first and second gate contacts CB11 and CB12, a detailed description thereof will be omitted below.

The eighth to fourteenth connection contacts CM21 to CM27 may be respectively connected to some of the seventh to twelfth source/drain contacts CA21 to CA26 or some of the third and fourth gate contacts CB21 and CB22. . Since the arrangement of the eighth to fourteenth connection contacts CM21 to CM27 may be similar to the arrangement of the first to seventh connection contacts CM11 to CM17, a detailed description thereof will be omitted below.

The second output wire OW2 may be disposed in the first routing area I to overlap the ninth connection contact CM22. In addition, a first routing via VA1 connecting the ninth connection contact CM22 and the second output line OW2 may be formed. Accordingly, the eighth source/drain contact CA22 may be connected to the second output line OW2 .

The third input wire IW3 may be disposed in the second routing region II to overlap the eleventh connection contact CM24. In addition, a first routing via VA1 connecting the eleventh connection contact CM24 and the third input line IW3 may be formed. Accordingly, the third gate contact CB21 may be connected to the third input line IW3 . The third input line IW3 may function as an input line that provides the first input signal to the second cell region CR2 .

The second connection wire CW2 may be disposed in the third routing region III to overlap the twelfth connection contact CM25. In addition, a first routing via VA1 connecting the twelfth connection contact CM25 and the second connection line CW2 may be formed. Accordingly, the fourth gate contact CB22 may be connected to the second connection line CW2 . The second connection line CW2 may function as an input line that provides a second input signal to the second cell region CR2 .

The third output wire OW3 may be disposed in the fourth routing region IV to overlap the fourteenth connection contact CM27. In addition, a first routing via VA1 connecting the fourteenth connection contact CM27 and the third output line OW3 may be formed. Accordingly, the twelfth source/drain contact CA26 may be connected to the third output line OW3 .

The third input line IW3 , the second connection line CW2 , the second output line OW2 , and the third output line OW3 may be formed in a BEOL process. The third input wire IW3, the second connection wire CW2, the second output wire OW2, and the third output wire OW3 may be formed at the same routing level. For example, the third input wire (IW3), the second connection wire (CW2), the second output wire (OW2), and the third output wire (OW3) may be disposed in the first routing level (M1).

The third routing wire (DW2) may extend in the second direction (Y), and overlap the second output wire (OW2) and the third output wire (OW3). In addition, a second routing via (VA2) connecting the second output wiring (OW2) and the third routing wiring (DW2), and a second routing connecting the third output wiring (OW3) and the third routing wiring (DW2) A via VA2 may be formed. Accordingly, the eighth source/drain contact CA22 may be connected to the twelfth source/drain contact CA26 .

The third routing wire (DW2) may be formed in the BEOL process step. The third routing wire (DW2) may be formed at a higher level than the third input wire (IW3), the second connection wire (CW2), the second output wire (OW2) and the third output wire (OW3). For example, the third routing wire (DW2) may be disposed in the second routing level (M2).

The first pillar wiring FW1 may connect the first connection wiring CW1 and the second connection wiring CW2. Accordingly, the output signal of the first cell region CR1 may be provided as the second input signal of the second cell region CR2 .

Referring to FIG. 14 , in the semiconductor device according to some embodiments, the first pillar wiring FW1 includes the pillar contact Fa, the first pillar via Fb, and the second pillar described above with reference to FIGS. 1 to 6 . It may include a pillar via Fc.

Referring to FIG. 15 , in the semiconductor device according to some embodiments, the first pillar wiring FW1 may include the third pillar via Fd described above with reference to FIGS. 9 and 10 .

Referring to FIG. 16 , in the semiconductor device according to some embodiments, the first pillar wiring FW1 may include the pillar routing wiring Fe described above with reference to FIGS. 11 and 12 .

Referring to FIG. 17 , in the semiconductor device according to some embodiments, the second connection line CW2 may be disposed in the second routing region II.

For example, the second connection wire (CW2) may be disposed in the second routing area (II) to overlap the eleventh connection contact (CM24). In addition, a first routing via VA1 connecting the eleventh connection contact CM24 and the second connection line CW2 may be formed. Accordingly, the third gate contact CB21 may be connected to the second connection line CW2 .

In some embodiments, the third input wiring IW3 may be disposed in the third routing region III to overlap the twelfth connection contact CM25 . In addition, a first routing via VA1 connecting the twelfth connection contact CM25 and the third input line IW3 may be formed. Accordingly, the fourth gate contact CB22 may be connected to the third input line IW3 .

In some embodiments, the first pillar wiring (FW1) may extend in the second direction (Y) over the second to fourth routing regions (II to IV). Accordingly, the first pillar wiring (FW1) may be connected to the second connection wiring (CW2) in the second routing region (II).

Referring to FIG. 18 , the routing line (eg, the first connection line CW1) of the first cell area CR1 may be routed to the second cell area CR2 through the first pillar line FW1. have.

For example, the first connection wire CW1 may be connected to a routing wire (eg, the second connection wire CW2 ) of the second cell region CR2 through the first filler wire FW1 . Accordingly, the first cell region CR1 provides an output signal to the second cell region CR2 through the first filler interconnection FW1 and the second connection interconnection CW2 or from the second cell region CR2 . An input signal may be provided.

19 to 21 are various exemplary layout diagrams for explaining functions of pillar wirings of a semiconductor device according to some embodiments. For convenience of description, portions overlapping those described above with reference to FIGS. 1 to 18 will be briefly described or omitted.

Referring to FIG. 19 , the semiconductor device according to some embodiments further includes a third cell region CR3 and a second pillar region FR2 .

A standard cell provided from a cell library may be provided in the third cell region CR3 . For example, various standard cells such as NAND cells, NOR cells, and XOR cells may be provided in the third cell region CR3 . The second filler region FR2 may be a dummy cell region that fills an empty space between cell regions in which standard cells are provided.

The second filler region FR2 may be interposed between the second cell region CR2 and the third cell region CR3 . For example, the first cell region CR1 , the first pillar region FR1 , the second cell region CR2 , the second pillar region FR2 , and the third cell region CR3 are in the first direction X may be sequentially arranged along the

In some embodiments, the routing line (eg, the third connection line CW3) of the second cell area CR2 may be routed to the third cell area CR3 through the second pillar line FW2. .

For example, the second pillar wiring FW2 extending in the second direction Y and connected to the third connection wiring CW3 may be formed in the second pillar region FR2 . The third connection wire CW3 may be connected to a routing wire (eg, the fourth connection wire CW4 ) of the third cell region CR3 through the second pillar wire FW2 . Accordingly, the second cell region CR2 provides an output signal to the third cell region CR3 through the second filler interconnection FW2 and the fourth connection interconnection CW4 or from the second cell region CR2 . An input signal may be provided.

The second filler interconnection FW2 may be formed at the same level as or lower than the first to fourth connection interconnections CW1 , CW2 , CW3 , and CW4 . For example, the second pillar wiring (FW2) may be disposed at a level below the first routing level (M1). Since the second pillar wiring FW2 may be similar to the first pillar wiring FW1 , a detailed description thereof will be omitted below.

Referring to FIG. 20 , the semiconductor device according to some embodiments further includes a fourth cell region CR4 , a fifth cell region CR5 , and a third pillar region FR3 .

The fourth cell region CR4 may be arranged along the first cell region CR1 and the second direction Y. The fifth cell region CR5 may be arranged along the second cell region CR2 and the second direction Y. A standard cell provided from a cell library may be provided in the fourth cell region CR4 and the fifth cell region CR5 , respectively. For example, various standard cells such as NAND cells, NOR cells, and XOR cells may be provided in the fourth cell region CR4 and the fifth cell region CR5 , respectively.

The third pillar region FR3 may be interposed between the fourth cell region CR4 and the fifth cell region CR5 . For example, the fourth cell area CR4 , the third pillar area FR3 , and the fifth cell area CR5 may be sequentially arranged in the first direction X . The third filler region FR3 may be a dummy cell region that fills an empty space between cell regions in which standard cells are provided.

In some embodiments, the routing line (eg, the first connection line CW1 ) of the first cell area CR1 may be routed to the fifth cell area CR5 through the first pillar line FW1 . .

For example, the first pillar wiring FW1 may extend in the second direction Y across the first pillar region FR1 and the third pillar region FR3 . The first connection wire CW1 may be connected to a routing wire (eg, the fifth connection wire CW5) of the fifth cell region CR5 through the first pillar wire FW1. Accordingly, the first cell region CR1 provides an output signal to the fifth cell region CR5 through the first filler interconnection FW1 and the fifth connection interconnection CW5 or from the fifth cell region CR5 . An input signal may be provided.

Referring to FIG. 21 , the semiconductor device according to some embodiments further includes a fourth pillar region FR4 .

The fourth pillar area FR4 may be arranged along the first pillar area FR1 and the first direction X. For example, the first cell area CR1 , the first pillar area FR1 , and the fourth pillar area FR4 may be sequentially arranged in the first direction X . Also, the fourth pillar region FR4 may be arranged along the fifth cell region CR5 and the second direction Y. The fourth filler region FR4 may be a dummy cell region that fills an empty space between cell regions in which standard cells are provided.

In some embodiments, the routing line (eg, the first connection line CW1 ) of the first cell area CR1 may be routed to the fifth cell area CR5 through the third pillar line FW3 . .

For example, a third pillar wiring FW3 extending in the second direction Y and connected to the fifth connection wiring CW5 may be formed in the fourth pillar region FR4 . Accordingly, the first cell region CR1 provides an output signal to the fifth cell region CR5 through the third pillar interconnection FW3 and the fifth connection interconnection CW5 or from the fifth cell region CR5 . An input signal may be provided.

The third pillar interconnection FW3 may be formed at a level equal to or lower than that of the first to fifth connection interconnections CW1 , CW2 , CW3 , CW4 , and CW5 . For example, the third pillar wiring (FW3) may be disposed at a level below the first routing level (M1). Since the third pillar wiring FW3 may be similar to the first pillar wiring FW1 , a detailed description thereof will be omitted below.

22 is a block diagram of a computer system for performing layout design of a semiconductor device according to some embodiments.

Referring to FIG. 22 , the computer system may include a CPU 10 , a working memory 30 , an input/output device 50 , and an auxiliary storage device 70 . Here, the computer system may be provided as a dedicated device for layout design of a semiconductor device according to some embodiments. In some embodiments, the computer system may include various design and verification simulation programs.

The CPU 10 may execute software (application programs, operating systems, device drivers) to be executed in a computer system. The CPU 10 may execute an operating system loaded into the working memory 30 . The CPU 10 may execute various application programs to be driven based on the operating system. For example, CPU 10 may execute layout design tool 32 , placement and routing tool 34 and/or OPC tool 36 loaded into working memory 30 .

The operating system or the application programs may be loaded into the working memory 30 . When the computer system is booted, the operating system image (not shown) stored in the auxiliary storage device 70 may be loaded into the working memory 30 based on a booting sequence. All input/output operations of the computer system may be supported by the operating system.

A layout design tool 32 for designing a layout of a semiconductor device according to some embodiments may be loaded into the working memory 30 from the auxiliary storage device 70 . Then, a placement and routing tool 34 that places the designed standard cells, rearranges internal wiring patterns within the placed standard cells, and routes the placed standard cells is loaded from the auxiliary storage device 70 into the working memory 30 . can be Subsequently, an OPC tool 36 that performs Optical Proximity Correction (OPC) on the designed layout data may be loaded into the working memory 30 from the auxiliary storage device 70 .

The input/output device 50 may control user input and output from user interface devices. For example, the input/output device 50 may include a keyboard or a monitor to receive information from a user. By using the input/output device 50 , a user may receive information about a semiconductor region or data paths requiring adjusted operating characteristics. In addition, the processing process and processing result of the OPC tool 36 may be displayed through the input/output device 50 .

The auxiliary storage device 70 may be provided as a storage medium of a computer system. The auxiliary storage device 70 may store application programs, an operating system image, and various data.

The system interconnector 90 may be a system bus for providing a network inside the computer system. Through the system interconnector 90 , the CPU 10 , the working memory 30 , the input/output device 50 , and the auxiliary storage device 70 may be electrically connected and data may be exchanged.

23 is a flowchart illustrating a layout design method and a manufacturing method of a semiconductor device according to some embodiments.

Referring to FIG. 23 , a high level design of a semiconductor integrated circuit may be performed using the computer system described above with reference to FIG. 22 ( S10 ). High-level design may mean describing a design target integrated circuit in a language higher than a computer language. For example, a higher-level language such as C can be used for higher-level design. Circuits designed by high-level design can be more specifically expressed by Register Transfer Level (RTL) coding or simulation. Then, the code generated by the register transfer level coding may be converted into a netlist and synthesized into an entire semiconductor device. The synthesized schematic circuit is verified by a simulation tool, and an adjustment process may be accompanied according to the verification result.

Subsequently, a layout design for implementing a logically completed semiconductor integrated circuit on a silicon substrate may be performed ( S20 ). For example, the layout design may be performed with reference to a schematic circuit synthesized in a higher-level design or a netlist corresponding thereto. The layout design may include a routing procedure of placing and connecting various standard cells provided from a cell library according to a prescribed design rule.

Layout may actually be a procedure for defining the shape or size of a pattern for configuring transistors and metal wirings to be formed on a silicon substrate. For example, in order to actually form an inverter circuit on a silicon substrate, layout patterns such as PFETs, NFETs, P-WELLs, N-WELLs, gate electrodes, and wiring patterns to be disposed thereon may be appropriately disposed. have.

Routing to the selected and deployed standard cells may then be performed. Specifically, upper wirings (routing patterns) may be disposed on the disposed standard cells. By performing routing, the deployed standard cells can be connected to each other according to the design.

After routing, verification of the layout may be performed whether there is a part that violates the design rule. The items to be verified may include a Design Rule Check (DRC), an Electrical Rule Check (ERC), and a Layout vs Schematic (LVS).

Subsequently, an optical proximity correction (OPC) procedure may be performed (S30). By using a photolithography process, layout patterns provided through layout design may be implemented on a silicon substrate. In this case, the optical proximity correction may be a technique for correcting distortion that may occur in the photolithography process.

Next, a photomask may be manufactured based on the layout changed by the optical proximity correction ( S40 ). The photomask may be manufactured in a manner that depicts layout patterns using, for example, a chromium film applied on a glass substrate.

Subsequently, a semiconductor device may be manufactured using the generated photomask ( S50 ). In a semiconductor device manufacturing process using a photomask, various types of exposure and etching processes may be repeated. Through these processes, shapes of patterns configured during layout design may be sequentially formed on a silicon substrate.

24 to 27 are layout diagrams for explaining a layout design method of a semiconductor device according to some embodiments. For convenience of description, parts overlapping those described above with reference to FIGS. 1 to 23 will be briefly described or omitted.

Referring to FIG. 24 , cell regions CR may be arranged according to a prescribed design rule. Various standard cells provided from a cell library may be disposed in each of the cell regions CR. As the cell regions CR have various sizes, empty spaces ES may be formed between the arranged cell regions CR.

Subsequently, referring to FIG. 25 , the filler regions FR may be disposed in the empty spaces ES. The filler regions FR may be dummy cell regions that fill empty spaces ES between cell regions CR in which standard cells are provided.

Referring to FIG. 26 , various cell layouts may be provided in the pillar regions FR according to the disposition of the first and second connection lines CW1 and CW2 .

For example, cell layouts according to (a) to (f) of FIG. 26 may be provided according to the disposition of the first and second connection wires CW1 and CW2 . The various cell layouts shown in FIG. 26 are merely exemplary, and the technical spirit of the present invention is not limited thereto. For example, according to the arrangement of the first connecting line CW1 and the second connecting line CW2 , it goes without saying that the shape and arrangement of the first filler line FW1 may be further varied.

Referring to FIG. 27 , various filler interconnections FW may be disposed in the filler regions FR.

Each of the pillar wirings FW may be, for example, one of the first pillar wirings FW1 described above with reference to FIG. 26 . Accordingly, a layout design method of a semiconductor device in which power loss and PnR resource loss are reduced may be provided.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the above embodiments, but may be manufactured in various different forms, and those of ordinary skill in the art to which the present invention pertains. It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

100: substrate 105: field insulating film
110: first interlayer insulating film 120: gate dielectric film
130: gate conductive layer 140: gate spacer
150: gate capping pattern 160: first source/drain region
AR1, AR: active area CA11 to CA16: source/drain contact
CM11 to CM17: connection contact CR1: first cell area
CW1, IW1, IW2, OW1: 1st routing wire
DW1: second routing wire FR1: first pillar area
FW1: first pillar wiring G1, G2: gate electrode
VA1, VA2: routing vias V _DD , V _SS : power wiring

Claims (10)

A semiconductor device comprising a first cell region and a filler region arranged in a first direction adjacent to each other,
an active pattern extending in the first direction in the first cell region;
a gate electrode extending in a second direction crossing the first direction on the active pattern;
a gate contact connected to an upper surface of the gate electrode;
a source/drain contact connected to a source/drain region of the active pattern on one side of the gate electrode;
a connection line extending in the first direction over the first cell region and the pillar region and connected to one of the gate contact and the source/drain contact; and
and a filler wire extending in the second direction in the filler region and connected to the connection wire,
an upper surface of the gate contact and an upper surface of the source/drain contact are coplanar;
A height of an upper surface of the filler wiring is equal to or less than a height of an upper surface of the connection wiring. The method of claim 1,
a first connection contact connected to an upper surface of the gate contact;
a second connection contact connected to an upper surface of the source/drain contact;
a routing via connected to one of an upper surface of the first connection contact and an upper surface of the second connection contact;
The connection wiring is connected to an upper surface of the routing via. 3. The method of claim 2,
and the filler wiring includes a filler contact whose upper surface is coplanar with an upper surface of the first connection contact and an upper surface of the second connection contact. 3. The method of claim 2,
The filler wiring includes a pillar via, the upper surface of which is coplanar with the upper surface of the routing via. The method of claim 1,
The upper surface of the filler wiring is disposed on a coplanar surface with the upper surface of the connection wiring. The method of claim 1,
a routing via connected to the upper surface of the connection wiring;
and a routing wire extending in the second direction and connected to an upper surface of the routing via. The method of claim 1,
and a first cell separation layer extending in the second direction between the first cell region and the filler region to separate the first cell region and the filler region. 8. The method of claim 7,
a second cell separator spaced apart from the first cell separator with the filler region interposed therebetween and extending in the second direction to define the filler region;
The first cell isolation layer and the second cell isolation layer are spaced apart from each other by one gate pitch (1CPP). A semiconductor device comprising: a first cell region and a second cell region arranged in a first direction; and a filler region between the first cell region and the second cell region;
a gate electrode extending in a second direction crossing the first direction in the first cell region;
a source/drain contact on one side of the gate electrode;
a first connection line extending in the first direction over the first cell region and the filler region and connected to the source/drain contact;
a second gate electrode extending in the second direction in the second cell region;
a gate contact connected to an upper surface of the second gate electrode;
a second connection line extending in the first direction over the pillar region and the second cell region and connected to the gate contact; and
and a filler wire extending in the second direction in the filler area to connect the first connection wire and the second connection wire,
The first connection wire and the second connection wire are disposed at a first routing level,
and the filler wiring is disposed at a level below the first routing level. a first power line and a second power line extending side by side in a first direction;
a first cell separator, a second cell separator, and a third cell separator that are sequentially arranged in the first direction and extend side by side in a second direction intersecting the first direction;
a first active pattern extending in the first direction between the first power line and the second power line;
a first gate electrode extending in the second direction between the first cell separator and the second cell separator;
a first source/drain contact on one side of the first gate electrode and connected to a first source/drain region of the first active pattern;
a first connection contact connected to an upper surface of the first source/drain contact;
a first routing via connected to an upper surface of the first connection contact;
a first routing wire extending in the first direction and connected to an upper surface of the first routing via;
a second routing via connected to the upper surface of the first routing wire;
a second routing wire extending in the second direction and connected to an upper surface of the second routing via; and
Between the second cell separator and the third cell separator, extending in the second direction and including a filler wire connected to the first routing wire,
The height of the upper surface of the filler wire is less than or equal to the height of the upper surface of the first routing wire.

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