KR20210117460A - Display apparatus and manufacturing method thereof - Google Patents

Abstract

Provided is a display device according to one embodiment of the present specification. The display device includes: a first thin film transistor including a polycrystalline semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode; a second thin film transistor including an oxide semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode; a second gate insulating layer between the oxide semiconductor layer and the second gate electrode; and a second interlayer insulating layer on the second gate insulating layer, wherein at least one of the second gate insulating layer and the second interlayer insulating layer includes a doped portion to which impurities are added. A method of manufacturing a display device is provided according to another embodiment of the present specification, which includes the following steps of: forming a polycrystalline semiconductor layer; depositing a first gate insulating layer on the polycrystalline semiconductor layer; forming a first gate electrode on the first gate insulating layer; depositing a first interlayer insulating layer on the first gate electrode; forming an oxide semiconductor layer on the first interlayer insulating layer; depositing a second gate insulating layer on the oxide semiconductor layer; forming a second gate electrode on the second gate insulating layer; depositing a second interlayer insulating layer on the second gate electrode; forming a first contact hole exposing the polycrystalline semiconductor layer; performing a heat treatment process; forming a second contact hole exposing the oxide semiconductor layer; doping impurities; and forming source and drain electrodes.

Description

DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF

The present specification relates to a display device and a manufacturing method thereof, and more particularly, to a display device in which a plurality of thin film transistors are formed of different semiconductors and a manufacturing method thereof.

Recently, as the information age has entered a full-fledged information age, the field of display that visually expresses electrical information signals has developed rapidly. is being developed

Specific examples of such a display device include a liquid crystal display device (LCD), and an electroluminescence display device such as an organic light emitting display device (OLED) and a quantum dot light emitting display device (QLED). In particular, an electroluminescent display device is a next-generation display device having self-luminous characteristics, and has superior characteristics in terms of viewing angle, contrast, response speed, and consumption strategy, etc., compared to a liquid crystal display device.

The electroluminescent display device includes a display area for displaying an image and a non-display area disposed adjacent to the display area. In addition, the display area includes a pixel circuit and a light emitting device. A plurality of thin film transistors are positioned in the pixel circuit to drive the light emitting devices disposed in the plurality of pixels.

The thin film transistor may be classified according to a material constituting the semiconductor layer. Among them, low temperature polysilicon (LTPS) thin film transistors and oxide semiconductor thin film transistors are most widely used. Meanwhile, development of an electroluminescent display device in which a low-temperature polycrystalline silicon thin film transistor and an oxide semiconductor thin film transistor are formed on the same substrate is being actively developed.

The inventors of the present invention have recognized that, in a method of manufacturing a display device, operating characteristics of a pixel can be improved by forming a plurality of thin film transistors using different semiconductors.

The inventor of the present specification has invented a display device in which a plurality of thin film transistors are formed of different semiconductors and damage to each semiconductor element can be reduced.

In addition, when the doping process performed to improve the conductivity of the oxide semiconductor is performed before the heat treatment process performed to stabilize the low-temperature polycrystalline silicon semiconductor, hydrogen generated inside the display device by the heat treatment process is diffused into the oxide semiconductor. A short circuit between the source and drain electrodes may occur, and the effective channel width of the oxide semiconductor may decrease, resulting in a decrease in semiconductor performance.

Accordingly, an object of the present specification is to provide a thin film transistor and a display device without a short circuit between source and drain electrodes and a reduction in effective channel width of an oxide semiconductor.

The tasks of the present specification are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the following description.

According to an embodiment of the present specification, a display device is provided. The display device includes a polycrystalline semiconductor layer, a first gate electrode, a first thin film transistor including a first source electrode and a first drain electrode, an oxide semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode. A second thin film transistor comprising: a second gate insulating layer between the oxide semiconductor layer and a second gate electrode; and a second interlayer insulating layer on the second gate insulating layer, wherein the second gate insulating layer and at least one of the second interlayer insulating layers may include a doped portion to which impurities are added.

Another exemplary embodiment of the present specification provides a method of manufacturing a display device. The method includes forming a polycrystalline semiconductor layer, depositing a first gate insulating layer on the polycrystalline semiconductor layer, forming a first gate electrode on the first gate insulating layer, on the first gate electrode depositing a first interlayer insulating layer on the first interlayer insulating layer, forming an oxide semiconductor layer on the first interlayer insulating layer, depositing a second gate insulating layer on the oxide semiconductor layer, on the second gate insulating layer forming a second gate electrode on the second gate electrode, depositing a second interlayer insulating layer on the second gate electrode, forming a first contact hole exposing the polycrystalline semiconductor layer, performing a heat treatment process; The method may include forming a second contact hole exposing the oxide semiconductor layer, doping an impurity, and forming source and drain electrodes.

The details of other embodiments are included in the detailed description and drawings.

In the display device according to the exemplary embodiment of the present specification, reliability may be improved by disposing thin film transistors including different semiconductor materials.

For example, in the manufacturing method according to the embodiment of the present specification, the doping process performed to improve the conductive properties of the second semiconductor layer is performed after the heat treatment process performed to stabilize the first semiconductor layer, so the heat treatment process Thus, it is possible to prevent hydrogen generated inside the display device from diffusing into the second semiconductor.

And, in the manufacturing method according to the embodiment of the present specification, diffusion of impurities from the conductive region, the second source region, and the second drain region of the second semiconductor layer to the channel region of the second semiconductor layer by a heat treatment process Thus, it is possible to prevent a short circuit between the source and drain electrodes of the second semiconductor layer.

In addition, the manufacturing method according to the embodiment of the present specification prevents the effective channel width of the second semiconductor layer from being reduced by the heat treatment process, thereby improving the charge mobility of the second semiconductor layer, , to implement a high-resolution display device.

1 is a cross-sectional view illustrating a display device according to a first exemplary embodiment of the present specification.
2 is a flowchart illustrating a process of manufacturing the display device according to the first exemplary embodiment of the present specification.
3A to 3J are cross-sectional views sequentially illustrating a manufacturing process of the display device according to the first exemplary embodiment of the present specification.
4 is a cross-sectional view illustrating a display device according to a second exemplary embodiment of the present specification.
5 is a cross-sectional view illustrating a display device according to a third exemplary embodiment of the present specification.
6 is a flowchart illustrating a process of manufacturing a display device according to a third exemplary embodiment of the present specification.
7A to 7D are cross-sectional views sequentially illustrating a manufacturing process of a display device according to a third exemplary embodiment of the present specification.

It will become clear with reference to the embodiments described below in detail in conjunction with the drawings. However, the present specification is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the embodiments allow the disclosure of the present specification to be complete, and those of ordinary skill in the art to which the present invention pertains. It is provided to fully inform the person of the scope of the invention, and the present specification is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present specification are exemplary, and thus the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present specification, the detailed description thereof will be omitted. When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between the two parts unless 'directly' is used.

Reference to a device or layer “on” another device or layer includes any intervening layer or other device directly on or in the middle of another device.

Although first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present specification.

Like reference numerals refer to like elements throughout.

The size and thickness of each component shown in the drawings are illustrated for convenience of description, and the present invention is not necessarily limited to the size and thickness of the illustrated component.

Each feature of the various embodiments of the present specification may be partially or wholly combined or combined with each other, and as those skilled in the art will fully understand, technically various interlocking and driving are possible, and each embodiment may be independently implemented with respect to each other. It may be possible to implement together in a related relationship.

Hereinafter, various embodiments of the present specification will be described in detail with reference to the accompanying drawings.

<First embodiment>

1 is a cross-sectional view illustrating a display device according to a first exemplary embodiment of the present specification.

Referring to FIG. 1 , the display device according to the first exemplary embodiment of the present specification includes a substrate 100 , a first buffer layer 101 , a first thin film transistor 110 , a second thin film transistor 120 , and a first gate insulation. layer 102 , the first interlayer insulating layer 103 , the second gate insulating layer 104 , the doped portion 104D of the second gate insulating layer, the second interlayer insulating layer 105 , and the second interlayer insulating layer. A doped portion 105D may be included.

The substrate 100 may support various components of the display device. The substrate 100 may be made of glass or a plastic material having flexibility. When the substrate 100 is made of a plastic material, it may be made of, for example, polyimide (PI). When the substrate 100 is made of polyimide (PI), a display device manufacturing process is performed in a situation where a support substrate made of glass is disposed under the substrate 100 , and after the display device manufacturing process is completed, the support substrate is released ( can be released). In addition, after the support substrate is released, a back plate for supporting the substrate 100 may be disposed under the substrate 100 .

When the substrate 100 is made of polyimide (PI), moisture permeates through the substrate 100 made of polyimide (PI) to the first thin film transistor 110 or the light emitting device to improve the performance of the display device. can lower it The display device according to the first exemplary embodiment of the present specification may be formed of double polyimide (PI) in order to prevent the performance of the display device from being deteriorated due to moisture permeability. And, by forming an inorganic film between the two polyimides (PI), it is possible to block the moisture component from passing through the lower polyimide (PI), thereby improving product performance reliability. The inorganic layer may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof.

The first buffer layer 101 may be formed on the entire surface of the substrate 100 . The first buffer layer 101 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. The first buffer layer 101 may improve adhesion between the layers formed on the first buffer layer 101 and the substrate 100 , and block alkali components leaking from the substrate 100 , and the like. In addition, the first buffer layer 101 is not an essential component, and may be omitted based on the type and material of the substrate 100 , the structure and type of the thin film transistor, and the like.

According to the first embodiment of the present specification, the first buffer layer 101 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof.

When the first buffer layer 101 is formed of multiple layers, silicon oxide (SiO2) and silicon nitride (SiNx) may be alternately formed. In addition, the uppermost layer and the lowermost layer of the first buffer layer 101 made of multiple layers may be formed of a silicon oxide (SiOx) material. For example, the first buffer layer 101 made of a plurality of layers includes an upper layer in contact with the first active layer 111 of the first thin film transistor 110 , a lower layer in contact with the substrate 100 , and between the upper and lower layers. It may include an intermediate layer located in the. In addition, the upper layer and the lower layer may be formed of a silicon oxide (SiOx) material, and the intermediate layer may be formed of a silicon nitride (SiNx) material.

The first thin film transistor 110 may be disposed on the first buffer layer 101 . The first thin film transistor 110 may include a first semiconductor layer 111 , a first gate electrode 112 , a first source electrode 113 , and a first drain electrode 114 . Here, according to the design of the pixel circuit, the first source electrode 113 may be a drain electrode, and the first drain electrode 114 may be a source electrode.

The first semiconductor layer 111 may include low temperature poly-silicon (LTPS). Since the polycrystalline silicon material has high mobility (100 cm 2 /Vs or more) and excellent reliability, it can be applied to a gate driver and/or a multiplexer (MUX) for driving devices that drive thin film transistors for display devices, etc. It may be applied as a semiconductor layer of a driving thin film transistor in the display device according to the first embodiment, but is not limited thereto. For example, it may be applied as a semiconductor layer of a switching thin film transistor according to characteristics of a display device.

The first semiconductor layer 111 is formed by depositing an amorphous silicon (a-Si) material on the first buffer layer 101, performing a dehydrogenation process and a crystallization process to form polycrystalline silicon, and patterning the polycrystalline silicon. A first semiconductor layer 111 may be formed. The first semiconductor layer 111 includes a first channel region 111A in which a channel is formed when the first thin film transistor 110 is driven, a first source region 111S on both sides of the first channel region 111A, and a first A drain region 111D may be included. The first source region 111S is a portion of the first semiconductor layer 111 connected to the first source electrode 113 , and the first drain region 111D is a first semiconductor connected to the first drain electrode 114 . part of the layer 111 . The first source region 111S and the first drain region 111D may be generated by ion doping the polysilicon material, and the first channel region 111A may refer to a portion remaining as the polysilicon material without ion doping. have.

In the polycrystalline semiconductor manufacturing process, the polycrystalline semiconductor material deteriorates when voids exist. Therefore, hydrogen contained in the insulating layer itself, such as silicon nitride (SiNx) or silicon oxide (SiOx), is polycrystalline through a heat treatment process to be described later. diffuse into the semiconductor material. As a result, the first semiconductor layer 111, which is a semiconductor layer including polycrystalline silicon, may be stabilized.

A first gate insulating layer 102 may be disposed on the first semiconductor layer 111 of the first thin film transistor 110 .

The first gate insulating layer 102 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. In the first gate insulating layer 102 , each of the first source electrode 113 and the first drain electrode 114 of the first thin film transistor 110 is formed of the first semiconductor layer 111 of the first thin film transistor 110 . A contact hole may be formed to be connected to each of the first source region 111A and the first drain region 111D.

A first gate electrode 112 of the first thin film transistor 110 may be disposed on the first gate insulating layer 102 .

The first gate electrode 112 may include any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd). Or it may be formed of a single layer or multiple layers made of an alloy thereof. The first gate electrode 112 may be formed on the first gate insulating layer 102 to overlap the first channel region 111A of the first semiconductor layer 111 of the first thin film transistor 110 .

A first interlayer insulating layer 103 may be disposed on the first gate insulating layer 102 and the first gate electrode 112 .

The first interlayer insulating layer 103 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. A contact hole for exposing the first source region 111S and the first drain region 111D of the first semiconductor layer 111 of the first thin film transistor 110 may be formed in the first interlayer insulating layer 103 . have.

A second semiconductor layer 121 of the second thin film transistor 120 may be disposed on the first interlayer insulating layer 103 .

The second thin film transistor 120 includes a second semiconductor layer 121 , a second gate insulating layer 104 , a second gate electrode 122 , a second source electrode 123 , and a second drain electrode 124 . can do. Here, according to the design of the pixel circuit, the second source electrode 123 may be a drain electrode, and the second drain electrode 124 may be a source electrode.

The second semiconductor layer 121 includes a second channel region 121A in which a channel is formed when the second thin film transistor 120 is driven, a second source region 121S on both sides of the second channel region 121A, and a second A drain region 121D may be included. The second source region 121S is a portion of the second semiconductor layer 121 connected to the second source electrode 123 , and the second drain region 121D is a second semiconductor connected to the second drain electrode 124 . It may refer to a portion of the layer 121 .

The second semiconductor layer 121 may be formed of an oxide semiconductor. Since the oxide semiconductor material has a larger bandgap than the silicon material, electrons do not cross the bandgap in the off state, and thus the off-current is low. Accordingly, a thin film transistor including a semiconductor layer made of an oxide semiconductor may be suitable for a switching thin film transistor having a short on time and a long off time, but is not limited thereto. Depending on the characteristics of the display device, it may be applied as a driving thin film transistor. And, since the off-current is small, the size of the storage capacitor can be reduced, which is suitable for a high-resolution display device.

For example, the second semiconductor layer 121 may be made of a metal oxide, and may be made of various metal oxides such as indium-gallium-zinc-oxide (IGZO). The second semiconductor layer 121 of the second thin film transistor 120 has been described as being formed based on the IGZO layer on the assumption that it is made of IGZO among various metal oxides, but is not limited thereto and is not limited thereto. oxide), indium-gallium-tin-oxide (IGTO), or other metal oxides such as indium-gallium-oxide (IGO).

The conductive properties of the metal oxide material may be improved by a doping process in which impurities are implanted.

A channel is formed in the second semiconductor layer 121 when the second thin film transistor 120 is driven by a doping process, which will be described later, and a second channel region 121A and a second channel region 121A that are not doped with a doping process. It may include a second source region 121S and a second drain region 121D that are conductive by a doping process on both sides. The second source region 121S is a portion of the second semiconductor layer 121 connected to the second source electrode 123 , and the second drain region 121D is a second semiconductor connected to the second drain electrode 124 . part of the layer 121 . The second source region 121S and the second drain region 121D may be generated by a doping process of implanting one of a group III element, such as boron, into the metal oxide material.

A second gate insulating layer 104 may be disposed on the second semiconductor layer 121 of the second thin film transistor 120 .

The second gate insulating layer 104 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof.

A contact hole for exposing the first semiconductor layer 111 of the first thin film transistor 110 and the second semiconductor layer 121 of the second thin film transistor 120 may be formed in the second gate insulating layer 104 . have. For example, the second gate insulating layer 104 has a contact hole for exposing the first source region 111S and the first drain region 111D of the first semiconductor layer 111 in the first thin film transistor 110 . can be formed. In addition, a contact hole for exposing the second source region 121S and the second drain region 121D of the second semiconductor layer 121 of the second thin film transistor 120 may be formed.

Some impurities may be included in the second gate insulating layer 104 during a doping process of implanting impurities into the second semiconductor layer 121 of the second thin film transistor 120 .

The second gate insulating layer 104 includes a doped portion 104D containing a predetermined impurity. The doped portion 104D may be positioned on the second semiconductor layer 121 . The impurity may be made of one of group 3 elements, such as boron.

The doped portion 104D of the second gate insulating layer 104 may include regions corresponding to the second source region 121S and the second drain region 121D of the second semiconductor layer 121 , and a doping process is performed. A region not exposed to the doping material by the second gate electrode 122 is excluded.

The second gate electrode 122 of the second thin film transistor 120 may be disposed on the second gate insulating layer 104 .

The second gate electrode 122 may include any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd). Or it may be formed of a single layer or multiple layers made of an alloy thereof. The second gate electrode 122 may be formed on the second gate insulating layer 104 to overlap the second channel region 121A of the second semiconductor layer 121 of the second thin film transistor 120 .

A second interlayer insulating layer 105 may be disposed on the second gate insulating layer 104 and the second gate electrode 122 .

The second interlayer insulating layer 105 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof.

A contact hole for exposing the first semiconductor 111 of the first thin film transistor 110 and the second semiconductor layer 121 of the second thin film transistor 120 may be formed in the second interlayer insulating layer 105 . . For example, in the second interlayer insulating layer 105 , a contact hole for exposing the first source region 111S and the first drain region 111D of the first semiconductor layer 111 in the first thin film transistor 110 . can be formed. A contact hole for exposing the second source region 121S and the second drain region 121D of the second semiconductor layer 121 of the second thin film transistor 120 is formed in the second interlayer insulating layer 105 . can be

The second interlayer insulating layer 105 may include impurities implanted into the second semiconductor layer 121 of the second thin film transistor 120 . For example, the second interlayer insulating layer 105 includes a doped portion 105D containing impurities on the second semiconductor layer 121 of the second thin film transistor 120 . The impurity may be made of one of group 3 elements, such as boron.

The doped portion 105D of the second interlayer insulating layer 105 may include a portion on which the second semiconductor layer 121 is formed.

The first source electrode 113 and the first drain electrode 114 of the first thin film transistor 110 and the second source electrode 123 and the second electrode 123 of the second thin film transistor 120 are formed on the second interlayer insulating layer 105 . Two drain electrodes 124 may be disposed.

The first source electrode 113 and the first drain electrode 114 of the first thin film transistor 110 include a first gate insulating layer 102 , a first interlayer insulating layer 103 , and a second gate insulating layer 104 . and the first semiconductor layer 111 of the first thin film transistor 110 through a contact hole formed in the second interlayer insulating layer 105 . Accordingly, the first source electrode 113 of the first thin film transistor 110 includes the first gate insulating layer 102 , the first interlayer insulating layer 103 , the second gate insulating layer 104 , and the second interlayer insulating layer. It may be connected to the first source region 111S of the first semiconductor layer 111 through the contact hole formed in the 105 . In addition, the first drain electrode 114 of the first thin film transistor 110 includes a first gate insulating layer 102 , a first interlayer insulating layer 103 , a second gate insulating layer 104 , and a second interlayer insulating layer. It may be connected to the first drain region 111D of the first semiconductor layer 111 through the contact hole formed in the 105 .

In addition, the second source electrode 123 and the second drain electrode 124 of the second thin film transistor 120 are formed through contact holes formed in the second gate insulating layer 104 and the second interlayer insulating layer 105 . 2 may be connected to the semiconductor layer 121 . Accordingly, the second source electrode 123 of the second thin film transistor 120 is connected to the second semiconductor layer 121 through the contact hole formed in the second gate insulating layer 104 and the second interlayer insulating layer 105 . The second drain electrode 124 of the second thin film transistor 120 may be connected to the second source region 121S through a contact hole formed in the second gate insulating layer 104 and the second interlayer insulating layer 105 . It may be connected to the second drain region 121D of the second semiconductor layer 121 .

The first source electrode 113 and the first drain electrode 114 of the first thin film transistor 110 and the second source electrode 123 and the second drain electrode 124 of the second thin film transistor 120 are the same It can be formed by a process. In addition, the first source electrode 113 and the first drain electrode 114 of the first thin film transistor 110 , and the second source electrode 123 and the second drain electrode 124 of the second thin film transistor 120 . may be formed of the same material. The first source electrode 113 and the first drain electrode 114 of the first thin film transistor 110 and the second source electrode 123 and the second drain electrode 124 of the second thin film transistor 120 are formed of molybdenum. (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd) any one or a single layer or multiple consisting of an alloy thereof It can be formed in layers. For example, the first source electrode 113 and the first drain electrode 114 of the first thin film transistor 110 , and the second source electrode 123 and the second drain electrode 123 of the second thin film transistor 120 . 124 may have a three-layer structure of titanium (Ti)/aluminum (Al)/titanium (Ti) made of a conductive metal material, but is not limited thereto.

Hereinafter, a method of manufacturing the display device according to the first exemplary embodiment of the present specification will be described with further reference to FIGS. 2 and 3A to 3J .

2 is a flowchart illustrating a process of manufacturing the display device according to the first embodiment of the present specification, and FIGS. 3A to 3J are cross-sectional views sequentially illustrating the manufacturing process of the display device according to the first embodiment of the present specification. .

A first buffer layer 101 is deposited on the substrate 100 . The first buffer layer 101 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. (S100)

A first semiconductor layer 111 is formed by depositing an amorphous silicon (a-Si) material on the first buffer layer 101 and transforming it into poly-Si using a crystallization process. (S101)

Crystallization processes include solid phase crystallization (SPC), liquid phase recrystallization (LPR), excimer laser annealing (ELA), Metal Induced Crystallization (MIC), or metal induction. Lateral crystallization (Metal Induced Lateral Crystallization, MILC) may be performed by a method such as. The polysilicon material is patterned by a first mask process to form a first semiconductor layer 111 .

The first gate insulating layer 102 is formed by depositing an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) on the entire surface of the substrate on which the first semiconductor layer 111 is formed. The first gate insulating layer 102 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. (S102)

A gate metal material is deposited on the first gate insulating layer 102 and patterned by a second mask process to form a first gate electrode 112 . The first gate electrode 112 is disposed to overlap the first semiconductor layer 111 . (S103)

The first interlayer insulating layer 103 is formed by depositing an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) on the entire surface of the substrate 100 on which the first gate electrode 112 is formed. The first interlayer insulating layer 103 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. (S104)

Referring to FIG. 3A , a second semiconductor layer 121 made of an oxide semiconductor material is formed on the first interlayer insulating layer 103 .

Oxide semiconductor materials include Indium Gallium Zinc Oxide (IGZO), Indium Gallium Oxide (IGO), Indium Gallium Tin Oxide (IGTO), and Indium-Zinc Oxide. At least one of oxides (Indium Zinc Oxide: IZO). The oxide semiconductor material is patterned by a third mask process to form the second semiconductor layer 121 . (S110)

Referring to FIG. 3B , an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) is deposited on the entire surface of the substrate on which the first interlayer insulating layer 103 and the second semiconductor layer 121 are formed to form the second gate. An insulating layer 104 is formed. The second gate insulating layer 104 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. (S111)

Referring to FIG. 3C , a gate metal material is deposited on the second gate insulating layer 104 and patterned by a fourth mask process to form a second gate electrode 122 . The second gate electrode 122 is disposed to overlap the second semiconductor layer 121 .

The second gate electrode 122 may include any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd). Or it may be formed of a single layer or multiple layers made of an alloy thereof. (S112)

Referring to FIG. 3D , the second interlayer insulating layer 105 is formed by depositing an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) on the entire surface of the substrate 100 on which the second gate electrode 122 is formed. to form The second interlayer insulating layer 105 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. (S113)

Referring to FIG. 3E, the first gate insulating layer 102, the first interlayer insulating layer 103, the second gate insulating layer 104, and the second interlayer insulating layer 105 are patterned by a fifth mask process, The first source contact hole SH1 exposing the first source region 111S of the first semiconductor layer 111 of the first thin film transistor 111 and the first drain region 111D of the first semiconductor layer 111 are shown. A first drain contact hole DH1 exposing the (S120)

Referring to FIG. 3F , a heat treatment process is performed on the first semiconductor layer 111 of the first thin film transistor 110 . The heat treatment process is performed at a temperature of 350°C to 380°C. Through the heat treatment process, a large amount of hydrogen contained in the first gate insulating layer 102 or the first interlayer insulating layer 103 is diffused into the first semiconductor layer 111 including polycrystalline silicon. As a result, the pores of the first semiconductor layer 111 may be filled with hydrogen through the heat treatment process to achieve stabilization. (S130)

Referring to FIG. 3G , a photoresist pattern PR is formed on the second interlayer insulating layer 105 by a sixth mask process, a doping region is defined, and a doping process is performed ( S140 ).

At this time, photoresist is applied to the entire substrate except for the portion where the second semiconductor layer 121 is formed on the second interlayer insulating layer 105 and patterned to form a photoresist pattern PR.

Next, a doping process of implanting an impurity made of one of group III elements such as boron into the second semiconductor layer 121 is performed using the photoresist pattern PR as a mask.

For the doping process, impurities are implanted into the substrate on which the second interlayer insulating layer 105 is formed at an acceleration voltage of 40 to 100 Kv and a current density of 1E15/cm3.

When the doping process is completed, the photoresist pattern PR is removed through an etching process.

Referring to FIG. 3H , as a result of the doping process of FIG. 3G , the second semiconductor layer 121 is exposed by the second gate electrode 122 and the photoresist pattern PR. The source region 121S and the second drain region 121D, the second gate electrode 122 and the second channel region 121A are not doped with impurities and are not conductive because they are blocked by the photoresist pattern PR. do.

The resistance of the second source region 121S and the second drain region 121D of the conductive second semiconductor layer 121 is lowered, so that device performance of the second thin film transistor 120 may be improved.

In addition, some impurities may be included in the second gate insulating layer 104 and the second interlayer insulating layer 105 on the second semiconductor layer 121 during the doping process. The second gate insulating layer 104 and the second interlayer insulating layer 105 include doped portions 104D and 105D including impurities on the second semiconductor layer 121 of the second thin film transistor 120 , respectively. .

Each of the doped portions 104D and 150D of the second gate insulating layer 104 and the second interlayer insulating layer 105 may include a material of a group III element, such as boron.

The doped portion 104D of the second gate insulating layer 104 may include a portion in which the second source region 121S and the second drain region 121D of the second semiconductor layer 121 are formed. A region not exposed by the second gate electrode 122 is excluded.

The doped portion 105D of the second interlayer insulating layer 105 may include a portion on which the second semiconductor layer 121 is formed.

Therefore, since the doping process performed to improve the conductivity of the second semiconductor layer 121 is performed after the heat treatment performed for stabilization of the first semiconductor layer 111 , the heat treatment process generated inside the display device Diffusion of hydrogen into the second semiconductor 121 may be prevented.

Then, the second channel region of the second semiconductor layer 121 by a heat treatment process from the second source region 121S and the second drain region 121D of the second semiconductor layer 121 containing impurities by the doping process. By preventing the impurity from diffusing into 121A, it is possible to prevent a short circuit between the source and drain electrodes.

In addition, the effective channel width of the second channel region 121A of the second semiconductor layer 121 is prevented from being reduced by the heat treatment process, thereby improving the charge mobility of the second semiconductor layer 121 . and to implement a high-resolution display device.

Referring to FIG. 3I , the second gate insulating layer 104 and the second interlayer insulating layer 105 are patterned by a seventh mask process to expose the second source region 121S of the second semiconductor layer 121 . A second drain contact hole DH2 exposing the second source contact hole SH2 and the second drain region 121D of the second semiconductor layer 121 is formed. (S150)

Referring to FIG. 3J , a second interlayer insulating layer in which a first source contact hole SH1 , a first drain contact hole DH1 , a second source contact hole SH2 , and a second drain contact hole DH2 are formed. Deposit the source-drain metal on (105). A first source electrode 113 and a first drain electrode 114 and a second source electrode 123 and a second drain electrode 124 are formed by patterning the source-drain metal by an eighth mask process.

The first source electrode 113 and the first drain electrode 114 of the first thin film transistor 110 and the second source electrode 123 and the second drain electrode 124 of the second thin film transistor 120 are formed of molybdenum. (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd) any one or a single layer or multiple consisting of an alloy thereof It can be formed in layers. For example, the first source electrode 113 and the first drain electrode 114 of the first thin film transistor 110 , and the second source electrode 123 and the second drain electrode 123 of the second thin film transistor 120 . 124 may have a three-layer structure of titanium (Ti)/aluminum (Al)/titanium (Ti) made of a conductive metal material, but is not limited thereto.

The first source electrode 113 is connected to the first source region 111S which is one side of the first semiconductor layer 111 through the first source contact hole SH1 . The first drain electrode 114 is connected to the first drain region 111D, which is the other side of the first semiconductor layer 111 through the first drain contact hole DH1. The second source electrode 123 is connected to the second source region 121S that is one side of the second semiconductor layer 121 through the second source contact hole SH2 . In addition, the second drain electrode 124 is connected to the second drain region 121D, which is the other side of the second semiconductor layer 121 through the second drain contact hole DH2 . (S160)

<Second embodiment>

4 is a cross-sectional view illustrating a display device according to a second exemplary embodiment of the present specification.

The second embodiment of the present invention has the same basic configuration as the first embodiment. If there is a difference, the impurity of the second gate insulating layer 104 and the second interlayer insulating layer 105 is included in the doped region.

For example, in the first embodiment, the photoresist pattern PR is formed and the doping process is performed by a separate mask process to define the doped region, but in the second embodiment, the photoresist pattern PR is not formed. , a doping process is performed on the entire surface of the substrate 100 .

That is, as shown in FIG. 3F , a heat treatment process is performed on the first semiconductor layer 111 of the first thin film transistor 110 in which the first source contact hole SH1 and the first drain contact hole DH1 are formed. Then, a doping process of implanting an impurity made of one of group III elements such as boron into the second semiconductor layer 121 of the second thin film transistor 120 is performed on the entire surface of the substrate.

Due to the difference in these processes, referring to FIG. 4 , the doped portion 204D including impurities may include the second gate insulating layer except for the portion not exposed by the second gate electrode 122 during the doping process. have.

In addition, since the entire region of the doped portion including impurities of the second interlayer insulating layer 205 is exposed during the doping process, the entire second interlayer insulating layer 205 may become the doped portion.

In addition, since the doping process is performed on the second semiconductor layer 121 of the second thin film transistor 120 while the first source contact hole SH1 and the first drain contact hole DH1 are exposed, the first gate insulation A doped portion 102D of the first gate insulation layer 102 and a doped portion 103D of the first interlayer insulation layer 103 are included around the contact hole of the layer 102 and the first interlayer insulation layer 103, respectively. can do.

In addition, the doped portion 102D of the first gate insulating layer 102 and the doped portion 103D of the first interlayer insulating layer 103 are formed between the first source contact hole SH1 and the first drain contact hole DH1 . It is formed in the periphery, and is spaced apart from the end of the first semiconductor layer 111 by a predetermined distance.

Compared with the first embodiment, the second embodiment has the same process as the first embodiment except for the step of forming the photoresist pattern PR for defining the doped region of the second semiconductor layer 121 , so the same effect as the first embodiment Since the mask process is reduced, it is more effective in reducing productivity and cost.

<Third embodiment>

5 is a cross-sectional view illustrating a display device according to a third exemplary embodiment of the present specification.

The third embodiment of the present specification has the same basic configuration as the first embodiment. If there is a difference, the first semiconductor layer 111 of the first thin film transistor 110 of the present specification, the second semiconductor layer 121 of the second thin film transistor 120 , the second gate insulating layer 104 , and the second The impurity of the interlayer insulating layer 105 is in the doped portions 304D and 305D.

Further, in the first embodiment, after the heat treatment process (S130), the doping region definition and doping (S140), and the second source and drain contact hole formation (S150) were performed in the order of the process, but in the third embodiment, the second source and drain By changing the order of forming the contact hole, defining the doping region, and doping, the process is performed in the order of forming the second source and drain contact hole (S240), defining the doping region, and doping (S250) after the heat treatment process (S230). There is a difference .

Referring to FIG. 5 , the display device according to the exemplary embodiment of the present specification includes a substrate 100 , a first buffer layer 101 , a first thin film transistor 110 , a second thin film transistor 120 , and a first gate insulating layer ( 102), a second interlayer insulating layer 103, a second gate insulating layer 104, a doped portion of the second gate insulating layer 304D, a second interlayer insulating layer 105, a doped portion of the second interlayer insulating layer (305D) may be included.

5 shows the first semiconductor layer 111 of the first thin film transistor 110 , the second semiconductor layer 121 of the second thin film transistor 120 , and the second gate insulating layer 104 with differences from the first embodiment. There may be a doped portion 304D of , and a doped portion 305D of the second interlayer insulating layer 105 . Other components other than this are substantially the same as those of the first embodiment. Accordingly, the redundant description of the configuration of FIG. 5 that is substantially the same as that of FIG. 1 will be omitted or briefly described.

The second thin film transistor 120 includes a second semiconductor layer 121 , a second gate insulating layer 104 , a second gate electrode 122 , a second source electrode 123 , and a second drain electrode 124 . can do. Here, according to the design of the pixel circuit, the second source electrode 123 may be a drain electrode, and the second drain electrode 124 may be a source electrode.

The second semiconductor layer 121 includes a second channel region 121A in which a channel is formed when the second thin film transistor 120 is driven, a second source region 121S on both sides of the second channel region 121A, and a second A drain region 121D may be included. The second source region 121S is a portion of the second semiconductor layer 121 connected to the second source electrode 123 , and the second drain region 121D is a second semiconductor connected to the second drain electrode 124 . It may refer to a portion of the layer 121 .

The second semiconductor layer 121 may be formed of an oxide semiconductor. For example, the second semiconductor layer 121 may be made of a metal oxide, and may be made of various metal oxides such as indium-gallium-zinc-oxide (IGZO). The second semiconductor layer 121 of the second thin film transistor 120 has been described as being formed based on the IGZO layer on the assumption that it is made of IGZO among various metal oxides, but is not limited thereto and is not limited thereto. oxide), indium-gallium-tin-oxide (IGTO), or other metal oxides such as indium-gallium-oxide (IGO).

The conductive properties of the metal oxide material may be improved by a doping process in which impurities are implanted.

A channel is formed in the second semiconductor layer 121 when the second thin film transistor 120 is driven by a doping process, which will be described later, and a second channel region 121A and a second channel region 121A that are not subjected to a doping process. It may include a second source region 121S and a second drain region 121D that are conductive by a doping process on both sides. The second source region 121S is a portion of the second semiconductor layer 121 connected to the second source electrode 123 , and the second drain region 121D is a second semiconductor connected to the second drain electrode 124 . part of the layer 121 . The second source region 121S and the second drain region 121D may be formed by a doping process of implanting one of a group III element, such as boron, into the metal oxide material.

The second source region 121S and the second drain region 121D are formed in the second semiconductor layer, and ends of the second source region 121S and the second drain region 121D are respectively formed in the second channel region 121A. ) is in contact with

A second gate insulating layer 104 may be disposed on the second semiconductor layer 121 of the second thin film transistor 120 .

The second gate insulating layer 104 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof.

A contact hole for exposing the second semiconductor layer 121 of the second thin film transistor 120 may be formed in the second gate insulating layer 104 . For example, the second gate insulating layer 104 has a contact hole for exposing the second source region 121S and the second drain region 121D of the second semiconductor layer 121 of the second thin film transistor 120 . can be formed.

Some impurities may be included in the second gate insulating layer 104 during a doping process of implanting impurities into the second semiconductor layer 121 of the second thin film transistor 120 .

The second gate insulating layer 104 includes a doped portion 304D including impurities on the second semiconductor layer 121 of the second thin film transistor 120 .

The impurity may be made of one of group 3 elements, such as boron.

The doped portion 104D of the second gate insulating layer 104 may include a portion in which the second source region 121S and the second drain region 121D of the second semiconductor layer 121 are formed.

A second interlayer insulating layer 105 may be disposed on the second gate insulating layer 104 and the second gate electrode 122 .

The second interlayer insulating layer 105 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof.

A contact hole for exposing the second semiconductor layer 121 of the second thin film transistor 120 may be formed in the second interlayer insulating layer 105 . For example, the second interlayer insulating layer 105 has a contact hole for exposing the second source region 121S and the second drain region 121D of the second semiconductor layer 121 of the second thin film transistor 120 . can be formed.

Some impurities may be included in the second interlayer insulating layer 105 during a doping process of implanting impurities into the second semiconductor layer 121 of the second thin film transistor 120 .

The second interlayer insulating layer 105 includes a doped portion 305D including impurities on the second semiconductor layer 121 of the second thin film transistor 120 .

The impurity may be made of one of group 3 elements, such as boron.

The doped portion 305D of the second interlayer insulating layer 105 may include a portion in which the second source region 121S and the second drain region 121D of the second semiconductor layer 121 are formed.

In addition, since the doping process is performed on the second semiconductor layer 121 of the second thin film transistor 120 while the second source contact hole SH2 and the second drain contact hole DH2 are exposed, the second gate insulation a doped portion 304D of the second gate insulating layer 104 and a doped portion 305D of the second interlayer insulating layer 105 around the contact hole of the layer 104 and the second interlayer insulating layer 105, respectively can do.

In addition, the doped portion 304D of the second gate insulating layer 104 and the doped portion 305D of the second interlayer insulating layer 105 are formed between the first source contact hole SH1 and the first drain contact hole DH1 . It is formed in the periphery, and is spaced apart from the end of the second semiconductor layer 121 by a predetermined distance.

Compared to the first embodiment, in the third embodiment, the second source and drain contact hole formation (S240), doping region definition, and doping (S250) are changed in the order, and the second semiconductor layer 121 is doped after the heat treatment process (S230). Since the process is performed, it has the same effect as that of the first embodiment.

Hereinafter, a method of manufacturing a display device according to a third exemplary embodiment of the present specification will be described with further reference to FIGS. 6 and 7A to 7D .

6 is a flowchart illustrating a process of manufacturing the display device according to the third exemplary embodiment of the present specification, and FIGS. 7A to 7D are cross-sectional views sequentially illustrating the manufacturing process of the display device according to the third exemplary embodiment of the present specification. .

Since the processes of S200 to S230 of FIG. 6 are the same as those of S100 to S130 of FIG. 2 , a detailed description thereof will be omitted. Hereinafter, a process of manufacturing the display device according to the third embodiment will be described.

Referring to FIG. 7A , the second gate insulating layer 104 and the second interlayer insulating layer 105 are patterned by a sixth mask process on the substrate on which the heat treatment process is completed, so that the second source of the second semiconductor layer 121 is A second source contact hole SH2 exposing the region 121S and a second drain contact hole DH2 exposing the second drain region 121D of the second semiconductor layer 121 are formed. (S240)

Referring to FIG. 7B , a photoresist pattern PR is formed on the second interlayer insulating layer 105 by a seventh mask process, a doping region is defined, and a doping process is performed.

At this time, photoresist is applied and patterned to the entire substrate except for the second source contact hole SH2 and the second drain contact hole DH2 on the second interlayer insulating layer 105 to form a photoresist pattern PR. do.

Next, a doping process of implanting an impurity made of one of group III elements such as boron into the second semiconductor layer 121 is performed using the photoresist pattern PR as a mask. (S250)

When the doping process is completed, the photoresist pattern PR is removed through an etching process.

Referring to FIG. 7C , as a result of the doping process of FIG. 7B , the second semiconductor layer 121 is exposed by the photoresist pattern PR, and the second source region 121S and the second semiconductor layer 121S doped with impurities to make a conductor. The drain region 121D, the second gate electrode 122 and the second channel region 121A are not formed into a conductor because they are not doped with impurities because they are blocked by the photoresist pattern PR.

The resistance of the second source region 121S and the second drain region 121D of the conductive second semiconductor layer 121 is lowered, so that device performance of the second thin film transistor 120 may be improved.

In addition, some impurities may be included in the second gate insulating layer 104 and the second interlayer insulating layer 105 on the second semiconductor layer 121 during the doping process. The second gate insulating layer 104 and the second interlayer insulating layer 105 are formed on the second source region 121S and the second drain region 121D of the second semiconductor layer 121 of the second thin film transistor 120 . and doped portions 304D and 305D containing impurities.

In addition, since the doping process is performed on the second semiconductor layer 121 of the second thin film transistor 120 while the second source contact hole SH2 and the second drain contact hole DH2 are exposed, the second gate insulation a doped portion 304D of the second gate insulating layer 102 and a doped portion 305D of the second interlayer insulating layer 105 around the contact hole of the layer 104 and the second interlayer insulating layer 105, respectively can do.

Also, the doped portion 304D of the second gate insulating layer 104 may include a portion in which the second source region 121S and the second drain region 121D of the second semiconductor layer 121 are formed.

The first portion 305D of the second interlayer insulating layer 105 may include a portion in which the second source region 121S and the second drain region 121D of the second semiconductor layer 121 are formed.

In addition, the doped portion 304D of the second gate insulating layer 104 and the doped portion 305D of the second interlayer insulating layer 105 are formed between the second source contact hole SH2 and the second drain contact hole DH2 . It is formed in the periphery, and is spaced apart from the end of the second semiconductor layer 121 by a predetermined distance.

Referring to FIG. 7D , a second interlayer insulating layer in which a first source contact hole SH1 , a first drain contact hole DH1 , a second source contact hole SH2 , and a second drain contact hole DH2 are formed. Deposit the source-drain metal on (105). A first source electrode 113 and a first drain electrode 114 and a second source electrode 123 and a second drain electrode 124 are formed by patterning the source-drain metal by an eighth mask process.

The first source electrode 113 and the first drain electrode 114 of the first thin film transistor 110 and the second source electrode 123 and the second drain electrode 124 of the second thin film transistor 120 are formed of molybdenum. (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd) any one or a single layer or multiple consisting of an alloy thereof It can be formed in layers. For example, the first source electrode 113 and the first drain electrode 114 of the first thin film transistor 110 , and the second source electrode 123 and the second drain electrode 123 of the second thin film transistor 120 . 124 may have a three-layer structure of titanium (Ti)/aluminum (Al)/titanium (Ti) made of a conductive metal material, but is not limited thereto.

The first source electrode 113 is connected to the first source region 111S which is one side of the first semiconductor layer 111 through the first source contact hole SH1 . The first drain electrode 114 is connected to the first drain region 111D, which is the other side of the first semiconductor layer 111 through the first drain contact hole DH1. The second source electrode 123 is connected to the second source region 121S that is one side of the second semiconductor layer 121 through the second source contact hole SH2 . In addition, the second drain electrode 124 is connected to the second drain region 121D, which is the other side of the second semiconductor layer 121 through the second drain contact hole DH2 . (S260)

<Fourth embodiment>

The fourth embodiment of the present specification has the same basic configuration as the third embodiment.

In particular, in the third embodiment, the photoresist pattern PR is formed and the doping process is performed by a separate mask process to define the doped region, but in the fourth embodiment, the photoresist pattern PR is not formed, and the substrate (100) A doping process is performed on the entire surface.

That is, as shown in FIG. 7A , the second gate insulating layer 104 and the second interlayer insulating layer 105 are patterned by a sixth mask process on the substrate on which the heat treatment process has been completed, so that the second semiconductor layer 121 is formed. A second source contact hole SH2 exposing the source region 121S and a second drain contact hole DH2 exposing the second drain region 121D of the second semiconductor layer 121 are formed.

Then, a doping process of implanting an impurity made of one of group III elements such as boron into the second semiconductor layer 121 of the second thin film transistor 120 is performed on the entire surface of the substrate.

Although there is a difference in the process, the first source contact hole SH1, the first drain contact hole DH1, the second source contact hole SH2, and the second drain contact hole DH2 are formed before the doping process, Since the first photoresist pattern PR is not formed, the same doped portion as in FIG. 4 of the second embodiment is formed.

Compared with the third embodiment, the fourth embodiment has the same process as the third embodiment except for the step of forming the photoresist pattern PR for defining the doped region of the second semiconductor layer 121 , so the same effect as the third embodiment Since the mask process is reduced, it is more effective in reducing productivity and cost.

The display device 100 according to the embodiment of the present specification includes a liquid crystal display device (LCD), a field emission display device (FED), and an organic light emitting display device: OLED), and a Quantum Dot Display Device.

A display device according to an embodiment of the present specification is a laptop computer, a television, a computer monitor, an automotive display apparatus, or another vehicle (vehicle), which is a complete product or final product including an LCM, an OLED module, and the like. Also includes a set electronic device apparatus or set device such as an electronic device including a form and the like, a mobile electronic device such as a smart phone or an electronic pad, etc. can do.

A display device according to an embodiment of the present specification may be described as follows.

A display device according to an embodiment of the present specification includes a polycrystalline semiconductor layer, a first gate electrode, a first thin film transistor including a first source electrode and a first drain electrode, an oxide semiconductor layer, a second gate electrode, a second source electrode, and a second thin film transistor including a second drain electrode, a second gate insulating layer between the oxide semiconductor layer and the second gate electrode, and a second interlayer insulating layer on the second gate insulating layer, the second gate At least one of the insulating layer and the second interlayer insulating layer may include a doped portion to which impurities are added.

In the display device according to the exemplary embodiment of the present specification, the impurities may include any one or more of Group 3 elements.

In the display device according to the exemplary embodiment of the present specification, the impurity may include fluorine.

In the display device according to the exemplary embodiment of the present specification, the oxide semiconductor layer, the second gate insulating layer, and the second interlayer insulating layer may be doped in the same process.

In the display device according to the embodiment of the present specification, the doped portion may be formed on the oxide semiconductor layer.

In the display device according to the embodiment of the present specification, the oxide semiconductor layer may include a second channel region, a second source region, and a second drain region, and a doped portion may be formed on the second source region and the second drain region. have.

In the display device according to the exemplary embodiment of the present specification, ends of the second source region and the second drain region may be in contact with the channel region.

The display device according to the embodiment of the present specification further includes a first gate insulating layer disposed between the polycrystalline semiconductor layer and the first gate electrode, and a first interlayer insulating layer disposed on the gate insulating layer, the first gate insulating layer or At least one of the first interlayer insulating layers may further include a doped portion to which impurities are added.

In the display device according to the embodiment of the present specification, the polycrystalline semiconductor layer may include a first channel region, a first source region, and a first drain region, and a doped portion may be formed on the first source region and the first drain region. have.

In the display device according to the exemplary embodiment of the present specification, the first gate insulating layer may include silicon nitride (SiNx).

A method of manufacturing a display device according to an exemplary embodiment of the present specification includes forming a polycrystalline semiconductor layer, depositing a first gate insulating layer on the polycrystalline semiconductor layer, and forming a first gate electrode on the first gate insulating layer. depositing a first interlayer insulating layer on the first gate electrode, forming an oxide semiconductor layer on the first interlayer insulating layer, depositing a second gate insulating layer on the oxide semiconductor layer; 2 Forming a second gate electrode on the gate insulating layer, depositing a second interlayer insulating layer on the second gate electrode, forming a first contact hole exposing the polycrystalline semiconductor layer, and performing a heat treatment process and forming a second contact hole exposing the oxide semiconductor layer, doping with impurities, and forming source and drain electrodes.

In the method of manufacturing the display device according to the exemplary embodiment of the present specification, the doping of impurities may be performed after the heat treatment process.

In the method of manufacturing the display device according to the exemplary embodiment of the present specification, the step of doping the impurity may be performed before the step of forming the second contact hole.

In the method of manufacturing the display device according to the embodiment of the present specification, the step of doping the impurity may be performed after the step of forming the second contact hole.

In the method of manufacturing a display device according to an exemplary embodiment of the present specification, the doping may include implanting impurities into the oxide semiconductor layer with a material including any one or more of Group III elements.

In the method of manufacturing a display device according to an exemplary embodiment of the present specification, the Group 3 element may include fluorine.

In the method of manufacturing a display device according to an exemplary embodiment of the present specification, the doping may include implanting impurities into the oxide semiconductor layer, the second gate insulating layer, and the second interlayer insulating layer in the same process.

In the method of manufacturing a display device according to an exemplary embodiment of the present specification, the doping may be performed at an acceleration voltage of 40 to 100 keV.

The method of manufacturing a display device according to an exemplary embodiment of the present specification may further include a step of defining a doping region by forming a photoresist pattern on the second interlayer insulating layer before the step of doping.

The method of manufacturing a display device according to an exemplary embodiment of the present specification may further include a doping region defining step of defining an entire surface of the second interlayer insulating layer as a doping region before the doping step.

Although the embodiments of the present specification have been described in more detail with reference to the accompanying drawings, the present specification is not necessarily limited to these embodiments, and various modifications may be made without departing from the technical spirit of the present invention. . Accordingly, the embodiments disclosed in the present specification are for explanation rather than limiting the technical spirit of the present invention, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be interpreted by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100: substrate
101: first buffer layer
102: first gate insulating layer
103: first interlayer insulating layer
104: second gate insulating layer
105: second interlayer insulating layer
110: first thin film transistor
111: first semiconductor layer
111A: first channel region
111S: first source region
111D: first drain region
112: first gate electrode
113: first source electrode
114: first drain electrode
120: second thin film transistor
121: second semiconductor layer
121A: second channel area
121S: second source region
121D: second drain region
122: second gate electrode
123: second source electrode
124: second drain electrode
102D, 103D, 104D, 105D, 204D, 205, 304D, 305D: doped part

Claims (20)

a first thin film transistor including a polycrystalline semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode;
a second thin film transistor including an oxide semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode;
a second gate insulating layer between the oxide semiconductor layer and the second gate electrode; and
a second interlayer insulating layer over the second gate insulating layer; including,
at least one of the second gate insulating layer and the second interlayer insulating layer includes a doped portion to which an impurity is added. According to claim 1,
The impurity may include at least one of a group 3 element. 3. The method of claim 2,
The impurity includes fluorine. According to claim 1,
The oxide semiconductor layer, the second gate insulating layer, and the second interlayer insulating layer are doped in the same process. According to claim 1,
The doped portion is formed on the oxide semiconductor layer. According to claim 1,
The oxide semiconductor layer includes a second channel region, a second source region, and a second drain region,
The doped portion is formed on the second source region and the second drain region. 7. The method of claim 6,
Ends of the second source region and the second drain region are in contact with the channel region. According to claim 1,
a first gate insulating layer between the polycrystalline semiconductor layer and the first gate electrode;
A first interlayer insulating layer on the gate insulating layer; further comprising,
At least one of the first gate insulating layer and the first interlayer insulating layer further includes a doped portion to which an impurity is added. 9. The method of claim 8,
The polycrystalline semiconductor layer includes a first channel region, a first source region, and a first drain region, and the doped portion is formed on the first source region and the first drain region. 9. The method of claim 8,
and the first gate insulating layer includes silicon nitride (SiNx). forming a polycrystalline semiconductor layer;
depositing a first gate insulating layer on the polycrystalline semiconductor layer;
forming a first gate electrode on the first gate insulating layer;
depositing a first interlayer insulating layer on the first gate electrode;
forming an oxide semiconductor layer on the first interlayer insulating layer;
depositing a second gate insulating layer on the oxide semiconductor layer;
forming a second gate electrode on the second gate insulating layer;
depositing a second interlayer insulating layer on the second gate electrode;
forming a first contact hole exposing the polycrystalline semiconductor layer;
performing a heat treatment process;
forming a second contact hole exposing the oxide semiconductor layer;
doping impurities;
A method of manufacturing a display device comprising: forming source and drain electrodes. 12. The method of claim 11,
The doping step is performed after the heat treatment process. 12. The method of claim 11,
The doping is performed before the forming of the second contact hole. 12. The method of claim 11,
The doping is performed after the forming of the second contact hole. 12. The method of claim 11,
The doping may include implanting impurities into the oxide semiconductor layer with a material including at least one of Group III elements. 16. The method of claim 15,
The method for manufacturing a display device, wherein the group 3 element includes fluorine. 12. The method of claim 11,
The doping may include implanting impurities into the oxide semiconductor layer, the second gate insulating layer, and the second interlayer insulating layer in the same process. 12. The method of claim 11,
The doping may include performing an acceleration voltage of 40 to 100 keV. 12. The method of claim 11,
and defining a doped region by forming a photoresist pattern on the second interlayer insulating layer before the doping. 12. The method of claim 11,
A method of manufacturing a display device in which the entire surface of the second interlayer insulating layer is doped before the doping step.

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