KR20210100249A - Array edge repeater in memory device - Google Patents

Abstract

Provided is a memory device. The memory device comprises a plurality of sub-arrays, a row control unit, a column control unit, a plurality of sense amplifiers, a plurality of sub-word drivers, and a repeater. Each of the sub-arrays is electrically coupled to one another. The row control unit is configured to control one or more rows of the sub-arrays. The column control unit is configured to control one or more columns of the sub-arrays. The plurality of sense amplifiers are adapted to the sub-arrays respectively and periodically enabled during data access operation. The plurality of sub-word drivers are disposed adjacent to the sub-arrays respectively and provide a driving signal corresponding to the sub-arrays. The repeater is configured to be disposed at an edge of the sub-arrays.

Description

Array edge repeater in memory devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device, and more particularly, to an array edge repeater for a memory device.

Memory devices are widely used today in artificial intelligence AI, machine learning applications. In these applications, the array size of the memory device leads to slow array access by using long column selector lines and row selector lines. With the development of process technology, the total area of the memory device is reduced and the memory density is increased. When the memory density is increased, it has a long parasitic capacitance and parasitic resistance, which causes array accessing speed degradation.

Several architectures have been proposed to overcome the array access slowdown during data access operations, for example, each memory cell of a memory device is divided into a plurality of banks. In another example, adding a repeater in the middle (center) of a memory cell to reduce loading stress. By employing a repeater in the memory device, the loading of the column selector lines transferred from the column decoder to the memory bank and the row selector lines transferred from the row decoder to the memory bank are reduced. However, the array access speed degradation is addressed by the above architecture, but increases the total area by using additional dummy blocks in the memory device.

For example, referring to FIG. 1 , a block diagram of a conventional memory device is shown. A conventional memory device 100 includes a plurality of memory cells 110 . Each memory cell 110 includes a plurality of memory banks A to H and a corresponding plurality of column decoders 120 , a plurality of row decoders 130 , and a plurality of It is divided into a sense amplifier (140).

The memory array 100 further includes a repeater 150 disposed in the center of the memory array. Specifically, the repeater 150 is disposed between the memory banks A to D and the memory banks E to H.

Each of the memory banks A to H includes at least one column decoder 120 , at least one row decoder 130 , and at least one sense amplifier 140 for performing a data access operation in the memory banks A to H . includes

Since the layout structure of the memory device 100 as described above is known in the art, a detailed description of the structure and operation thereof will be omitted.

According to the above layout arrangement, each memory cell 110 needs to be divided into a plurality of banks A to H, and as a result, in order to access each memory bank A to H of the memory cell 110 . Data lines (ie, bit lines and word lines), a column decoder 120 and a row decoder 130 are increased. In addition, an additional dummy block is required in the memory cell 110 for an additional circuit such as a peripheral circuit for accessing each of the memory banks A to H, so that the memory Increase the chip size of the device 100 .

In order to overcome the access speed degradation and comply with the requirement of no additional dummy blocks, it would be desirable to develop memory devices with improved array access speed in memory cells for specific applications in the art without dividing the memory cells into multiple banks. can do.

The memory device of the present disclosure includes a plurality of sub-arrays, a row controller, a column controller, a plurality of sense amplifiers, a plurality of sub-word drivers, and a repeater. Each of the sub-arrays is electrically coupled to each other. The row control unit is configured to control at least one row of the sub-array. The column control is configured to control at least one column of the sub-array. A sense amplifier is adapted to each sub-array and is periodically enabled during data access operations. A sub-word driver is disposed adjacent to each sub-array and provides a driving signal corresponding to the sub-array. The repeater is configured to be placed at the edge of the sub-array.

Based on the foregoing, in the embodiment of the present invention, the loading of the column selector line transmitted from the column decoder and the row selector line transmitted from the row decoder are improved, without dividing each memory cell into a plurality of banks. Improve column access speed and row access speed. Additionally, additional dummy blocks are avoided by applying a repeater at the edge of the sub-array.

In order to make the foregoing easier to understand, several embodiments are described in detail in conjunction with the drawings.

The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure, and together with the description serve to explain the principles of the disclosure.
1 shows a block diagram of a conventional memory device.
2 shows a block diagram of a memory device according to an exemplary embodiment of the present disclosure.
3 shows a block diagram of a memory device according to an exemplary embodiment of the present disclosure.
4 shows a circuit diagram of a repeater according to an exemplary embodiment of the present disclosure.
5 shows a circuit diagram of a repeater according to an exemplary embodiment of the present disclosure.
6 shows a circuit diagram of a repeater according to an exemplary embodiment of the present disclosure.

It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention. It is also to be understood that the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including,” “comprising,” or “having,” and variations thereof herein, is intended to include the hereinafter recited items and their equivalents, as well as additional items. Unless otherwise limited, the terms "connected", "coupled" and "mounted" and variations thereof are used broadly and include direct and indirect connections, couplings, and mounting. do.

2 is a block diagram illustrating a memory device according to an embodiment of the present invention. Referring to FIG. 2 , a memory device 200 includes a plurality of memory cells 210 . Each of the memory cells 210 is subdivided into a plurality of sub-arrays 250 . The number of sub-arrays 250 in each memory cell 210 is determined according to the density of the memory device 200 .

Since the memory device 200 may be a volatile memory device and/or a non-volatile memory device, the type of the memory device 200 is not limited in the present disclosure. Memory device 200 includes a number of memory cells, typically 8 to 64 arrays within each memory cell. In general, the size of the sub-array 250 may be 16x 8Kb, 64x 8Kb, or 512x 8Kb, but the size of the sub-array 250 of the present invention is not limited thereto.

Each of the memory cells 210 includes a row address decoder 220 , a row control 225 , a column address decoder 230 , and a column control 235 . , a plurality of sub word drivers (SWD) 251 , a plurality of sense amplifiers (SA) 252 , and a column repeater 270 .

The sub-array 250 is coupled to a corresponding sub-word driver 251 and a sense amplifier 252 , and the sub-word driver 251 is disposed adjacent to both sides of the sub-array 250 , and is connected to the sub-array 250 . and provide a corresponding drive signal. Sub-array 250 internally connected by an internal data bus. Data movement and/or data access operations between the sub-arrays 250 are performed through an internal data bus.

The row controller 225 and the column controller 235 may receive a control signal from an address register (not shown) to access data corresponding to the sub-array 250 . The row control unit 225 is configured to control rows of the sub-array 250 . Similarly, the column control 235 is configured to control the columns of the sub-array 250 . In the present disclosure, access data refers to a read operation, a write operation, and/or a backup operation. Accordingly, in the present disclosure, the function of access data is not limited. Based on the control signal from the address register to access data, the row control unit 225 provides a row control signal to the row address decoder 220 . Meanwhile, the column control unit 235 provides a column control signal to the column address decoder 230 .

A row address decoder 220 associated with each memory cell 210 is configured to select at least one row of memory cells 210 . Similarly, a column address decoder 230 is associated with each memory cell 210 configured to select at least one column of memory cells 210 .

A sense amplifier 252 is applied to each sub-array 250 . The sense amplifier 252 is periodically activated/deactivated during a data access operation in the sub-array 250 .

A column repeater 270 is disposed at the edge of the memory cell 210 . Based on this configuration, the memory cell 210 does not need to be divided into a plurality of banks, and the array access speed of the memory cell 210 is improved.

3 is a block diagram illustrating a memory device according to an embodiment of the present invention. Referring to FIG. 3 , the memory device 300 includes a plurality of memory cells 310 . Each of the memory cells 310 is divided into a plurality of sub-arrays 350 .

Each of the memory cells 310 includes a row address decoder 320 , a row controller 325 , a column address decoder 330 , a column controller 335 , a plurality of sub word drivers (SWD) 351 , and a plurality of sense amplifiers ( 352 ) and a row repeater 370 . The row address decoder 320 , the row controller 325 , the column address decoder 330 , the column controller 335 , the sub-word driver 351 , and the sense amplifier 352 each include the row address decoder 220 with reference to FIG. 2 . ), a row control unit 225 , a column address decoder 230 , a column control unit 235 , a plurality of sub word drivers 251 and a plurality of sense amplifiers 252 , and thus a row address decoder 320 , A detailed description of the structures and operations of the row controller 325 , the column address decoder 330 , the column controller 335 , the sub-word driver 351 , and the sense amplifier 352 will be omitted.

The row repeater 370 is disposed at the edge of the memory cell 310 . According to this arrangement, the memory cells do not need to be divided into a plurality of banks and the array access speed of the memory cells 310 is improved.

4 shows a circuit diagram of a repeater according to an exemplary embodiment of the present disclosure. The repeater 400 includes a delay circuit 410 , a logic circuit 420 , and a pull-up transistor 430 .

The delay circuit 410 includes two inverters INV1 to INV2. The delay circuit 410 receives a selector signal from a selector line SL and generates a delay signal DS. Specifically, the inverter INV1 receives the selector signal from the selector line SL to generate an output, and the inverter INV2 receives the output from the inverter INV1 and generates the delay signal DS. In this embodiment, the number of inverters in the delay circuit 410 is two inverters INV1 and INV2 connected in series. However, in some embodiments, the number of inverters is greater than two. The time delay of the delay signal DS is changed by selecting the number of inverters in the delay circuit 410 .

The logic circuit 420 includes two logic gates L1 to L2. In this embodiment, logic gate L1 is a two-input NOR gate and logic gate L2 is a two-input NAND gate. The logic gate L1 and the logic gate L2 are connected in series. The logic circuit 420 is configured to receive the delay signal DS from the delay circuit 410 and generate the control signal CS. Specifically, the logic gate L1 receives the delay signal DS as one input to generate the logic signal FLS and the other input is the reset signal RST. At this time, the logic gate L2 receives the logic signal FLS from the logic gate L1 as one input to generate the control signal CS and the other input is the selector signal from the selector line SL. In some embodiments, the logic gates L1 to L2 may be any logic gates such as AND, OR, NOT, EXOR, EXNOR, flip-flop, and the like. Therefore, the logic gates L1 to L2 of the present invention are not limited thereto.

In this embodiment, the pull-up transistor 430 includes a P-MOS transistor M1. The P-MOS transistor M1 has a gate terminal, a source terminal and a drain terminal. The source terminal is coupled to the power supply VDD, the drain terminal is coupled to the selector line SL, and the gate terminal is coupled to the logic circuit 420 . The pull-up transistor 430 is configured to receive the control signal CS from the logic circuit 420 , and data access in the memory device is performed by the row address decoder 220 and the column address decoder 230 with reference to FIG. 2 . do. In detail, the control terminal of the pull-up transistor 430 receives the control signal CS from the logic gate L2 and performs data access in the memory device.

In one embodiment, referring to FIG. 2 , the selector signal from the selector line SL received by the delay circuit 410 , the logic circuit 420 and the pull-up transistor 430 accesses at least one column in the memory device. It can be a column selector line for

In one embodiment, referring to FIG. 3 , the selector signal from the selector line SL received by the delay circuit 410 , the logic circuit 420 and the pull-up transistor 430 is in at least one row in the memory device. It can be a row selector line to access.

This configuration improves the loading of the column selector line sent from the column decoder and the row selector line sent from the row decoder, which improves the column access speed and row access without dividing the memory cells of each memory device into multiple banks. improve speed.

5 shows a circuit diagram of a repeater according to an exemplary embodiment of the present disclosure. The repeater 500 includes a delay circuit 510 , a logic circuit 520 , and a pull-down transistor 530 .

Delay circuit 510 and logic circuit 520 are similar to delay circuit 410 and logic circuit 420 with reference to FIG. 4, respectively. Accordingly, detailed descriptions of the structures and operations of the delay circuit 510 and the logic circuit 520 will be omitted here.

The logic circuit 520 includes logic gates L3 to L4. In this embodiment, logic gate L3 is a two-input NAND gate and logic gate L4 is a two-input NOR gate. Similarly, the logic circuit 520 is configured to receive the delay signal DS from the delay circuit 510 and generate the control signal CS. Specifically, the logic gate L3 receives the delay signal DS as one input to generate the logic signal FLS, and the other input is the reset signal RSTB. The logic gate L4 receives the logic signal FLS from the logic gate L3 as one input to generate the control signal CS, and the other input is the selector signal from the selector line SL.

In this embodiment, pull-down transistor 530 includes an N-MOS transistor. The N-MOS transistor M2 has a gate terminal, a source terminal and a drain terminal. The source terminal is coupled to the ground potential GND, the drain terminal is coupled to the selector line SL, and the gate terminal is coupled to the logic circuit 520 .

The pull-down transistor 530 is configured to receive the control signal CS from the logic circuit 520 , and data access in the memory device is performed by the row decoder 220 and the column address decoder 230 with reference to FIG. 2 . . In detail, the control terminal of the pull-down transistor 430 receives the control signal CS from the logic gate L4 and performs data access in the memory device.

In one embodiment, referring to Figure 2, the selector signal from the selector line SL received by the delay circuit 510, the logic circuit 520 and the pull-up transistor 530 access at least one column in the memory device. It can be a column selector line for

In one embodiment, referring to FIG. 3 , the selector signal from the selector line SL received by the delay circuit 510 , the logic circuit 520 and the pull-up transistor 530 are in at least one row in the memory device. It can be a row selector line to access.

6 shows a circuit diagram of a repeater according to an exemplary embodiment of the present disclosure. The repeater 600 includes a plurality of delay circuits 610 and 615 , a plurality of logic circuits 620 and 625 , a pull-up transistor 630 , and a pull-down transistor 635 .

The delay circuits 610 and 615 are configured to receive the selector signal from the selector line SL and generate corresponding delay signals DS1 and DS2.

The logic circuit 620 receives the delay signal DS1 and generates the control signal CS1. Similarly, logic circuit 625 receives delay signal DS2 and generates control signal CS2. The logic circuit 620 includes logic gates L11 to L12. Similarly, logic circuit 625 includes logic gates L21-L22.

The logic gate L11 receives another signal as a delay signal DS1 and a reset signal RST from the delay circuit 610 as one input to generate the logic signal FLS1 . The logic gate L12 receives a logic signal FLS1 as one input and another input as a selector signal from a selector line SL to generate a control signal CS1 for driving the pull-up transistor M1. Similarly, the logic gate L21 receives the delay signal DS2 as one input and the other input as the reset signal RSTB from the delay circuit 615 as one input to generate the logic signal FLS2. Logic gate L22 receives a logic signal FLS2 as one input and another input as a selector signal from a selector line SL to generate a control signal CS2 for driving the pull-down transistor M2.

The pull-up transistor 630 receives the control signal CS1 from the logic circuit 620 and the pull-down transistor 625 receives the control signal CS2 from the logic circuit 625 .

Delay circuit 610 , logic circuit 620 , and pull-up transistor 630 are similar to delay circuit 410 , logic circuit 420 , and pull-up transistor 430 with reference to FIG. 4 , respectively. Furthermore, delay circuit 615, logic circuit 625, and pull-down transistor 635 are similar to delay circuit 510, logic circuit 520, and pull-down transistor 530 with reference to FIG. is omitted.

In summary, in an embodiment of the present invention based on the layout configuration, the loading of the column selector line sent from the column decoder and the row selector line sent from the row decoder is improved, which transfers each memory cell into multiple banks in the memory device. Column access speed and row access speed are improved without partitioning.

It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the present disclosure. In view of the foregoing, this disclosure is intended to cover modifications and variations provided they come within the scope of the following claims and their equivalents.

Claims (19)

A memory device comprising:
a plurality of sub-arrays, each said sub-array electrically coupled to one another;
a row control unit configured to control at least one row of the sub-array;
a column control configured to control at least one column of the sub-array;
a plurality of sense amplifiers applied to each of the sub-arrays periodically enabled during data access operations;
a plurality of sub-word drivers disposed adjacent to each of the sub-arrays and providing driving signals corresponding to the sub-arrays; and
a repeater disposed at the edge of the sub-array
containing
Device.
According to claim 1,
The repeater is
a delay circuit comprising a plurality of inverters coupled in series, the delay circuit configured to receive a selector signal and generate a delay signal during the data access operation; and
a logic circuit configured to receive the delay signal and generate a control signal
containing
Device.
3. The method of claim 2,
The delay circuit is
a first logic gate configured to receive a reset signal and the delay signal to generate a first logic signal; and
a second logic gate configured to receive a first logic signal and a selector signal to generate the control signal;
wherein the first logic gate and the second logic gate are connected in series.
Device.
According to claim 1,
The repeater is
a column repeater configured to access at least one column of the memory device using a column selector line.
Device.
According to claim 1,
The repeater is
a row repeater configured to access at least one row of the memory device using a row selector line.
Device.
3. The method of claim 2,
The repeater is a pull-up repeater
Device.
7. The method of claim 6,
The repeater is
a pull-up transistor configured to receive the control signal from the logic circuit
further comprising
Device.
8. The method of claim 7,
The pull-up transistor is
a source terminal coupled to a power source;
a drain terminal coupled to the selector signal; and
a control terminal coupled to the output of the logic circuit
containing
Device.
8. The method of claim 7,
The logic circuit is
a first logic gate, wherein the first logic gate is a two-input NOR gate; and
a second logic gate, wherein the second logic gate is a two-input NAND gate;
containing
Device.
3. The method of claim 2,
The repeater is a pull-down repeater
Device.
11. The method of claim 10,
The repeater is:
a pull-down transistor configured to receive the control signal from the logic circuit
further comprising
Device.
12. The method of claim 11,
The pull-down transistor is:
source terminal coupled to ground;
a drain terminal coupled to the selector signal; and
a control terminal coupled to the output of the logic circuit
containing
Device.
12. The method of claim 11,
The logic circuit is:
a first logic gate, wherein the first logic gate is a two-input NOR gate; and
a second logic gate, wherein the second logic gate is a two-input NAND gate;
containing
Device.
According to claim 1,
The repeater is a push-pull repeater
Device.
15. The method of claim 14,
The repeater is:
a plurality of delay circuits, each said delay circuit comprising a plurality of inverters connected in series;
a plurality of logic circuits, each logic circuit configured to receive a delay signal corresponding to each of the delay circuits and generate a first control signal and a second control signal;
a pull-up transistor configured to receive the first control signal from the logic circuit; and
a pull-down transistor configured to receive the second control signal from the logic circuit
further comprising
Device.
16. The method of claim 15,
The delay circuit is:
a first delay circuit configured to receive a selector signal and generate a first delay signal during the data access operation; and
a second delay circuit configured to receive a selector signal and generate a second delay signal during the data access operation
containing
Device.
17. The method of claim 16,
The logic circuit is:
a first logic circuit configured to receive the first delay signal and generate a first control signal; and
a second logic circuit configured to receive the second delay signal and generate a second control signal
containing
Device.
16. The method of claim 15,
The pull-up transistor is:
a source terminal coupled to a power source;
a drain terminal coupled to the selector signal; and
a control terminal coupled to the output of the logic circuit
containing
Device.
16. The method of claim 15,
The pull-down transistor is:
source terminal coupled to ground;
a drain terminal coupled to the selector signal; and
a control terminal coupled to the output of the logic circuit
containing
Device.

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