KR20210088652A - network interface device - Google Patents

Abstract

A network interface device comprising a hardware module comprising a plurality of processing units. Each of the plurality of processing units is associated with at least one predefined operation of its own. At compile time, the hardware module by arranging at least some of the plurality of processing units to perform, in a predetermined order, their respective at least one operation with respect to the data packet, to perform a function with respect to the data packet is composed A compiler is provided for allocating a different processing stage to each processing unit. A controller is provided for on-the-fly switching between different processing circuitry so that one processing circuitry may be used while the other processing circuitry is being compiled.

Description

network interface device

This application relates to a network interface device for performing a function in connection with a data packet.

Network interface devices are known and are typically used to provide an interface between a computing device and a network. The network interface device may be configured to process data received from the network and/or to process data to be placed on the network.

According to an aspect, there is provided a network interface device for interfacing a host device to a network, the network interface device comprising: a first interface, the first interface configured to receive a plurality of data packets; a configurable hardware module comprising a plurality of processing units, each processing unit associated with a predefined type of operation executable in a single step, wherein each processing unit comprises a predefined predefined type of operation executable in a single step; type of operation, wherein at least some of the plurality of processing units are associated with a different predefined type of operation, the hardware module being configured to configure a first data processing pipeline for processing one or more of the plurality of data packets. provide to interconnect at least a portion of the plurality of processing units to perform a first function in connection with the one or more of the plurality of data packets.

In some embodiments, the first function includes a filtering function. In some embodiments, the functionality includes at least one of tunneling, encapsulation, and routing functionality. In some embodiments, the first function comprises an extended Berkley packet filter function.

In some embodiments, the first function comprises a distributed denial of service scrubbing operation.

In some embodiments, the first function comprises firewall operation.

In some embodiments, the first interface is configured to receive a first data packet from the network.

In some embodiments, the first interface is configured to receive a first data packet from a host device.

In some embodiments, two or more of at least some of the plurality of processing units are configured to perform their associated at least one predefined operation in parallel.

In some embodiments, two or more of at least some of the plurality of processing units are configured to perform their associated predefined type of operation according to a common clock signal of the hardware module.

In some embodiments, each of two or more of at least some of the plurality of processing units is configured to perform its associated predefined type of operation within a predefined length of time defined by the clock signal.

In some embodiments, two or more of at least some of the plurality of processing units are configured to: access the first data packet within a time period of a predefined length of time; and in response to the end of the predefined length of time, send a result of each at least one operation to the next processing unit.

In some embodiments, the result includes at least one or more of the following: at least a value from one or more of the plurality of data packets; update on map state; and metadata.

In some embodiments, each of the plurality of processing units includes an application specific integrated circuit configured to perform at least one operation associated with the respective processing unit.

In some embodiments, each of the processing units includes an array of field programmable gates. In some embodiments, each of the processing units includes any other type of soft logic.

In some embodiments, at least one of the plurality of processing units includes a memory that stores digital circuitry and state related to processing executed by the digital circuitry, the digital circuitry being, in communication with the memory, associated with each processing unit is configured to perform an action of a predefined type.

In some embodiments, the network interface device includes a memory accessible to two or more of the plurality of processing units, wherein the memory is configured to store a state associated with the first data packet, and wherein the hardware module performs a first function. while at least two of the plurality of processing units are configured to access and modify the state.

In some embodiments, a first of at least some of the plurality of processing units is configured to stall during access of a value of the state by a second of the plurality of processing units.

In some embodiments, one or more of the plurality of processing units are configurable to perform an operation unique to each pipeline, individually, based on their associated predefined type of operation.

In some embodiments, the hardware module is configured to receive the instruction, and in response to the instruction, do at least one of the following: provide a data processing pipeline for processing one or more of the plurality of data packets. interconnecting at least some of the plurality of processing units for causing one or more of the plurality of processing units to perform an operation of their associated predefined type with respect to the one or more data packets; adding one or more of the plurality of processing units to a data processing pipeline; and removing one or more of the plurality of processing units from a data processing pipeline.

In some embodiments, the predefined action includes at least one of: loading at least one value of the first data packet from memory; storing at least one value of the data packet in a memory; and performing a lookup on the lookup table to determine an action to be performed with respect to the data packet.

In some embodiments, a hardware module is configured to receive an instruction, wherein the hardware module is configured to: in response to the instruction, provide a data processing pipeline for processing one or more of the plurality of data packets. configurable to interconnect at least some of the units, the instructions comprising a data packet transmitted via a third processing pipeline.

In some embodiments, one or more of at least some of the plurality of processing units are configured to, in response to the instruction, perform a selected one of their associated predefined type of operation with respect to the one or more data of a plurality of data packets. It is possible.

In some embodiments, the plurality of components comprises a second of the plurality of components configured to provide a first function in circuitry different from the hardware module, wherein the network interface device comprises: and at least one controller configured to cause the packet to be processed by one of: a first of the plurality of components and a second of the plurality of components.

In some embodiments, the network interface device includes at least one controller configured to issue a command to cause the hardware module to start performing a first function related to the data packet, the command comprising: 1's are configured to be inserted into the processing pipeline.

In some embodiments, the network interface device includes at least one controller configured to issue an instruction to cause the hardware module to begin performing a first function related to the data packet, the instruction being transmitted through a processing pipeline and a control message transmitted and configured to cause a first of the plurality of components to be activated.

In some embodiments, for one or more of at least some of the plurality of processing units, the related at least one operation comprises at least one of: fetching at least one value of the first data packet from a memory of the network interface device. loading; storing at least one value of the first data packet in a memory of the network interface device; and performing a lookup against the lookup table to determine an action to be performed with respect to the first data packet.

In some embodiments, one or more of at least some of the plurality of processing units are configured to communicate at least one result of its associated at least one predefined operation to a next processing unit in the first processing pipeline, wherein: The burn processing unit is configured to perform a next predefined operation depending on the at least one result.

In some embodiments, each of the different predefined types of operations is defined by a different template.

In some embodiments, the predefined type of action includes at least one of: accessing a data packet; accessing a lookup table stored in the memory of the hardware module; performing logical operations on data loaded from data packets; and performing logical operations on data loaded from the lookup table.

In some embodiments, the hardware module includes routing hardware, wherein the hardware module is configured by configuring the routing hardware to route data packets between the plurality of processing units in a particular order defined by the first data processing pipeline. configurable to interconnect at least some of the plurality of processing units to provide a data processing pipeline.

In some embodiments, a hardware module is configured to provide a second data processing pipeline for processing one or more of the plurality of data packets to perform a second function different from the first function, the plurality of processing units being configured to: configurable to interconnect at least some of the

In some embodiments, a hardware module, after interconnecting at least some of the plurality of processing units to provide a first data processing pipeline, is configured to provide at least one of the plurality of processing units to provide a second data processing pipeline. Configurable to interconnect some.

In some embodiments, the network interface device includes additional circuitry separate from the hardware module and configured to perform a first function for one or more of the plurality of data packets.

In some embodiments, the additional circuitry includes at least one of: a field programmable gate array; and a plurality of central processing units.

In some embodiments, the network interface device includes at least one controller, wherein the additional circuitry is configured to perform a first function with respect to the data packet during a compilation process for a first function to be performed in the hardware module. and the at least one controller is configured to, in response to completion of the compilation process, control the hardware module to start performing a first function relating to the data packet.

In some embodiments, the additional circuitry includes a plurality of central processing units.

In some embodiments, the at least one controller is configured to, in response to the determining that the compilation process for the first function to be performed in the hardware module is complete, control the additional circuitry to stop performing the first function with respect to the data packet do.

In some embodiments, the network interface device includes at least one controller, wherein the hardware module is configured to perform a first function with respect to the data packet during a compilation process for the first function to be performed in the additional circuitry, wherein the at least one The controller of the is configured to determine that a compilation process for a first function to be performed in the additional circuitry is complete, and in response to the determination, control the additional circuitry to start performing the first function with respect to the data packet. .

In some embodiments, the additional circuitry includes a field programmable gate array.

In some embodiments, the at least one controller is configured to, in response to the determining that the compilation process for the first function to be performed in the additional circuitry is complete, control the hardware module to stop performing the first function with respect to the data packet do.

In some embodiments, the network interface device includes at least one controller configured to perform a compilation process to provide a first function to be performed in a hardware module.

In some embodiments, the compilation process includes providing instructions at the hardware module to provide a control plane interface that is responsive to control messages.

According to another aspect, there is provided a data processing system comprising a network interface device and a host device according to the first aspect, wherein the data processing system is configured to perform a compilation process to provide a first function to be performed in a hardware module at least one controller.

In some embodiments, the at least one controller is provided by one or more of: a network interface device; and host devices.

In some embodiments, the compilation process is performed in response to a determination by the at least one controller that the computer program representing the first functionality is safe for execution in kernel mode of the host device.

In some embodiments, the at least one controller configures, to each of at least a portion of the plurality of processing units, at least one operation from the plurality of operations represented by a sequence of computer code instructions to be specified in the first data processing pipeline. in order, to perform a compilation process by assigning to perform, the plurality of operations providing a first function with respect to one or more of the plurality of data packets.

In some embodiments, the at least one controller is configured to: send, prior to completion of the compilation process, a first instruction to cause additional circuitry of the network interface device to perform a first function with respect to the data packet to do; and following completion of the compilation process, sending a second instruction to cause the hardware module to start performing a first function related to the data packet.

According to another aspect, there is provided a method for implementation in a network interface device, the method comprising: receiving, at a first interface, a plurality of data packets; and a first data processing pipeline for processing one or more of the plurality of data packets to perform a first function in connection with the one or more of the plurality of data packets; configuring hardware modules to interconnect at least some, wherein each processing unit is associated with a predefined type of operation executable in a single step, wherein at least some of the plurality of processing units are of a different predefined type related to action.

According to another aspect, there is provided a non-transitory computer-readable medium comprising program instructions for causing a network interface device to perform a method, the method comprising: receiving, at a first interface, a plurality of data packets; and a first data processing pipeline for processing one or more of the plurality of data packets to perform a first function in connection with the one or more of the plurality of data packets; configuring hardware modules to interconnect at least some, wherein each processing unit is associated with a predefined type of operation executable in a single step, wherein at least some of the plurality of processing units are of a different predefined type related to action.

According to another aspect, there is provided a processing unit, configured to: perform at least one predefined operation with respect to a first data packet received at a network interface device; coupled to a first additional processing unit configured to perform a first additional at least one predefined operation in connection with the first data packet; coupled to a second additional processing unit configured to perform a second additional at least one predefined operation with respect to the first data packet; to receive, from the first additional processing unit, a result of the first additional at least one predefined operation; to perform the at least one predefined action depending on a result of the first additional at least one predefined action; and send a result of the at least one predefined operation to the second additional processing unit for processing in the second additional at least one predefined operation.

In some embodiments, the processing unit is configured to receive a clock signal for timing the at least one predefined operation, wherein the processing unit is configured to perform the at least one predefined operation in at least one cycle of the clock signal. do.

In some embodiments, the processing unit is configured to perform at least one predefined operation in a single cycle of the clock signal.

In some embodiments, the at least one predefined operation, the first additional at least one predefined operation, and the second additional at least one predefined operation are configured in connection with the first data packet received at the network interface device. Forms part of the function performed.

In some embodiments, the first data packet is received from a host device, wherein the network interface device is configured to interface the host device to a network.

In some embodiments, the first data packet is received from a network, wherein the network interface device is configured to interface the host device to the network.

In some embodiments, the function is a filtering function.

In some embodiments, the filtering function is an extended Berkeley packet filter function.

In some embodiments, the processing unit includes an application specific integrated circuit configured to perform at least one predefined operation.

In some embodiments, the processing unit comprises: a digital circuit configured to perform at least one predefined operation; and a memory storing state related to at least one predefined operation to be executed.

In some embodiments, the processing unit is configured to access a memory accessible to the first additional processing unit and the second additional processing unit, the memory configured to store a state associated with the first data packet, the at least one predefined The performed operation involves modifying the state stored in memory.

In some embodiments, the processing unit is configured to, during a first clock cycle, read the value of the state from memory and provide the value to a second additional processing unit for modification by the second additional processing unit, wherein the processing unit is configured to: The unit is configured to stall for a second clock cycle following the first clock cycle.

In some embodiments, the at least one predefined action includes at least one of: loading a first data packet from a memory of the network interface device; storing the first data packet in a memory of the network interface device; and performing a lookup against the lookup table to determine an action to be performed with respect to the first data packet.

According to another aspect, there is provided a method implemented in a processing unit, the method comprising: performing at least one predefined operation with respect to a first data packet received at a network interface device; coupling to a first additional processing unit configured to perform a first additional at least one predefined operation in connection with the first data packet; coupling to a second additional processing unit configured to perform a second additional at least one predefined operation with respect to the first data packet; receiving, from the first additional processing unit, a result of the first additional at least one predefined operation; performing the at least one predefined action depending on a result of the first additional at least one predefined action; and sending the result of the at least one predefined operation to the second additional processing unit for processing in the second additional at least one predefined operation.

According to another aspect, there is provided a computer readable non-transitory storage device that stores instructions that, when executed by a processing unit, cause the processing unit to perform a method comprising: first data received at a network interface device performing at least one predefined action with respect to the packet; coupling to a first additional processing unit configured to perform a first additional at least one predefined operation in connection with the first data packet; coupling to a second additional processing unit configured to perform a second additional at least one predefined operation with respect to the first data packet; receiving, from the first additional processing unit, a result of the first additional at least one predefined operation; performing the at least one predefined action depending on a result of the first additional at least one predefined action; and sending the result of the at least one predefined operation to the second additional processing unit for processing in the second additional at least one predefined operation.

According to another aspect, there is provided a network interface device for interfacing a host device to a network, the network interface device comprising: at least one controller; a first interface, wherein the first interface is configured to receive a data packet; a first circuitry configured to perform a first function with respect to a data packet received at the first interface; and a second circuitry, wherein the first circuitry is configured to perform a first function with respect to a data packet received at the first interface during a compilation process for the first function to be performed in the second circuitry, the at least one The controller is configured to determine whether a compilation process for a first function to be performed in the second circuitry has been completed and, in response to the determination, to initiate performance of the first function relating to a data packet received at the first interface. is configured to control

In some embodiments, the at least one controller, in response to the determining that the compilation process for the first function to be performed in the second circuitry is complete, stops performing the first function in connection with the data packet received at the first interface It is configured to control the first circuit unit to do so.

In some embodiments, the at least one controller is configured to: in response to the determining that the compilation process for the first function to be performed in the second circuitry is complete: a first associated with a data packet of a first data flow received at the first interface to begin performing the function; and control the first circuit unit to stop performing a first function related to the data packet of the first data flow.

In some embodiments, the first circuitry includes at least one central processing unit, wherein each of the at least one central processing unit is configured to perform a first function in connection with at least one data packet received at the first interface. .

In some embodiments, the second circuitry includes a field programmable gate array configured to initiate performance of a first function associated with a data packet received at the first interface.

In some embodiments, the second circuitry includes a hardware module comprising a plurality of processing units, each processing unit associated with at least one predefined operation, the first interface configured to receive the first data packet and the hardware modules, following a compilation process for the first function to be performed in the second circuitry, cause at least some of the plurality of processing units to perform at least their associated at least one function in connection with the first data packet. It is configured to perform one predefined action in a specific order.

In some embodiments, the first circuitry includes a hardware module comprising a plurality of processing units, each processing unit associated with at least one predefined operation, the first interface configured to receive a first data packet and the hardware module, during a compilation process for a first function to be performed in the second circuitry, causes at least a portion of the plurality of processing units to perform a first function in connection with the first data packet. It is configured to perform predefined actions in a specific order.

In some embodiments, the at least one controller is configured to perform a compilation process for compiling a first function to be performed by the second circuitry.

In some embodiments, the at least one controller is configured to: instruct the first circuitry to perform a first function with respect to a data packet received at the first interface, prior to completion of the compilation process.

In some embodiments, a compilation process for compiling the first function to be performed by the second circuitry is performed by a host device, wherein the at least one controller is configured to: in response to receiving an indication of completion of the compilation process from the host device and determine that the compilation process is complete.

In some embodiments, a processing pipeline for processing a data packet received at a first interface, wherein the processing pipeline is each configured to perform one of a plurality of functions with respect to a data packet received at the first interface a plurality of components comprising: a first of the plurality of components configured to provide a first function when provided by the first circuitry, and a second of the plurality of components to a second at least one processing unit. and provide the first function when provided by

In some embodiments, the at least one controller controls the second circuitry to begin performing a first function relating to a data packet received at the first interface by inserting a second of the plurality of components into the processing pipeline. configured to do

In some embodiments, the at least one controller, in response to the determining that the compilation process for the first function to be performed in the second circuitry is complete, by removing the first one of the plurality of components from the processing pipeline and control the first circuit unit to stop performing a first function related to a data packet received on the first interface.

In some embodiments, the at least one controller performs performance of a first function relating to a data packet received at the first interface by sending a control message through the processing pipeline to activate a second one of the plurality of components. and control the second circuitry to start.

In some embodiments, the at least one controller controls via the processing pipeline to deactivate a second of the plurality of components in response to the determining that the compilation process for the first function to be performed in the second circuitry is complete. and control the first circuitry to stop performing a first function relating to a data packet received at the first interface by sending the message.

In some embodiments, a first of the plurality of components is configured to provide a first function with respect to a data packet of a first data flow passing through a processing pipeline, wherein a second of the plurality of components is configured to provide a processing pipeline and provide a first function with respect to a data packet in a second data flow passing therethrough.

In some embodiments, the first function comprises filtering the data packet.

In some embodiments, the first interface is configured to receive a data packet from the network.

In some embodiments, the first interface is configured to receive a data packet from a host device.

In some embodiments, the compile time of the first function for the second circuitry is greater than the compile time of the first function for the first circuitry.

According to another aspect, a method is provided, the method comprising: receiving a data packet at a first interface of a network interface device; performing, in a first circuit portion of the network interface device, a first function with respect to a data packet received at the first interface; The first circuitry is configured to perform a first function with respect to a data packet received at the first interface during a compilation process for a first function to be performed in the second circuitry, the method comprising: a second circuitry determining that the compilation process for the first function to be performed in is completed; and in response to the determination, controlling the second circuitry of the network interface device to begin performing a first function relating to a data packet received at the first interface.

According to another aspect, there is provided a non-transitory computer-readable medium comprising program instructions for causing a data processing system to perform a method, the method comprising: receiving a data packet at a first interface of a network interface device; ; performing, in a first circuitry of the network interface device, a first function with respect to a data packet received at the first interface, wherein the first circuitry comprises: performing a first function during a compilation process for a first function to be performed in a second circuitry; configured to perform a first function with respect to a data packet received at the first interface, the method comprising: determining that a compilation process for the first function to be performed in the second circuitry is completed; and in response to the determination, controlling the second circuitry of the network interface device to begin performing a first function relating to a data packet received at the first interface.

According to another aspect, there is provided a non-transitory computer-readable medium comprising program instructions for causing a data processing system to perform the following: Compiling a first function to be performed by second circuitry of a network interface device to perform the compilation process for; prior to completion of the compilation process, sending a first instruction to cause the first circuitry of the network interface device to perform a first function with respect to a data packet received at the first interface of the network interface device; and following completion of the compilation process, sending a second instruction to cause the second circuitry to begin performing a first function relating to a data packet received at the first interface.

In some embodiments, a non-transitory computer-readable medium includes program instructions for causing a data processing system to perform an additional compilation process to compile a first function to be performed by first circuitry, wherein: The time taken is longer than the time taken for the additional compilation process.

In some embodiments, the data processing system includes a host device, wherein the network interface device is configured to interface the host device with a network.

In some embodiments, the data comprising the system comprises a network interface device, wherein the network interface device is configured to interface the host device with the network.

In some embodiments, a data processing system includes a host device and a network interface device, wherein the network interface device is configured to interface the host device with a network.

In some embodiments, the first function includes filtering data packets received at the first interface from the network.

In some embodiments, the non-transitory computer-readable medium includes program instructions for causing a data processing system to perform: Following completion of a compilation process, causing the first circuitry to: receive at a first interface Transmitting a third command to stop performing a function related to the data packet being received.

In some embodiments, a non-transitory computer-readable medium includes program instructions for causing a data processing system to perform: cause a second circuitry to cause a first function with respect to a data packet in a first data flow. sending a command to perform and sending an instruction to cause the first circuitry to stop performing a first function with respect to the data packet in the first data flow.

In some embodiments, the first circuitry includes at least one central processing unit, wherein prior to completion of the second compilation process, each of the at least one central processing unit is associated with at least one data packet received at the first interface. to perform the first function.

In some embodiments, the second circuitry includes a field programmable gate array configured to initiate performance of a first function associated with a data packet received at the first interface.

In some embodiments, the second circuitry includes a hardware module comprising a plurality of processing units, each processing unit associated with at least one predefined operation, wherein the data packet received at the first interface includes the first data packet, wherein the hardware module is configured such that, subsequent to completion of the second compilation process, each processing unit of at least some of the plurality of processing units performs its respective at least one operation with respect to the first data packet. and perform a first function with respect to the first data packet by

In some embodiments, the first circuitry includes a hardware module comprising a plurality of processing units configured to provide a first function in connection with a data packet, each processing unit being associated with at least one predefined operation. wherein the data packet received at the first interface includes the first data packet, and the hardware module is configured to: prior to completion of the second compilation process, each processing unit of at least some of the plurality of processing units with the first data packet and perform a first function in association with the first data packet by performing its respective at least one operation in association.

In some embodiments, the compilation process comprises assigning, in a particular order, to each of a plurality of processing units of the second circuitry to perform at least one operation associated with one of a plurality of processing stages of a sequence of computer code instructions. include

In some embodiments, a first function provided by the first circuitry is provided as a component of a processing pipeline for processing a data packet received at a first interface, wherein the first function provided by the second circuitry is processing It is provided as a component of the pipeline.

In some embodiments, the first instruction comprises an instruction configured to cause a first one of the plurality of components to be inserted into the processing pipeline.

In some embodiments, the second instruction comprises an instruction configured to cause a second one of the plurality of components to be inserted into the processing pipeline.

In some embodiments, the non-transitory computer readable medium causes the data processing system to: subsequent to completion of the compilation process, cause the first circuitry to stop performing a first function relating to a data packet received at the first interface. program instructions to cause to perform sending a third instruction to do so, wherein the third instruction comprises instructions configured to cause a first one of the plurality of components to be removed from the processing pipeline.

In some embodiments, the first instruction includes a control message to be transmitted via the processing pipeline to activate a second one of the plurality of components.

In some embodiments, the second instruction includes a control message to be transmitted via the processing pipeline to activate a second of the plurality of components.

In some embodiments, the non-transitory computer-readable medium is configured to cause the data processing system to:, subsequent to completion of a compilation process, cause the first circuitry to cease performing a function relating to a data packet received at the first interface. program instructions to cause sending a third instruction for: a third instruction comprising a control message passing through a processing pipeline to deactivate a first one of the plurality of components.

According to another aspect, there is provided a data processing system comprising at least one processor and at least one memory comprising computer program code, wherein the at least one memory and computer program code, together with the at least one processor, comprise a data processing system to: perform a compilation process to compile a function to be performed by the second circuitry of the network interface device; instruct the first circuitry of the network interface device to perform a function with respect to a data packet received at the first interface of the network interface device prior to completion of the compilation process; and instruct the second at least one processing unit to start performing a function related to the data packet received at the first interface following completion of the second compilation process.

According to another aspect, there is provided a method for implementation in a data processing system, the method comprising: performing a compilation process to compile a function to be performed by second circuitry of a network interface device; prior to completion of the compilation process, sending a first instruction to cause the first circuitry of the network interface device to perform a function with respect to a data packet received at the first interface of the network interface device; and following completion of the compilation process, sending a second instruction to cause the second circuitry to begin performing a function relating to the data packet received at the first interface.

According to another aspect, a method for causing a data processing system to assign to each of a plurality of processing units to perform, in a particular order, at least one operation associated with each of a plurality of processing stages of a sequence of computer code instructions A non-transitory computer-readable medium comprising program instructions is provided, wherein a plurality of processing stages provide a first function in connection with a first data packet received at a first interface of a network interface device, each of the plurality of processing units is configured to perform one of a plurality of types of processing, at least some of the plurality of processing units are configured to perform a different type of processing, and, for each of the plurality of processing units, allocating, is performed in accordance with determining that it is configured to perform a suitable type of processing to perform the at least one operation.

In some embodiments, each type of processing is defined by one of a plurality of templates.

In some embodiments, the type of processing includes at least one of: accessing a data packet received at the network interface device; accessing a lookup table stored in the memory of the hardware module; performing logical operations on data loaded from data packets; and performing logical operations on data loaded from the lookup table.

In some embodiments, two or more of at least some of the plurality of processing units are configured to perform their associated at least one operation according to a common clock signal of the hardware module.

In some embodiments, assigning comprises assigning to each of two or more of at least some of the plurality of processing units to perform its associated at least one operation within a predefined length of time defined by a clock signal. include

In some embodiments, allocating comprises allocating to two or more of the at least some of the plurality of processing units to access the first data packet within a time period of a predefined length of time.

In some embodiments, assigning, in response to an end of a time period of a predefined length of time, to each of two or more of the at least some of the plurality of processing units, to each of the at least one Includes allocating what to send to the unit

In some embodiments, the non-transitory computer-readable medium contains program instructions for causing a data processing system to perform the following: Allocating to at least some of the plurality of stages to occupy a single clock cycle.

In some embodiments, the non-transitory computer-readable medium contains program instructions for causing a data processing system to assign to two or more of a plurality of processing units to execute at least one of their assigned operations to be executed in parallel. include

In some embodiments, the network interface device includes a hardware module that includes a plurality of processing units.

In some embodiments, a non-transitory computer-readable medium includes computer program instructions for causing a data processing system to: perform a compilation process comprising assignment; prior to completion of the compilation process, sending a first instruction to cause circuitry of the network interface device to perform a first function with respect to a data packet received at the first interface; and, subsequent to completion of the compilation process, sending a second instruction to cause the plurality of processing units to begin performing a first function relating to a data packet received at the first interface.

In some embodiments, for one or more of at least some of the plurality of processing units, the assigned at least one operation comprises at least one of: at least one value of the first data packet from a memory of the network interface device loading ; storing at least one value of the first data packet in a memory of the network interface device; and performing a lookup against the lookup table to determine an action to be performed with respect to the first data packet.

In some embodiments, the non-transitory computer-readable medium is configured to cause the data processing system to route the first data packet between the plurality of processing units in a particular order to perform a first function in connection with the first data packet. and computer program instructions for causing the computer to issue instructions for configuring routing hardware of the network interface device.

In some embodiments, the first functionality provided by the plurality of processing units is provided as a component of a processing pipeline for processing a data packet received at the first interface.

In some embodiments, the non-transitory computer readable medium is configured to cause a first data packet to be received in connection with a data packet received at the first interface by causing the data processing system to issue instructions for causing a component to be inserted into a processing pipeline. and computer program instructions for causing a plurality of processing units to initiate performance of a function.

In some embodiments, the non-transitory computer-readable medium is configured to cause a first data packet to be received at a first interface by causing the data processing system to issue instructions to cause a component to be activated in a processing pipeline. and computer program instructions for causing a plurality of processing units to initiate performance of a function.

In some embodiments, the data processing system includes a host device, wherein the network interface device is configured to interface the host device with a network.

In some embodiments, the data processing system includes a network interface device.

In some embodiments, a data processing system includes: a network interface device; and a host device, wherein the network interface device is configured to interface the host device with the network.

According to another aspect, there is provided a data processing system comprising at least one processor and at least one memory comprising computer program code, wherein the at least one memory and computer program code, together with the at least one processor, comprise a data processing system assign to each of the plurality of processing units to perform, in a particular order, at least one operation associated with one of the plurality of processing stages of the sequence of computer code instructions, the plurality of processing stages comprising: provide a first function in connection with a first data packet received at a first interface of the interface device, each of the plurality of processing units configured to perform one of a plurality of types of processing, wherein at least a portion of the plurality of processing units is configured to perform a different type of processing, and, for each of the plurality of processing units, the assigning includes determining that the processing unit is configured to perform a type of processing suitable for performing each at least one operation. performed depending on

According to another aspect, there is provided a method comprising assigning, in a particular order, to each of a plurality of processing units to perform at least one operation related to one of a plurality of processing stages of a sequence of computer code instructions, The plurality of processing stages provides a first function in connection with a first data packet received at a first interface of the network interface device, each of the plurality of processing units being configured to perform one of a plurality of types of processing; wherein at least some of the processing units of are configured to perform different types of processing, and for each of the plurality of processing units, assigning is such that the processing unit performs a type of processing suitable for performing each at least one operation. It is performed depending on determining what constitutes.

The processing units of hardware modules have been described as executing their type of operation in a single step. However, those skilled in the art will recognize that this feature is only a preferred feature and is not essential or essential to the functioning of the present invention.

According to one aspect, there is provided a method comprising: at a compiler, a bit file description of a circuit, the bit file description comprising a description of routing of a portion of a circuit, and receiving a program that; and compiling the program using the bit file description to output a bit file for the program.

The method may include using the bit file to configure at least a portion of the portion of the circuitry to perform a function associated with the program.

The bit file description may include information regarding routing between a plurality of processing units of said portion of a circuit.

The bit file description may include routing information for at least one of the plurality of processing units indicating at least one of the following: to which one or more other processing units data may be output; and from which one or more other processing units the data may be received.

The bit file description may include routing information indicating one or more routes between two or more respective processing units.

The bit file description may include information indicating only the root available by the compiler when compiling the program to provide the bit file for the program.

The bit file may include information indicating, for each processing unit, at least one of the following: a bit file description for each processing unit whose input is from any one or more of the one or more other processing units. should be provided from; Output should be provided in the bit file description for each processing unit to which one or more of the one or more other processing units.

A portion of the circuit may include at least a portion of a configurable hardware module comprising a plurality of processing units, each processing unit associated with a predefined type of operation executable in a single step, the plurality of processing units at least some of which relate to different predefined types of operation, the bit file description includes information regarding routing between at least some of a plurality of processing units, the method comprising: the bit file to provide a first data processing pipeline for processing to cause hardware to interconnect at least some of the plurality of processing units to perform a first function in connection with the one or more of the plurality of data packets may include the use of

The bit file description may be of at least a portion of the FPGA.

The bit file description may be part of a dynamically programmable FPGA.

The program may include one of an eBPF program and a P4 program.

The compiler and FPGA may be provided in a network interface device.

According to another aspect, there is provided an apparatus comprising at least one processor and at least one memory comprising computer code for one or more programs, the at least one memory and computer code, together with the at least one processor, into the apparatus to receive at least: a bit file description, the bit file description including a description of routing of a portion of a circuit, and a program; and compile the program using the bit file description to output a bit file for the program.

At least one memory and computer code, together with at least one processor, may be configured to cause an apparatus to use the bit file to configure at least a portion of the portion of the circuit to perform a function associated with the program. may be

The bit file description may include information regarding routing between a plurality of processing units of said portion of a circuit.

The bit file description may include routing information for at least one of the plurality of processing units indicating at least one of the following: to which one or more other processing units data may be output; and from which one or more other processing units the data may be received.

The bit file description may include routing information indicative of one or more routes between two or more respective processing units.

The bit file description may include information indicating only the root available by the compiler when compiling the program to provide the bit file for the program.

The bit file may include information indicating, for each processing unit, at least one of the following: a bit file description for each processing unit whose input is from any one or more of the one or more other processing units. should be provided from; Output should be provided in the bit file description for each processing unit to which one or more of the one or more other processing units.

A portion of the circuit may include at least a portion of a configurable hardware module comprising a plurality of processing units, each processing unit associated with a predefined type of operation executable in a single step, the plurality of processing units at least some of which relate to different predefined types of operation, wherein the bit file description includes information regarding routing between at least some of the plurality of processing units, the at least one memory and computer code comprising: at least one processor together with an apparatus to provide a first data processing pipeline for processing one or more of the plurality of data packets to cause hardware to perform a first function with respect to the one or more of the plurality of data packets. and use the bit file to interconnect at least some of the plurality of processing units.

The bit file description may be of at least a portion of the FPGA.

The bit file description may be part of a dynamically programmable FPGA.

The program may include one of an eBPF program and a P4 program.

According to another aspect, there is provided a network interface device comprising: a first interface, the first interface configured to receive a plurality of data packets; a configurable hardware module comprising a plurality of processing units, each processing unit associated with a predefined type of operation executable in a single step; a compiler, wherein the compiler is configured to receive a bit file description, wherein the bit file description includes a description of routing of at least a portion of the configurable hardware module, and to receive a program, and to output a bit file for the program. configured to compile the program using a description, wherein the hardware module is configurable using the bit file to perform a first function associated with the program.

The network interface device may be for interfacing a host device to a network.

At least some of the plurality of processing units may be associated with different predefined types of operation.

A hardware module is configured to provide a first data processing pipeline for processing one or more of the plurality of data packets to perform a first function in relation to the one or more of the plurality of data packets, wherein the plurality of the processing units are configured to: may be configurable to interconnect at least some of the

In some embodiments, the first function includes a filtering function. In some embodiments, the functionality includes at least one of tunneling, encapsulation, and routing functionality. In some embodiments, the first function comprises an extended Berkeley packet filter function.

In some embodiments, the first function comprises a distributed denial of service scrubbing operation.

In some embodiments, the first function comprises firewall operation.

In some embodiments, the first interface is configured to receive a first data packet from the network.

In some embodiments, the first interface is configured to receive a first data packet from a host device.

In some embodiments, two or more of at least some of the plurality of processing units are configured to perform their associated at least one predefined operation in parallel.

In some embodiments, two or more of at least some of the plurality of processing units are configured to perform their associated predefined type of operation according to a common clock signal of the hardware module.

In some embodiments, each of two or more of at least some of the plurality of processing units is configured to perform its associated predefined type of operation within a predefined length of time defined by the clock signal.

In some embodiments, two or more of at least some of the plurality of processing units are configured to: access the first data packet within a time period of a predefined length of time; and in response to the end of the predefined length of time, send a result of each at least one operation to the next processing unit.

In some embodiments, the result includes at least one or more of the following: at least a value from one or more of the plurality of data packets; update on map state; and metadata.

In some embodiments, each of the plurality of processing units includes an application specific integrated circuit configured to perform at least one operation associated with the respective processing unit.

In some embodiments, each of the processing units includes an array of field programmable gates. In some embodiments, each of the processing units includes any other type of soft logic.

In some embodiments, at least one of the plurality of processing units includes a memory that stores digital circuitry and state related to processing executed by the digital circuitry, the digital circuitry being, in communication with the memory, associated with each processing unit is configured to perform an action of a predefined type.

In some embodiments, the network interface device includes a memory accessible to two or more of the plurality of processing units, wherein the memory is configured to store a state associated with the first data packet, and wherein the hardware module performs a first function. while at least two of the plurality of processing units are configured to access and modify the state.

In some embodiments, a first one of at least some of the plurality of processing units is configured to stall during access of a value of the state by a second one of the plurality of processing units.

In some embodiments, one or more of the plurality of processing units are configurable to perform an operation unique to each pipeline, individually, based on their associated predefined type of operation.

In some embodiments, the hardware module is configured to receive the instruction, and in response to the instruction, do at least one of the following: provide a data processing pipeline for processing one or more of the plurality of data packets. interconnecting at least some of the plurality of processing units for causing one or more of the plurality of processing units to perform an operation of their associated predefined type with respect to the one or more data packets; adding one or more of the plurality of processing units to a data processing pipeline; and removing one or more of the plurality of processing units from a data processing pipeline.

In some embodiments, the predefined action includes at least one of: loading at least one value of the first data packet from memory; storing at least one value of the data packet in a memory; and performing a lookup on the lookup table to determine an action to be performed with respect to the data packet.

In some embodiments, a hardware module is configured to receive an instruction, wherein the hardware module is configured to: in response to the instruction, provide a data processing pipeline for processing one or more of the plurality of data packets. configurable to interconnect at least some of the units, the instructions comprising a data packet transmitted via a third processing pipeline.

In some embodiments, one or more of at least some of the plurality of processing units are configured to, in response to the instruction, perform a selected one of their associated predefined type of operation with respect to the one or more data of a plurality of data packets. It is possible.

In some embodiments, the plurality of components comprises a second of the plurality of components configured to provide a first function in circuitry different from the hardware module, wherein the network interface device causes the data packet passing through the processing pipeline to: , at least one controller configured to cause processing by one of: a first of the plurality of components and a second of the plurality of components.

In some embodiments, the network interface device includes at least one controller configured to issue a command to cause the hardware module to start performing a first function related to the data packet, the command comprising: 1's are configured to be inserted into the processing pipeline.

In some embodiments, the network interface device includes at least one controller configured to issue an instruction to cause the hardware module to begin performing a first function related to the data packet, the instruction being transmitted through a processing pipeline and a control message transmitted and configured to cause a first of the plurality of components to be activated.

In some embodiments, for one or more of at least some of the plurality of processing units, the related at least one operation comprises at least one of: fetching at least one value of the first data packet from a memory of the network interface device. loading; storing at least one value of the first data packet in a memory of the network interface device; and performing a lookup against the lookup table to determine an action to be performed with respect to the first data packet.

In some embodiments, one or more of at least some of the plurality of processing units are configured to communicate at least one result of its associated at least one predefined operation to a next processing unit in the first processing pipeline, wherein: The burn processing unit is configured to perform a next predefined operation depending on the at least one result.

In some embodiments, each of the different predefined types of operations is defined by a different template.

In some embodiments, the predefined type of action includes at least one of: accessing a data packet; accessing a lookup table stored in the memory of the hardware module; performing logical operations on data loaded from data packets; and performing logical operations on data loaded from the lookup table.

In some embodiments, the hardware module includes routing hardware, wherein the hardware module is configured by configuring the routing hardware to route data packets between the plurality of processing units in a particular order defined by the first data processing pipeline. configurable to interconnect at least some of the plurality of processing units to provide a data processing pipeline.

In some embodiments, a hardware module is configured to provide a second data processing pipeline for processing one or more of the plurality of data packets to perform a second function different from the first function, the plurality of processing units being configured to: configurable to interconnect at least some of the

In some embodiments, a hardware module, after interconnecting at least some of the plurality of processing units to provide a first data processing pipeline, is configured to provide at least one of the plurality of processing units to provide a second data processing pipeline. Configurable to interconnect some.

In some embodiments, the network interface device includes additional circuitry separate from the hardware module and configured to perform a first function for one or more of the plurality of data packets.

In some embodiments, the additional circuitry includes at least one of: a field programmable gate array; and a plurality of central processing units.

In some embodiments, the network interface device includes at least one controller, wherein the additional circuitry is configured to perform a first function with respect to a data packet during a compilation process for a first function to be performed in the hardware module, wherein the at least one The controller of the , in response to the completion of the compilation process, is configured to control the hardware module to start performing a first function related to the data packet.

In some embodiments, the additional circuitry includes a plurality of central processing units.

In some embodiments, the at least one controller is configured to, in response to the determining that the compilation process for the first function to be performed in the hardware module is complete, control the additional circuitry to stop performing the first function with respect to the data packet do.

In some embodiments, the network interface device includes at least one controller, wherein the hardware module is configured to perform a first function with respect to the data packet during a compilation process for the first function to be performed in the additional circuitry, wherein the at least one The controller of the is configured to determine that a compilation process for a first function to be performed in the additional circuitry is complete, and in response to the determination, control the additional circuitry to start performing the first function with respect to the data packet. .

In some embodiments, the additional circuitry includes a field programmable gate array.

In some embodiments, the at least one controller is configured to, in response to the determining that the compilation process for the first function to be performed in the additional circuitry is complete, control the hardware module to stop performing the first function with respect to the data packet do.

In some embodiments, the network interface device includes at least one controller configured to perform a compilation process to provide a first function to be performed in a hardware module.

In some embodiments, the compilation process includes providing instructions at the hardware module to provide a control plane interface that is responsive to control messages.

According to another aspect, a computer-implemented method is provided, the computer-implemented method comprising: determining routing information for at least a portion of a configurable hardware module comprising a plurality of processing units, wherein each processing unit performs a single step and wherein at least some of the plurality of processing units are associated with different predefined types of operations, wherein the routing information relates to at least an available route between the plurality of processing units. provides

A configurable hardware module may include a substantially static portion and a substantially dynamic portion, wherein determining includes determining routing information for the substantially dynamic portion.

Determining routing information for the substantially dynamic portion may include determining, in the substantially dynamic portion, routing used by one or more of the processing units in the substantially static portion.

Determining may include analyzing a bit file description of at least a portion of the configurable hardware module to determine the routing information.

According to another aspect, there is provided a non-transitory computer-readable medium comprising program instructions for determining routing information for at least a portion of a configurable hardware module comprising a plurality of processing units, each processing unit comprising: associated with a predefined type of operation executable in the step, wherein at least some of the plurality of processing units are associated with different predefined types of operation, and the routing information relates to at least an available route between the plurality of processing units. provide information.

A computer program comprising program code means adapted to perform the method(s) may also be provided. The computer program may be stored on a carrier medium and/or otherwise embodied.

In the foregoing, many different embodiments have been described. It should be appreciated that additional embodiments may be provided by a combination of any two or more of the embodiments described above.

Various other and additional embodiments are also set forth in the following detailed description and in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS Some embodiments will now be described by way of example only with reference to the accompanying drawings, in which:
1 shows a schematic diagram of a data processing system coupled to a network;
2 shows a schematic diagram of a data processing system including a filtering operation application configured to run in user mode on a host computing device;
3 shows a schematic diagram of a data processing system including a filtering operation configured to run in kernel mode on a host computing device;
4 shows a schematic diagram of a network interface device comprising a plurality of CPUs for performing functions in connection with data packets;
5 shows a schematic diagram of a network interface device including a field programmable gate array executing an application for performing a function in connection with a data packet;
6 shows a schematic diagram of a network interface device comprising hardware modules for performing functions in connection with data packets;
7 shows a schematic diagram of a network interface device comprising at least one processing unit and a field programmable gate array for performing a function in connection with a data packet;
8 illustrates a method implemented in a network interface device in accordance with some embodiments;
9 illustrates a method implemented in a network interface device in accordance with some embodiments;
10 illustrates an example of processing a data packet by a series of programs;
11 illustrates an example of processing a data packet by a plurality of processing units;
12 illustrates an example of processing a data packet by a plurality of processing units;
13 illustrates an example of a pipeline of a processing stage for processing a data packet;
14 illustrates an example of a slice architecture with a plurality of pluggable components;
15 illustrates an exemplary representation of an arrangement and order of processing of a plurality of processing units;
16 illustrates an example method of compiling a function;
17 illustrates an example of a stateful processing unit;
18 illustrates an example of a stateless processing unit;
19 depicts a method of some embodiments;
20A and 20B illustrate routing between slices in an FPGA; And
21 schematically illustrates a partition on FGPA.

The following description is provided to enable any person skilled in the art to make and use the invention, and is provided in the context of a particular application. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art.

The generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention. Accordingly, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

When data is to be transferred between two data processing systems over a data channel, such as a network, each of the data processing systems is provided with an appropriate network interface to allow each of them to communicate over the channel. Often, networks are based on Ethernet technology. A data processing system that must communicate over a network must have a network interface that can support the physical and logical requirements of the network protocol. The physical hardware component of the network interface is referred to as a network interface device or network interface card (NIC).

Most computer systems include an operating system (OS) through which user-level applications communicate with a network. Part of the operating system, known as the kernel, includes a protocol stack for converting commands and data between applications and device drivers specific to network interface devices. The device driver may directly control the network interface device. By providing these functions in the operating system kernel, the complexity and differences between network interface devices can be hidden from user level applications. Network hardware and other system resources (eg, memory) may be securely shared by many applications, and the system may be protected against faulty or malicious applications.

A typical data processing system 100 for effecting transmission over a network is shown in FIG. 1 . The data processing system 100 includes a host computing device 101 coupled to a network interface device 102 arranged to interface a host to a network 103 . The host computing device 101 includes an operating system 104 that supports one or more user level applications 105 . The host computing device 101 may also include a network protocol stack (not shown). For example, a protocol stack may be a component of an application, a library to which an application is linked, or may be provided by an operating system. In some embodiments, more than one protocol stack may be provided.

The network protocol stack may be a Transmission Control Protocol (TCP) stack. An application 105 can send and receive TCP/IP messages by opening a socket and writing data to and reading data from the socket, and the operating system 104 causes the message to be sent over the network. make it For example, the application may call a syscall for transmission of data to the network 103 over a socket and then over the operating system 104 . This interface for sending messages may be known as a message passing interface.

Instead of implementing the stack at the host 101 , some systems offload the protocol stack to the network interface device 102 . For example, when the stack is a TCP stack, the network interface device 102 may include a TCP Offload Engine (TOE) for performing TCP protocol processing. By performing protocol processing at the network interface device 102 instead of performing at the host computing device 101 , the demands on the processor 101 of the host system may be reduced. Data to be transmitted over the network may be transmitted by the application 105 through a TOE-enabled virtual interface driver, by partially or fully bypassing the kernel TCP/IP stack. Therefore, data transmitted along this fast path need only be formatted to meet the requirements of the TOE driver.

The host computing device 101 may include one or more processors and one or more memory. In some embodiments, host computing device 101 and network interface device 102 may communicate via a bus, eg, a peripheral component interconnect express (PCIe bus).

During operation of the data processing system, data to be transmitted over a network may be transmitted from the host computing device 101 to the network interface device 102 for transmission. In one example, the data packet may be sent directly from the host to the network interface device by the host processor. The host may provide data to one or more buffers 106 located on the network interface device 102 . The network interface device 102 may then prepare the data packets and transmit them over the network 103 .

Alternatively, the data may be written to the buffer 107 in the host system 101 . The data may then be retrieved from the buffer 107 by the network interface device and transmitted over the network 103 .

In both of these cases, the data is temporarily stored in one or more buffers prior to transmission over the network. Data transmitted over the network may be returned to the host (in a lookback).

When data packets are sent over and received from network 103, there are many processing tasks that can be expressed as operations on data packets that are either data packets to be transmitted over the network or data packets received from the network. . For example, to protect the host system 101 from distributed denial of service (DDOS) filtering, a filtering process may be performed on the received data packets. Such a filtering process may be performed by a simple pack examination or an extended Berkley packet filter (eBPF). As another example, encapsulation and forwarding may be performed on data packets to be transmitted over the network 103 . These processes may consume many CPU cycles and may be a burden on conventional OS architectures.

Reference is made to FIG. 2 , which illustrates one way in which a filtering operation or other packet processing operation may be implemented in the host system 220 . Processes performed by the host system 220 are shown to be performed in either user space or kernel space. A reception path for delivering a data packet received from the network in the network interface device 210 to a terminating application 250 exists in the kernel space. This receive path includes a driver 235 , a protocol stack 240 , and a socket 245 . The filtering operation 230 is implemented in user space. Incoming packets provided by the network interface device 210 to the host system 220 bypass the kernel (where protocol processing takes place) and are provided directly to the filtering operation 230 .

The filtering operation 230 is a virtual interface (this is an ether fabric virtual interface (EFVI) or data plane development kit (DPDK) for exchanging data packets with other elements in the host system 220 ). ) or any other suitable interface). The filtering operation 230 may perform DDOS scrubbing and/or other types of filtering. A DDOS scrubbing process may be run for all packets that are readily recognized as DDOS candidates - for example, sample packets, copies of packets, and packets that have not yet been classified. Packets that are not transferred to the filtering operation 230 may be directly transferred from the network interface to the driver 235 . Operation 230 may provide an extended Berkeley packet filter (eBPF) for performing filtering. If the received packet passes the filtering provided by operation 230 , operation 230 is configured to re-inject the packet into a receive path within the kernel for processing the received packet. Specifically, the packet is provided to the driver 235 or stack 240 . The packet is then protocol processed by the protocol stack 240 . The packet is then forwarded to the socket 245 associated with the end application 250 . The end application 250 issues a recv() call to retrieve the data packet from the buffer of the associated socket.

However, there are several problems with this approach. First, the filtering operation 230 is executed on the host CPU. In order to perform filtering 230, the host CPU must process data packets at the rate at which they are received from the network. When data is sent to and received from the network at a high rate, this can constitute a large waste of processing resources of the host CPU. High data flow rates for filtering operation 230 may result in large consumption of other limited resources, such as I/O bandwidth and internal memory/cache bandwidth.

In order to perform the re-injection of the data packet into the kernel, it is necessary to provide the filtering operation 230 with a privileged API for performing the re-injection. The re-injection process can be cumbersome as it requires attention to packet order. To perform reinjection, operation 230 may require a dedicated CPU core in many cases.

Providing and re-injecting data into the operation requires that the data be copied to or from memory. This copy becomes a resource burden on the system.

A similar problem may arise when providing other types of operation other than filtering for data to be transmitted/received over a network.

Some operations (eg, DPDK type operations) may require forwarding the processed packets back to the network.

Reference is made to FIG. 3 which illustrates another approach. Like elements are referenced using like reference numbers. In this example, an additional layer known as the express data path (XDP) 310 is inserted into the transmit and receive paths within the kernel. Extensions to XDP 310 allow insertion into the transmit path. The XDP helper allows packets to be transmitted (as a result of a receive operation). XDP 310 is inserted at the driver level of the operating system, and before the data packets are protocol-processed by stack 240, programs are executed at this level to perform operations on data packets received from the network. allow XDP 310 also allows programs to run at this level to perform operations on data packets to be transmitted over the network. Thus, eBPF programs and other programs can operate in the transmit and receive paths.

As illustrated in FIG. 3 , a filtering operation 320 may be inserted into the XDP from user space to form a program 330 that is part of the XDP 310 . Operation 320 is inserted using the XDP control plane to be executed on the data receive path to provide a program 330 that performs filtering operations (eg, DDOS scrubbing) on packets on the receive path. Such a program 330 may be an eBPF program.

Program 330 is shown to be inserted into the kernel between driver 235 and protocol stack 240 . However, in other examples, the program 330 may be inserted at another point in the receive path of the kernel. Program 330 may be part of a separate control path for receiving data packets. Program 330 may be provided by an application by providing an extension to an application programming interface (API) of socket 245 for that application.

The program 330 may additionally or alternatively perform one or more operations on data being transmitted over the transmission path. The XDP 310 then calls the transmit function of the driver 235 to transmit data over the network via the network interface device 210 . In this case, the program 330 may provide a load balancing or routing operation with respect to the data packet to be transmitted over the network. Program 330 may provide segment re-encapsulation and forwarding operations with respect to data packets to be transmitted over the network.

Program 330 may also be used for firewall and virtual switching or other operations that do not require protocol termination or application processing.

One advantage of using XDP 310 in this manner is that program 330 can directly access memory buffers handled by the driver, without an intermediate copy.

In order to insert the program 330 for operation in the kernel in this way, it is necessary to ensure that the program 330 is secure. When an unsafe program is inserted into the kernel, it presents certain risks: an infinite loop that can break the kernel; Performance problems caused by buffer overflows, uninitialized variables, compiler errors, and large programs.

To ensure that the program 330 is secure prior to insertion into the XDP 310 in this manner, a verifier may be run on the host system 220 to verify the safety of the program 330 . The verifier may be configured to guarantee that no loops exist. A reverse jump operation may be allowed if it does not cause a loop. The verifier may be configured to ensure that the program 330 has no more than a predefined number (eg, 4000) of instructions. The verifier may perform a check on the validity of the register usage by passing through the data path of the program 330 . If there are too many possible paths, the program 330 will be rejected as unsafe to run in kernel mode. For example, if there are more than 1000 branches, the program 330 may be rejected.

It will be appreciated by those skilled in the art that XDP, whereby the secure program 330 may be installed in the kernel, is one example, and that there are other ways in which this may be accomplished.

For example, if an operation can be expressed in a secure (or sandboxed) language required to execute code in the kernel, the approach discussed above with respect to FIG. 3 is the approach discussed above with respect to FIG. 2 . It may be as effective as the approach The eBPF language can run efficiently on x86 processors and Just in Time (JIT) compilation technology enables eBPF programs to be compiled into native machine code. The language is designed to be secure, eg, state is limited to mapping only constructs that are shared data structures (eg, hash tables). Limited looping is allowed, instead allowing one eBPF program to tail-call another program. The state space is limited.

However, in some implementations, there may be a significant waste of resources (eg, I/O bandwidth and internal memory/cache bandwidth, host CPU) of the host system 220 in this approach. Operations on data packets are still being performed by the host CPU required to perform those operations at the rate at which data is being transmitted/received.

Another proposal is to perform the operations discussed above in the network interface device instead of in the host system. Doing so may free up CPU cycles used by the host CPU when executing operations, in addition to consumed I/O bandwidth, memory and cache bandwidth. Moving the execution of processing operations from the host to the hardware of the network interface device may present certain challenges.

One proposal for implementing processing in network hardware is to provide, in a network interface device, a network processing unit (NPU) comprising a plurality of CPUs, which is specialized for packet processing and/or manipulation operations.

Reference is made to FIG. 4 , which illustrates an example of a network interface device 400 including an array 410 of a central processing unit (CPU), eg, CPU 420 . The CPU is configured to perform functions such as filtering data packets sent to and received from the network. Each CPU in the array 410 of CPUs may be an NPU. Although not shown in FIG. 4 , the CPU may additionally or alternatively be configured to perform operations, such as load balancing, on data packets received from a host for transmission over a network. These CPUs are specialized for such packet processing/manipulation operations. The CPU executes an instruction set that is optimized for such packet processing/manipulation operations.

The network interface device 400 further includes memory (not shown) shared among the arrays 410 of CPUs and accessible to the arrays 410 of CPUs.

The network interface device 400 includes a network medium access control (MAC) layer 430 for interfacing the network interface device 400 with a network. MAC layer 430 is configured to receive data packets from the network and transmit data packets over the network.

Operations on packets received at the network interface device 400 are parallelized through the CPU. As shown, when a data flow is received at the MAC layer 430 , it is passed to a spreading function 440 , which extracts data packets from the flow and puts them into the NPU 410 . Distributed across a plurality of CPUs, the CPUs are configured to perform processing, eg, filtering, of these data packets. The spreading function 440 may parse the received data packet to identify a data flow to which the received data packet belongs. Spreading function 440 generates, for each packet, an indication of the position of each packet in the data flow to which it belongs. The indication may be, for example, a tag. The spreading function 440 adds each indication to the associated metadata of each packet. Associated metadata for each data packet may be appended to the data packet. The associated metadata may be passed to the spreading function 440 as side-band control information. Indications are added depending on the flow to which the data packet belongs, and as a result, the order of the data packet for any particular flow may be reconstructed.

After programming by the plurality of CPUs 410 , the data packets are then reordered by a reordering function 450 that rearranges the packets of the data flow into their correct order before passing the packets of the data flow to the host interface layer 460 . ) is transferred to The reordering function 450 may reorder data packets within a flow by comparing the indications (eg, tags) within the data packets of the flows to reconstruct the order of the data packets. The reordered data packet is then passed through the host interface 460 to the host system 220 .

Although Figure 4 illustrates an array 410 of a CPU that operates only on data packets received from the network, similar principles (including spreading and reordering) may be performed for data packets received from a host for transmission over the network. Alternatively, the CPU's array 410 performs a function (eg, load balancing) on these data packets received from the host.

The program executed by the CPU may be a compiled or transcoded version of the program to be executed on the host CPU in the example described above with respect to FIG. 3 . In other words, the set of instructions to be executed on the host CPU to perform the operation is translated for execution on each CPU of the array of special CPUs in the network interface 400 .

To achieve parallelism across CPUs, multiple instances of a program are compiled and executed in parallel on multiple CPUs. Each instance of the program may be responsible for processing a different set of data packets received at the network interface device. However, each individual data packet is processed by a single CPU when providing the functions of the program in relation to that data packet. The overall effect of parallel program execution may be the same as the execution of a single program (eg, program 330 ) on the host CPU.

One of the special CPUs can even process data packets as high as 50 million packets per second. This operating speed may be lower than the operating speed of the host CPU. Thus, parallelization may be used to achieve the same performance that would be achieved by running an equivalent program on the host CPU. To perform parallelization, data packets are distributed across the CPU and then reordered after processing by the CPU. The requirement to process each flow's data packets in order in conjunction with the reordering step 450 may introduce a bottleneck, increase memory resource overhead, and limit the available throughput of the device. This requirement and reordering step 450 may increase the jitter of the device as processing throughput may vary depending on the content of the network traffic and the degree to which parallelism can be applied.

One advantage of using such a special CPU may be shorter compile times. For example, it may be possible to compile a filtering application to run in less than a second on such a CPU.

When this approach scales to higher link speeds, there may be problems in the use of the CPU's array. Host network interfaces may be required to reach terabit/s speeds in the near future. When scaling such an array 410 of CPUs to these higher speeds, the amount of power required can be an issue.

Another proposal is to include, within a network interface device, a field programmable gate array (FPGA) and use an FPGA to perform operations on data packets received from the network.

5 , which illustrates an example of use in a network interface device 500 of an FPGA 510 having an FPGA application 515 for performing operations on data packets received at the network interface device 500 . Reference is made Elements that are the same as those in FIG. 4 are referenced using the same reference numerals.

Although FIG. 5 illustrates an FPGA application 515 that only operates on data packets received from a network, such FPGA application 515 can be used for transmission over a network or back to another network interface on a host or system. It may also be used to perform functions (eg, load balancing and/or firewall functions) on these data packets received from the host for this purpose.

The FPGA application 515 may be provided by compiling a program written in a common system level language such as C or C++ or Scala to run on the FPGA 510 .

The FPGA 510 may have network interface functionality and FPGA functionality. The FPGA functionality may provide an FPGA application 515 that may be programmed into the FPGA 510 according to the needs of a network interface device user. FPGA application 515 may provide, for example, filtering of messages on a receive path from network 230 to a host. The FPGA application 515 may provide a firewall.

FPGA 510 may be programmable to provide FPGA applications 515 . Some of the network interface device functionality may be implemented as “hard” logic within the FPGA 510 . For example, the hard logic may be an application specific integrated circuit (ASIC) gate. FPGA application 515 may be implemented as “soft” logic. Soft logic may be provided by programming an FPGA look up table (LUT). Hard logic may be clocked at a higher rate compared to soft logic.

Network interface device 500 includes a host interface 505 configured to transmit and receive data with a host. The network interface device 520 includes a network medium access control (MAC) interface 520 that is configured to transmit and receive data with a network.

When a data packet is received from the network at the MAC interface 520 , the data packet is passed to an FPGA application 515 that is configured to perform a function, such as filtering, with respect to the data packet. The data packet (if it passes any filtering) is then forwarded to the host interface 505, where it is forwarded from the host interface 505 to the host. Alternatively, the data packet FPGA application 515 may decide to drop or retransmit the data packet.

One problem with this approach of using FPGAs to perform functions with respect to data packets is that they require relatively long compile times. FPGAs are made up of many logic elements (eg, logic cells) that individually represent primitive logic operations such as AND, OR, NOT, and the like. These logic elements are arranged in a matrix using programmable interconnects. To provide functionality, these logic cells may need to work together to implement circuit definitions and synchronous clock timing constraints. Placing each logic cell and routing between cells may be an algorithmically difficult challenge. Compilation times may be less than 10 minutes when compiling on FPGAs with lower levels of utilization. However, as FPGA devices become more utilized by a variety of applications, the challenges of place and route may increase and, as a result, the time to compile a given function onto the FPGA increases. As such, adding additional logic to an FPGA where most of its routing resources have already been consumed can take hours of compilation time.

One approach is to design the hardware using specific processing primitives such as parsing, match, and action primitives. These may be used to construct a processing pipeline where every packet goes through each of the three processes. First, the packet is parsed to construct a metadata representation of the protocol header. Second, packets are flexibly matched against rules maintained in the table. Finally, if a match is found, the packet is acted upon depending on the entry from the table selected in the match action.

The P4 programming language (or similar language) may be used to implement functions using the parsing/match/action model. The P4 programming language is target independent, meaning that programs written in P4 can be compiled to run on different types of hardware, such as CPU, FPGA, ASIC, NPU, etc. Each different type of target has its own compiler that maps the P4 source code to the appropriate target switch model.

P4 may be used to provide a programming model that allows high-level programs to express packet processing operations for the packet processing pipeline. This approach works well for movements that naturally express themselves in a declarative style. In the P4 language, the programmer expresses the parsing, matching, and action stages as operations to be performed on received data packets. These operations are brought together so that dedicated hardware performs them efficiently. However, this declarative style may not be suitable for expressing a program of an imperative nature, such as an eBPF program.

In a network interface device, a sequence of eBPF programs may be required to be executed serially. In this case, a chain of eBPF programs is created, one calling the other. Each program can modify its state, and the output is as if the entire chain of programs were running serially. It can be difficult for the compiler to collect all the parsing, matching and action steps. However, even if a chain of eBPF programs is already installed, it may be necessary to install, uninstall, or modify the chain, which may present additional challenges.

To provide an example of such a program that requires repeated execution, reference is made to FIG. 10 , which illustrates an example of a sequence of _{programs e 1} , e ₂ , e _{3 configured to process data packets.} For example, each of the programs may be an eBPF program. Each of the programs is configured to perform a lookup on the table 1010 to determine an action on a matching entry in the table 1010 to parse the received data packet, and then perform an action with respect to the data packet. do. The action may include modifying the packet. Each of the eBPF programs may also perform actions depending on local and shared state. The data packet P ₀ is initially processed by the _{eBPF program e 1} before being forwarded and modified to the next program e _{2 in the pipeline.} The output of the sequence of programs is the output of the last program in the pipeline, ie e ₃ .

Combining the effects of each of n such programs into a single P4 program may be complex for the compiler. Additionally, certain programming models (eg, XDP) may require that programs be quickly and dynamically inserted and removed at any point in the sequence of programs in response to changing circumstances.

According to some embodiments of the application, a network interface device comprising a plurality of processing units is provided. Each processing unit is configured to perform at least one predefined operation in hardware. Each processing unit includes a memory that stores its own local state. Each processing unit includes digital circuitry that modifies this state. The digital circuit may be an application specific integrated circuit. Each processing unit is configured to execute a program comprising configurable parameters to perform a respective plurality of operations. Each processing unit may be a smallest atom. The smallest unit is defined by specific programming and routing of predefined templates. It defines its specific operational behavior and logical place in a flow provided by a plurality of connected processing units. When the term 'minimum unit' is used herein, it may be understood to refer to a data processing unit configured to execute its operation in a single step. In other words, the minimum unit executes its operation as the minimum unit operation.

A minimal unit may be thought of as a collection of hardware structures that can be configured to iteratively perform one of various kinds of calculations, taking one or more inputs and producing one or more outputs.

The smallest unit is provided by the hardware. The minimum unit may be configured by the compiler. The smallest unit may be configured to perform calculations.

During compilation, at least some of the plurality of processing units are arranged to perform an operation such that a function is performed in relation to a data packet received at the network interface device by the at least some of the plurality of processing units. Each of at least some of the plurality of processing units is configured to perform its respective at least one predefined operation to perform a function with respect to the data packet. In other words, the operations the connected processing unit is configured to perform are performed in relation to the received data packets. The operations are sequentially performed by at least some of the plurality of processing units. Collectively, each performance of the plurality of operations provides functionality, eg, filtering, with respect to received packets.

By arranging each of the smallest units to execute at least one predefined operation of each of them to perform a function, the compile time may be reduced compared to the FPGA application example described above with respect to FIG. 5 . . Moreover, the network interface to perform the function for each data packet as discussed above with respect to FIG. 4 by performing the function using a processing unit specifically dedicated to performing a particular operation in hardware. With respect to using a CPU to run software in a device, the speed at which functions can be performed may be improved.

Reference is made to FIG. 6 , which illustrates an example of a network interface device 600 according to an embodiment of the present application. The network interface device includes a hardware module 610 configured to perform processing of data packets received at an interface of the network interface device 600 . Although FIG. 6 illustrates a hardware module 610 that performs functions (eg, filtering) on data packets on a receive path, the hardware module 610 performs functions on data packets on a transmit path that are received from a host ( It may also be used to perform load balancing or firewalls, for example.

The network interface device 600 includes a host interface 620 for transmitting and receiving data packets with a host and a network MAC interface 630 for transmitting and receiving data packets with the network.

The network interface device 600 includes a hardware module 610 including a plurality of processing units 640a, 640b, 640c, 640d. Each of the processing units may be a minimum unit processing unit. The term smallest unit is used in the description to refer to a processing unit. Each of the processing units is configured to perform at least one operation in hardware. Each of the processing units includes digital circuitry 645 configured to perform at least one operation. The digital circuit 645 may be an application specific integrated circuit. Each of the processing units further includes a memory 650 for storing state information. The digital circuit 645 updates state information as it executes each of the plurality of operations. In addition to local memory, each of the processing units may access a shared memory 660 that may also store state information accessible to each of the plurality of processing units.

State information in shared memory 660 and/or state information in memory 650 of a processing unit may include at least one of the following: metadata, temporary variables, and content of data packets passed between processing units. , the content of one or more shared maps.

In summary, the plurality of processing units may provide functions to be performed in connection with data packets received at the network interface device 600 . The compiler is configured to: a hardware module to perform a function in relation to an incoming data packet by arranging at least some of the plurality of processing units to perform at least one predefined operation in each of them with respect to each incoming data packet Outputs a command for configuring 610 . This involves chaining (ie, concatenating) at least some of the processing units 640a , 640b , 640c , 640d together such that each of the connected processing units performs at least one of their respective operations with respect to each incoming data packet. It may be achieved by doing Each of the processing units performs their respective at least one operation in a particular order to perform a function. The order may be such that two or more of the processing units are executed in parallel with each other, ie concurrently. For example, one processing unit may be configured for a period of time (defined by a periodic signal (eg, a clock signal) of the hardware module 610 ) during which a second processing unit also reads from a different location within the same data packet. It can also read from data packets.

In some embodiments, the data packet passes through each stage represented by a processing unit in the sequence. In this case, each processing unit completes its processing before forwarding the data packet to the next processing unit to perform the processing of the next processing unit.

In the example shown in FIG. 6 , processing units 640a , 640b , and 640d are coupled together at compile time, so that each of them performs a function, eg, filtering, in relation to the received data packet. each of them performs at least one action for The processing units 640a, 640b, 640d form a pipeline for processing data packets. Data packets may travel along this pipeline in stages each having the same period of time. The time period may be defined according to a period signal or bit. The time period may be defined by a clock signal. The various periods of the clock may define one time period for each stage of the pipeline. The data packet travels along one stage in the pipeline at the end of each occurrence of a repeating time period. The time period may be a fixed interval. Alternatively, each time period for a stage in the pipeline may require a variable amount of time. When the previous processing stage has completed its operation, a signal may be generated indicative of the next stage in the pipeline, which may require a variable amount of time. A stall may be introduced at any stage in the pipeline by delaying the signal for some predetermined amount of time.

Each of the processing units 640a , 640b , 640d may be configured to access the shared memory 660 as part of at least one operation of their respective one. Each of the processing units 640a , 640b , 640d may be configured to pass metadata between each other as part of their respective at least one operation. Each of the processing units 640a , 640b , 640d may be configured to access a data packet received from the network as part of at least one operation of their respective one.

In this example, processing unit 640c is omitted from the pipeline, although it is not used to perform processing of received data packets to provide functionality.

Data packets received at the network MAC layer 630 may be forwarded to the hardware module 610 for processing. Although not shown in FIG. 6 , the processing performed by the hardware module 610 may be part of a larger processing pipeline that provides additional functionality with respect to data packets in addition to the functionality provided by the hardware module 610 . . This is illustrated with respect to FIG. 14 and will be described in more detail below.

The first processing unit 640a is configured to perform at least one first operation with respect to the data packet. This first at least one operation may include at least one of: reading from a data packet, reading and writing to a shared state in memory 660 , and/or a table for determining an action. Perform a lookup on . The first processing unit 640a is then configured to generate a result from its at least one operation. The result may be in the form of metadata. The results may include modifications to the data packet. The results may include modifications to the shared state of memory 660 . The second processing unit 640b is configured to perform its at least one operation with respect to the first data packet depending on a result from the operation performed by the first processing unit 640a. The second processing unit 640b generates a result from its at least one operation and sends the result to a third processing unit 640d configured to perform its at least one operation with respect to the first data packet. transmit The first processing unit 640a , the second processing unit 640b and the third processing unit 640d are, together, configured to provide a function in connection with a data packet. The data packet may then be forwarded to a host interface 620 from where it is forwarded to the host system.

Accordingly, it may be seen that the connected processing unit forms a pipeline for processing data packets received at the network interface device. This pipeline may provide processing of the eBPF program. The pipeline may provide for processing of a plurality of eBPF programs. A pipeline may provide processing of a plurality of modules that are executed in sequence.

Connecting the processing units together in the hardware module 610 may be performed by programming the routing function of a pre-assembled interconnection fabric of the hardware module 610 . This interconnect fabric provides connections between the various processing units of the hardware module 610 . The interconnect fabric is programmed according to the topology supported by the fabric. A possible exemplary topology is discussed below with reference to FIG. 15 .

The hardware module 610 supports at least one bus interface. At least one bus interface receives data packets from the hardware module 610 (eg, from a host or network). At least one bus interface outputs data packets from the hardware module 610 (eg, to a host or network). At least one bus interface receives a control message from the hardware module 610 . The control message may be for configuring the hardware module 610 .

The example shown in FIG. 6 has the benefit of reduced compile time with respect to the FPGA application 515 shown in FIG. 5 . For example, the hardware module 610 of FIG. 6 may require less than 10 seconds to compile the filtering function. The example shown in FIG. 6 has the advantage of improved processing speed with respect to the example of the array of CPUs shown in FIG. 4 .

An application may be compiled for execution in such a hardware module 610 by mapping a generic program (or multiple programs) to a pre-synthesized data path. The compiler builds a data path by concatenating an arbitrary number of processing stage instances, each instance being built from one of the pre-synthesized processing stage minimal units.

Each of the smallest units is built from a circuit. Each circuit may be defined using a register transfer language (RTL) or high-level language. Each circuit is synthesized using a compiler or tool chain. The smallest unit may be synthesized in hard logic and thus may be available as a hard (ASIC) resource in a hardware module of the network interface device. The minimum unit may be synthesized by soft logic. The smallest unit of soft logic may have the constraint of allocating and maintaining route information and placement of the synthesized logic on the physical device. The minimum unit may be designed using configurable parameters that specify the behavior of the minimum unit. Each parameter may be a variable, or even a sequence of operations (microprogram), that may specify at least one operation to be performed by the processing unit during a clock cycle of the processing pipeline. The logic implementing the smallest unit may be clocked synchronously or asynchronously.

The processing pipeline of the smallest unit itself may be configured to operate according to a periodic signal. In this case, each of the metadata and data packets moves one stage along the pipeline in response to each occurrence of the signal. The processing pipeline may be operated in an asynchronous manner. In this case, backpressure at higher levels of the pipeline will cause each downstream stage to start processing only when data from the upstream stage has been provided to it.

When compiling functions to be executed by a plurality of such minimal units, the sequence of computer code instructions is divided into a plurality of operations, each mapped to a single minimal unit. Each operation may represent a single line of decomposed instructions in computer code instructions. Each operation is assigned to one of the smallest units to be executed by one of the smallest units. There may be one minimum unit per representation in computer code instructions. Each smallest unit is associated with a type of operation and is selected to execute at least one operation in computer code instructions based on its associated type of operation. For example, a minimum unit may be preconfigured to perform a load operation from a data packet. Accordingly, such smallest unit is designated to execute instructions representing a load operation from a data packet of computer code.

One minimum unit per line in computer code instructions may be selected. Accordingly, when implementing a function in a hardware module including such a minimum unit, there may be 100 such minimum unit, each performing their respective operation to perform a function with respect to the data packet.

Each minimal unit may be constructed according to one of a set of processing stage templates that determine its associated type of operation. The compilation process is configured to generate instructions for controlling each minimal unit, based on its associated type, to perform at least one particular operation. For example, if the smallest unit is preconfigured to perform a packet access operation, the compilation process performs an operation for loading, in that smallest unit, predetermined information (eg, the source ID of the packet) from the header of the packet. can also be assigned. The compilation process is configured to send instructions to the hardware modules, where the smallest unit is configured to perform operations assigned to them by the compilation process.

A processing stage template that specifies the minimum level of behavior is a logic stage template (eg, providing operations across registers, scratch pad memory, and stack as well as branches), packet access state templates (eg, to provide packet data loads and/or packet data storage), and map access stage templates (eg, map lookup algorithms, map table sizes).

The packet access stage may include at least one of: reading a sequence of bytes from the data packet; replacing one sequence of bytes in a data packet with a different sequence of bytes; inserting bytes into data packets; and deleting bytes from the data packet.

The map access stage can be used to access different types of maps (eg, lookup tables), including direct indexed arrays and associative arrays. The map access stage may include at least one of: reading a value from a location; writing a value to a location; Replacing a value at one location in the map with a different value. The map access stage may include a compare operation in which a value is read from a location in the map and compared to a different value. If the value read from the location is less than the different value, then a first action (eg, do nothing, exchange the value at that location for a different value, or add the values together) may be performed. Otherwise, a second action (eg, do nothing, exchange a value, or add a value) may be performed. In either case, the value read from the location may be provided to the next processing stage.

Each map access stage may be implemented in a stateful processing unit. Reference is made to FIG. 17 , which illustrates an example of circuitry 1700 that may be included in the smallest unit configured to perform processing of the map access stage. Circuitry 1700 may include a hash function 1710 configured to perform a hash of an input value used as an input to a lookup table. The circuit unit 1700 includes a memory 1720 configured to store states related to a minimum unit of operation. The circuitry 1700 includes an arithmetic logic unit 1730 configured to perform operations.

A logic stage may perform calculations on values provided by previous stages. The processing unit configured to implement the logic stage may be a stateless processing unit. Each stateless processing unit can perform simple arithmetic operations. Each processing unit may perform an 8-bit operation, for example.

Each logic stage may be implemented in a stateless processing unit. Reference is made to FIG. 18 , which illustrates an example of circuitry 1800 that may be included in the smallest unit configured to perform processing of a logic stage. Circuitry 1800 includes an arithmetic logic unit (ALU) and an array of multiplexers. ALUs and multiplexers are arranged in layers, where the output of one layer of processing by the ALU is used by the multiplexer to provide an input to the next layer of the ALU.

The pipeline of stages implemented in the hardware module includes a first packet access stage (pkt0), a first logical stage following (logic0), a first map access stage following (map0), and a subsequent second logic stage (logic1). , followed by a second packet access stage pkt1 , and the like. Thus, it may take the form:

Pkt0 -> logic0 -> map0 -> logic1 -> pkt1

In some examples, stage pkt0 extracts the necessary information from the packet. The stage pkt0 passes this information to the stage logic0. A stage (logic0) determines whether the packet is a valid IP packet. In some cases, logic0 forms a map request and sends the map request to map0, which executes the map operation. The stage map0 may perform an update to the lookup table. The stage logic1 then collects the result from the map operation and decides whether to drop the packet as a result.

In some cases, MAP requests are disabled to cover cases where MAP operations should not be performed on this packet. If the map operation is not performed, logic0 indicates to logic1 whether the packet should be dropped or not, depending on whether the packet is a valid IP packet or not. In some examples, the lookup table includes 256 entries, where each entry is an 8-bit value.

This example described includes only five stages. However, as noted, more may be used. Moreover, not all operations need to all be executed sequentially, however, some operations involving the same data packet may be executed concurrently by different processing units.

The hardware module 610 shown in FIG. 6 exemplifies a single pipeline of a minimum unit for performing a function in relation to a data packet. However, the hardware module 610 may include multiple pipelines for processing data packets. Each of the plurality of pipelines may perform a different function with respect to the data packet. The hardware module 610 is configurable to interconnect a first set of minimal units of the hardware module 610 to form a first data processing pipeline. The hardware module 610 is also configurable to interconnect a second set of minimum units of the hardware module 610 to form a second data processing pipeline.

A series of steps starting from a sequence of computer code may be executed to compile a function to be implemented in a hardware module comprising a plurality of processing units. A compiler, which may be executing on a processor on a host device or on a network interface device, has access to the decomposed sequence of computer code.

First, the compiler is configured to split a sequence of computer code instructions into distinct stages. Each stage may include an operation according to one of the processing stage templates described above. For example, one stage may provide a read from a data packet. One stage may provide an update of map data. Other stages may make pass drop decisions. The compiler assigns each of the plurality of operations represented by the code to one of the plurality of stages.

Second, the compiler is configured to allocate each of the processing stages determined from code to be executed by a different processing unit. This means that each of each at least one operation of the processing stage is executed by a different processing stage. The output of the compiler can then be used to cause the processing unit to perform the operations of each stage in a particular order to perform the function.

The output of the compiler includes generated instructions that are used to cause the processing units of the hardware modules to execute operations associated with each processing stage.

The output of the compiler may also be used to generate logic in the hardware module that responds to control messages for configuring the hardware module 610 . Such control messages are described in more detail below with respect to FIG. 14 .

A compilation process for compiling a function to be executed on the network interface device 600 may be performed in response to determining that the process for providing the function is safe for execution in the kernel of the host device. The determination of the safety of the program may be performed by an appropriate verifier as described above with respect to FIG. 3 . Once a process is determined to be safe for execution in the kernel, the process may be compiled for execution on a network interface device.

Reference is made to FIG. 15 , which illustrates a representation of at least some of a plurality of processing units, each of which performs at least one operation to perform a function with respect to the data packet. Such representations may be generated by a compiler and used to configure hardware modules to perform functions. Representations indicate the order in which the operations may be executed and how some of the processing units perform their operations in parallel.

Representation 1500 is in the form of a table with rows and columns. Some of the entries in the table indicate a minimum unit configured to perform their respective operations, for example, a minimum unit 1510a. The row to which a processing unit belongs indicates the timing of operations performed by that processing unit with respect to a particular data packet. Each row may correspond to a single period of time represented by one or more cycles of the clock signal. Processing units belonging to the same row perform their operations in parallel.

The input to the logic stage is provided in row 0, and the computation flows forward towards the later row. By default, the smallest unit receives results from processing by the smallest unit in the same column as itself but in the previous row. For example, the minimum unit 1510b receives results from processing by the minimum unit 1510a and relies on these results to perform its own processing.

When using local routing resources, the smallest unit may also access the output from the smallest unit in the previous row where the column numbers differ by no more than two. For example, the smallest unit 1510d may receive a result from the processing performed by the smallest unit 1510c.

When using global routing resources, the smallest unit may also access the output from the smallest unit in the previous two rows and in any column. This may be done using global routing resources. For example, the smallest unit 1510f may receive a result from the processing performed by the smallest unit 1510e.

These constraints regarding routing between minimum units are given as examples and other constraints may apply. Applying more restrictive constraints may make routing of information between the smallest units easier. Applying less restrictive constraints may make scheduling easier. If the number of minimum units of a given type (eg, map, logic or packet access) is exhausted or routing between the minimum units cannot be made, then compilation of the function into a hardware module will fail.

Specific constraints are determined by the topology supported by the interconnect fabric supported by the hardware module. The interconnect fabric is programmed to cause the smallest units of hardware modules to perform their operations in a particular order and to provide data between each other within constraints. 15 shows one specific example of how an interconnect fabric may be programmed as such.

A placement and route algorithm is used during synthesis of the FPGA application 515 onto the FPGA (as illustrated in FIG. 5 ). However, in this case, the solution space is limited, and thus the algorithm has a short bounded execution time.

There is a trade-off between processing speed or efficiency and compile time. According to an embodiment of the present application, a program is initialized on at least one processing unit (which may be a minimal unit or a CPU as described above with respect to FIG. 6 ) for providing a function in relation to a received data packet. It may be desirable to compile and run the . The at least one processing unit may then execute and perform a function with respect to the data packet received during the first time period. a second at least one processing unit (which may be a processing unit of the FPGA application or template type as described above with respect to FIG. 6 ) for performing a function in connection with the data packet during operation of the network interface device This may be configured. The function is then configured to: then perform the function, from the first at least one processing unit, to the second at least one It can be migrated to a processing unit. Thus, the slower compile time of the second at least one processing unit does not prevent the network interface device from performing a function with respect to the data packet before the function is compiled for the second at least one processing unit. The reason is that the first at least one processing unit may be compiled faster, and the function may be used to perform a function in connection with a data packet while the function is compiled for the second at least one processing unit. Because. Since the second at least one processing unit typically has faster processing times, moving to the second at least one processing unit when compiled allows for faster processing of data packets received at the network interface device.

According to an embodiment of the present application, the compilation process may be configured to run on at least one processor of the data processing system, the at least one processor to perform at least one function with respect to the data packet at an appropriate time; and transmit instructions to the first at least one processing unit and the second at least one processing unit. The at least one processor may include a host CPU. The at least one processor may include a control processor on the network interface device. The at least one processor may include a combination of one or more processors on the host system and one or more processors on the network interface device.

Accordingly, the at least one processor is configured to perform a first compilation process to compile a function to be performed by the first at least one processing unit of the network interface device. The at least one processing unit is further configured to perform a second compilation process to compile a function to be performed by a second at least one processing unit of the network interface device. Prior to completion of the second compilation process, the at least one processing unit instructs the first at least one processing unit to perform a function with respect to a data packet received from the network. Subsequently, following completion of the second compilation process, the at least one processing unit instructs the second at least one processing unit to start performing a function relating to a data packet received from the network.

Performing these steps means that, while waiting for the second compilation process to complete, the network interface device causes the first at least one processing unit (which may have a shorter compile time but may have slower and/or less efficient processing). may have) to make it possible to perform a function. When the second compilation process is complete, the network interface device then, in addition to or instead of the first at least one processing unit, a second at least one processing unit (which may have a longer compile time but more may have faster and/or more efficient processing).

Reference is made to FIG. 7 , which illustrates an exemplary network interface device 700 in accordance with an embodiment of the present application. Reference elements that are the same as those shown in the previous figures are denoted by the same reference numbers.

The network interface device comprises a first at least one processing unit 710 . The first at least one processing unit 710 may include a hardware module 610 shown in FIG. 6 including a plurality of processing units. The first at least one processing unit 710 may include one or more CPUs, as shown in FIG. 4 .

the function is compiled to be executed on the first at least one processing unit 710 such that, during the first time period, the function is performed by the first at least one processing unit 710 in connection with a data packet received from the network do. The first at least one processing unit 710 is configured to, prior to completion of a second compilation process for the second at least one processing unit, to the at least one processor to perform a function with respect to a data packet received from the network. directed by

The network interface device includes a second at least one processing unit 720 . The second at least one processing unit 720 may comprise an FPGA with an FPGA application (as illustrated in FIG. 5 ) or a hardware module 610 shown in FIG. 6 comprising a plurality of processing units. may include

During the first time period, a second compilation process is executed to compile the function for execution on a second at least one processing unit. That is, the network interface device is configured to compile the FPGA application 515 on-the-fly.

Subsequent to the first time period (ie, following completion of the second compilation process), the second at least one processing unit 720 is configured to begin performing a function relating to a data packet received from the network.

Subsequent to the first time period, the first at least one processing unit 710 may stop performing a function relating to a data packet received from the network. In some embodiments, the first at least one processing unit 710 may stop, in part, from performing a function related to the data packet. For example, if the first at least one processing unit includes a plurality of CPUs, subsequent to the first time period, one or more of the CPUs may stop performing processing with respect to a data packet received from the network. However, the remaining CPUs among the plurality of CPUs continue to perform processing.

The first at least one processing unit 710 may be configured to perform a function in relation to a data packet of a first data flow. When the second compilation process is completed, the second at least one processing unit 720 may start performing a function related to the data packet of the first data flow. When the second compilation process is completed, the first at least one processing unit may stop performing a function related to the data packet of the first data flow.

Different combinations are also possible for the first at least one processing unit and for the second at least one processing unit. For example, in some embodiments, the first at least one processing unit 710 includes a plurality of CPUs (as illustrated in FIG. 4 ), while the second at least one processing unit 720 comprises: A hardware module comprising a plurality of processing units (as illustrated in FIG. 6 ). In some embodiments, the first at least one processing unit 710 includes a plurality of CPUs (as illustrated in FIG. 4 ), while the second at least one processing unit 720 (as illustrated in FIG. 5 ) as exemplified in) an FPGA. In some embodiments, the first at least one processing unit 710 comprises a hardware module comprising a plurality of processing units (as illustrated in FIG. 6 ), while the second at least one processing unit ( 720 (as illustrated in FIG. 5) includes an FPGA.

Reference is made to FIG. 11 , which illustrates how a coupled plurality of processing units 640a , 640b , 640d may perform their respective at least one operation with respect to a data packet. Each of the processing units is configured to perform its respective at least one operation with respect to the received data packet.

At least one operation of each processing unit may represent a logic stage in a function (eg, a function of an eBPF program). At least one operation of each processing unit may be expressible by instructions executed by the processing unit. The instruction may determine the behavior of the smallest unit.

11 illustrates how a packet P ₀ proceeds along a processing stage implemented by each processing unit.

Each processing unit performs processing with respect to the packets in a specific order specified by the compiler. The order may be such that some of the processing units are configured to perform their processing in parallel. This processing may include accessing at least a portion of the packet maintained in memory. Additionally or alternatively, this processing may include performing a lookup against a lookup table to determine an action to be performed on the packet. Additionally or alternatively, this processing may include modifying state 1110 .

The processing units _{exchange metadata M 0} , M ₁ M ₂ , M ₃ with each other. The first processing unit 640a is configured to perform its respective at least one predefined operation and to generate _{metadata M 1 in response.} The first processing unit 640a _{is configured to pass the metadata M 1} to the second processing unit 640b.

At least some of the processing units perform their respective at least one operation depending on at least one of the following: the content of the data packet, its own stored state, a global shared state, and metadata associated with the data packet. (eg, M ₀ , M ₁ , M ₂ , M ₃ ). Some of the processing units may be stateless.

Each of the processing units may perform its associated type of operation on the _{data packet P 0} for at least one clock cycle. In some embodiments, each of the processing units may perform its associated type of operation during a single clock cycle. Each of the processing units may be individually clocked to perform their operations. This clocking may be in addition to the clocking of the processing pipeline of the processing unit.

Looking more closely at the operation of the second processing unit 640b , the second processing unit 640b is configured to perform a first at least one predefined operation with respect to the first data packet. ) to be connected to. The second processing unit 640b is configured to receive, from the first additional processing unit, a result of the first at least one predefined operation. The second processing unit 640b is configured to perform the second at least one predefined operation depending on a result of the first at least one predefined operation. The second processing unit 640b is configured to be coupled to a third processing unit 640d, which is configured to perform a third at least one predefined operation with respect to the first data packet. The second processing unit 640b is configured to send a result of the second at least one predefined operation to the third processing unit 640d for processing in the third at least one predefined operation.

The processing unit may similarly operate to provide functionality in connection with each of the plurality of data packets.

An embodiment of the present application is such that multiple packets may be pipelined concurrently if the function permits.

Reference is made to FIG. 12 , which illustrates the pipelining of data packets. As shown, different packets may be processed concurrently by different processing units. The first processing unit 640a is executing its respective at least one operation at a first time t _{0 with respect to the third data packet P 2 .} The second processing unit 640b is executing its respective at least one operation at the first time t _{0 with respect to the second data packet P 1 .} The third processing unit 640d is executing its respective at least one operation at a first time t _{0 with respect to the first data packet P 0 .}

After each at least one operation is executed by each of the processing units, each of the packets moves along one stage in the sequence. For example, at a subsequent second time t ₁ , the first processing unit 640a performs its respective at least one operation at the first time t _{0 with respect to the fourth data packet P 3 .} is running The second processing unit 640b is executing its respective at least one operation at the first time t _{0 with respect to the third data packet P 2 .} The third processing unit 640d is executing its respective at least one operation at a first time t _{0 with respect to the first data packet P 1 .}

It should be appreciated that in some embodiments, there may be multiple packets to be present in a given stage.

In some embodiments, a packet may move from one stage to the next, but is not necessarily in a lock phase.

As long as there is no pipeline risk, such a pipeline running at a fixed clock may have a constant bandwidth. This may reduce jitter in the system.

To avoid risks (eg, conflicts when accessing shared state) when executing instructions, each of the processing units executes a no-action (no-action) (i.e., the processing unit stalls) instruction when needed. It can also be configured to run.

In some embodiments, operations (eg, simple arithmetic, increment, addition/subtraction of constant values, shifts, addition/subtraction of values from data packets or from metadata) require one clock cycle to be executed by the processing unit. do it with This may mean that the value in the shared state needed by one processing unit has not yet been updated by another processing unit. Thus, out of date values in shared state 1110 may be read by the processing unit that needs them. Therefore, a risk may arise when reading and writing values to a shared state. On the other hand, operations on intermediate values may be passed as metadata without incurring risk.

An example of a risk in reading and writing to a shared state 1110 that may be avoided may be given in the context of an incremental operation. Such an increment operation may be an operation to increment a packet counter in the shared state 1110 . In one implementation of the increment operation, during the first time slot of the pipeline, the second processing unit 640b reads the value of the counter from the shared state 1110, and outputs the output of this read operation (e.g. for example, as metadata M ₂ ) to the third processing unit 640d . The third processing unit 640d is configured to receive the value of the counter from the second processing unit 640b. During the second time slot, the third processing unit 640d increments this value and writes the newly incremented value to the shared state 1110 .

A problem may arise when performing such an increment operation, which occurs when, during a second time slot, the second processing unit 640b attempts to access a counter stored in the shared state 1110 , the second The processing unit 640b may read the previous value of the counter before the counter value in the shared state 1110 is updated by the third processing unit 640d.

Thus, to address this problem, the second processing unit 640b may be stalled for a second time slot (via execution by the second processing unit 640b of a no action instruction or pipeline bubble). A stall may be understood as a delay in the execution of the next instruction. This delay may be implemented by the execution of a "no action" instruction instead of the next instruction. The second processing unit 640b then reads the counter value from the shared state 1110 during a subsequent third time slot. During the third time slot, the counter in the shared state 1110 has been updated, thus ensuring that the second processing unit 640b reads the updated value.

In some embodiments, each minimal unit is configured to read from the state, update the state, and write the updated state, during a single pipeline time slot. In this case, stalling of the processing unit described above may not be used. However, stalling the processing unit may reduce the required memory interface cost.

In some embodiments, to avoid risk, processing units in the pipeline may wait for other processing units in the pipeline to complete their processing before performing their own operations.

As mentioned, the compiler builds a data path by linking an arbitrary number of processing stage instances, where each instance is one of a predefined number (three in the given example) of pre-synthesized processing stage templates. is built from Processing stage templates include logic stage templates (e.g., providing arithmetic operations across registers, scratch pad memory, and metadata), packet access state templates (e.g. providing packet data loads and/or packet data storage). , and a map access stage template (eg, map lookup algorithm, map table size).

Each processing stage instance may be implemented by a single one of the processing units. That is, each processing stage includes a respective at least one operation executed by a processing unit.

13 illustrates an example of how processing stages may be coupled together in pipeline 1300 to process received data packets. As shown in FIG. 13 , a first data packet is received and stored in FIFO 1305 . One or more calling arguments are received in the first logic stage 1310 . The call argument may include a program selector that identifies the function to be executed on the received data packet. The call argument may include an indication of the packet length of the received data packet. The first logic stage 1310 is configured to process the call argument and provide an output to the first packet access stage 1315 .

A first packet access stage 1315 loads data from a first packet at a network tap 1320 . The first packet access stage 1315 may also write data to the first packet depending on the output of the first logic stage 1310 . The first packet access stage 1315 may write data to the front of the first data packet. The first packet access stage 1315 may overwrite the data in the data packet.

The loaded data and any other metadata and/or arguments are then provided to a second logic stage 1325, which performs processing with respect to the first data packet and outputs arguments. is provided to the first map access stage 1330 . The first map access stage 1330 uses the output from the second logic stage 1325 to perform a lookup on a lookup table to determine the action to be performed with respect to the first data packet. The output is then passed to a third logic stage 1335 , which processes the output and passes the result to a second packet access stage 1340 .

The second packet access stage 1340 may read data from and/or write data to the first data packet depending on the output of the third logic stage 1335 . The result of the second packet access stage 1340 is then passed to a fourth logic stage 1345 that is configured to perform processing with respect to the input it receives.

A pipeline may include a plurality of packet access stages, logic stages, and map access stages. The final logic stage 1350 may be configured to output a return argument. The return argument may include a pointer identifying the start of the data packet. The return argument may include an indication of an action to be performed with respect to the data packet. The indication of an action may indicate whether the packet should be dropped or not. The indication of an action may indicate whether the packet should or should not be forwarded to the host system. The network interface device may include at least one processing unit configured to drop each data packet in response to an indication that the packet should be dropped.

The pipeline 1300 may additionally include one or more bypass FIFOs 1355a, 1355b, and 1355c. The bypass FIFO may be used to convey processing data, eg, data from the first data packet around the map access stage and/or packet access stage. In some embodiments, the map access stage and/or the packet access stage do not require data from the first data packet to perform their respective at least one operation. The map access stage and/or the packet access stage may perform their respective at least one operation depending on the input argument.

Reference is made to FIG. 8 , which illustrates a method 800 performed by a network interface device 600 , 700 according to an embodiment of the present application.

In S810, a hardware module of the network interface device is disposed to perform a function. A hardware module includes a plurality of processing units each configured to perform a type of operation in hardware with respect to a data packet. S810 includes arranging at least some of the plurality of processing units to perform an operation of their respective predefined type in a particular order to provide a function with respect to each received data packet. Such arranging the hardware module includes coupling at least some of the plurality of processing units such that the received data packet is subjected to processing by each of a plurality of operations of at least some of the plurality of processing units. The connection may be achieved by configuring the routing hardware of the hardware module to route data packets and associated metadata between processing units.

In S820 , a first data packet is received from the network at a first interface of the network interface device.

In S830 , the first data packet is processed by each of at least some processing units that were connected during the compilation process of S810 . Each of the at least some processing units performs a type of operation that is preconfigured to perform in connection with the at least one data packet. Therefore, a function is performed in association with the first data packet.

In S840, the processed first data packet continues to be transmitted to its destination. This may include sending the data packet to the host as well. This may include sending data packets over the network.

Reference is made to FIG. 9 , which illustrates a method 900 that may be performed in a network interface device 700 according to an embodiment of the present application.

In S910 , the first at least one processing unit (ie, first circuitry) of the network interface device is configured to receive and process the data packet received via the network. This processing includes performing a function with respect to the data packet. The processing is performed during the first time period.

In S920 , a second compilation process is performed for a first time period to compile a function for execution on a second at least one processing unit (ie, a second circuit unit).

In S930, it is determined whether the second compilation process is completed or not. If not, it returns back to S910 and S920, where the first at least one processing unit continues to perform processing with respect to the data packet received from the network, and the second compilation process continues.

In S940 , in response to determining that the second compilation is complete, the first at least one processing unit stops performing a function related to the received data packet. In some embodiments, the first at least one processing unit may cease to perform a function only with respect to a given data flow. Then, the second at least one processing unit may instead perform the function (in S950 ) with respect to their given data flow.

In S950 , when the second compilation process is completed, the second at least one processing unit is configured to start performing a function related to the data packet received from the network.

Reference is made to FIG. 16 , which illustrates a method 1600 according to an embodiment of the present application. Method 1600 may be performed at a network interface device or a host device.

In S1610, a compilation process for compiling a function to be performed by the first at least one processing unit is performed.

In S1620, a compilation process is performed to compile a function to be performed by the second at least one processing unit. The process comprises assigning to each of the plurality of processing units of the second at least one processing unit to perform at least one operation associated with the stage of the plurality of stages for processing the data packet to provide a first function. include that Each of the plurality of processing units is configured to perform one type of processing, and the assigning is performed in dependence on a determination that the processing unit is configured to perform the appropriate type of processing to perform each at least one operation. In other words, the processing units are selected according to their template.

In 1630 , before completion of the compilation process of S1620, an instruction for causing the first at least one processing unit to perform a function is transmitted. This command may be transmitted before the compilation process of S1620 starts.

In S1640, following the completion of the compilation process in S1620, an instruction for causing the second circuitry to perform a function with respect to the data packet is sent to the second circuitry. This instruction may include compiled instructions generated in S1620.

Functionality according to embodiments of the present application may be provided as a pluggable component of a processing slice in a network interface. Reference is made to FIG. 14 , which illustrates an example of how slice 1425 may be used in network interface device 600 . Slice 1425 may be referred to as a processing pipeline.

The network interface device 600 includes a transmit queue 1405 for receiving and storing data packets from a host to be processed by the slice 1425 and then to be transmitted over the network. The network interface device 600 includes a receive queue 1410 for storing data packets received from the network 1410 to be processed by the slice 1425 and then forwarded to the host. Network interface device 600 includes receive queue 1415 for storing data packets processed by slice 1425 and received from the network for delivery to a host. Network interface device 600 includes a transmit queue for storing data packets processed by slice 1425 and received from a host that are for delivery to a network.

Slice 1425 of network interface device 600 includes a plurality of processing functions for processing data packets on a receive path and a transmit path. Slice 1425 may include a protocol stack configured to perform protocol processing of data packets on a receive path and a transmit path. In some embodiments, the network interface device 600 may have multiple slices. At least one of the plurality of slices may be configured to process a received data packet received from the network. At least one of the plurality of slices may be configured to process a transmit data packet for transmission over a network. A slice may be implemented by a hardware processing device such as at least one FPGA and/or at least one ASIC.

Accelerator components 1430a, 1430b, 1430c, and 1430d may be inserted at different stages of the slice as shown. Each accelerator component provides a function with respect to a data packet passing through a slice. The accelerator component may be inserted or removed on the fly, ie during operation of the network interface device. Accordingly, the accelerator component is a pluggable component. The accelerator component is a logical region allocated for slice 1425 . Each of them supports a streaming packet interface that allows packets passing through the slice to be streamed into and out of the component.

For example, one type of accelerator component may be configured to provide encryption of data packets on a receive or transmit path. Another type of accelerator component may be configured to provide decoding of data packets on a receive or transmit path.

The functionality discussed above provided by executing an operation performed by a plurality of coupled processing units (as discussed above with reference to FIG. 6 ) may be provided by an accelerator component. Similarly, the functionality provided by the array of network processing CPUs (as discussed above with reference to FIG. 4) and/or the FPGA application (as discussed above with reference to FIG. 5) is provided by the accelerator component. could be

As described, during operation of the network interface device, processing performed by the first at least one processing unit (eg, a plurality of coupled processing units) may be migrated from the second at least one processing unit. To implement this migration, one of the components of the slice 1425 for processing by the first at least one processing unit may be replaced by a component for processing by the second at least one processing unit.

The network interface device may include a control processor configured to insert and remove components from the slice 1425 . During the first time period discussed above, a component for performing a function by a first at least one processing unit may be present in the slice 1425 . The control processor is configured to: subsequent to the first period of time: remove from the slice 1425 a pluggable component providing functionality by the first at least one processing unit and disable the functionality by the second at least one processing unit. It may be configured to insert the provided pluggable component into the slice 1425 .

In addition to or instead of inserting and removing components from a slice, the control processor may load programs into the components and issue control-plane commands to control the flow of frames into the components. In this case, the component may or may not become operational without being inserted or removed from the pipeline.

In some embodiments, control plane or configuration information is carried over a data path, rather than requiring a separate control bus. In some embodiments, the request to update the configuration of the data path component is encoded as a message carried over the same bus as the network packet. Thus, a data path may carry two types of packets: network packets and control packets.

Control packets are formed by the control processor and injected into slice 1425 using the same mechanism used to transmit or receive data packets using slice 1425 . This same mechanism may be a transmit queue or a receive queue. Control packets may be distinguished from network packets in any suitable manner. In some embodiments, different types of packets may be distinguished by a bit or bits within a metadata word.

In some embodiments, the control packet includes a routing field in the metadata word that determines the path through the slice 1425 that the control packet takes. A control packet may carry a sequence of control commands. Each control command may target one or more components of slice 1425 . Each data path component is identified by a component ID field. Each control command encodes a request for each identified component. The request may be to make a change to the configuration of that component. The request may control whether the component is active or not, that is, whether the component performs its function with respect to data packets passing through the slice or not.

Accordingly, in some embodiments, the control processor of the network interface device 600 is configured to send a message to cause one of the components of the slice to begin performing a function relating to a data packet received at the network interface device. This message is a control plane message that is sent through a pluggable component and causes an atomic switch over of a frame to the component to perform a function. This component is then executed on every received data packet passing through the slice, until the slice is switched out. The control processor is configured to send a message to cause another of the components of the slice to stop performing a function relating to the data packet received at the network interface device 600 .

Sockets may exist at various points in the ingress and egress data paths to switch components in and out of data slice 1425 . The control processor may couple additional logic into and out of slice 1425 . This additional logic may take the form of a FIFO placed between components.

The control processor may send a control plane message via slice 1425 to configured components of slice 1425 . The configuration may determine the functions performed by the components of the slice 1425 . For example, a control message transmitted over slice 1425 may cause a hardware module to be configured to perform a function with respect to a data packet. Such control messages may cause a minimum unit of hardware modules to be interconnected into a pipeline of hardware modules to provide certain functions. Such a control message may cause an individual smallest unit of the hardware module to be configured to select an operation to be performed by the individually selected smallest unit. Since each minimum unit is preconfigured to perform one type of operation, the selection of an operation for each minimum unit is made dependent on the type of operation that each minimum unit is preconfigured to perform.

Some additional embodiments will now be described with reference to FIGS. 19-21 . In this embodiment, the packet processing program or feedforward pipeline is executed in the FPGA. A method for causing a subunit of an FPGA to implement a packet processing program or a feedforward pipeline will be described. The packet processing program or feedforward pipeline may be an eBPF program or a P4 program or any other suitable program.

This FPGA may be provided in a network interface device. In some embodiments, the packet processing program is deployed or executed only after the network interface device is installed in association with its host.

A packet processing program or feedforward pipeline may implement a loop-free logic flow.

In some embodiments, a program may be written in a less privileged domain or a non-privileged domain, such as at the user level. A program may run on a privileged or higher privileged domain, such as the kernel. The hardware executing the program may require that there are no loops.

In the following embodiments, reference is made to eBPF program examples. It should be appreciated, however, that other embodiments may be used with any other suitable program.

It should be appreciated that one or more of the following embodiments may be used in connection with one or more of the preceding embodiments.

Some embodiments may be provided in the context of an FPGA, ASIC, or any other suitable hardware device. Some embodiments use subunits such as FPGAs or ASICs or the like. The following examples are described with reference to FPGAs. It should be appreciated that a similar process may be performed using an ASIC or any other suitable hardware device.

A subunit may be a minimum unit. Some examples of minimum units have been described previously. It should be appreciated that any of those previously described examples of minimum units may alternatively or additionally be used as subunits. Alternatively or additionally, these subunits may be referred to as “slices” or configurable logic blocks.

Each of these subunits may be configured to perform a single instruction or a plurality of related instructions. In the latter case, the associated instruction may provide a single output (which may be defined by one or more bits).

A subunit may be considered to be a computational unit. Subunits may be arranged in a pipeline in which packets are processed in order. In some embodiments, a subunit may be dynamically assigned to execute each instruction (or instructions) in a program.

In some embodiments, a subunit may be, for example, all or part of a unit used to define a block of an FPGA. In some FPGAs, blocks of FPGAs are referred to as slices. In some embodiments, a subunit or smallest unit is considered equal to a slice.

By mapping each smallest unit or subunit to each block or slice of the FPGA, improved resource utilization may be achieved as compared to an approach of mapping an RTL smallest unit to an FPGA resource. Such a latter approach may result in RTL minimum units requiring a relatively large number of individual blocks or slices of the FPGA.

In some embodiments, the compilation may be for a minimum unit level. This may have the advantage that processing is pipelined. Packets may be processed in order. The compilation process may be performed relatively quickly.

In some embodiments, the arithmetic operation may require one slice per byte. A logical operation may require half a slice per byte. A shift operation may require aggregation of slices depending on the width of the shift operation. The compare operation may require one slice per byte. The select operation may require half a slice per byte.

As part of the compilation process, placement and routing are performed. Deployment is the allocation of a particular physical subunit to perform a particular instruction or instructions. Routing ensures that the output or outputs of a particular subunit are routed to the correct destination, which may be, for example, another subunit or subunits.

Placement and routing may use a process in which actions are assigned to specific subunits, starting at one end of the pipeline. In some embodiments, the most important actions may be placed prior to the less important actions. In some embodiments, routing may be assigned at the same time a particular operation is being deployed. In some embodiments, the route may be selected from a limited set of pre-computed routes. This will be explained in detail later.

In some embodiments, if a route cannot be assigned, the operation will be retained for later.

In some embodiments, the pre-computed route may be a byte wide route. However, this is by way of example only, and in other embodiments, routes of different widths may be defined. In some embodiments, a plurality of different sized routes may be provided.

In some embodiments, routing may be limited to routing between neighboring subunits.

In some embodiments, subunits may be physically arranged in regular structures on the FPGA.

In some embodiments, to facilitate routing, rules may be made regarding how subunits may communicate. For example, a subunit may only provide output to a subunit next to it, above it, or below it.

Alternatively or additionally, one may place a limit on how far the next subunit is for routing purposes. For example, a subunit may output data only to an adjacent subunit or a subunit within a defined distance (eg, there is only one intervening subunit).

Reference is made to FIG. 19 , which illustrates a method of some embodiments.

In some embodiments, an FPGA may have one or more “static” regions and one or more “dynamic” regions. Static domains provide standard configuration and dynamic functions can also provide functionality based on end-user needs. The static part may be defined, for example, before the end user receives the network interface device, eg before the network interface device is installed with respect to the host. For example, a static area may be configured to cause a network interface device to provide certain functionality. A static region will be given a pre-computed route between the smallest units. As will be discussed in more detail later, there may be routing between one or more static regions through one or more dynamic regions. The dynamic area may be configured by end users according to their needs when the network interface device is deployed in relation to the host. Dynamic regions may be configured to perform different functions for end users over time.

In step S1 , a first compilation process is performed to provide a main bit file 50 and a first bit file referred to as a tool checkpoint 52 . This is a bit file for at least a portion of a static region in some embodiments. The bit file, when downloaded to the FPGA, will cause the FPGA to function as specified in the program - the bit file was compiled from this program. In some embodiments, the program used in the first compilation process may be any one or more programs or a test program specifically designed to support the determination of routing within a portion of the FPGA. In some embodiments, a series of simple programs may alternatively or additionally be used.

A program may have reconfigurable partitions that may be modified or used by the compiler. The program may be modified to make the compiler's job easier by moving the net out of the reconfigurable partition.

Step S1 may be performed in a design tool. By way of example only, the Vivado tool may be used with Xilinx FPGAs. The checkpoint file may be provided by the design tool. A checkpoint file represents a snapshot of the design at the point at which the bit file is created. A checkpoint file may include one or more synthesized netlists, design constraints, placement information, and routing information.

In step S2, the bit file is analyzed taking into account the checkpoint file to provide a bit file description 54. The analysis may be one or more of detecting a resource, creating a route, checking timing, generating one or more partial bit files, and generating a bit file description.

The analysis may be configured to extract routing information from the bit file. The analysis may be configured to determine on which wire or route the signal propagated.

The analysis phase may be performed at least in part in a synthesis or design tool. In some embodiments Vivado's scripting tools may be used. The scripting tool may be a tool command language (TCL). TCL can be used to add or modify the capabilities of Vivado. Vivado's functions can also be invoked and controlled by TCL scripts.

The bit file description 54 defines how a given portion of the FPGA can be used. For example, the bit file description may indicate which smallest unit may be routed to any other minimal unit and one or more routes that enable routing between those smallest units. For example, for each minimum unit, the bit file description may include where the input to that minimum unit may originate and where the output from that minimum unit may be routed along with one or more routes for data output. will indicate The bit file description is independent of any program.

The bit file description may include one or more of route information, an indication of which pairs of routes collide, and a description of how to create a bit file from the minimum unit of necessary configuration.

The bit file description may provide the set of roots available between the set of minimum units, but before any particular instruction is executed by the given minimum unit.

The bit file description may be for a part of the FPGA. The bit file description may be for a dynamic FPGA part. The bit file description will include which routes are available and/or which routes are not. For example, the bit file may have any route to the dynamic portion of the FPGA, taking into account any routing across the dynamic portion of the FPGA that is required by, for example, the static portion(s) of the FPGA. It can also indicate whether it is available.

It should be appreciated that, in some embodiments, the bit file description may be obtained in any suitable manner. For example, the bit file description may be provided by the FPGA or ASIC provider.

In some embodiments, the bit file description may be provided by a design tool. In this embodiment, the analysis step may be omitted. The design tool may output a bit file description. The bit file description may be for a static portion of the FPGA, including any necessary routing across the dynamic portion of the FPGA.

It should be appreciated that any other suitable technique may be used to generate the bit file description. In the example described above, the tools used to design the FPGA are used to provide the analysis used to generate the bit files.

It should be appreciated that in other embodiments, different tools may be used. A tool may, in some embodiments, be specific to a product or a range of products. For example, the FPGA provider may provide related tools for managing the FPGA.

In other embodiments, generic scripting tools may be used.

In some embodiments, different tools or different techniques may be used to determine the partial bit file. For example, the main bits file may be analyzed to determine which features correspond to which features. This may require that multiple partial bit files be created.

It should be appreciated that step S3 is performed when the network interface device is installed in association with the host and executed on the physical FPGA device. Steps S1 and S2 may be performed as part of the design synthesis process to generate a bit file image implementing the network interface device. In some embodiments, step S1 and/or step S2 is used to characterize the behavior of the FPGA. Once the FPGA is characterized, the bit file description is stored in memory for all physical network interface devices that will operate in a given defined manner.

In step S3, compilation is performed using the bit file description and the eBPF program. The output of the compilation is a partial bit file to the eBPF program. Compilation will add the root to the partial bit files and programming to be performed by individual slices of the slice.

It should be appreciated that the bit file description may be provided by the system being deployed. The bit file description may be stored in memory. The bit file description may be stored on the FPGA, on a network interface device, or on a host device. In some embodiments, the bit file description is stored in flash memory or the like that is coupled to the FPGA on the network interface device. The flash memory may also include a main bit file.

The eBPF program may be stored separately or together with the bit file description. The eBPF program may be stored on the FPGA, on the network interface device, or on the host. In the case of eBPF, programs may be transferred from user mode programs to the kernel, both running on the host. The kernel will send the program to the device driver, which will then send it to the compiler running on either the host or network interface device. In some embodiments, the eBPF program may be stored on the network interface device so that it can be executed before the host OS is booted.

The compiler may be provided in a network interface device, FPGA, or any suitable location on the host. By way of example only, the compiler may run on a CPU on a network interface device.

Now, the compiler flow will be described. The front end of the compiler accepts eBPF programs. The eBPF program may be written in any suitable language. For example, the eBPF program may be written in a C type language. A compiler is configured at the front end to translate the program into an intermediate representation (IR). In some embodiments, the IR may be LLVM-IR or any other suitable IR.

In some embodiments, pointer analysis may be performed to generate packet/map access primitives.

It should be appreciated that, in some embodiments, optimization of IR may be performed by a compiler. This may be optional in some embodiments.

The compiler's high-level synthesis backend is configured to split the program pipeline into stages, generate packet access taps, and emit C code. In some embodiments, the HLS portion of the design tool and/or the design tool being used may be invoked to synthesize the output of the HLS phase.

The compiler backend to the FPGA smallest unit splits the pipeline into stages and creates packet access taps. To convert a control dependency into a data dependency, an if-conversion may be performed. The design is placed and routed. Partial bit files for eBPF programs are emitted.

As shown in FIG. 20A with routing conflicts, routing problems may arise. For example, slice A may communicate with slice C, and slice B may communicate with slice D. In the arrangement of FIG. 20A , a common routing portion 60 has been allocated for communication between slices B and D as well as communication between slices A and C. In some embodiments, such routing conflicts may be avoided. Reference is made to FIG. 20b in this regard. As can be seen, a separate route 62 is provided between slice A and slice C compared to route 64 between slice B and slice D.

In some embodiments, the bit file description may include a plurality of different routes for at least some pairs of subunits. The compilation process will check for routing conflicts as shown in Fig. 20A. In the case of routing conflicts, the compiler may resolve or avoid such conflicts by choosing an appropriate alternative route among the routes.

21 shows a partition 66 of the FPGA for performing the eBPF program. The partition interfaces with the static portion of the FPGA via, for example, a series of input flip-flops 68 and a series of output flip-flops. In some embodiments, there may be routing 70 throughout the design as discussed above.

The compiler may need to handle routing across the FPGA area being configured by the compiler. The compiler needs to create a partial bitfile that fits into a reconfigurable partition within the main bitfile. If the main bit file is created with reconfigurable partitions, the design tool will avoid using those resources within the reconfigurable partition so that logical resources can be used by the partial bit files. However, the design tool may not be able to prevent the use of routing resources within the reconfigurable partition.

As a result, the analysis tool will need to avoid the use of routing resources that were used by the design tool in the main bit file. The analysis tool may need to ensure that its list of available routes in the bit file description does not contain anything using resources being used by the main bit file. The available routes may be defined in terms of route templates that can be used in a large number of places within the FPGA, since FPGAs are highly regular. The routing resources used by the main bit file break the regularity, meaning that the analysis tool prevents them from using their templates in places where they would collide with the main bit file. Analysis tools may require creating new route templates that can be used at those locations and/or preventing certain route templates from being used at specific locations.

Some examples of functionality provided by the compiler in converting some exemplary eBPF program fragments into instructions to be executed by a minimal unit will now be described.

Some embodiments may use any suitable synthesis tool to generate the bit file description. By way of example only, some embodiments may use the Bluespec tool, which is based on a mode that uses atomic transactions for hardware.

In a first example, the eBPF program fragment has two instructions:

Command 1: r1 += r2

Command 2: r1 += r3

The first instruction adds the number in register 1 (r1) to the number in register 2 (r2) and places the result in r1. The second instruction adds r1 to r3 and places the result in r1. Both instructions in this example use 64-bit registers, but only the lowest 32 bits. The upper 32 bits of the result are padded with zeros.

The compiler will translate these into instructions to be executed by the smallest unit. A 32-bit add instruction requires 32 pairs of lookup tables (LUTs), a 32-bit carry chain and 32 flip-flops.

Each pair of lookup tables adds two bits to produce a 2-bit result. A carry chain is a structure that allows one bit to be moved from a digit column to the next during addition, and allows a bit to be borrowed from the next column, during subtraction.

The 32 flip-flops are storage elements that accept a value on one clock cycle and reproduce it on the next clock cycle. They may be used to limit the amount of work done per clock cycle and to simplify timing analysis.

In some embodiments, an FPGA may include multiple slices. In some example slices, the carry chain propagates from the bottom of the slice (CIN) to the top of the slice (COUT), which is then connected to the CIN input of the next slice.

In the example where each slice has a 4-bit carry chain, eight slices are used to perform a 32-bit addition. In this embodiment, the minimum unit may be considered as provided by a pair of slices. This is because in some embodiments it may be convenient for the smallest unit to operate on 8-bit values.

In the example where each slice has an 8-bit carry chain, four slices are used to perform a 32-bit addition. In this embodiment, the smallest unit may be considered as being provided by a slice.

It should be appreciated that this is by way of example only, and, as discussed above, the minimum unit may be defined in any suitable manner.

In this example, now the case where the FPGA has a slice that supports 8-bit carry chains will be used in the compilation of the fragment of the first exemplary eBPF program.

There are three input values that are 32 bits wide and one output value that are 32 bits wide. There may be other older instructions that generated those three inputs. In the following, some arbitrary position of the slice (minimum unit) will be assumed.

The following numbering convention will be used. Slices (minimum units) are arranged in a regular row and column arrangement. XnYm represents the position of the smallest unit in the array. Xn represents a column and Ym represents a row. X6Y0 indicates that the slice is in column 6 and in row 0. It should be appreciated that any other suitable numbering scheme may be used in other embodiments.

Assume that the initial values were generated concurrently in the following locations:

r1: slices X6Y0, X6Y1, X6Y2 and X6Y3

r2: slices X6Y4, X6Y5, X6Y6 and X6Y7

r3: slices X6Y8, X6Y9, X6Y10 and X6Y11

The result of the first instruction needs to be computed by the four adjacent slices in the same column so that the carry chain is correctly connected up. The compiler may choose to compute the result in slices X7Y0, X7Y1, X7Y2 and X7Y3. For it to work, the input needs to be wired up. There will be a connection from X6Y0 to X7Y0, another connection from X6Y1 to X7Y1, a connection from X6Y2 to X7Y2, and a connection from X6Y3 to X7Y3. Also, there needs to be a corresponding connection from X6Y4-X6Y7 to X7Y0-X7Y3.

These would be full-byte connections meaning that each of the 8 input bits is connected to the corresponding output bit. For example:

Slice X6Y0 Flip Output from flip-flip 0 connected to input 0 of slice X7Y0 LUT 0.

Slice X6Y0 Flip Flip 1's output connected to input 0 of slice X7Y0 LUT 1.

It's like that until the next time

Slice X6Y0 Flip Output from flip 7 connected to input 0 of slice X7Y0 LUT 7.

During the first clock cycle, the r1 and r2 values of slice X6Y0-X6Y7 will be passed to the input of slice X7Y0-X7Y3, will be processed by the LUT and carry chain, and the result will be ready for use on the next cycle , they will be stored in the flip flip of slices X7Y0-X7Y3.

Go to command 2. The compiler needs to choose where to compute the result of instruction 2. It may select slices X7Y4 to X7Y7. Again, there will be a full byte concatenation from the result of instruction 1 (X7Y0 to X7Y3) to the input to instruction 2 (X7Y4 to X7Y7).

The r3 value is also required. If r1, r2 and r3 were generated in cycle 0, then r1 + r2 would be generated in cycle 1. The value of r3 needs to be delayed by a clock cycle so that it is generated in cycle 1. The compiler may choose to generate r3 in cycle 1 using slices X7Y8 through X7Y11. Then there will need to be a concatenation from the original slice that produced r3 in cycle 0 (X6Y8 to X6Y11) to the new slice that produced the same value in cycle 1 (X7Y8 to X7Y11). Having done that, now we need to have a connection from their new slice to the slice for instruction 2. Thus, the output of the slice X7Y8 rotor is connected to the input of the slice X7Y4 and so on.

Then the FPGA bit file will contain the following features:

- whole byte concatenation from X6Y0 to X7Y0 input 0 (initial r1 byte 0)

- whole byte concatenation from X6Y1 to X7Y1 input 0 (initial r1 byte 1)

- whole byte concatenation from X6Y2 to X7Y2 input 0 (initial r1 byte 2)

- whole byte concatenation from X6Y3 to X7Y3 input 0 (initial r1 byte 3)

- whole byte concatenation from X6Y4 to X7Y0 input 1 (initial r2 byte 0)

- whole byte concatenation from X6Y5 to X7Y1 input 1 (initial r2 byte 1)

- Concatenate full bytes from X6Y6 to X7Y2 input 1 (initial r2 byte 2)

- whole byte concatenation from X6Y7 to X7Y3 input 1 (initial r2 byte 3)

- whole byte concatenation from X6Y8 to X7Y8 input 0 (initial r3 byte 0)

- whole byte concatenation from X6Y9 to X7Y9 input 0 (initial r3 byte 1)

- Concatenate whole bytes from X6Y10 to X7Y10 input 0 (initial r3 byte 2)

- Concatenate whole bytes from X6Y11 to X7Y11 input 0 (initial r3 byte 3)

- Slice X7Y0 configured to add input 0 to input 1 (instruction 1 byte 0)

- Slice X7Y1 configured to add input 0 to input 1 (instruction 1 byte 1)

- Slice X7Y2 configured to add input 0 to input 1 (instruction 1 byte 2)

- Slice X7Y3 configured to add input 0 to input 1 (instruction 1 byte 3)

- Slice X7Y8 (r3 delay byte 0) configured to copy input 0 to output

- Slice X7Y9 (r3 delay byte 1) configured to copy input 0 to output

- Slice X7Y10 (r3 delay byte 2) configured to copy input 0 to output

- Slice X7Y11 (r3 delay byte 3) configured to copy input 0 to output

- Concatenate all bytes from X7Y0 to X7Y4 input 0 (command 1 byte 0)

- Concatenate all bytes from X7Y1 to X7Y5 input 0 (command 1 byte 1)

- Concatenate all bytes from X7Y2 to X7Y6 input 0 (command 1 byte 2)

- Concatenate all bytes from X7Y3 to X7Y7 input 0 (command 1 byte 3)

- whole byte concatenation from X7Y8 to X7Y4 input 1 (r3 delay byte 0)

- whole byte concatenation from X7Y9 to X7Y5 input 1 (r3 delay byte 1)

- whole byte concatenation from X7Y10 to X7Y6 input 1 (r3 delay byte 2)

- whole byte concatenation from X7Y11 to X7Y7 input 1 (r3 delay byte 3)

- Slice X7Y4 configured to add input 0 to input 1 (instruction 2 byte 0)

- Slice X7Y5 configured to add input 0 to input 1 (instruction 2 byte 1)

- Slice X7Y6 configured to add input 0 to input 1 (instruction 2 byte 2)

- Slice X7Y7 configured to add input 0 to input 1 (instruction 2 byte 3)

The compiler does not need to generate the upper 32 bits of the instruction 2 result, since they are known to be zero. It can just take note of that fact and use zeros whenever they are used.

Now, a second example of compilation of eBPF fragments will be described.

Command 1: r1 & = 0xff

Command 2: r2 & = 0xff

Command 3: Go to L1 if r1 < r2

Command 4: r1 = r2

Label L1.

The first instruction performs a bitwise AND of r1 with the constant 0xff and places the result in r1. A given bit in the result will be set to 1 if the corresponding bit was originally set to 1 in r1 and the corresponding bit was set to 1 in the constant. Otherwise, it will be set to zero. The constant 0xff causes bits 0-7 to be set and bits 8-63 cleared, so the result will be that bits 0-7 of r1 will not be changed but bits 8-63 will be set to zero. This simplifies things for the compiler, because the compiler understands that bits 8 through 63 are zero and need not generate them. The second instruction does the same for r2.

Instruction 3 checks whether r1 is less than r2, and if so, jumps to label L1. This skips instruction 4. Instruction 4 simply copies the value from r2 to r1. This sequence of instructions finds the smallest of r1 byte 0 and r2 byte 0, and places the result in r1 byte 0.

The compiler may use a technique known as “if conversion” to convert conditional jumps into select instructions:

Command 1: r1 & = 0xff

Command 2: r2 & = 0xff

Command 5: c1 = (r1 < r2)

Command 6: r1 = c1 ? r1 : r2

Instruction 5 compares r1 to r2, sets c1 to 1 if r1 is less than r2, otherwise sets c1 to zero. Command 6 is an optional command that copies r1 to r1 if c1 is set (this has no effect), otherwise copies r2 to r1. If c1 is equal to 1, then instruction 3 will skip instruction 4, which means r1 will keep its value from instruction 1. In this case, the select instruction also leaves r1 unchanged. If c1 is equal to zero, then instruction 3 will not skip instruction 4, so r2 will be copied to r1 by instruction 4. Again, the select instruction will copy r2 to r1, so the new sequence has the same effect as the old sequence.

Instruction 6 is not a valid eBPF instruction. However, while the compiler is running, the instructions are expressed in LLVM-IR. Instruction 6 would be a valid instruction in LLVM-IR.

Now these instructions need to be allocated in the smallest unit. Assume that input r1 is available in slices X0Y0 through X0Y7 and r2 is available in slices X0Y8 through X0Y15. Instructions 1 and 2 cause the compiler to note that the upper 7 bytes of r1 and r2 are set to zero.

The compiler may then choose to compute the result of instruction 5 in slice X1Y0. A full byte concatenation is required from the output of slice X0Y0 to input 0 of slice X1Y0 and a full byte concatenation is required from the output of slice X0Y8 to input 1 of slice X1Y0. The way to compare two values is to see if the computation overflows by subtracting one value from the other and trying to borrow from the next higher bit. The result of this comparison is then stored in flip-flop 7 of slice X1Y1.

As in the first example, r1 and r2 will need to be delayed by one cycle to provide a value to instruction 6 at the correct time. The compiler may use slices X1Y1 and X1Y2 for r1 and r2, respectively.

The select command requires three inputs: c1, r1 and r2. Note that r1 and r2 are 1 byte wide, but c1 is only 1 bit wide. Assume that compilation computes the result of the selection instruction slice X2Y0. Selection is performed on a bit-by-bit basis, with each LUT in slice X2Y0 handling 1 bit:

If c1 is set, then bit 0 of the result is r1 bit 0 and r2 bit 0

other

If c1 is set then bit 1 of the result is r1 bit 1 and r2 bit 1

other

...and so on

If c1 is set then bit 7 of the result is r1 bit 7 and r2 bit 7

other.

Each LUT may need to access the corresponding bit from r1 and the corresponding bit from r2, but all LUTs need to access c1. This means that c1 needs to be copied over the bits of input 0 of the slice. So the connection to the input of command 6 would be:

Duplicate bit 7 of the output of slice X1Y0 to input 0 of slice X2Y0.

Concatenation of whole bytes from output of slice X1Y1 to input 1 of slice X2Y0.

Concatenation of whole bytes from output of slice X1Y2 to input 2 of slice X2Y0.

Another problem that needs to be addressed relates to shift instructions. Consider the following example:

A 16 bit left shift by 5 bits needs to do the following:

Set output bit 0 to zero

set output bit 1 to zero

set output bit 2 to zero

set output bit 3 to zero

set output bit 4 to zero

Copies input bit 0 to output bit 5

Copies input bit 1 to output bit 6

...

Copies input bit 10 to output bit 15

Note that the input and output here are of the connection. The input of the concatenation comes from the output of the first slice. The output of the concatenation goes to the input of the second slice.

It may not be possible to make this kind of connection within a slice, but rather may be possible by the interconnection between the slices. The compiler can assume that a 16-bit input value was generated by two adjacent slices in the same column, because the compiler can verify that the value is generated there.

As an example, assume that the input is produced by slices X0Y4 and X0Y5 and that the output goes to slices X1Y4 and X1Y5. In that case, the following connections are required:

Slice X1Y4 bit 0 is known to be zero and is therefore not needed

Slice X1Y4 bit 1 is known to be zero and is therefore not needed

Slice X1Y4 bit 2 is known to be zero and is therefore not needed

Slice X1Y4 bit 3 is known to be zero and is therefore not needed

Slice X1Y4 bit 4 is known to be zero and is therefore not needed

Slice X1Y4 bit 5 comes from slice X0Y4 bit 0

Slice X1Y4 bit 6 comes from slice X0Y4 bit 1.

Slice X1Y4 bit 7 comes from slice X0Y4 bit 2

Slice X1Y5 bit 0 comes from slice X0Y4 bit 3

Slice X1Y5 bit 1 comes from slice X0Y4 bit 4

Slice X1Y5 bit 2 comes from slice X0Y4 bit 5

Slice X1Y5 bit 3 comes from slice X0Y4 bit 6

Slice X1Y5 bit 4 comes from slice X0Y4 bit 7

Slice X1Y5 bit 5 comes from slice X0Y5 bit 0

Slice X1Y5 bit 6 comes from slice X0Y5 bit 1.

Slice X1Y5 bit 7 comes from slice X0Y5 bit 2

The eight connections to the input of slice X1Y5 can be considered as shifted connections or shifted roots. The same structure could be used for slice X1Y4, but with inputs from X1Y3 and X1Y4, bits 5-7 match and slice can ignore bits 0-4 so it doesn't matter what input is presented there because it doesn't

It may be necessary to be able to shift between 1 bit and 7 bits by an arbitrary amount. A concatenation that shifts by 0 or 8 bits is exactly the same as a full byte concatenation, since in that case each bit is concatenated to the corresponding bit of the other slice.

Shifting by a variable amount may be done in two or three stages, depending on the width of the value being shifted. The stages are as follows:

Stage 1: Shift by 0, 1, 2 or 3.

Stage 2: Shift by 0, 4, 8 or 12.

Stage 3: Shift by 0, 16, 32 or 48 (32-bit or 64-bit only).

As another example, assuming there is an arithmetic right shift of bytes by a variable amount, the value to be shifted is generated by the slice X3Y2 and the shift amount is generated by X3Y3.

Arithmetic right shift requires an "arithmetic right shift" type of connection. This type of concatenation takes the output of one slice and connects them to the input of another slice, but shifts them right by a certain amount in the process, duplicating the sign bits as needed.

For example, an "arithmetic right shift by 3" link would look like this:

Output bit 0 comes from input bit 3

Output bit 1 is from input bit 4

Output bit 2 comes from input bit 5

output bit 3 comes from input bit 6

Output bit 4 comes from input bit 7

Output bit 5 comes from input bit 7 (sign bit)

Output bit 6 comes from input bit 7 (sign bit)

Output bit 7 comes from input bit 7 (sign bit)

Stage 1 may be computed on slice X4Y2, in which case it would require the following concatenation:

Total bytes from slice X3Y2 to slice X4Y2 input 0

arithmetic right shift by 1 from slice X3Y2 to slice X4Y2 input 1

arithmetic right shift by 2 from slice X3Y2 to slice X4Y2 input 2

arithmetic right shift by 3 from slice X3Y2 to slice X4Y2 input 3

Duplicate slice X3Y3 bit 0 to slice X4Y2 input 4

Duplicate slice X3Y3 bit 1 to slice X4Y2 input 5

Slice X4Y2 is then configured to select one of the first four inputs based on inputs 4 and 5 as follows:

input 4 is 0 and input 5 is 0: select input 0

input 4 is 1 and input 5 is 0: select input 1

input 4 is 0 and input 5 is 1: select input 2

input 4 is 1 and input 5 is 1: select input 3

The shift amount may be copied from slice X3Y3 to slice X4Y3 to provide a delayed version.

Stage 2 may be computed on slice X5Y2, in which case it would require the following concatenation:

Total bytes from slice X4Y2 to slice X5Y2 input 0

Arithmetic right shift by 4 from slice X4Y2 to slice X5Y2 input 1

Duplicate slice X4Y3 bit 2 to slice X5Y2 input 2

Slice X5Y2 will then be configured to select either input 0 or input 1 based on input 2 as follows:

input 2 is 0: input 0 is selected

input 2 is 1: select input 1

The output of slice X5Y2 will be the result of a variable arithmetic shift right operation.

The bit file for a given smallest unit may be:

The smallest unit of identity information

A list of other minimum units for which a given minimum unit can receive an input and an available route to that input.

A list of other minimum units for which a given minimum unit can give an output and an available route to that output.

It should be appreciated that since FPGAs are regular structures, there may be a common template that can be used for multiple minimum units with modifications to the respective minimum units of the minimum unit as needed.

As an example, the bit file description for slice X7Y1 may specify the following possible inputs and outputs:

Input from X6Y1 via route A or route B

Input from X6Y5 via route C or route D

Input from X7Y0 via route E or route F

Output to X8Y1 via route G or route H

Output to X7Y2 via route I or route J

Output to X7Y5 via route K or route L.

The compiler will use this bit file description to provide a partial bit file for the input and output of slice X7Y1 for the previously described first eBPF example of the following.

Input from X6Y1 via route A

Input from X6Y5 via route C

Output to X7Y5 via route K or route L.

As an example, the bit file description for slice XnYm may specify the following possible inputs and outputs:

Input from Xn-1Ym via route A or route B

Input from Xn-1Ym+4 via route C or route D

Input from XnYm-1 via route E or route F

Output to Xn+1Ym via route G or route H

Output to XnYm+1 via route I or route J

Output to XnYm+4 via route K or route L.

This bit file description may be modified to remove one or more roots that are not available for use by the compiler, as described above. This may be because the route is used by other minimal units or for routing through partitions.

It should be appreciated that a compiler may be implemented by a computer program comprising computer executable instructions that may be executed by one or more computer processors. A compiler may run on hardware, such as at least one processor operating in conjunction with one or more memories.

While exemplary embodiments have been described above, it is noted that there are many variations and modifications that may be made to the disclosed solutions without departing from the scope of the present invention.

Accordingly, embodiments may vary within the scope of the appended claims. In general, some embodiments may be implemented in hardware or special purpose circuitry, software, logic, or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software that may be executed by a controller, microprocessor, or other computing device, although embodiments are not limited to controllers, microprocessors, or other computing devices. may be

Embodiments may be implemented by computer software stored in a memory and executable by at least one data processor of an accompanying entity, or by hardware, or by a combination of software and hardware.

The software may be stored on a physical medium such as a memory chip, or a memory block implemented within a processor, a magnetic medium such as a hard disk or floppy disk, and an optical medium such as, for example, a DVD and its data variants, a CD. have.

The memory may be of any type suitable for the local technology environment, and implemented using any suitable data storage technology, such as semiconductor-based memory devices, magnetic memory devices and systems, optical memory devices and systems, fixed memory and removable memory. could be

A data processor may be of any type suitable for the local technical environment, and includes, by way of non-limiting examples, a general purpose computer, a special purpose computer, a microprocessor, a digital signal processor (DSP), an application specific integrated circuit (ASIC). , gate level circuits, and processors based on multi-core processor architectures.

Various modifications and adaptations may become apparent to those skilled in the relevant art in light of the foregoing description when read in conjunction with the accompanying drawings and appended claims. However, all such and similar modifications of the present teachings will still fall within the scope as defined in the appended claims.

Claims (30)

A network interface device for interfacing a host device to a network, comprising:
a first interface configured to receive a plurality of data packets;
a plurality of processing units, each processing unit associated with a predefined type of operation executable in a single step, wherein at least some of the plurality of processing units are associated with a different predefined type of operation Configurable hardware modules
includes,
The hardware module is configured to: provide a first data processing pipeline for processing one or more of the plurality of data packets to perform a first function on the one or more of the plurality of data packets, the A network interface device, configurable to interconnect at least a portion. The network interface device of claim 1 , wherein two or more of the at least some of the plurality of processing units are configured to perform an associated at least one predefined operation in parallel. 3. The method of claim 1 or claim 2, wherein two or more of the at least some of the plurality of processing units include:
to perform an operation of an associated predefined type within a predefined length of time defined by the clock signal; And
in response to the end of the predefined length of time, transmit the result of each at least one operation to a next processing unit;
configured, a network interface device. 4. The method of any one of claims 1 to 3, wherein each of the plurality of processing units comprises an application specific integrated circuit configured to perform at least one operation associated with the respective processing unit. , a network interface device. 5. The digital circuit according to any one of claims 1 to 4, wherein at least one of the plurality of processing units comprises a memory for storing digital circuitry and states related to processing performed by the digital circuitry, the digital circuitry comprising: , in communication with the memory to perform the predefined type of operation associated with the respective processing unit. 6. The hardware device of any one of claims 1 to 5, wherein at least two of the plurality of processing units comprise an accessible memory, the memory configured to store a state associated with a first data packet; and during performance of the first function by a module, at least two of the plurality of processing units are configured to access and modify the state. 7. The network of claim 6, wherein a first processing unit of the at least some of the plurality of processing units is configured to stall during access of the value of the state by a second processing unit of the plurality of processing units. interface device. 8. The method of any preceding claim, wherein one or more of the plurality of processing units are individually configurable to perform an operation specific to each pipeline based on an associated predefined type of operation. network interface device. 9. The method of any one of claims 1 to 8, wherein the hardware module is configured to receive an instruction, and in response to the instruction:
interconnecting at least a portion of the plurality of processing units to provide a data processing pipeline for processing one or more of the plurality of data packets;
causing one or more of the plurality of processing units to perform an associated predefined type of operation on one or more data packets;
adding one or more of the plurality of processing units to a data processing pipeline; and
removing one or more of the plurality of processing units from a data processing pipeline;
A network interface device configured to do at least one of: 10. The method according to any one of claims 1 to 9, wherein the predefined type of operation comprises:
loading at least one value of the first data packet from memory;
storing at least one value of the data packet in a memory; and
performing a lookup on a lookup table to determine the action to be performed on the data packet
A network interface device comprising at least one of: 11. The method of any one of claims 1 to 10, wherein at least one of the at least some of the plurality of processing units is configured to perform at least one result of an associated at least one predefined operation in the first processing pipeline. then forward to a processing unit, wherein the subsequent processing unit is configured to perform a next predefined action depending on the at least one result. The network interface device according to any one of the preceding claims, wherein each of the different predefined types of operation is defined by a different template. 13. The method according to any one of claims 1 to 12, wherein the predefined type of operation comprises:
accessing data packets;
accessing a lookup table stored in a memory of the hardware module;
performing logical operations on data loaded from data packets; and
performing logical operations on data loaded from the lookup table;
A network interface device comprising at least one of: 14. The method of any one of claims 1 to 13, wherein the hardware module comprises routing hardware, and wherein the hardware module connects between the plurality of processing units in a particular order defined by the first data processing pipeline. configurable to interconnect at least a portion of the plurality of processing units to provide the first data processing pipeline by configuring the routing hardware to route data packets. 15. The second function according to any one of claims 1 to 14, wherein the hardware module provides a second data processing pipeline for processing one or more of the plurality of data packets to provide a second function different from the first function. A network interface device configurable to interconnect at least some of the plurality of processing units to perform 16. The method of any one of claims 1 to 15, wherein the hardware module, after interconnecting at least some of the plurality of processing units to provide the first data processing pipeline, configures a second data processing pipeline. A network interface device configurable to interconnect at least a portion of the plurality of processing units to provide The network interface device of claim 1 , comprising additional circuitry separate from the hardware module and configured to perform the first function for one or more of the plurality of data packets. . 18. The method of claim 17, wherein the additional circuitry comprises:
field programmable gate arrays; and
Multiple central processing units
A network interface device comprising at least one of: 19. The device according to claim 17 or 18, wherein the network interface device comprises at least one controller, and wherein the additional circuitry is configured to process the first data packet during a compilation process for the first function to be performed in the hardware module. and the at least one controller is configured to, in response to completion of the compilation process, control the hardware module to start performing the first function on a data packet. 20. The method of claim 19, wherein the at least one controller is further configured to, in response to determining that the compilation process for the first function to be performed in the hardware module is complete, to stop performing the first function on a data packet. A network interface device configured to control additional circuitry. 19. The network interface device according to claim 17 or 18, wherein the network interface device comprises at least one controller, and the hardware module is configured to: and, in response to the determining, to determine that the compilation process for the first function to be performed in the additional circuitry is complete, and in response to the determination, the at least one controller is configured to: and control the additional circuitry to start performing 22. The method of claim 21, wherein the at least one controller is further configured to, in response to the determining that the compilation process for the first function to be performed in the additional circuitry is complete, stop performing the first function on a data packet. and a network interface device configured to control the hardware module. 23. A device as claimed in any preceding claim, comprising at least one controller configured to perform a compilation process to provide the first function to be performed in the hardware module. 24. A data processing system comprising the network interface device of any one of claims 1 to 23 and a host device, wherein the data processing system performs a compilation process to provide the first function to be performed in the hardware module. A data processing system comprising at least one controller configured to: 25. The method of claim 24, wherein the at least one controller comprises:
the network interface device; and
the host device
provided by one or more of the data processing systems. 26. The method of claim 24 or 25, wherein the compilation process is performed in response to a determination by the at least one controller that a computer program representing the first function is safe for execution in a kernel mode of the host device. being a data processing system. 27. The method of claim 24, 25, or 26, wherein the at least one controller executes at least one operation from a plurality of operations represented by a sequence of computer code instructions in the first data processing pipeline. and perform the compilation process by assigning, in a particular order, to each of the at least some of the plurality of processing units to perform, the plurality of operations performing the first function for the one or more of the plurality of data packets. provided by a data processing system. 28. The method of any one of claims 24-27, wherein the at least one controller comprises:
send, prior to completion of the compilation process, a first instruction for causing additional circuitry of the network interface device to perform the first function on a data packet; And
subsequent to the completion of the compilation process, send a second instruction for causing the hardware module to start performing the first function on the data packet;
configured, a data processing system. A method for implementation in a network interface device, comprising:
receiving, at the first interface, a plurality of data packets; and
at least a portion of a plurality of processing units of a hardware module to provide a first data processing pipeline for processing one or more of the plurality of data packets to perform a first function on the one or more of the plurality of data packets configuring the hardware module to interconnect
includes,
Each processing unit is associated with a predefined type of operation executable in a single step,
and at least some of the plurality of processing units are associated with different predefined types of operation. A non-transitory computer-readable medium comprising program instructions for causing a network interface device to perform a method, the method comprising:
receiving, at the first interface, a plurality of data packets; and
at least a portion of a plurality of processing units of a hardware module to provide a first data processing pipeline for processing one or more of the plurality of data packets to perform a first function on the one or more of the plurality of data packets configuring the hardware module to interconnect
includes,
Each processing unit is associated with a predefined type of operation executable in a single step,
and at least some of the plurality of processing units are associated with different predefined types of operation.

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