KR20210086139A - Organic light emitting display device - Google Patents

Abstract

An organic light emitting display device according to one embodiment of the present invention includes: a substrate including an active region and an inactive region surrounding the active region; an anode disposed on the substrate corresponding to the active region; a bank layer covering the edge of the anode to define a light emitting region; an organic light emitting layer disposed on the anode; a cathode disposed on the organic light emitting layer; a plurality of connection electrodes disposed in the inactive region and having a shape elongated in a first direction from the active region to the inactive region; and a low potential block electrode disposed in the inactive region and connected to the low potential wiring. The plurality of connection electrodes are connected to the cathode and the low potential block electrode.

Description

Organic light emitting display device {ORGANIC LIGHT EMITTING DISPLAY DEVICE}

The present invention relates to an organic light emitting diode display capable of realizing a uniform image by maintaining a stable voltage across a panel.

Unlike a liquid crystal display device (LCD) having a backlight, an organic light emitting display device (OLED) includes an organic light emitting device, which is a self-luminous device, and can be manufactured in a lightweight and thin form. The advantage is that the process is simple. In addition, the organic light emitting diode display can be driven at a low voltage and has an advantage of having a fast response speed. The organic light emitting device has a structure in which an organic light emitting layer is formed between an anode and a cathode. When a voltage is applied, holes injected from the anode and electrons injected from the cathode form excitons in the organic light emitting layer, and the excitons are stable in an unstable excited state. The image is displayed using the light emitted while falling to the state.

The organic emission layer is mainly formed through a deposition method using a mask. In this case, it is difficult to implement a large-area and high-resolution display device due to sagging of the mask, manufacturing deviation, shadow effect, and the like. Accordingly, a method of forming an organic light emitting layer by a solution process of dropping ink into the light emitting region has been proposed. In the solution process, the organic light emitting layer is formed by forming a bank defining a light emitting area and a non light emitting area on the anode, then injecting ink onto the light emitting area while scanning using an ejection device, and curing it.

SUMMARY OF THE INVENTION An object of the present invention is to provide an outer structure of an organic light emitting diode display in which low-potential wiring is disposed.

Another problem to be solved by the present invention is to minimize the problem of heat generation due to low-potential wiring.

Another object of the present invention is to provide a display device having improved display quality by minimizing a thickness variation of an organic light emitting layer.

The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

An organic light emitting diode display according to an embodiment of the present invention includes a substrate including an active region and an inactive region surrounding the active region, an anode disposed on the substrate corresponding to the active region, and a light emitting region by covering the edges of the anode a bank layer, an organic light emitting layer disposed on the anode, a cathode disposed on the organic light emitting layer, a plurality of connection electrodes disposed in the inactive region and having a shape elongated in a first direction from the active region to the inactive region; and a low potential block electrode disposed in inactive and connected to the low potential wiring, wherein the plurality of connection electrodes are connected to the cathode and the low potential block electrode.

The details of other embodiments are included in the detailed description and drawings.

The present invention can suppress the heat generation phenomenon occurring at the point where the low potential wiring and the cathode are connected.

According to the present invention, the thickness variation of the organic light emitting layer can be minimized and the profile can be made uniform when the organic light emitting device is manufactured through a solution process.

According to the present invention, the size of the dummy area in which the dummy pixels are disposed can be increased without increasing the size of the non-display area.

The effect according to the present invention is not limited by the contents exemplified above, and more various effects are included in the present invention.

1 is a plan view of an organic light emitting diode display according to an exemplary embodiment.
FIG. 2 is a schematic enlarged plan view of area A of FIG. 1 .
FIG. 3 is a cross-sectional view of the organic light emitting diode display taken along line III-III′ of FIG. 1 .
4 is a cross-sectional view of the organic light emitting diode display taken along line IV-IV' of FIG. 1 .
5 is a schematic plan view of an organic light emitting diode display according to a comparative example.
6 is an enlarged plan view of an organic light emitting diode display taken along line VI-VI' of FIG. 5 .

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different shapes, only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention pertains It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative and the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. When 'include', 'have', 'consists of', etc. mentioned in the present invention are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between the two parts unless 'directly' is used.

Reference to a device or layer “on” another device or layer includes any intervening layer or other device directly on or in the middle of another device.

Also, although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

Like reference numerals refer to like elements throughout.

The area and thickness of each component shown in the drawings are shown for convenience of description, and the present invention is not necessarily limited to the area and thickness of the illustrated component.

Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship. may be

Hereinafter, the present invention will be described with reference to the drawings.

1 to 4 are diagrams for explaining an organic light emitting diode display according to an exemplary embodiment. 1 is a plan view of an organic light emitting diode display according to an exemplary embodiment. FIG. 2 is a schematic enlarged plan view of area A of FIG. 1 . FIG. 3 is a cross-sectional view of the organic light emitting diode display taken along line III-III′ of FIG. 1 . 4 is a cross-sectional view of the organic light emitting diode display taken along line IV-IV' of FIG. 1 .

Referring to FIG. 1 , an organic light emitting diode display 100 according to an exemplary embodiment includes a substrate 110 , a flexible film 180 , and a printed circuit board 190 .

The substrate 110 is a substrate 110 for supporting and protecting various components of the organic light emitting diode display 100 . The substrate 110 may be made of glass or a plastic material having flexibility. When the substrate 110 is made of a plastic material, it may be made of, for example, polyimide (PI), but is not limited thereto.

The substrate 110 includes an active area AA and an inactive area IA.

The active area AA is an area in which a plurality of sub-pixels SP are disposed to substantially display an image. A sub-pixel SP including an emission area for displaying an image and a driving circuit for driving the sub-pixel SP may be disposed in the active area AA. For example, a plurality of data lines and a plurality of gate lines are disposed on the substrate 110 . The sub-pixel SP is a minimum unit constituting a screen, and each of the plurality of sub-pixels SP may include a light emitting device and a driving circuit. Each sub-pixel SP may be defined as an intersection region of a plurality of gate lines disposed in a first direction and a plurality of data lines DL disposed in a second direction different from the first direction. The first direction may be a horizontal direction of FIG. 1 , and the second direction may be a vertical direction of FIG. 1 , but is not limited thereto.

Each sub-pixel SP may emit light of different wavelengths. For example, the plurality of sub-pixels SP may include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel G. However, the present invention is not limited thereto, and the plurality of sub-pixels SP may further include a white sub-pixel.

The inactive area IA surrounds the active area AA. The inactive area IA is an area in which an image is not substantially displayed, and various wirings, a driving IC, a printed circuit board 190, etc. for driving the sub-pixels SP and the driving circuit disposed in the active area AA. this is placed For example, various ICs such as a gate driver IC and a data driver IC may be disposed in the inactive area IA. On the other hand, as described above, in the inactive area IA, a driving IC, a printed circuit board 190, etc. may be disposed, and a predetermined area is required for a driving IC, a printed circuit board 190, etc. to be disposed. . In this case, the driving IC may include a gate driver, a data driver, and the like. The driving IC and driving circuit can be arranged in the GIP (Gate In Panel) method, COF (Chip On Film) method, TAB (Tape Automated Bonding) method, TCP (Tape Carrier Package) method, COG (Chip On Glass) method, etc. have.

The inactive area IA may include a dummy area DA, a contact area CA, and a pad area PA.

The pad area PA supplies a data signal to a data line according to a data control signal input from a timing controller disposed on the printed circuit board 190 . The pad area PA may be manufactured as a driving chip, mounted on the flexible film 180 , and disposed on the inactive area IA of the substrate 110 in a tape automated bonding (TAB) method.

The contact area CA may connect the low potential line VSS and the cathode 133 included in the sub-pixel SP disposed inside the active area AA. More specifically, the low potential block electrode 170 connected to the low potential wiring VSS in the contact area CA may be electrically connected to the cathode 133 . For example, the contact area CA may be provided in an area overlapping the edge of the cathode 133 to be electrically connected through the contact hole CTH.

The flexible film 180 is disposed on the side of the substrate 110 . The flexible film 180 transmits various signals from the printed circuit board 190 to the sub-pixels SP. A driving circuit (eg, an IC chip) may be mounted on the flexible film 180 . The driving circuit may generate a data signal or a gate signal in response to driving power and various signals transmitted from the printed circuit board 190 , and supply the data signal or gate signal to the sub-pixel SP. To this end, the driving circuit may have a type including both a data driver for generating a data signal and a gate driver for generating a scan signal, or a form in which the data driver and the gate driver are separated from each other. In this case, the flexible film 180 may transmit signals output from the printed circuit board 190 to the driving circuit or may transmit signals output from the driving circuit to the sub-pixels SP. The flexible film 180 is attached on the pad area PA using an anisotropic conducting film, whereby wirings of the pad area PA and the flexible film 180 may be connected.

The printed circuit board 190 may be attached to the flexible film 180 to transmit various signals to the sub-pixels SP. For example, a timing controller may be disposed on the printed circuit board 190 . The timing controller may supply various signals to the driving circuit. For example, the timing controller may generate a data driver control signal (DDC), a gate driver control signal (GDC), etc. and supply them to the driving circuit.

2 to 4 , the organic light emitting diode display 100 according to an embodiment of the present invention includes a substrate 110 , a thin film transistor 120 , an organic light emitting diode 130 , a bank layer 140 , and a connection electrode. (160), including a low potential block electrode (170).

The substrate 110 includes an active area AA and an inactive area IA. In this case, the inactive area IA may include a dummy area DA, a contact area CA, and a pad area PA.

A buffer layer 111 is disposed on the substrate 110 . The buffer layer 111 may improve adhesion between the layers formed on the buffer layer 111 and the substrate 110 . In addition, the buffer layer 111 may block alkali components leaking from the substrate 110 , and may prevent moisture and/or oxygen penetrating from the outside of the substrate 110 from diffusing. The buffer layer 111 may be formed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto. Also, the buffer layer 111 may be omitted based on the type and material of the substrate 110 , the structure and type of the thin film transistor 120 , and the like.

A thin film transistor 120 including a gate electrode 122 , an active layer 121 , a source electrode 123 , and a drain electrode 124 is disposed on the buffer layer 111 . 3 illustrates only a driving thin film transistor among various thin film transistors that may be included in the organic light emitting diode display 100 for convenience of description, but other transistors such as a switching thin film transistor may also be disposed.

Meanwhile, the thin film transistor 120 illustrated in FIG. 2 is illustratively described as having a coplanar structure, but is not limited thereto, and a thin film transistor having an inverted staggered structure may also be used. In addition, the thin film transistor 120 is a thin film transistor having a top gate structure in which the gate electrode 122 is disposed on the active layer 121 or a thin film transistor having a bottom gate structure in which the gate electrode 122 is disposed under the active layer 121 . may be implemented as

An active layer 121 is disposed on the buffer layer 111 . The active layer 121 is a region in which a channel is formed when the thin film transistor 120 is driven. The active layer 121 may be formed of an oxide semiconductor, amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or an organic semiconductor, but is not limited thereto. does not

A gate insulating layer 112 is disposed on the active layer 121 . The gate insulating layer 112 insulates the active layer 121 from the gate electrode 122 . The gate insulating layer 112 may be formed of a single layer or multiple layers of inorganic silicon nitride (SiNx) or silicon oxide (SiOx). As shown in FIG. 3 , the gate insulating layer 112 may be patterned to have the same width as the gate electrode 122 , and may be formed over the entire surface of the substrate 110 , but is not limited thereto.

The gate electrode 122 is disposed on the gate insulating layer 112 . The gate electrode 122 is disposed on the gate insulating layer 112 to overlap the channel region of the active layer 121 . The gate electrode 122 may be formed of various metal materials, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and It may be made of any one of copper (Cu), an alloy of two or more, or a multilayer thereof, but is not limited thereto.

An interlayer insulating layer 113 is disposed on the buffer layer 111 and the gate electrode 122 . The interlayer insulating layer 113 insulates the gate electrode 122 , the source electrode 123 , and the drain electrode 124 . The interlayer insulating layer 113 may be formed of a single layer or multiple layers of inorganic silicon nitride (SiNx) or silicon oxide (SiOx). In the interlayer insulating layer 113 , a contact hole is formed for the source electrode 123 and the drain electrode 124 to contact each of the source region and the drain region of the active layer 121 .

The source electrode 123 and the drain electrode 124 are disposed on the interlayer insulating layer 113 . The source electrode 123 and the drain electrode 124 are electrically connected to the active layer 121 through a contact hole of the interlayer insulating layer 113 . The source electrode 123 and the drain electrode 124 may be formed of various metal materials, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), It may be made of any one of neodymium (Nd) and copper (Cu), an alloy of two or more, or a multilayer thereof, but is not limited thereto.

A passivation layer 114 for protecting the thin film transistor 120 is disposed on the thin film transistor 120 . A contact hole for exposing the source electrode 123 or the drain electrode 124 of the thin film transistor 120 may be formed in the passivation layer 114 . The passivation layer 114 may be formed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx).

A planarization layer 115 for planarizing an upper portion of the thin film transistor 120 is disposed on the passivation layer 114 . A contact hole for exposing the source electrode 123 or the drain electrode 124 of the thin film transistor 120 is formed in the planarization layer 115 . The planarization layer 115 is an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ( polyphenylene) resin, polyphenylene sulfide resin, benzocyclobutene, and photoresist, but is not limited thereto.

Referring to FIG. 2 , a plurality of sub-pixels SP are disposed in the active area AA. For example, in the plurality of sub-pixels SP, red sub-pixels R, green sub-pixels G, and blue sub-pixels B are sequentially and repeatedly arranged in a first direction (vertical direction), Sub-pixels SP emitting the same color in two directions (Y-axis direction) are repeatedly arranged. Each of the sub-pixels SP includes an organic light emitting diode 130 .

Specifically, the organic light emitting diode 130 is disposed on the planarization layer 115 to correspond to the active area AA. The organic light emitting device 130 of the present invention is a light emitting device that emits light, and may be driven by the thin film transistor 120 disposed in each sub-pixel SP. Each organic light emitting device 130 includes an anode 131 , an organic light emitting layer 132 , and a cathode 133 .

The anode 131 is disposed on the planarization layer 115 . The anode 131 may be formed on the planarization layer 115 to be separated for each sub-pixel SP. The anode 131 is a component for supplying holes to the organic emission layer 142 and is formed of a conductive material having a high work function. For example, the anode 131 is indium-tin-oxide (ITO), indium-zinc-oxide (IZO), indium-tin-zinc-oxide (indium-tin) Transparent conductivity such as -zinc oxide, ITZO), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium-copper-oxide (ICO) and aluminum:zinc oxide (Al:ZnO, AZO) It may be formed of at least one selected from oxides, but is not limited thereto. When the organic light emitting diode display 100 is driven by the top emission method, the anode 131 may have a structure in which a layer formed of a transparent conductive oxide and a reflective layer formed of a metal material are stacked. The reflective layer is formed of a metal having a high reflectance so that light emitted from the organic light emitting layer 132 can be reflected upward.

A bank layer 140 is disposed on the anode 131 and the planarization layer 115 . The bank layer 140 is formed at the boundary between the plurality of sub-pixels SP to distinguish adjacent sub-pixels SP. The bank layer 140 may be disposed to open a portion of the anode 131 , and the bank layer 140 may define an emission area EA and a non-emission area. For example, the bank layer 140 may be disposed to cover the edge of the anode 131 in the non-emission area to block light generation in the non-emission area. Since the bank layer 140 is not disposed in the light emitting area EA, the light emitting layer 132 is directly positioned on the anode 131 to generate light from the light emitting layer 132 . That is, an area in which the bank layer 140 is disposed may be defined as a non-emission area, and an area in which the bank layer 140 is not disposed may be defined as an emission area EA.

The bank layer 140 may be made of a hydrophobic material. For example, the hydrophobic bank layer 140 may be made of a hydrophobic organic insulating material, or the bank layer 140 may be a structure in which a hydrophobic treatment is performed on the surface of the insulating material. Accordingly, when the organic emission layer 132 is formed by a solution process, the flow of the organic emission layer 132 to another adjacent sub-pixel SP may be prevented.

The organic emission layer 132 is disposed on the anode 131 that is not covered by the bank layer 140 . Referring to FIG. 3 , the organic emission layer 132 may be disposed in the emission area EA of each sub-pixel SP, and may be disposed in contact with the side surface of the bank layer 140 defining the emission area EA. can be

The organic light emitting layer 132 is a layer that emits light by combining electrons and holes. The organic light emitting layer 132 includes an organic light emitting material having a color corresponding to each of the sub-pixels SP. For example, each sub-pixel SP may be a red sub-pixel R, a green sub-pixel G, or a blue sub-pixel B. The organic emission layer 132 may further include various layers such as a hole transport layer, a hole injection layer, a hole blocking layer, an electron injection layer, an electron transport layer, and an electron blocking layer.

The organic light emitting layer 132 may be formed through a solution process such as inkjet printing or nozzle printing. However, the solution process method is not limited thereto, and the organic light emitting layer 132 may be formed by various known solution process methods to form the organic light emitting layer 132 . When each organic light-emitting layer 132 is formed on each sub-pixel SP through a solution process, ink having a color corresponding to each sub-pixel SP is sprayed or dropped, and then cured to form the organic light-emitting layer ( 132) is formed. When the organic light emitting layer 132 is formed through a solution process, manufacturing cost can be reduced compared to forming the organic light emitting layer through a deposition process, and a large area display device can be provided.

The cathode 133 is disposed on the organic emission layer 132 . Referring to FIG. 3 , the cathode 133 is disposed as one layer on the organic emission layer 132 and the bank layer 140 in the emission area EA. For example, the cathode 133 may be disposed in contact with the organic light emitting layer 132 and may be disposed along the shape of the organic light emitting layer 132 . The cathode 133 may be formed as a continuous layer without being separated for each of the plurality of sub-pixels SP.

When the organic light emitting diode display 100 is driven in the top emission mode, the cathode 133 is formed of a metal material such as silver (Ag), copper (Cu), or magnesium-silver alloy (Mg:Ag) in a very thin thickness. It may be formed of a transflective electrode or a transparent electrode including a transparent conductive oxide or a ytterbium (Yb) alloy, but is not limited thereto.

Meanwhile, the dummy area DA surrounds the active area AA. Specifically, the dummy area DA is provided at the upper, lower, left, and right outer sides of the active area AA. A plurality of dummy pixels DP are disposed in the dummy area DA. Also, a bank defining the dummy pixel DP is provided in the dummy area DA similarly to the active area AA, and the dummy light emitting layer 150 is provided in the dummy pixel DP. The anode 131 may or may not be disposed in the dummy pixel DP. The bank 400 is formed in a matrix structure throughout the active area AA and the dummy area DA to simultaneously define the sub-pixel SP and the dummy pixel DP.

Since the dummy area DA is not a display area for displaying an image, the dummy pixel DP provided in the dummy area DA does not emit light. The dummy area DA serves to uniformly form the profile of the central organic light emitting layer in the active area AA and the profile of the organic light emitting layer 132 at the edge of the active area AA. do.

When the organic emission layer 132 is formed by a solution process, a difference in drying speed of the organic emission layer 132 may occur between the center and the edge of the substrate 110 . Accordingly, when only the active area AA is provided without the dummy area DA, the profile of the central organic emission layer in the active area AA and the edge of the active area AA due to the difference in drying speed Profiles of the organic light emitting layers of are formed to be non-uniform with each other, so that light emission between the center and the edge in the active area AA may be non-uniform. Accordingly, in the organic light emitting diode display 100 of the present invention, when the dummy area DA is formed outside the active area AA and the organic light emitting layer 132 is formed in the active area AA by a solution process, the Since the dummy emission layer 150 is also formed in the dummy area DA by a solution process, the profile of the dummy emission layer 150 and the profile of the organic emission layer of the sub-pixel SP may be non-uniform. Profiles of the organic light emitting layer 132 in the whole may be made uniform to each other.

Meanwhile, the connection electrode 160 is disposed on the planarization layer 115 of the dummy area DA. The connection electrode 160 is formed to contact the cathode 133 . The connection electrode 160 may contact the cathode 133 to reduce resistance of the cathode 133 . In addition, the connection electrode 160 extends to the contact area CA to overlap the cathode 133 , and is connected to the low potential block electrode 170 through the contact hole CTH. The low potential voltage applied through the low potential block electrode 170 is transferred to the cathode 133 through the connection electrode 160 . Also, the connection electrode 160 may extend toward the contact area CA while being in contact with the cathode 133 on the planarization layer 115 . The sheet resistance of the cathode 133 may be reduced by increasing the size of the area in contact with the connection electrode 160 and the cathode 133 .

The connection electrode 160 may be made of a metal material having high conductivity. Also, the connection electrode 160 may be formed of the same material as the anode 131 of the organic light emitting diode 130 through the same process.

2 and 3 , the connection electrode 160 is formed to overlap a portion of the dummy pixel DP disposed in the dummy area DA. For example, the connection electrode 160 may be disposed under the dummy emission layer 150 of some dummy pixels DP. However, the present invention is not limited thereto, and the connection electrode 160 may be disposed to completely overlap the dummy area DA, and some bank layers 140 may be disposed in the dummy area DA without overlapping the dummy emission layer 150 . It may be arranged to overlap with the

Referring to FIG. 2 , the connection electrode 160 has a shape elongated in a direction from the active area AA to the inactive area IA. That is, the connection electrode 160 may have a bar shape having a width narrower than a length. Also, the connection electrode 160 may be disposed in a shape bent in an “L” shape in the dummy area DA. Since the dummy area DA is not long in the second direction (Y-axis direction), it does not extend in a straight line in the second direction (Y-axis direction) in order to maximize the contact area with the cathode 133 or reduce the sheet resistance in the first direction. It may have a shape bent in the (X-axis direction). However, the shape of the connection electrode 160 is not limited thereto, and may be an oblique line, a curved line, or a zigzag shape.

A contact area CA is provided outside the dummy area DA. A low potential block electrode 170 connected to the low potential wiring VSS is disposed in the contact area CA. The low potential block electrode 170 is disposed on the gate insulating layer to directly contact the connection electrode 160 , and is electrically connected to the connection electrode 160 and the cathode 133 .

A contact hole CTH may be formed in the interlayer insulating layer 113 , the passivation layer 114 , and the planarization layer 115 in the contact area CA to expose the top surface of the low potential block electrode 170 . The connection electrode 160 and the cathode 133 may be connected to the low potential block electrode 170 through the contact hole CTH, and finally may be electrically connected to the low potential wiring VSS.

The low potential block electrode 170 may be connected to the plurality of connection electrodes 160 at a plurality of points. That is, the low potential block electrode 170 may directly contact the plurality of connection electrodes 160 through the plurality of contact holes CTH. Referring to FIG. 2 , the low-potential block electrode 170 includes a plurality of micro-block patterns 175 that are split from the center. Each of the fine block patterns 175 may be arranged to extend from the center of the low potential block electrode 170 in the dummy area DA direction, and may be respectively connected to the plurality of connection electrodes 160 .

When the low potential block electrode and the connection electrode contact each other through a single point or a single contact hole, heat may be generated. Specifically, in a contact hole in which the low potential block electrode and the connection electrode or the cathode are connected, the current coming from the low potential wiring VSS is concentrated in a specific region, so that the current density is rapidly increased. As the current is concentrated in a specific area, heat is generated around the contact hole, and the generated heat melts or damages the surrounding organic material. In particular, since the polarizing material disposed on the display element has a very weak physical property to heat, it may melt due to the heat generated by the current coming from the low potential wiring (VSS). Accordingly, the organic light emitting diode display 100 according to an embodiment of the present invention connects the low potential block electrode 170 and the low potential block electrode 170 at a plurality of points through a plurality of contact holes using a plurality of connection electrodes 160 , thereby making contact. It is possible to prevent the current from being concentrated to a specific area of the hole and to distribute the current. For this reason, the exothermic phenomenon can be suppressed.

Referring to FIG. 2 , the low potential block electrode 170 may have a shape including the fine block pattern 175 branched from the center in order to contact the plurality of connection electrodes 160 , but the plurality of connection electrodes 160 . ) and can be connected at a plurality of points, and is not particularly limited as long as it has a shape in which the contact holes CTH for connection can be dispersed. Meanwhile, an interval between the fine block patterns 175 may become narrower toward the active region.

Meanwhile, the low potential block electrode 170 may be formed of the same material as the source electrode 123 and the drain electrode 124 of the thin film transistor 120 through the same process.

On the other hand, the organic light emitting diode display 100 according to an embodiment of the present invention uses a plurality of connection electrodes 160 to connect the low potential block electrode 170 and the plurality of points at a plurality of points. The size of the dummy area DA may be increased without increasing the size of the area IA. As described above, by forming the dummy emission layer 150 of the dummy pixel DP disposed in the dummy area DA together with the organic emission layer 132 of the organic light emitting device 130 using a solution process, the organic emission layer ( 132) can be made uniform. Accordingly, if the size of the dummy area DA is increased in a line that does not increase the area of the inactive area IA, the profile of the organic emission layer 132 may be more uniform.

An increase in the size of the above-described dummy area DA will be described through comparison with the structure of a conventional organic light emitting diode display.

5 and 6 are plan views illustrating a structure of an organic light emitting diode display according to a comparative example. In the organic light emitting diode display according to the comparative example, the shapes of the low potential block electrode 70 and the connection electrode 60 are different from those of the organic light emitting diode display 100 of the present invention.

Specifically, referring to FIG. 5 , the low potential block electrode 70 has a triangular shape in which the width becomes narrower as it progresses from the outer portion of the inactive area IA to the active area AA. The triangular-shaped structure is due to the arrangement structure of the high-potential voltage link wiring extending from the flexible film 80 positioned adjacent to the low-potential block electrode 70 . This is because the high potential voltage link wiring has a shape in which the width increases from the inactive area IA to the active area AA. Accordingly, since the width of the low potential block electrode 70 having a triangular shape becomes narrower toward the active area AA, an area capable of contacting the cathode and the connection electrode 60 is reduced. Accordingly, it is not easy to change the structure to increase the connection point and area between the low potential block electrode 70 and the connection electrode 60 .

However, the organic light emitting diode display 100 according to an embodiment of the present invention uses a plurality of connection electrodes 160 having a narrow width and a low potential block electrode 170 having a plurality of fine block patterns 175 . , the position and shape of the contact point can be easily adjusted and changed. Accordingly, the contact point of the connection electrode 160 and the low-potential block may be moved to the outer portion of the inactive area, thereby increasing the length of the dummy area DA.

The organic light emitting diode display according to various embodiments of the present disclosure may be described as follows.

An organic light emitting diode display according to an embodiment of the present invention includes a substrate including an active region and an inactive region surrounding the active region, an anode disposed on the substrate corresponding to the active region, and a light emitting region by covering the edges of the anode a bank layer, an organic light emitting layer disposed on the anode, a cathode disposed on the organic light emitting layer, a plurality of connection electrodes disposed in the inactive region and having a shape elongated in a first direction from the active region to the inactive region; and a low potential block electrode disposed in inactive and connected to the low potential wiring, wherein the plurality of connection electrodes are connected to the cathode and the low potential block electrode.

According to another feature of the present invention, the plurality of connection electrodes may be disposed under the cathode and may extend in contact with the cathode.

According to another feature of the present invention, the plurality of connection electrodes may have a shape bent in a second direction different from the first direction.

According to another feature of the present invention, the plurality of connection electrodes may contact the low potential block electrode at a plurality of points.

According to another feature of the present invention, it further comprises a thin film transistor disposed on the substrate and connected to the anode, a passivation layer disposed on the thin film transistor, and a planarization layer disposed on the passivation layer, wherein the passivation layer is located in an inactive region Through the plurality of contact holes formed on the layer and the planarization layer, the plurality of connection electrodes and the low potential block electrode may contact each other.

According to another feature of the present invention, the connection electrode may be formed on the same layer with the same material as the anode, and the low potential block electrode may be formed on the same layer with the same material as the gate electrode constituting the thin film transistor.

According to another feature of the present invention, the low potential block electrode may further include a plurality of microblock patterns extending toward the active region, and each of the plurality of microblock patterns may contact each of the plurality of connection electrodes.

According to another feature of the present invention, the distance between the fine block patterns may become narrower toward the active region.

According to still another feature of the present invention, the inactive region includes a dummy region positioned outside the active region and a connection region positioned outside the dummy region, and a plurality of connection electrodes, a cathode, and a low-potential block electrode in the connection region This can be connected

According to another feature of the present invention, the connection electrode may extend from the dummy region toward the connection region and may have a shape bent at least once in the dummy region.

According to another feature of the present invention, the organic light emitting layer of the plurality of sub-pixels arranged in a first direction and the dummy pixel further comprising a plurality of sub-pixels provided in the active area and a plurality of dummy pixels provided in the dummy area The dummy emission layer may include the same emission material.

According to another feature of the present invention, the thickness deviation of the organic emission layer of the sub-pixel may be smaller than the thickness deviation of the dummy emission layer of the dummy pixel.

According to another feature of the present invention, the bank layer may be made of a hydrophobic material.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made within the scope without departing from the technical spirit of the present invention. . Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to illustrate, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100: organic light emitting display device
110: substrate
120: thin film transistor
130: organic light emitting device
140: bank layer
150: dummy light emitting layer
160: connection electrode
170: low potential block electrode
180: flexible film
190: printed circuit board
AA: active area
IA: inactive area
CA: contact area
DA: dummy area
PA: pad area
CTH: contact hole
SP: sub pixel
DP: Dummy Pixel

Claims (13)

a substrate comprising an active region and an inactive region surrounding the active region;
an anode disposed on the substrate to correspond to the active region;
a bank layer covering an edge of the anode to define a light emitting region;
an organic light emitting layer disposed on the anode;
a cathode disposed on the organic light emitting layer;
a plurality of connection electrodes disposed in the inactive region and having a shape elongated in a first direction from the active region to the inactive region; and
and a low potential block electrode disposed in the inactive and connected to the low potential wiring,
and the plurality of connection electrodes are connected to the cathode and the low potential block electrode. According to claim 1,
The plurality of connection electrodes are disposed under the cathode and extend in contact with the cathode. According to claim 1,
The plurality of connection electrodes have a shape bent in a second direction different from the first direction. According to claim 1,
and the plurality of connection electrodes are in contact with the low potential block electrode at a plurality of points. 5. The method of claim 4,
a thin film transistor disposed on the substrate and connected to the anode;
a passivation layer disposed on the thin film transistor; and
Further comprising a planarization layer disposed on the passivation layer,
and the plurality of connection electrodes and the low potential block electrode are in contact with each other through a plurality of contact holes located in the inactive region and formed on the passivation layer and the planarization layer. 6. The method of claim 5,
The connection electrode is formed on the same layer with the same material as the anode,
and the low potential block electrode is formed on the same layer with the same material as the gate electrode constituting the thin film transistor. According to claim 1,
The low-potential block electrode further includes a plurality of micro-block patterns extending toward the active region, and each of the plurality of micro-block patterns is in contact with each of the plurality of connection electrodes. 8. The method of claim 7,
The organic light emitting display device, wherein the distance between the fine block patterns becomes narrower toward the active region. According to claim 1,
The inactive region includes a dummy region positioned outside the active region and a connection region positioned outside the dummy region,
The organic light emitting diode display device, wherein the plurality of connection electrodes, the cathode, and the low potential block electrode are connected in the connection region. 10. The method of claim 9,
the connection electrode extends from the dummy region toward the connection region;
An organic light emitting diode display having a shape bent at least once in the dummy area. 10. The method of claim 9,
Further comprising: a plurality of sub-pixels provided in the active region and a plurality of dummy pixels provided in the dummy region;
The organic light emitting layer of the plurality of sub-pixels arranged in the first direction and the dummy light emitting layer of the dummy pixel include the same light emitting material. 12. The method of claim 11,
The organic light emitting display device, wherein the thickness deviation of the organic emission layer of the sub-pixel is smaller than the thickness deviation of the dummy emission layer of the dummy pixel. According to claim 1,
and the bank layer is made of a hydrophobic material.

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