KR20210086048A - Display Device - Google Patents

Abstract

The present disclosure relates to a display device which compensates and outputs a change in a high potential voltage ELVDD. The display device includes: a display panel including a plurality of pixels; a driving circuit which transmits a driving signal to the display panel; and a power supply circuit for supplying a high potential voltage (ELVDD) to the display panel. The driving circuit calculates an average pixel value of input image data and provides a compensation signal PMIC_CONT for compensating the high potential voltage ELVDD according to a calculated average pixel value to the power supply circuit. The power supply circuit may adjust the high potential voltage ELVDD based on the compensation signal and supply the high potential voltage ELVDD to the display panel.

Description

Display Device {Display Device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and to a display device that compensates for and outputs a high potential voltage (ELVDD).

Recently, among display devices, display devices have been widely used as display devices due to their excellent image quality, light weight, thinness, and low power. As a display device, there are a liquid crystal display (LCD), an organic light emitting diode display (OLED), etc., and most of these are commercialized and marketed.

The display device includes a display panel in which a plurality of pixels are arranged in a matrix, a gate driver driving gate lines of the display panel, and a data driver driving data lines of the display panel.

The gate driver sequentially drives the gate lines of the display panel.

The data driver converts the digital data signal into an analog data signal whenever the gate lines are driven and supplies the converted digital data signal to the data lines of the display panel.

When the transition of image data input to the display device is large, a problem of poor image quality such as crosstalk may occur.

The above-mentioned background art is technical information possessed by the inventor for derivation of the present invention or acquired in the process of derivation of the present invention, and cannot necessarily be said to be a known technique disclosed to the general public prior to filing of the present invention.

According to an exemplary embodiment of the present disclosure, it is a technical task to supply the high potential voltage ELVDD to a display panel by compensating for variations in the high potential voltage ELVDD.

The tasks of the present specification are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the following description.

A display device according to an embodiment of the present disclosure includes a display panel including a plurality of pixels; a driving circuit that transmits a driving signal to the display panel; and a power supply circuit supplying a high potential voltage (ELVDD) to the display panel. wherein the driving circuit calculates an average pixel value of input image data and applies a compensation signal PMIC_CONT for compensating the high potential voltage ELVDD according to the calculated average pixel value to the power supply. provided to a supply circuit, wherein the power supply circuit adjusts the high potential voltage (ELVDD) based on the compensation signal and supplies it to the display panel.

The driving circuit may include an APL calculator that calculates the average pixel value, and the APL calculator calculates an average pixel value of image data for each horizontal line.

The driving circuit calculates an average pixel difference APL_DIFF_L for each line, which is a value obtained by subtracting an average pixel value of the previous horizontal line image data from an average pixel value of the current horizontal line image data, and an absolute value of the average pixel difference APL_DIFF_L for each line a determination unit that determines whether the predetermined reference value is exceeded and generates a compensation determination signal V_CONT to determine whether to compensate the high potential voltage ELVDD; Including, characterized in that.

The driving circuit may include: a compensation signal generator for generating the compensation signal PMIC_CONT based on the value of the compensation determination signal V_CONT of the determination unit and the average pixel difference APL_DIFF_L for each line and outputting the compensation signal to the power supply circuit; It is characterized in that it further comprises.

The compensation signal generator is configured to adjust the high potential voltage ELVDD in a positive direction when the average pixel difference APL_DIFF_L for each line has a negative value, and to adjust the average pixel difference APL_DIFF_L for each line. When it has a positive value, the high potential voltage ELVDD is adjusted in a negative direction.

The compensation signal generator may determine a magnitude of the adjustment value of the high potential voltage ELVDD in proportion to an absolute value of the average pixel difference APL_DIFF_L for each line.

The driving circuit may generate the compensation signal PMIC_CONT in units of one horizontal line.

The driving circuit may include an APL calculator that calculates the average pixel value, and the APL calculator calculates an average pixel value of the image data in units of each frame.

The driving circuit calculates an average pixel difference for each frame (APL_DIFF_F), which is a value obtained by subtracting the average pixel value of the previous frame image data from the average pixel value of the current frame image data, and the absolute value of the average pixel difference for each frame (APL_DIFF_F) is a determination unit generating a compensation determination signal V_CONT for determining whether the high potential voltage ELVDD is compensated by determining whether the set reference value is exceeded; Including, characterized in that.

The driving circuit may generate the compensation signal PMIC_CONT in units of one frame.

According to an exemplary embodiment of the present disclosure, a method of driving a display device including a power supply circuit for supplying a high potential voltage (ELVDD) includes: calculating an average pixel value of image data; calculating an average pixel difference; determining whether the absolute value of the average pixel difference exceeds a preset reference value; and providing a compensation signal PMIC_CONT for compensating the high potential voltage ELVDD to the power supply circuit.

The calculating of the average pixel value may include calculating an average pixel value of the image data for each horizontal line.

The calculating of the average pixel difference may include calculating an average pixel difference APL_DIFF_L for each line, which is a value obtained by subtracting an average pixel value of the previous horizontal line image data from an average pixel value of the current horizontal line image data.

The compensation signal PMIC_CONT adjusts the high potential voltage ELVDD in a positive direction when the average pixel difference APL_DIFF_L for each line has a negative value, and adjusts the average pixel difference APL_DIFF_L for each line. When the value has a positive value, the high potential voltage ELVDD is adjusted in a negative direction.

The compensation signal PMIC_CONT determines the magnitude of the adjustment value of the high potential voltage ELVDD in proportion to the absolute value of the average pixel difference APL_DIFF_L for each line.

The calculating of the average pixel value may include calculating an average pixel value of the image data in units of each frame.

The calculating of the average pixel difference may include calculating an average pixel difference APL_DIFF_F for each frame, which is a value obtained by subtracting an average pixel value of image data of a previous frame from an average pixel value of image data of a current frame.

According to the present invention, the high-potential voltage ELVDD is supplied to the display panel by compensating for the fluctuation of the high-potential voltage ELVDD, thereby improving the image quality problem.

1 is a block diagram illustrating a configuration of a display device according to an exemplary embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating an exemplary embodiment of the pixel illustrated in FIG. 1 .
3 and 4 are exemplary views illustrating a pixel arrangement of an organic light emitting diode display according to an exemplary embodiment.
5 is a diagram of a gamma reference voltage generation circuit for generating gamma reference voltages gamma1 to gamma9 according to an exemplary embodiment.
6 is a graph illustrating generation of gamma reference voltages gamma1 to gamma9 using a voltage irrelevant to the high potential voltage ELVDD as a reference voltage according to an exemplary embodiment.
FIG. 7 is a graph illustrating generation of gamma reference voltages gamma1 to gamma9 using a voltage linked to a high potential voltage ELVDD as a reference voltage according to an exemplary embodiment.
8 and 9 show a high potential voltage (ELVDD) variation waveform and a waveform of V_Data (Source2160) that is source output data in a pattern image having a large transition of image data.
10 is a block diagram of a driving circuit according to an embodiment of the present invention.
11 is a flowchart illustrating a high potential voltage (ELVDD) compensation method according to an embodiment of the present invention.
12 is a diagram illustrating a waveform output by compensating the high potential voltage ELVDD in units of frames according to an embodiment of the present invention.
13 is a diagram illustrating a waveform output by compensating the high potential voltage ELVDD in units of horizontal lines according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this specification, when an element (or region, layer, portion, etc.) is referred to as "on," "connected to," or "coupled to," another element, it is on the other element. It means that they can be directly connected/coupled or that a third component can be placed between them.

Like reference numerals refer to like components. In addition, in the drawings, thicknesses, ratios, and dimensions of components are exaggerated for effective description of technical content. “and/or” includes any combination of one or more that the associated configurations may define.

Terms such as first, second, etc. may be used to describe various elements, but the elements are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component. The singular expression includes the plural expression unless the context clearly dictates otherwise.

Terms such as "below", "below", "above", "upper" and the like are used to describe the relationship of the components shown in the drawings. The above terms are relative concepts, and are described based on directions indicated in the drawings.

"Comprise." Or "have." The term such as is intended to designate that there is a feature, number, step, action, component, part, or combination thereof described in the specification, but one or more other features or number, step, action, component, part or It should be understood that it does not preclude the possibility of the existence or addition of combinations thereof.

1 is a block diagram illustrating a configuration of a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1 , a display device 1 includes a timing controller 10 , a gate driver 20 , a data driver 30 , a power supply unit 40 , and a display panel 50 .

The timing controller 10 may receive an image signal RGB and a control signal CS from the outside. The image signal RGB may include a plurality of grayscale data. The control signal CS may include, for example, a horizontal synchronization signal, a vertical synchronization signal, and a main clock signal.

The timing controller 10 processes the image signal RGB and the control signal CS to be suitable for the operating conditions of the display panel 50 , and thus the image data DATA, the gate driving control signal CONT1, and the data driving control signal. (CONT2) and the power supply control signal (CONT3) can be generated and output.

The gate driver 20 may be connected to the pixels PX of the display panel 50 through the plurality of gate lines GL1 to GLn. The gate driver 20 may generate gate signals based on the gate driving control signal CONT1 output from the timing controller 10 . The gate driver 20 may provide the generated gate signals to the pixels PX through the plurality of gate lines GL1 to GLn.

The data driver 30 may be connected to the pixels PX of the display panel 50 through a plurality of data lines DL1 to DLm. The data driver 30 may generate data signals based on the image data DATA and the data driving control signal CONT2 output from the timing controller 10 . The data driver 30 may provide the generated data signals to the pixels PX through the plurality of data lines DL1 to DLm.

The power supply unit 40 may be connected to the pixels PX of the display panel 50 through a plurality of power lines PL1 and PL2 . The power supply unit 40 may generate a driving voltage to be provided to the display panel 50 based on the power supply control signal CONT3 . The driving voltage may include, for example, a high potential driving voltage ELVDD and a low potential driving voltage ELVSS. The power supply unit 40 may provide the generated driving voltages ELVDD and ELVSS to the pixels PX through the corresponding power lines PL1 and PL2 .

A plurality of pixels PX (or referred to as sub-pixels) are disposed on the display panel 50 . The pixels PX may be arranged, for example, in a matrix form on the display panel 50 .

Each pixel PX may be electrically connected to a corresponding gate line and data line. The pixels PX may emit light with luminance corresponding to the gate signal and the data signal supplied through the gate lines GL1 to GLn and the data lines DL1 to DLm.

Each pixel PX may display any one of the first to third colors. In an embodiment, each pixel PX may display any one of red, green, and blue. In another exemplary embodiment, each pixel PX may display any one of cyan, magenta, and yellow. In various embodiments, the pixels PX may be configured to display any one of four or more colors. For example, each pixel PX may display any one of red, green, blue, and white.

The timing control unit 10, the gate driver 20, the data driver 30, and the power supply unit 40 are each composed of a separate integrated circuit (IC) or at least a part of an integrated circuit. . For example, at least one of the data driver 30 and the power supply unit 40 may be configured as an integrated circuit (D-IC) integrated with the timing controller 10 .

Also, in FIG. 1 , the gate driver 20 and the data driver 30 are illustrated as separate components from the display panel 50 , but at least one of the gate driver 20 and the data driver 30 may be configured as a component of the display panel 50 . ) and integrally formed in an in-panel method. For example, the gate driver 20 may be integrally formed with the display panel 50 according to a gate in panel (GIP) method.

FIG. 2 is a circuit diagram illustrating an exemplary embodiment of the pixel illustrated in FIG. 1 . FIG. 2 illustrates the pixel PXij connected to the i-th gate line GLi and the j-th data line DLj as an example.

Referring to FIG. 2 , the pixel PX includes a switching transistor ST, a driving transistor DT, a storage capacitor Cst, and a light emitting device LD.

The first electrode (eg, the source electrode) of the switching transistor ST is electrically connected to the j-th data line DLj, and the second electrode (eg, the drain electrode) is connected to the first node N1 and electrically connected. The gate electrode of the switching transistor ST is electrically connected to the i-th gate line GLi. The switching transistor ST is turned on when the gate signal of the gate-on level is applied to the i-th gate line GLi, and transmits the data signal V_data applied to the j-th data line DLj to the first node N1 . forward to

The first electrode of the storage capacitor Cst may be electrically connected to the first node N1 , and the second electrode may be configured to receive the high potential voltage ELVDD. The storage capacitor Cst may be charged with a voltage corresponding to a difference between the voltage applied to the first node N1 and the high potential voltage ELVDD.

The first electrode (eg, the source electrode) of the driving transistor DT is configured to receive the high potential voltage ELVDD, and the second electrode (eg, the drain electrode) of the light emitting device LD is configured to receive the first electrode (eg, the drain electrode). electrically connected to an electrode (eg, an anode electrode). The gate electrode of the driving transistor DT is electrically connected to the first node N1 . The driving transistor DT is turned on when a gate-on level voltage is applied through the first node N1 , and the amount of the driving current I_DS flowing through the light emitting device LD in response to the voltage applied to the gate electrode can be controlled.

The amount of the driving current I_DS flowing through the light emitting device LD is as shown in [Equation 1] below.

That is, the amount of the driving current I_DS flowing through the light emitting device LD is the voltage high potential voltage ELVDD of the first electrode (eg, the source electrode) of the driving transistor DT and the voltage V_data provided to the gate electrode. ) is controlled according to the magnitude of V_GS, which is the difference value.

The light emitting element LD outputs light corresponding to the driving current. The light emitting device LD may output light corresponding to any one of red, green, and blue. The light emitting device LD may be an organic light emitting diode (OLED) or an ultra-small inorganic light emitting diode having a size ranging from micro to nano scale, but the present invention is not limited thereto. Hereinafter, the technical idea of the present invention will be described with reference to an embodiment in which the light emitting device LD is configured of an organic light emitting diode.

In the present invention, the structure of the pixels PX is not limited to that illustrated in FIG. 2 . According to an embodiment, the pixels PX are configured to compensate for the threshold voltage of the driving transistor DT or initialize the voltage of the gate electrode of the driving transistor DT and/or the voltage of the anode electrode of the light emitting device LD. It may further include one element.

2 shows an example in which the switching transistor ST and the driving transistor DT are NMOS transistors, but the present invention is not limited thereto. For example, at least some or all of the transistors constituting each pixel PX may be configured as PMOS transistors. In various embodiments, each of the switching transistor ST and the driving transistor DT is a low temperature poly silicon (LTPS) thin film transistor, an oxide thin film transistor, or a low temperature polycrystalline oxide (LTPO) thin film transistor. can be implemented.

3 and 4 are exemplary diagrams illustrating a pixel arrangement of an organic light emitting diode display according to an exemplary embodiment.

3 and 4, for convenience of description, the sub-pixels sP are arranged in a 4 X 4 matrix. In addition, in FIGS. 3 and 4 , it is assumed that the image data input to the display device has a large variation in the input image data.

One sub-pixel sP is connected to the gate lines GL1 to GLn, the data lines DL1 to DLm, and the power lines PL11 to PL1x and PL21 to PL2x.

Recently, as a display device having a high resolution and a high pixel density has been developed, the constraint of a pixel arrangement space is increasing. One way to solve this limitation is to share a specific element, for example, the power lines PL11 to PL1x and PL21 to PL2x by a plurality of pixels. This is a method of saving the space occupied by the signal wiring by reducing the number of signal lines supplying a common signal to each pixel. For example, as shown in FIGS. 3 and 4 , a so-called flip structure in which two adjacent pixels (columns) share high potential power lines PL11 to PL1x and low potential power lines PL21 to PL2x is used.

The high potential power lines PL11 to PL1x and the low potential power lines PL21 to PL2x may be arranged in a direction parallel to each other, but according to an embodiment, the high potential power lines PL11 to PL1x may be arranged in a first direction (for example, horizontal direction), and the low potential power lines PL21 to PL2x may be arranged in a second direction (eg, a vertical direction) to cross each other.

FIG. 3 shows that the high potential power lines PL11 to PL1x and the low potential power lines PL21 to PL2x are arranged in a vertical direction parallel to each other, and FIG. 4 shows the high potential power lines PL11 to PL1x in the first direction. (eg, horizontal direction), and the low potential power lines PL21 to PL2x are arranged in the second direction (eg, vertical direction).

4 , when the high potential power lines PL11 to PL1x and the low potential power lines PL21 to PL2x are arranged in a direction crossing each other, the high potential voltage signal ELVDD and the low potential voltage signal ELVSS There is an advantage in that the signal interference between the two can be reduced.

In FIG. 3 , the gray level gl of the gray level voltage of the sub-pixels sP11 to sP41 and sP12 to sP42 in the first and second columns is 10, and the gray level gl of the sub-pixels sP13 to sP43 and sP14 to sP44 in the third and fourth columns is gray. The gray level (gl) of the voltage is 255. The first and second column sub-pixels sP11 to sP41 and sP12 to sP42 are supplied with the high potential voltage ELVDD through the high potential power line PL11. The third and fourth column sub-pixels sP13 to sP43 and sP14 to sP44 are supplied with the high potential voltage ELVDD through the high potential power line PL12.

In the first and second column sub-pixels sP11 to sP41 and sP12 to sP42, the gray level gl of the grayscale voltage is 10. In addition, in the third and fourth column sub-pixels sP13 to sP43 and sP14 to sP44, the gray level gl of the grayscale voltage is 255, which is the maximum gray level gl. Accordingly, the amount of the driving current I_DS flowing through the light emitting element LD of the third and fourth sub-pixels sP13 to sP43 and sP14 to sP44 than the first and second sub-pixels sP11 to sP41 and sP12 to sP42 this is bigger

The first and second column sub-pixels sP11 to sP41 and sP12 to sP42 are supplied with the high potential voltage ELVDD through the high potential power line PL11. Also, since the third and fourth column sub-pixels sP13 to sP43 and sP14 to sP44 are supplied with the high potential voltage ELVDD through the high potential power line PL12, the value of the current IR_11 flowing through PL11 is the current IR_12 flowing through PL12. smaller than

Meanwhile, since a resistance component exists in the power line, a voltage drop IR-Drop occurs in the high potential voltage ELVDD supplied to each sub-pixel sP through the high potential power line due to the resistance component of the power line. Since the voltage drop, IR-Drop due to the resistance component of the power line, is proportional to the amount of current, the degree of the voltage drop (IR-Drop) of the high potential voltage (ELVDD) at PL12 is greater than that at PL11.

In FIG. 4 , the gray level gl of the gray level voltage of the sub-pixels sP11 to sP14 and sP21 to sP24 in the first and second rows is 10, and the gray level gl in the third and fourth rows sub-pixels sP31 to sP34 and sP41 to sP44 is the gray level. The gray level (gl) of the voltage is 255. The first and second row sub-pixels sP11 to sP14 and sP21 to sP24 are supplied with the high potential voltage ELVDD through the high potential power line PL11. In addition, the third and fourth row sub-pixels sP31 to sP34 and sP41 to sP44 are supplied with the high potential voltage ELVDD through the high potential power line PL12.

According to the principle described above, also in the case of FIG. 4, the value of the current IR_11 flowing through PL11 is smaller than the current IR_12 flowing through PL12. Accordingly, the degree of voltage drop IR-Drop of the high potential voltage ELVDD at P12 is greater than at PL11.

Due to the resistance component of the high-potential power line, the high-potential voltage ELVDD supplied to each sub-pixel sP is not constant, and the image pattern input to the display device and the arrangement of the high-potential power line and the sub-pixel sP are not constant. The voltage drop of the high potential voltage ELVDD may occur in various ways depending on the shape.

As such, when the input image data has a large fluctuation, the high potential voltage ELVDD supplied from the power supply device 40 to the display panel 50 is not a constant voltage but fluctuates. A change in the high potential voltage ELVDD causes a deviation of the driving current I_DS of the driving transistor DT for each pixel PX, which causes a difference in luminance of the pixel PX. Such a difference in luminance for each pixel PX causes poor image quality of the display device.

As a method for solving the image quality problem, there is a technique for generating a gamma voltage V-Gamma compensated for as much as a change in the high potential voltage ELVDD in a driving circuit (specifically, a data driver).

5 is a diagram of a gamma reference voltage generating circuit for generating gamma reference voltages gamma1 to gamma9 according to an exemplary embodiment.

6 is a graph illustrating generation of gamma reference voltages gamma1 to gamma9 using a voltage irrelevant to the high potential voltage ELVDD as a reference voltage according to an exemplary embodiment.

7 is a graph illustrating generation of gamma reference voltages gamma1 to gamma9 using a voltage linked to a high potential voltage ELVDD as a reference voltage according to an exemplary embodiment.

The gamma reference voltage generation circuit may include a resistor string 530 and muxes 510 and 520 .

The gamma reference voltage generating circuit divides the high potential reference voltage GAM_TOP and the low potential reference voltage GMA_BOTTOM with the resistor string 530 to generate a plurality of gamma reference voltages gamma1 to gamma9 . The gamma reference voltage generating circuit according to an embodiment may generate a plurality of gamma reference voltages gamma1 to gamma9 irrespective of the high potential voltage ELVDD. Also, the gamma reference voltage generation circuit according to an embodiment may generate a plurality of gamma reference voltages gamma1 to gamma9 in association with the high potential voltage ELVDD.

A MUX may be used to generate the high potential reference voltage GAM_TOP and the low potential reference voltage GMA_BOTTOM. The MUX may be configured as a 2:1 MUX.

In order to select the high potential reference voltage GAM_TOP, the first mux 510 may select any one from the band gap reference voltage BGR_VREF, Band Gap Reference and the high potential voltage upper limit ELVDD_VREF_T.

The second mux 520 may select any one of the ground voltage GND and the high potential voltage lower limit ELVDD_VREF_B to select the low potential reference voltage GAM_BOTTOM.

The high potential voltage upper limit ELVDD_VREF_T may be a voltage obtained by adding a constant value to the high potential voltage ELVDD. The high potential voltage lower limit ELVDD_VREF_B may be a voltage obtained by subtracting a predetermined constant value from the high potential voltage ELVDD.

The first mux 510 selects the band gap reference voltage BGR_VREF as the high potential reference voltage GAM_TOP, and the second mux 520 selects the ground voltage GND as the low potential reference voltage GMA_BOTTOM. In the case of selecting , the plurality of gamma reference voltages gamma1 to gamma9 are formed regardless of the high potential voltage ELVDD. That is, as shown in FIG. 6 , even if the high potential voltage ELVDD is changed, the high potential reference voltage GAM_TOP and the low potential reference voltage GAM_BOTTOM do not change, and the plurality of gamma reference voltages gamma1 to gamma9 are also high. It is formed regardless of the above voltage ELVDD. In this case, as described above, a difference in luminance of the pixels PX occurs due to a change in the high potential voltage ELVDD, and the difference in luminance for each pixel PX leads to poor image quality of the display device.

Meanwhile, the first mux 510 selects the high potential voltage upper limit ELVDD_VREF_T as the high potential reference voltage GAM_TOP, and the second mux 520 selects the high potential voltage lower limit ELVDD_VREF_B as the low potential reference voltage GMA_BOTTOM. In the case of selecting , the plurality of gamma reference voltages gamma1 to gamma9 are formed in association with the high potential voltage ELVDD. That is, the gamma voltage V-Gamma compensated for by the variation of the high potential voltage ELVDD is generated. As shown in FIG. 7 , as the high potential voltage ELVDD fluctuates, the high potential reference voltage GAM_TOP and the low potential reference voltage GAM_BOTTOM are interlocked and fluctuate, and the plurality of gamma reference voltages gamma1 to gamma9 are also high. It is formed in association with the fluctuation of the above voltage ELVDD. A gamma voltage V-Gamma compensated for by the variation of the high potential voltage ELVDD is generated, and a data signal is generated using the compensated gamma voltage V-Gamma. When the data signal is generated in association with the high potential voltage ELVDD in this way, there is a variation in ELVDD connected to the first electrode (source electrode, see FIG. 2 ) of the driving transistor DT forming the pixel, but the driving transistor DT Since V_data applied to the gate electrode of ) is applied with a value that compensates for variations in ELVDD, a luminance difference for each pixel PX can be removed despite variations in ELVDD.

However, the inventors of the present specification are aware that the method of removing the luminance difference for each pixel PX by generating a data signal in association with the high potential voltage ELVDD presented above cannot be a perfect method of removing the image quality defect. found

When the fluctuation range of the high potential voltage ELVDD is relatively large, the gamma voltage and the V_Data value that is the source output data may not keep up with the fluctuation rate of the high potential voltage ELVDD due to the RC delay of the electronic circuit device. can

8 and 9 show an existing high potential voltage waveform (ELVDD_AS) and a high potential voltage compensation waveform (ELVDD_COM) for reducing the fluctuation range of the existing high potential voltage (ELVDD_AS) in a pattern image with a large transition of image data. and the adjusted high potential voltage waveform ELVDD_N, whose fluctuation range is reduced by application of the high potential voltage compensation waveform ELVDD_COM. FIG. 8 shows a case in which the grayscale value of the input image varies greatly for each horizontal line, and FIG. 9 shows a case in which the grayscale value of the input image varies greatly for each frame.

First, look at FIG. 8 .

In FIG. 8 (a), a black image is displayed on 1 horizontal line 1H, a white image is displayed on 2 horizontal lines 2H, a black image is displayed on 3 horizontal lines 3H, and 4 horizontal lines ( A white image is displayed at 4H) and a black image is displayed at 5 horizontal lines 5H.

(b) shows that the high potential voltage ELVDD_AS varies due to the large variation of the input image data for each horizontal line. Assuming that an image of two horizontal lines 2H is displayed at the present time, since the image data on the previous horizontal line 1H displays a black image, the current flowing to the high potential power line is relatively small at this time. Accordingly, the high potential voltage ELVDD_AS supplied by the power supply circuit through the high potential voltage line has a small voltage drop.

On the other hand, when the image of the two horizontal lines 2H is displayed, the image data displays a white image. At this time, the current flowing to the high potential power line is relatively large, and thus the power supply circuit is supplied through the high potential voltage line. In the high potential voltage ELVDD_AS, a large voltage drop occurs.

As such, when the fluctuation of the input image data is large, the high potential voltage ELVDD_AS supplied to each pixel through the high potential voltage line in the power supply circuit does not have a constant value but fluctuates greatly. In this case, as described above, a difference in luminance of the pixels PX occurs due to a change in the high potential voltage ELVDD_AS, and the difference in luminance for each pixel PX leads to poor image quality of the display device.

(c) shows the high potential voltage compensation waveform ELVDD_COM for reducing the fluctuation range of the conventional high potential voltage ELVDD_AS. The high potential voltage compensation waveform ELVDD_COM may be a square shape that lasts for one horizontal period. The amplitude of the high potential voltage compensation waveform ELVDD_COM may be proportional to the variation width of the high potential voltage ELVDD_AS. The fluctuation range of the high potential voltage ELVDD_AS is proportional to the absolute value of the average pixel difference for each line. Therefore, it is desirable to adjust the amplitude of the high potential voltage compensation waveform (ELVDD_COM) to be proportional to the absolute value of the average pixel difference for each line.

(d) shows the adjusted high potential voltage waveform ELVDD_N corresponding to a value obtained by adding the high potential voltage compensation waveform ELVDD_COM to the existing high potential voltage ELVDD_AS waveform. As shown in (d), it can be seen that the adjusted high potential voltage waveform ELVDD_N has a smaller variation than the conventional high potential voltage waveform ELVDD_AS. In addition, the adjusted high potential voltage waveform ELVDD_N is more gentle than the waveform shown in (d) because the adjusted high potential voltage compensation waveform ELVD_N output from the actual power supply circuit is due to the RC delay of the electronic circuit element. It has a single curved waveform.

9 illustrates a case in which the grayscale value of the input image varies greatly for each frame.

9A illustrates that a black image is displayed in one frame 1F and a white image is displayed in two frames 2F.

(b) shows that the high potential voltage ELVDD_AS varies due to the large variation of the input image data for each frame. Assuming that an image of two frames 2F is displayed at the present time, since the image data in the previous frame 1F displays a black image, the current flowing to the high potential power line at this time is relatively small. Accordingly, the high potential voltage ELVDD_AS supplied by the power supply circuit through the high potential voltage line has a small voltage drop.

On the other hand, when the image of the second frame 2F is displayed, the image data displays a white image. At this time, the current flowing to the high potential power line is relatively large, so the power supply circuit supplies through the high potential voltage line. The high potential voltage ELVDD_AS has a large voltage drop.

As described with reference to FIG. 8 , when the input image data varies greatly, the high potential voltage ELVDD_AS supplied to each pixel through the high potential voltage line in the power supply circuit does not have a constant value but fluctuates greatly. In this case, a difference in luminance of the pixels PX is generated due to a change in the high potential voltage ELVDD_AS, and the difference in luminance for each pixel PX leads to poor image quality of the display device.

(c) shows the high potential voltage compensation waveform ELVDD_COM for reducing the fluctuation range of the conventional high potential voltage ELVDD_AS. The high potential voltage compensation waveform ELVDD_COM may be a square shape that lasts for one horizontal period. The amplitude of the high potential voltage compensation waveform ELVDD_COM may be proportional to the variation width of the high potential voltage ELVDD_AS. The fluctuation range of the high potential voltage ELVDD_AS is proportional to the absolute value of the average pixel difference for each frame. Therefore, it is desirable to adjust the amplitude of the high potential voltage compensation waveform (ELVDD_COM) to be proportional to the absolute value of the average pixel difference for each frame.

(d) shows the adjusted high potential voltage waveform ELVDD_N corresponding to a value obtained by adding the high potential voltage compensation waveform ELVDD_COM to the existing high potential voltage ELVDD_AS waveform. As shown in (d), it can be seen that the adjusted high potential voltage waveform ELVDD_N has a smaller variation than the conventional high potential voltage waveform ELVDD_AS. In addition, the adjusted high potential voltage waveform ELVDD_N is more gentle than the waveform shown in (d) because the adjusted high potential voltage compensation waveform ELVD_N output from the actual power supply circuit is due to the RC delay of the electronic circuit element. It has a single curved waveform.

9 is a case in which a white image is displayed on a previous horizontal line and a black image is displayed on a current horizontal line. Since a white image is displayed and then a black image is displayed, the amount of current supplied by the high potential voltage ELVDD is reduced, and thus the amount of IR-drop due to the resistance component of the high potential power line is reduced. As a result, a voltage rise occurs in the high potential voltage ELVDD. Even in FIG. 9, on the same principle as that described in FIG. 8, the high potential voltage ELVDD fluctuates greatly including the peak, but due to the RC delay of the electronic circuit device, the source output data V_Data (Source2160) is high potential. A phenomenon in which the voltage ELVDD and the level are reversed occurs. Due to the level reversal of V_Data and the high potential voltage ELVDD, VGS of the driving transistor DT forming the pixel has a negative voltage, and the driving current I_DS is close to 0, so that the light emitting device LD does not emit light. won't As a result, it appears in the display device as poor image quality of dark lines.

The inventor of the present specification, having considered the problems discussed so far, compensating for the high potential voltage ELVDD to alleviate the fluctuation of the high potential voltage ELVDD may be a better way to improve the image quality problem. found that there is

10 is a block diagram of a driving circuit according to an embodiment of the present invention.

The driving circuit (D-IC, 100 ) according to an embodiment of the present invention includes an APL calculator 110 , a memory 120 , a determiner 130 , and a compensation signal generator 140 .

The driving circuit D-IC 100 may be configured as an integrated circuit in which at least a portion of a timing controller, a gate driver, and a data driver are integrated, and transmits a driving signal to the display panel 50 . The driving signal transmitted to the display panel 50 is the same as described above with reference to FIG. 1 , and overlapping descriptions will be omitted.

The driving circuit 100 according to an embodiment of the present invention calculates an average pixel value of input image data, and a compensation signal ( PMIC_CONT) is provided to the power supply circuit 40 . The power supply circuit adjusts the high potential voltage ELVDD based on the compensation signal PMIC_CONT and supplies it to the display panel 50 .

The APL calculator 110 calculates an average pixel value (Average Picture Level) of the input image data. The APL calculator 110 may calculate an average pixel value of image data for each horizontal line. The average pixel value of the image data for each horizontal line calculated by the APL calculator 110 is stored in the memory 120 .

Also, the APL calculator 110 may calculate an average pixel value of the image data in units of each frame. The average pixel value of the image data for each frame calculated by the APL calculator 110 is stored in the memory 120 .

The memory 120 stores the average pixel value of the image data for each horizontal line calculated by the APL calculator 110 . The memory 120 may store the average pixel value of the image data for each frame calculated by the APL calculator 110 . The memory 120 may store the average pixel value of the image data by distinguishing it for each horizontal line. In addition, the memory 120 may average the average pixel value of the image data for one frame, and store the averaged values for each frame. The memory 120 may store the reference value TH used for determination by the determination unit 130 .

The reference value TH may be stored in the memory 120 by simulating high potential voltage (ELVDD) compensation information supplied to the display panel by calculating the APL of the input image in units of horizontal lines. The reference value TH may vary according to characteristics of the display panel 50 . The reference value TH may be determined by simulating the amount of variation in the high potential voltage ELVDD according to the APL change when designing the display device.

The determiner 130 may calculate the average pixel difference APL_DIFF_L for each line, which is a value obtained by subtracting the average pixel value APL_P of the previous horizontal line image data from the average pixel value APL_N of the current horizontal line image data. The average pixel value APL_N of the current horizontal line image data and the average pixel value APL_P of the previous horizontal line image data may use values stored in the memory 120 .

Also, the determination unit 130 determines whether the absolute value of the average pixel difference APL_DIFF_L for each line exceeds a preset reference value TH, and determines whether to compensate the high potential voltage ELVDD. (V_CONT) is created. As a result of the determination, when the absolute value of the average pixel difference APL_DIFF_L for each line exceeds the preset reference value TH, the compensation determination signal V_CONT may have a value of 1. As a result of the determination, when the absolute value of the average pixel difference APL_DIFF_L for each line is less than or equal to the preset reference value TH, the compensation determination signal V_CONT may have a value of zero. The average pixel difference APL_DIFF_L and the compensation determination signal V_CONT for each line generated by the determination unit 130 are transmitted to the compensation signal generation unit 140 .

Also, the determination unit 130 calculates an average pixel difference for each frame (APL_DIFF_F), which is a value obtained by subtracting the average pixel value of the previous frame image data from the average pixel value of the current frame image data, and the absolute value of the average pixel difference for each frame (APL_DIFF_F) It is possible to generate a compensation determination signal V_CONT for determining whether to compensate the high potential voltage ELVDD by determining whether the value exceeds a preset reference value.

The compensation signal generator 140 generates a compensation signal PMIC_CONT based on the compensation determination signal V_CONT and the value of the average pixel difference APL_DIFF_L for each line, and outputs the generated compensation signal PMIC_CONT to the power supply circuit 40 . The compensation signal generator 140 generates the compensation signal PMIC_CONT when the compensation determination signal V_CONT received from the determination unit 130 has a value of 1. When the compensation determination signal V_CONT has a value of 0, the compensation signal PMIC_CONT is not generated.

The compensation signal generator 140 generates a compensation signal PMIC_CONT for adjusting the high potential voltage ELVDD in a positive direction when the average pixel difference APL_DIFF_L for each line has a negative value. In addition, when the average pixel difference APL_DIFF_L for each line has a positive value, the compensation signal generator 140 generates a compensation signal PMIC_CONT for adjusting the high potential voltage ELVDD in a negative direction. Also, the compensation signal generator 140 determines the magnitude of the adjustment value of the high potential voltage ELVDD in proportion to the absolute value of the average pixel difference APL_DIFF_L for each line. That is, the greater the absolute value of the average pixel difference APL_DIFF_L for each line, the greater the degree of adjustment of the high potential voltage ELVDD. The compensation signal generator 140 may generate the compensation signal PMIC_CONT in units of one horizontal line.

The power supply circuit 40 adjusts the high potential voltage ELVDD based on the compensation signal PMIC_CONT and supplies it to the display panel 50 .

11 is a flowchart illustrating a high potential voltage (ELVDD) compensation method according to an embodiment of the present invention.

According to an embodiment of the present invention, a method of driving a display device including a power supply circuit for supplying a high potential voltage (ELVDD) includes calculating an average pixel value of image data ( S111 ), and calculating an average pixel difference. Step S112, determining whether the absolute value of the average pixel difference exceeds a preset reference value (S113), and providing a compensation signal PMIC_CONT for compensating the high potential voltage ELVDD to the power supply circuit (S114).

In the calculating of the average pixel value ( S111 ), the APL calculator 110 may calculate the average pixel value of the image data for each horizontal line. Also, in the step of calculating the average pixel value ( S111 ), the APL calculator 110 may calculate the average pixel value of the image data in units of one frame.

In the step of calculating the average pixel difference ( S112 ), the average pixel difference for each line is a value obtained by subtracting the average pixel value APL_P of the previous horizontal line image data from the average pixel value APL_N of the current horizontal line image data by the determination unit 130 . (APL_DIFF_L) is calculated. Also, the determiner 130 may calculate the average pixel difference APL_DIFF_F for each frame, which is a value obtained by subtracting the average pixel value of the previous frame image data from the average pixel value of the current frame image data.

In the step S113 of determining whether the absolute value of the average pixel difference exceeds the preset reference value, the determination unit 130 determines whether the absolute value of the average pixel difference APL_DIFF_L for each line exceeds the preset reference value TH. It is a step of generating a compensation determination signal V_CONT for determining whether to compensate the high potential voltage ELVDD by determining whether or not to compensate the high potential voltage ELVDD.

In the step of providing the compensation signal PMIC_CONT for compensating the high potential voltage ELVDD to the power supply circuit ( S114 ), the compensation signal generator 140 generates the compensation determination signal V_CONT and the average pixel difference APL_DIFF_L for each line. This is a step of generating a compensation signal PMIC_CONT based on the value and outputting it to the power supply circuit 40 .

12 is a diagram illustrating a waveform output by compensating the high potential voltage ELVDD in units of frames according to an embodiment of the present invention.

12 illustrates a waveform in which the high potential voltage ELVDD is increased in one frame. The average pixel difference APL_DIFF_F for each frame, which is a value obtained by subtracting the average pixel value of one-frame image data from the average pixel value of the two-frame image data, may be greater than the reference value. Since a waveform in which the high potential voltage ELVDD is increased is shown, the average pixel difference APL_DIFF_F for each frame may have a positive value. The driving circuit 100 generates a compensation signal PMIC_CONT by determining an adjustment value of the high potential voltage ELVDD in proportion to the absolute value of the average pixel difference APL_DIFF_F for each frame. The compensation signal PMIC_CONT may be generated in units of one frame. The compensation signal PMIC_CONT includes ELVDD control data for controlling the high potential voltage ELVDD, and the compensation signal PMIC_CONT may be included in a PMIC_Data packet input to the power supply circuit.

13 is a diagram illustrating a waveform output by compensating the high potential voltage ELVDD in units of horizontal lines according to an embodiment of the present invention.

13 illustrates a waveform in which the high potential voltage ELVDD varies in 5 frames. In FIG. 13 , unlike FIG. 12 , compensation of the high potential voltage ELVDD is performed for each horizontal line. Since waveforms in which the high potential voltage ELVDD is increased in the first line and the second line are illustrated, the average pixel difference APL_DIFF_L for each line may have a positive value. The driving circuit 100 generates a compensation signal PMIC_CONT by determining an adjustment value of the high potential voltage ELVDD in proportion to the absolute value of the average pixel difference APL_DIFF_L for each line. The compensation signal PMIC_CONT may be generated in units of one horizontal line. The compensation signal PMIC_CONT includes ELVDD control data for controlling the high potential voltage ELVDD, and the compensation signal PMIC_CONT may be included in a PMIC_Data packet input to the power supply circuit.

It should be understood that the embodiments described above are illustrative in all respects and not restrictive. The scope of the present invention is indicated by the following claims rather than the above detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the claims of the present invention. .

10: timing control
20: gate driver
30: data driving unit
40: power supply
50: display panel

Claims (17)

a display panel including a plurality of pixels;
a driving circuit that transmits a driving signal to the display panel; and
a power supply circuit supplying a high potential voltage (ELVDD) to the display panel; including,
The driving circuit calculates an average pixel value of input image data and provides a compensation signal PMIC_CONT for compensating the high potential voltage ELVDD according to the calculated average pixel value to the power supply circuit and,
The power supply circuit adjusts the high potential voltage (ELVDD) based on the compensation signal and supplies it to the display panel.
display device.
According to claim 1,
The driving circuit is
and an APL calculator for calculating the average pixel value;
The APL calculator calculates an average pixel value of image data for each horizontal line,
display device.
3. The method of claim 2,
The driving circuit is
calculating the average pixel difference (APL_DIFF_L) for each line, which is a value obtained by subtracting the average pixel value of the previous horizontal line image data from the average pixel value of the current horizontal line image data,
a determination unit that determines whether an absolute value of the average pixel difference APL_DIFF_L for each line exceeds a preset reference value and generates a compensation determination signal V_CONT to determine whether to compensate the high potential voltage ELVDD; containing,
display device.
4. The method of claim 3,
The driving circuit is
a compensation signal generator for generating the compensation signal PMIC_CONT based on the value of the compensation determination signal V_CONT and the average pixel difference APL_DIFF_L for each line and outputting the compensation signal PMIC_CONT to the power supply circuit; further comprising,
display device.
5. The method of claim 4,
The compensation signal generator,
When the average pixel difference APL_DIFF_L for each line has a negative value, the high potential voltage ELVDD is adjusted in a positive direction;
When the average pixel difference APL_DIFF_L for each line has a positive value, the high potential voltage ELVDD is adjusted in a negative direction,
display device.
5. The method of claim 4,
The compensation signal generator,
characterized in that the magnitude of the adjustment value of the high potential voltage (ELVDD) is determined in proportion to the absolute value of the average pixel difference (APL_DIFF_L) for each line,
display device.
5. The method of claim 4,
The driving circuit is
characterized in that the compensation signal (PMIC_CONT) is generated in units of one horizontal line,
display device.
According to claim 1,
The driving circuit is
and an APL calculator for calculating the average pixel value;
The APL calculator calculates the average pixel value of the image data in units of each frame,
display device.
9. The method of claim 8,
The driving circuit is
calculating the average pixel difference (APL_DIFF_F) for each frame, which is a value obtained by subtracting the average pixel value of the previous frame image data from the average pixel value of the current frame image data,
a determination unit that determines whether an absolute value of the average pixel difference APL_DIFF_F for each frame exceeds a preset reference value and generates a compensation determination signal V_CONT to determine whether to compensate the high potential voltage ELVDD; containing,
display device.
10. The method of claim 9,
The driving circuit is
characterized in that the compensation signal (PMIC_CONT) is generated in units of one frame,
display device.
A method of driving a display device including a power supply circuit for supplying a high potential voltage (ELVDD), the method comprising:
calculating an average pixel value of the image data;
calculating an average pixel difference;
determining whether the absolute value of the average pixel difference exceeds a preset reference value;
providing a compensation signal (PMIC_CONT) for compensating for the high potential voltage (ELVDD) to the power supply circuit;
A method of driving a display device.
12. The method of claim 11,
Calculating the average pixel value includes:
Characterized in calculating the average pixel value of the image data for each horizontal line,
A method of driving a display device.
13. The method of claim 12,
The step of calculating the average pixel difference is
Computing the average pixel difference (APL_DIFF_L) for each line, which is a value obtained by subtracting the average pixel value of the previous horizontal line image data from the average pixel value of the current horizontal line image data,
A method of driving a display device.
14. The method of claim 13,
The compensation signal PMIC_CONT is
When the average pixel difference APL_DIFF_L for each line has a negative value, the high potential voltage ELVDD is adjusted in a positive direction;
When the average pixel difference APL_DIFF_L for each line has a positive value, the high potential voltage ELVDD is adjusted in a negative direction,
A method of driving a display device.
15. The method of claim 14,
The compensation signal PMIC_CONT is
characterized in that the magnitude of the adjustment value of the high potential voltage (ELVDD) is determined in proportion to the absolute value of the average pixel difference (APL_DIFF_L) for each line,
A method of driving a display device.
12. The method of claim 11,
Calculating the average pixel value includes:
characterized in that the average pixel value of the image data is calculated in units of each frame,
A method of driving a display device.
17. The method of claim 16,
The step of calculating the average pixel difference is
Computing the average pixel difference (APL_DIFF_F) for each frame, which is a value obtained by subtracting the average pixel value of the previous frame image data from the average pixel value of the current frame image data,
A method of driving a display device.

Images