KR20210084210A - Read out circuit and image sensor including the same - Google Patents

Abstract

The present invention provides a readout circuit including a capacitor array, which includes: an analog amplifier to which signals output from n (two or more) number of TDI stages are applied to an input terminal; and first to n^th feedback capacitors connected between the input terminal and an output terminal of the analog amplifier, disposed in parallel with each other, and corresponding to the n number of TDI stages.

Description

Read out circuit and image sensor including the same

The present invention relates to a readout circuit and an image sensor including the same.

In the method of implementing the image sensor, in terms of power efficiency and integration due to compatibility of pixel and readout circuit, a lot of conversion from CCD image sensor to CMOS image sensor is being made recently. However, the CMOS image sensor has a disadvantage in that it is structurally difficult to integrate many signals, and thus has a lower SNR (Singl to Noise Ratio) characteristic compared to the CCD image sensor. In order to overcome this disadvantage, the CMOS image sensor can increase the SNR by overlappingly integrating signals having the same position information by using the TDI (Time Delayed Integration) method.

A representative method for implementing DI is an analog method that continuously stacks up analog signals using an analog amplifier to increase the SNR of the final signal, and converts the stacked analog signal into a digital code and synthesizes the converted digital code several times. There are digital methods that increase the SNR of the final signal.

A basic example of an analog TDI scheme is shown in FIG. 1( a ). In the case of the analog method, the analog signal is continuously integrated with the analog amplifier, and the finally integrated TDI analog signal is transferred to the ADC (Analog to Digital Converter) to convert it into a digital code. The operation of repeatedly integrating the signal is determined by the characteristics of the analog system without the need to convert the domain of the signal into another form (eg, analog to digital), so it is faster than other systems that require additional blocks. integration is possible

In order to implement the analog TDI method as an actual system, it is necessary to have the position information of each pixel in each TDI signal individually. Another analog amplifier stage must capture and maintain positional information. And, in terms of integrating the signal, since the signal received at the previous position must be continuously transmitted, it must be serially connected in a pipeline-like configuration in the previous analog amplifier stage. Analog amplifier stages configured in series and parallel in this way must exist as many as the number of TDI stages of the TDI system in order to store pixel position information.

As the TDI stage increases and the integral amount of the signal increases, the SNR of the signal further increases, so that the effect of noise on the image output from the image sensor is reduced and excellent quality can be obtained. However, in the conventional structure, as the TDI stage is increased to increase the SNR, the analog amplifier stage including the analog amplifier and the input and feedback capacitors also increases. In this case, it is necessary to allocate a lot of layout area for configuring the analog amplifier stage, and also consumes a lot of power to drive the analog amplifier increased by the number of TDI stages.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for solving the problem that the size of an area for constituting an analog amplifier stage used in the analog TDI method is increased according to the TDI stage, and the size of the area is increased and power consumption increases.

The present invention provides an analog amplifier to which signals output from n (2 or more) TDI stages are applied to an input terminal; There is provided a readout circuit including a capacitor array connected between the input terminal and the output terminal of the analog amplifier and arranged in parallel with each other and including first to nth feedback capacitors corresponding to the n TDI stages.

Here, the n TDI stages may include the n rows and a plurality of pixels connected to each of the n rows.

An input capacitor and a gain boost capacitor are interposed between the n TDI stages and the input terminal of the analog amplifier and arranged in parallel with each other.

A timing controller for controlling a cycle of the feedback order of the first to nth feedback capacitors may be further included.

The capacitor array may include a capacitor switch connected between each of the first to nth feedback capacitors and the analog amplifier.

The timing controller may cycle the feedback order of the output signal of the analog amplifier for each TDI operation period with respect to the first to nth feedback capacitors.

The readout circuit of the present invention uses one input capacitor block, one analog amplifier, one feedback capacitor array for TDI operation, and one analog amplifier stage including a timing controller for analog TDI operation for multiple TDI stages. , compared to the conventional analog TDI method using a plurality of analog amplifier stages, it is possible to significantly reduce the circuit size.

Unlike the conventional structure using multiple analog amplifier stages, by using a method in which one analog amplifier is shared by multiple TDI stages, when the TDI stage is increased to obtain a high-quality image due to an increase in SNR, the analog amplifier The area of the semiconductor wafer required for integration can be significantly reduced, and the number of analog amplifiers can be significantly reduced, so that the size of the operating power is also greatly reduced, thereby increasing the possibility of developing a low-power system. In addition, since low-power driving is possible, there is no need to consider the restriction that the analog amplifier characteristics are reduced due to heat generation, so there is an advantage in that it can be developed without putting much weight on the design of the heat dissipation system to eliminate the characteristic reduction due to heat generation.

Since a relatively small layout area is required to build the same analog TDI system compared to the conventional structure, significant advantages can be obtained in terms of product production and yield, and thus the production cost can be greatly reduced. In addition, since the power consumption of the analog amplifier can be designed to be considerably low, it can be grafted into a low-power system, thereby gaining wide marketability. It can have the effect of lowering the unit cost.

1 is a diagram of a conventional analog TDI scheme.
2 is a schematic diagram schematically illustrating the principle of an analog TDI method of an image sensor according to an embodiment of the present invention.
Fig. 3 is a circuit diagram showing the structure of a readout circuit according to the present embodiment;
4 is a diagram illustrating an example of an operation sequence of a capacitor of a feedback capacitor array according to an embodiment of the present invention;
5 is a diagram schematically illustrating a line scan system operating in a TDI scheme according to an embodiment of the present invention.
6 is a diagram illustrating the configuration and operation of a circuit for performing a basic analog TDI scheme including two rows of pixels and two feedback capacitors according to an embodiment of the present invention.
7 is a view for explaining a structure of a timing controller according to an embodiment of the present invention and an operation of a readout circuit through the structure;
8 is a timing diagram for signals of an output terminal of the analog amplifier of FIG. 7, an output terminal of a pixel, and an output terminal of each feedback capacitor;

Hereinafter, embodiments of the present invention will be described in detail.

2 is a schematic diagram schematically illustrating the principle of an analog TDI method of an image sensor according to an embodiment of the present invention.

Referring to FIG. 2 , an image sensor according to an embodiment of the present invention includes a sensor panel in which a plurality of pixels are arranged in a matrix form, and a readout for reading out an analog signal (or a sensing signal) sensed by the pixels. circuit may be included.

The readout circuit of this embodiment is an analog TDI circuit, and compared with the conventional TDI circuit.

In the conventional TDI method shown in FIG. 1, analog amplifier stages are provided as many as the number of TDI stages and are configured to be connected in series in a pipeline structure.

On the other hand, in the TDI method of the present embodiment, one analog amplifier stage is used for a plurality of TDI stages, and the analog amplifier stage may be composed of one analog amplifier and a plurality of feedback capacitors equal to the number of the plurality of TDI stages. For this reason, as the TDI stage increases, the proportion that the analog amplifier occupies in the overall size of the readout circuit gradually decreases.

In general, the TDI system acquires a high-quality image by increasing the SNR by obtaining the same effect as integrating a larger amount of signals for a long time as the TDI stage increases. The greater the number, the better the effect can be obtained, and it is suitable for use in a very fast high-speed imaging system or an X-ray detector with a very low dose.

In the conventional structure, as the number of analog amplifier stages increases in order to obtain the advantages of the TDI circuit system, the analog amplifier has a high proportion, causing a problem in that the production cost of the product increases, which causes a lot of burden in development.

On the other hand, in the case of the TDI circuit of the present embodiment, the proportion of use of the analog amplifier in configuring the analog amplifier stage is substantially minimized, so that the development burden according to the cost can be greatly reduced.

3 is a circuit diagram showing the structure of a readout circuit according to the present embodiment.

Referring to FIG. 3 , the input capacitor block 10 is connected to the pixel output terminal PIXEL_OUT, which may include an input capacitor C_IN and a gain boost capacitor C_GAIN_BOOST connected in parallel to each other. Here, the input capacitor C_IN may function to receive an analog signal (or a sensing signal) that is basically sensed and output from the pixel. The gain boost capacitor C_GAIN_BOOST may amplify the analog signal of the pixel according to a capacity ratio of the gain boost capacitor C_GAIN_BOOST and the selected feedback capacitor to input the amplified analog signal to the analog amplifier AMP.

Here, in the conventional case, the input capacitor block should be configured for each analog amplifier stage like the analog amplifier. In this embodiment, the area occupied by the input capacitor block can also be reduced.

A feedback capacitor array block 20 implementing the TDI method of the present embodiment may be connected between an input terminal (eg, an inverting (-) input terminal) and an output terminal of the analog amplifier AMP.

The feedback capacitor array block may be configured by connecting a plurality of feedback capacitors CAP1 to CAP3 in parallel to perform a function of storing an analog signal including position information of individual pixels. Also, for the feedback capacitors CAP1 to CAP3, the capacitor switches SW_C1 to SW_C3 may be configured together as a connection switch of a series configuration for individual driving of each capacitor. In contrast, each capacitor switch may control the electrical connection between the corresponding feedback capacitor and the analog amplifier connected thereto.

A structure such as such a feedback capacitor array block will represent a structure in which a plurality of conventional analog amplifier stages are connected.

Meanwhile, the readout circuit may include a timing controller for controlling the analog TDI operation of the analog amplifier stage. In contrast, the timing controller outputs a control signal for normally performing the analog TDI operation in synchronization with the applied main clock MAIN_CLK to control the operation of switches provided in the analog amplifier stage including the feedback capacitor array. have.

In this embodiment, since a feedback capacitor array replacing the role of the conventional multiple analog amplifier stages is used, multiple analog amplifier stages are not required.

The analog amplifier stage of this embodiment may include an input capacitor block, a feedback capacitor array, an analog amplifier (AMP), and a timing controller, so that an analog TDI method can be implemented using one analog amplifier (AMP). Accordingly, since the number of analog amplifier stages is not increased to correspond to the number of analog TDI stages as in the prior art, an analog TDI system having a plurality of TDI stages to obtain a high-quality image with a smaller semiconductor wafer area and high SNR can be implemented.

The order in which the readout circuit of this embodiment operates is as follows.

(1) First, when the analog amplifier AMP performs a reset operation, one electrode of the pixel side of the input capacitor C_IN is the voltage of the output signal of the pixel, and the other electrode of the input capacitor C_IN is the analog amplifier AMP ) may be reset to the level of the reference voltage V_REF applied to the input terminal (eg, a non-inverting (+) input terminal). At this time, in the feedback capacitor array, the potential at the input terminal side of the analog amplifier (AMP) of the feedback capacitor that starts the current TDI operation is the level of the reference voltage (V_REF) of the analog amplifier (AMP), and the potential at the output terminal side of the analog amplifier (AMP) is the capacitor reset An initial value may be set to the level of the voltage V_RESET_CAP. Here, with respect to not setting the output terminal side of the feedback capacitor to the reset level of the analog amplifier AMP, the reset level set as the reference voltage V_REF may have offset and gain depending on the characteristics of the analog amplifier AMP. As the analog TDI is configured as a column, the initial value changes for each column, so it is set to the potential of the capacitor reset voltage (V_RESET_CAP), which is a constant value.

(2) After the reset operation is completed, an analog signal is inputted from the pixel. The magnitude of the input signal depends on the ratio of the total size (ie, capacitance) of the input capacitor block composed of the input capacitor (C_IN) and the gain boost capacitor (C_GAIN_BOOST) to the size of the capacitor (ie, capacitance) formed in the feedback capacitor array. can be decided.

(3) After the analog signal is applied and integrated in the feedback capacitor, the signal is stored in the integrated feedback capacitor under the control of the timing controller, the feedback capacitor for the next TDI is selected and connected, and the reset process performed previously is repeated. Repeat. Here, the analog signal stored in the previously selected feedback capacitor is not reset together even if the currently selected feedback capacitor is in the reset process. Therefore, the previously stored pixel information of other locations is kept in the previous TDI stage. In this way, the total number of TDI stages is repeated.

(4) When the TDI stage operates in the above method, it returns to the feedback capacitor that was initially reset and finally transfers the accumulated analog signal to the ADC (Analog to Digital Converter) to convert the final analog signal into a digital signal. . Then, repeat the operation of (1) above.

4 is a diagram illustrating an example of an operation sequence of a capacitor of a feedback capacitor array according to an embodiment of the present invention.

In FIG. 4 , a case in which the TDI operation is performed is exemplified when the first to sixteenth feedback capacitors CAP1 to CAP16 are used as 16 feedback capacitors. Here, there are 16 TDI stages, and 16 pixel rows (rows 1 to 16) of the sensor panel are configured. And, the order of integration (or signal output order) of the pixel rows does not change. On the other hand, what is changed are the feedback capacitors assigned to each pixel row.

First, the first feedback capacitor CAP1 may be reset and set to an initial value. Thereafter, the signal of row 1 is stored in the first feedback capacitor CAP1. After that, the signal of row 2 is sequentially applied to the second feedback capacitor CAP2 and the signal of row 3 is applied to the third feedback capacitor CAP3 in this order, and as such, the signal of row 16 is transferred to the 16th feedback capacitor CAP16 ) is stored in At this time, since the 16th feedback capacitor CAP16 already contains all of the 16th TDI signal, the finally accumulated signal is transferred to the ADC. After the ADC samples the analog TDI signal accumulated in the 16th feedback capacitor CAP16, the TDI operation may be continuously performed while the signal is converted. Since the signal for the last TDI operation with respect to the 16th feedback capacitor CAP16 is transmitted to the ADC, the 16th feedback capacitor CAP16 is reset and may operate as the first TDI capacitor in the next TDI phase.

Looking at the next TDI phase, it can be seen that the position of the 16th feedback capacitor CAP16 is raised to the top (that is, in the first order) to store the signal of row 1. And, since the position (ie, order) of the first feedback capacitor CAP1, which was on the top, stores the signal of row 2 in the next TDI phase, it can be seen that it is located in the order one space down from the first position. In the second TDI phase, the signal of row 1 is stored in the 16th feedback capacitor CAP16, and the signal of row 2 is stored in the first feedback capacitor CAP1. Here, the first feedback capacitor CAP1 stores the signal of row 1 in the first TDI phase and the signal of row 2 in this TDI phase. Here, the present embodiment exemplifies the TDI method of the line scan type image sensor system. In the first phase, containing the signal of row 1 and in the next phase, containing the signal of row 2 is the same as integrating the image of the same subject. it means The feedback capacitor on which the 16th TDI integration has been performed this time is the 15th feedback capacitor CAP15. The 15th feedback capacitor CAP15 contains the signal of row 16 in the same manner as in the previous phase, transfers the signal to the ADC, is reset, and rises first in the next TDI phase to contain the signal of row 1. Since the operations of the feedback capacitor are circulated in a predetermined order, this feedback capacitor operation method may be referred to as a revolving capacitor method.

In order to understand the above-described capacitor operation in more detail, reference may be made to FIG. 5 for a line scan system operating in a TDI manner. Referring to FIG. 5 , it can be confirmed whether the first feedback capacitor containing the signal of row 1 described above moves down one space after performing the cycle operation in the next phase to contain the signal of row 2, which contains the signal of the same subject. Fig. 5 is a schematic diagram of TDI operation in the case of operating for four rows.

This line scan system has 4 rows, and in each TDI phase, an image scan object moving at the bottom moves at regular intervals about a pixel pitch.

In order to understand the relationship with the circulating capacitor, it is assumed that 4 cyclic capacitors are used in the system. Looking at phase 2, part A of the object is detected through the row 1 part of the pixel array. At this time, the first feedback capacitor is in a reset state, and the signal (ie, data) of part A of the object input in row 1 is integrated. At this time, the second, third, and fourth feedback capacitors assigned to rows 2, 3, and 4 scan an empty space where there are no objects and integrate meaningless signals. At this time, in the case of the fourth feedback capacitor, since the fourth integration is completed, a signal is transmitted to the ADC. After the meaningless signal of the fourth feedback capacitor is transmitted, the fourth feedback capacitor is reset to contain a new TDI signal. After this process is performed, the timing controller cycles through the sequence of all feedback capacitors once. After the cycle ends, the row and feedback capacitors are assigned (or matched) as Row1-CAP4, Row2-CAP1, Row3-CAP2, Row4-CAP3.

Looking at phase 3, the object corresponding to row 1 is part B, and the object corresponding to row 2 is part A. Here, since the fourth feedback capacitor allocated to row 1 has been reset in the previous phase, the signal of part B newly sensed in row 1 is integrated. The first feedback capacitor currently allocated to row 2 is a state in which the signal of part A is contained once in the previous phase. The object detected in row 2 in this phase is part A. Therefore, once again, the first feedback capacitor allocated to row 2 integrates the signal of part A, which is the same signal as in the previous phase, once again. In the last row 4, the third feedback capacitor is currently allocated and contains a meaningless signal, but since the TDI operation is in the final stage, the signal in the third feedback capacitor is transferred to the ADC, and thereafter, it enters the reset state. And, all the feedback capacitors are cycled by the timing controller and allocated as Row1-CAP3, Row2-CAP4, Row3-CAP1, and Row4-CAP2.

In phase 4, row 1 is sensing part C. Therefore, the third feedback capacitor disposed in row 1 first integrates the signal of part C. Part B sensed in row 2 is integrated into the fourth feedback capacitor, and part A sensed in row 3 is integrated into the first feedback capacitor. Here, in the case of the first feedback capacitor, the signal for part A is contained a total of three times. The second feedback capacitor placed in row 4 sends a signal to the ADC after integration and is then reset. Then, a cycle process occurs for all the feedback capacitors, and they are allocated as Row1-CAP2, Row2-CAP3, Row3-CAP4, and Row4-CAP1.

In phase 5, row 1 is sensing part D. Therefore, the second feedback capacitor disposed in row 1 integrates the signal of the D part. Assuming that the same integration form as in the previous phases continues, the first feedback capacitor integrates part A in row 4. At this time, since the signal of part A is integrated 4 times with respect to the first feedback capacitor, and there are a total of 4 TDI stages, it can be regarded as the time when the TDI stage ends. Then, the signal of part A, which is accumulated 4 times in the first feedback capacitor, is transferred to the ADC and reset can be performed. The transferred signal is displayed in phase 6, and after a conversion time, the final converted digital signal in phase 7 may be output.

As described above, with the cyclic capacitor method by the timing controller, the same object part can be continuously stacked as the TDI capacitor responsible for pixel row is changed each time, so that the analog TDI method can be performed normally even without multiple analog amplifier stages. have.

For a more intuitive understanding of the above TDI method, reference may be made to FIG. 6, which shows the circuit configuration and operation form for performing a basic analog TDI method including two rows of pixels and two feedback capacitors. is showing Referring to FIG. 6 , a TDI operation is performed on pixels Pixel 1 and 2 respectively arranged in two rows in one column. In the corresponding operation, it can be seen that the second capacitor CAP2, in which a specific signal is already accumulated, finally contains the signal of row 2 and finally transmits the signal to the ADC. Since the corresponding operations are continuously repeated, the TDI operation can be effectively performed without an additional analog amplifier stage.

7 is a diagram for explaining a structure of a timing controller according to an embodiment of the present invention and an operation of a readout circuit through the structure.

FIG. 7 shows an example of a structure in which four pixels PIX1 to PIX4 and four feedback capacitors CAP1 to CAP4 can perform four TDI cycle operations. Looking at the structure of the timing controller, it may include a TDI counter, a capacitor selector, and a pixel selector, and each of these components may be configured as, for example, a 4-bit ring counter structure.

In this embodiment, assuming that the TDI cycle is 4 times, in relation to the operation of the TDI counter having a 4-bit ring counter structure, the capacitor selector, and the pixel selector, the pixel selector is a pixel connected to the output terminals of the pixels PIX1 to PIX4. The switches SW_P1 to SW_P4 are controlled, the capacitor selector controls the capacitor switches SW_C1 to SW_C4 connected to the feedback capacitors CAP1 to CAP4, and the TDI counter delays the operation of the pixel selector and the capacitor selector. ) gap can be generated so that cyclic capacitor operation can be performed. The cyclic capacitor operation may be implemented by generating a delay by one clock every last cycle of the TDI operation.

An operation according to the timing diagram of FIG. 7 will be described as follows.

(1) First, by resetting the TDI counter, the capacitor selector, and the pixel selector, which are ring counters of the timing controller, their output positions can be fixed to the first output stage. In this case, the feedback capacitors CAP1 to CAP4 may be initialized by applying a reset signal to the switches of the TDI capacitor array.

(2) Then, by applying the corresponding clock to each of the TDI counter, capacitor selector, and pixel selector of the timing controller and raising the clock step by step, each TDI cycle is increased. As the corresponding operation is performed, the ring counter values of the TDI counter, capacitor selector, and pixel selector increase simultaneously. As the ring counter value increases, the value of the selected pixel (i.e., number or position) and the value of the feedback capacitor ( That is, number or position) may increase together. This operation may operate until the positions of the pixel and the feedback capacitor are selected as PIX4 and CAP4 by the ring counters of the timing controller.

(3) In a state in which PIX4 and CAP4 are selected by the ring counters of the timing controller, the TDI operation can be regarded as the fourth performed, and the cyclic capacitor operation can be performed. In order to perform the cyclic capacitor operation, the feedback capacitor and the ring operation (ie, the cyclic operation) of the pixel may be delayed by 1 clock. Such a delay difference may be implemented through a TDI counter as shown in FIG. 7 and a logic combination, for example, an inverter and an AND gate combination. In this regard, referring to the timing diagram, the input clock signal PIX CLK IN to the pixel selector receives another clock after PIX4 is selected, and the order is changed to PIX1. Meanwhile, the input clock signal CAP CLK IN to the capacitor selector is not input because the clock is blocked from being input to the capacitor selector at the moment the clock is applied to the PIX CLK IN. As a result, the output of the capacitor selector (TDI CAP RING) COUNTER OUT) continuously selects CAP4. On the other hand, this delay operation may use a circuit having a similar function other than the ring counter.

(4) Through the above operation, the output of the pixel selector (PIX RING COUNTER OUT) causes the pixel selection to change from PIX4 to PIX1, and the output of the capacitor selector (TDI CAP RING COUNTER OUT) causes CAP4 to be continuously selected . However, since this is a stage to start a new TDI operation (i.e., phase) again, the switching signal of the capacitor reset switch (SW_CAP_RESET) is turned on to initialize the signal contained in CAP4 and corresponds to the starting potential for starting the TDI operation. The feedback capacitor is configurable.

As a result, during one cycle of the TDI operation (that is, the application period of the reset switch (SW_CAP_RESET)), the clocks of the ring counters of the timing controller increase together, and through a method of implementing a delay by one clock in the last cycle of the TDI operation period, additional Even without an analog amplifier stage, analog TDI operation may be possible.

For digital logic such as a timing controller used for the TDI method of this embodiment, it is relatively very small compared to the large size of the analog amplifier for maintaining the high performance of the readout circuit system, that is, high speed and low noise, In implementing the out-circuit system, there is an advantage in terms of reducing the size of the system that was originally intended to be obtained. In addition, since the need for standby current consumption of the analog amplifier to maintain high system performance is also eliminated, very low-power operation is possible compared to the conventional structure, and a more stable system can be maintained without overheating during system operation. driving becomes possible.

In the system of FIG. 7 , a case in which the timing controller generates and outputs all of the switching signals for controlling the switches for selecting the pixel and the feedback capacitor is illustrated as an example. Meanwhile, it is not necessary for the timing controller to generate both a switching signal for selecting a pixel and a feedback capacitor, and control of the switches for the feedback capacitors may be performed according to the synchronization of the pixel operation through an external sync clock or the like. .

The relationship between the operation of the above-described readout circuit and the signal integrated into the feedback capacitor may be referred to FIG. 8 . FIG. 8 further expands the area of the timing diagram of FIG. 7 to show the signals of the output terminal of the analog amplifier, the output terminal of the pixel, and the output terminal that is the right end of each feedback capacitor. As the cycle of the TDI stage progresses, the signal to the feedback capacitor It shows the correlation with how the is integrated.

In FIG. 8 , it can be seen that constant data is output from a pixel. In addition, it can be confirmed that the analog amplifier is set to the potential level contained in the feedback capacitor whenever the feedback capacitor is connected through feedback.

For CAP Integration, which represents the output stage of each feedback capacitor, the signal is continuously integrated until its own reset order comes after performing the integration.

For example, for CAP1 Integration, when SW_CAP_RESET is initially performed, it can be seen that the potential level accumulated in CAP1 is reset and rises. Thereafter, as the pixel output increases, the signal accumulated in CAP1 through the feedback connection operation of the analog amplifier is integrated once in a falling form. Thereafter, during the cycle in which the other feedback capacitors are performing the integration operation, the output terminal of CAP1 is in a floating state to maintain the potential to have a constant potential. After that, when its own integration sequence returns, the second integration is performed by integrating the signal of the input pixel through the analog amplifier and the feedback connection. In the right end of FIG. 8 , the third integration state is shown in CAP1.

As described above, the readout circuit of this embodiment uses one input capacitor block, one analog amplifier, one feedback capacitor array for TDI operation, and one analog amplifier stage including a timing controller for multiple TDI stages. Since it is possible to perform an analog TDI operation for , it is possible to significantly reduce the circuit size compared to the conventional analog TDI method using a plurality of analog amplifier stages.

Unlike the conventional structure using multiple analog amplifier stages, by using a method in which one analog amplifier is shared by multiple TDI stages, when the TDI stage is increased to obtain a high-quality image due to an increase in SNR, the analog amplifier The area of the semiconductor wafer required for integration can be significantly reduced, and the number of analog amplifiers can be significantly reduced, so that the size of the operating power is also greatly reduced, thereby increasing the possibility of developing a low-power system. In addition, since low-power driving is possible, there is no need to consider the restriction that the analog amplifier characteristics are reduced due to heat generation, so there is an advantage in that it can be developed without putting much weight on the design of the heat dissipation system to eliminate the characteristic reduction due to heat generation.

Since a relatively small layout area is required to build the same analog TDI system compared to the conventional structure, significant advantages can be obtained in terms of product production and yield, and thus the production cost can be greatly reduced. In addition, since the power consumption of the analog amplifier can be designed to be considerably low, it can be grafted into a low-power system, thereby gaining wide marketability. It can have the effect of lowering the unit cost.

The above-described embodiment of the present invention is an example of the present invention, and free modifications are possible within the scope included in the spirit of the present invention. Accordingly, the present invention includes modifications of the present invention provided they come within the scope of the appended claims and their equivalents.

Claims (6)

In the analog TDI type readout circuit,
an analog amplifier to which signals output from n (2 or more) TDI stages are applied to an input terminal;
and a capacitor array connected between the input terminal and the output terminal of the analog amplifier and disposed in parallel with each other and including first to nth feedback capacitors corresponding to the n TDI stages.
readout circuit.
According to claim 1,
and the n TDI stages include the n rows and a plurality of pixels connected to each of the n rows.
According to claim 1,
A readout circuit comprising an input capacitor and a gain boost capacitor interposed between the n TDI stages and an input terminal of the analog amplifier and arranged in parallel with each other.
According to claim 1,
Further comprising a timing controller for controlling the circulation of the feedback order of the first to nth feedback capacitors
readout circuit.
4. The method of claim 3,
wherein the capacitor array includes a capacitor switch connected between each of the first to nth feedback capacitors and the analog amplifier.
5. The method of claim 4,
The timing controller is a readout circuit for circulating a feedback order of an output signal of the analog amplifier for each TDI operation period with respect to the first to nth feedback capacitors.

Images