KR20210083599A - Neuromorphic synapse device having multi-bit characteristic and operation method thereof - Google Patents

Abstract

The present invention relates to a neuromorphic synaptic device with multi-bit characteristics and reliability for neuromorphic system application and an operating method thereof. According to the present invention, a plurality of synaptic units, in which a fixed resistor and a resistance change element (RRAM) are connected in series, are connected in parallel to implement and operate one synapse, so that multi-bit can be expressed, and thus it is possible to implement and operate the synapse with more extended characteristics than a single element synapse, and since it is possible to secure both a reliable operation and multi-bit characteristics of 1-bit devices, the present invention can be used for high-performance and stable artificial neural network hardware.

Description

Neuromorphic synapse device having multi-bit characteristic and operation method thereof

The present invention relates to a synaptic device and an operating method thereof, and more particularly, to a neuromorphic synaptic device having multi-bit characteristics and reliability for neuromorphic system applications and an operating method thereof.

An artificial neural network structure that mimics the human brain consists of synapses and neurons. Neurons perform tasks related to signal processing and transmission, and synapses connect neurons to neurons. Each synapse has a value called a weight and indicates the degree of connection between neurons. The signal may be further amplified or suppressed according to the weight value. That is, the synapse performs a role of processing signals while storing information as weights.

A memory is required to store the weight value stored in the synapse, and for this purpose, traditional memories such as flash memory, SRAM, and DRAM, and new memory such as RRAM, MRAM, and PCM may be used. The artificial neural network, which operates as a computer of the existing von Neumann structure, retrieves the weighted values of synapses stored in the memory, moves them to the central processor, processes the information, and moves the processed data back to the memory for storage. However, due to the structure of the artificial neural network, the number of operations to be processed is very large, whereas the computer of the von Neumann structure processes information one by one, so the time required for the operation is very large.

In order to solve this problem, recently new memory devices such as RRAM, MRAM, and PCM are implemented as a cross-point array to store the weight value of the synapse. The cross-point array consists of a plurality of input terminals and a plurality of output terminals, and a memory is located at the intersection of each input terminal and output terminal. The advantage of a cross-point array is that parallel operation is possible when multiple inputs are given at the same time and output is output at the same time. In addition, the memory area is small and the required power consumption is very low, so it is a suitable memory for an artificial neural network structure.

An ideal synapse that requires an artificial neural network should show analog weight changes and weight changes should be linear. Also, there is no upper and lower limit for the weight value. In order to realize such an ideal synaptic device, it must have a high multi-level characteristic that can store many levels for analog weight change.

Since the synaptic device can more accurately represent a weight as the number of states that can be expressed increases, it is desirable to implement a high multi-bit characteristic. However, implementing multi-bit in a single synaptic device is a difficult task. In addition, since synaptic devices showing high multi-bit characteristics still have reliability issues such as retention and variation, it is still difficult to use them as artificial neural network hardware.

On the other hand, synaptic devices exhibiting 1-bit characteristics have fewer reliability problems than multi-bit devices. However, since only two states can be expressed in one device, the performance is much lower than when using a multi-bit synaptic device in an artificial neural network of the same size.

Accordingly, there is a need for a new approach that can replace these conventional problems.

1. Republic of Korea Patent Publication No. 10-2005-0016700 2. Japanese Patent No. 5420067 3. Japanese Patent No. 2539177

A first object of the present invention for overcoming the problems according to the prior art is to provide a neuromorphic synaptic device with high reliability while implementing multi-bit characteristics.

In addition, a second object of the present invention is to provide a method of operating the neuromorphic synaptic device.

In order to achieve the first object, the present invention includes a synaptic unit in which a fixed resistor and a resistance change element (RRAM) are connected in series, a plurality of synaptic units are connected in parallel, and one end of the synaptic unit is write and read voltage It provides a neuromorphic synaptic device that is connected to a node that generates .

Also preferably, in the plurality of synaptic units, the fixed resistors may each have different resistance values.

Also preferably, in the plurality of synaptic units, the fixed resistor adjusts the resistance value so that the conductance value of the ON state of the nth synaptic unit is 2 ^(n-1) G _{0 , so that n synaptic units} In the case of a synaptic unit connected in parallel, n multi-bit states can be expressed.

Also preferably, the neuromorphic synaptic device may select a synaptic unit in a state in which the resistance state of the resistance change device is ON by adjusting the applied read voltage.

In order to achieve the second object, the present invention includes (a) a synaptic unit in which a fixed resistor and a resistance change element (RRAM) are connected in series, a plurality of synaptic units are connected in parallel, and one end of the synaptic unit is write and providing a neuromorphic synaptic device connected to a node generating a read voltage; (b) a writing step of applying a write pulse to the synaptic unit of the neuromorphic synaptic element to change the resistance state of the resistance change element of the synaptic unit selected from among the parallel-connected synaptic units to ON; and (c) applying a read voltage to the synaptic unit of the neuromorphic synaptic element, and reading the sum of the conductance of the selected synaptic unit as a signal. It provides a method of operating a neuromorphic synaptic element.

Also preferably, in the step of providing the neuromorphic synaptic element of (a), in the plurality of synaptic units, the fixed resistor has an ON state conductance value of 2 ^{(n) in the nth synaptic unit -1)} By adjusting the resistance value to become G ₀ , in the case of a synaptic unit in which n synaptic units are connected in parallel, n multi-bit states can be expressed.

Also preferably, in the writing step of (b), an alternating pulse scheme in which a write pulse and an erase pulse are alternately applied may be used.

Also preferably, in the reading step of (c), in order to widen a window between threshold voltages in units of synapses, the voltage application time may be adjusted for each synaptic unit.

According to the present invention, a plurality of synaptic units in which a fixed resistor and a resistance change element (RRAM) are connected in series are connected in parallel to implement and operate one synapse, so that multi-bit can be expressed with a simple configuration. , it is possible to implement and operate a synapse with more extended characteristics than a single device synapse while reducing the thickness and area of the device.

In addition, conventional synaptic devices exhibiting multi-bit characteristics cause reliability problems such as retention, durability, and variation, but a synaptic bundle structure in which a plurality of synaptic units according to the present invention are connected in parallel Since a synaptic device with , can secure both the reliable operation and multi-bit characteristics of a 1-bit device, it can be used for high-performance and stable artificial neural network hardware.

1 is a circuit diagram illustrating a synaptic unit in which a fixed resistor and a resistance change element (RRAM) are connected in series in a synaptic device according to an embodiment of the present invention.
Figure 2 is a synaptic device according to an embodiment of the present invention, the fixed resistor in the case of serially connected to the synaptic unit and when not connected to the current - a graph showing the voltage (IV) operating characteristics.
3 is a circuit diagram of a synaptic device having a synaptic bundle structure in which synaptic units including fixed resistors of different sizes are connected in parallel in a synaptic device according to an embodiment of the present invention.
Figure 4 shows the IV operation characteristics seen when a voltage is applied to the synaptic device according to an embodiment of the present invention.
Figure 5 shows a write pulse (write pulse) for writing an accurate conductance value to the synaptic device according to an embodiment of the present invention.
6 shows an alternating pulse method for writing an accurate conductance value to a synaptic device according to an embodiment of the present invention.
7 shows an example of a process of writing an accurate conductance value to a synaptic device according to an embodiment of the present invention.
8 shows a method of maximally securing a window by controlling a voltage sweep speed in a synaptic device according to an embodiment of the present invention.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

While the present invention is susceptible to various modifications and variations, specific embodiments thereof are illustrated and shown in the drawings and will be described in detail hereinafter. However, it is not intended to limit the invention to the particular form disclosed, but rather the invention includes all modifications, equivalents and substitutions consistent with the spirit of the invention as defined by the claims.

It will be understood that when an element, such as a layer, region, or substrate, is referred to as being “on” another component, it may be directly on the other element or intervening elements in between. .

Although the terms first, second, etc. may be used to describe various elements, components, regions, layers and/or regions, such elements, components, regions, layers and/or regions are not It will be understood that they should not be limited by these terms.

1. Neuromorphic synaptic device

1 and 3 show a circuit diagram of a synaptic device according to an embodiment of the present invention.

Specifically, FIG. 1 is a circuit diagram illustrating a synaptic unit in which a fixed resistor and a resistance change element (RRAM) are connected in series in a synaptic device according to an embodiment of the present invention, and FIG. 3 is a fixed resistor of different sizes. It is a circuit diagram of a synaptic device having a synaptic bundle structure in which the included synaptic units are connected in parallel.

1, the neuromorphic synaptic device according to the present invention includes a synaptic unit in which a fixed resistor and a resistance change device (RRAM) are connected in series.

Figure 2 is in the synaptic device according to an embodiment of the present invention, the fixed resistor in the case of serially connected to the synaptic unit and when not connected to the current-voltage (I-V) is a graph showing the operating characteristics.

In the synaptic device according to an embodiment of the present invention, as shown in FIG. 1 , when a fixed resistor (fixed resistor) is connected in series to a resistance variable element (RRAM), which is a 1-bit synaptic device, a synaptic unit is formed, as shown in FIG. As shown, the value of the threshold voltage at which the synaptic unit is turned on (turned on) increases compared to when there is no fixed resistor. In addition, since the series-connected fixed resistor limits the current value, the resistance value in units of synapses is determined by the value of the fixed resistor.

Therefore, when the fixed resistors of different sizes are connected in series to the parallel-connected resistance change elements (RRAM), the value of the threshold voltage at which each synaptic unit is turned on will be different, so by adjusting the applied read voltage, the resistance change element It will be possible to select a synaptic unit in a state in which the resistance state of is ON.

Accordingly, the neuromorphic synaptic device according to the present invention includes a plurality of synaptic units in which a fixed resistor and a resistance change device (RRAM) are connected in series, as shown in FIG. 3 , and the synaptic units are connected in parallel to form one synapse. It is characterized in that it forms a synaptic unit having a bundle structure. In this case, in the plurality of synaptic units, each of the fixed resistors may have different resistance values.

Preferably, in the plurality of synaptic units, the fixed resistor adjusts the resistance value so that the conductance value of the ON state of the nth synaptic unit is 2 ^(n-1) G ₀ , so that n synaptic units are In the case of a synaptic unit connected in parallel, it is possible to implement an n-bit state.

One end of the synaptic unit may be connected to a node generating a write pulse or a read voltage.

Figure 4 shows I-V operation characteristics in each synaptic unit when a voltage is applied to the synaptic device according to an embodiment of the present invention.

As shown in Figure 4, in the synaptic device according to the present invention, in a plurality of synaptic units including a fixed resistor, when the fixed resistors have different resistance values, the value of the threshold voltage at which each synaptic unit is turned on is different Therefore, it is possible to select a synaptic unit in a state in which the resistance state of the resistance change element is ON by adjusting the applied voltage.

2. How neuromorphic synaptic devices work

The method of operating a neuromorphic synaptic device according to the present invention

(a) a fixed resistor and a resistance change element (RRAM) are connected in series, including a synaptic unit in which a plurality of synaptic units are connected in parallel, and one end of the synaptic unit is connected to a node for generating write and read voltages, New providing a lomorphic synaptic device;

(b) a writing step of applying a write pulse to the synaptic unit of the neuromorphic synaptic element to change the resistance state of the resistance change element of the synaptic unit selected from among the parallel-connected synaptic units to ON; and

(c) applying a read voltage to the synaptic unit of the neuromorphic synaptic device, and a reading step indicating the sum of conductance of the selected synaptic unit as a signal.

Hereinafter, each step will be described in detail.

Step (a) is a step of providing a neuromorphic synaptic device, wherein the neuromorphic synaptic device includes a plurality of synaptic units in which a fixed resistor and a resistance change device (RRAM) are connected in series as described above, and the synapse The units are connected in parallel to form a synaptic unit having one synaptic bundle structure. In this case, in the plurality of synaptic units, each of the fixed resistors may have different resistance values.

Preferably, in the plurality of synaptic units, the fixed resistor adjusts the resistance value so that the conductance value of the ON state of the nth synaptic unit is 2 ^(n-1) G ₀ , so that n synaptic units are In the case of a synaptic unit connected in parallel, it is possible to implement an n-bit state.

Step (b) is a writing step of the neuromorphic synaptic device.

Figure 5 shows a write pulse (write pulse) for writing an accurate conductance value to the synaptic device according to an embodiment of the present invention.

In the synaptic device according to the present invention, in a plurality of synaptic units including a fixed resistor, when the fixed resistors have different resistance values, the threshold voltage at which each synaptic unit is turned on is different. It is possible to select a synaptic unit in a state in which the resistance state of the resistance change element is ON by adjusting.

Accordingly, it is possible to selectively turn on and off the synaptic unit by adjusting the magnitude of the applied voltage as shown in FIG. 5 . The applied voltage may turn on the synaptic unit when a write pulse is applied (ON state), and may turn off the synaptic unit when an erase pulse is applied in the opposite direction (OFF state). At this time, when adjusting so that the conductance value of the on state of each synaptic unit is doubled (ex. G ₀ , 2G ₀ , 4G ₀ , …), the n-bit state is set when n synaptic units are used. can be implemented

However, as shown in FIG. 5 , there are cases where an operation of turning on or off only one synaptic unit is impossible with only one write pulse or one erase pulse. Therefore, in order for the synapse to have a desired conductance, it is preferable to use an alternating pulse scheme in which a write pulse and an erase pulse are alternately applied.

For example, as shown in Figure 3, in a synaptic unit in which three synaptic units are connected in parallel, each synaptic unit is called synapse 1, synapse 2, and synapse 3 from the top, synapse 1 _{represents the conductance of G 0} , and synapse 2 If is 2G ₀ conductance and synapse 3 represents 4G ₀ conductance, as shown in FIG. 5 , the write pulse is V _w1 , V _w2 , It has three levels of _{V w3} , the voltage of _{V w1} turns on synapse 3 corresponding to _{4G 0 , the voltage of V w2} turns on synapse 3 and synapse 2 at the same time ( 4G ₀ +2G ₀ ), and the voltage of _{V w3 is} Synapses 3, 2, and 1 are turned on at the same time (4G ₀ +2G ₀ +G ₀ ). Similarly, the erase pulse V _e1, V _{e2, e3} has 3 levels of V, V _e1 is off the synapse 3, V _e2 is off the synaptic synapses 2 and 3 at the same time, V _e3 is at the same time the synaptic 1,2,3 will turn off

In this case, the synaptic unit having three synaptic units of FIG. 3 _{may represent a conductance of 0G 0} to 7G ₀ , and a write pulse (V _w1 , V _w2 , _{1G 0} , by appropriately alternating application of V _w3 ) and erase pulses (V _e1 , V _e2 , V _{e3 )} Detailed conductances of 2G ₀ , 3G ₀ , 4G ₀ , 5G ₀ and 5G ₀ may also be indicated. An alternating pulse method including a write pulse and an erase pulse for expressing each conductance is shown in FIG. 6 .

6 shows an alternating pulse method for writing an accurate conductance value to a synaptic device according to an embodiment of the present invention.

As shown in FIG. 6, in the case of a synaptic unit in which three synaptic units are connected in parallel, write pulses (V _w1 , V _w2 , Of V _w3) and the clearing pulse (of _{V e1, V e2, V e3} ) from the by the application to properly shift ₀ 7G 0 A desired size of conductance can be implemented. Thus, in the case of the synaptic connection unit of n units in parallel, synaptic 2 ⁿ by performing a shift pulse to the n-th phase method more Level conductance can be implemented.

7 shows an example of a process of writing an accurate conductance value to a synaptic device according to an embodiment of the present invention.

Referring to FIG. 7 , for example, to write the conductance corresponding to _{5G 0 in FIG. 6 , the synaptic unit may be turned on to become G 0} +4G ₀ , and for this purpose, in the write pulse shown in FIG. 5 , first V _w3 (4G ₀ If a voltage of +2G ₀ +G ₀ ) is applied and then an erase pulse of _{V e2} (4G ₀ +2G _{0 ) is applied, only the conductance of G 0} remains, and then, a voltage of _{V w1} corresponding to _{4G 0 is applied} It may represent a total conductance of 5G _{0 .}

In addition, to write the conductance corresponding _{to 2G 0} , erase all the existing conductance with the erase pulse of _{V e3 to zero the existing conductance, apply the V w2} write pulse to show _{the conductance of 4G 0} +2G ₀ , and then display the conductance of Ve ₁ (4G By applying an erase pulse of _{0 ), a total conductance of 2G 0} can be implemented.

Step (c) is a reading step of the neuromorphic synaptic device.

The read operation may be performed by applying a read voltage to the synaptic unit of the neuromorphic synaptic device, and representing the sum of conductances of the selected synaptic unit as a signal.

At this time, in order to minimize the influence of the threshold voltage distribution of the device, it is advantageous as the threshold voltage interval of the unit of the synaptic device is wider. In this way, in order to widen the threshold voltage interval (window) of the unit of the synaptic device, a voltage-time dilemma can be used in the present invention.

Figure 8 shows a method for maximally securing a window by controlling the voltage sweep speed in the synaptic device according to an embodiment of the present invention.

As shown in FIG. 8 , a voltage-time dilemma may be used to minimize the influence of the device threshold voltage distribution. Specifically, the longer the applied voltage is, the lower the threshold voltage is, and the shorter the time is, the higher the threshold voltage is. By using this, by adjusting the voltage application time of each synaptic unit, the interval between threshold voltages is widened as much as possible to minimize malfunction due to device dispersion.

Although the present invention has been described above with reference to the preferred embodiment, it should be understood that the present invention is not limited to the above embodiment. The present invention can variously change and modify the above embodiments within the scope of the claims described below, all of which fall within the scope of the present invention. Accordingly, the invention is limited only by the claims and their equivalents.

Claims (8)

A fixed resistor and a resistance change element (RRAM) are connected in series, a plurality of synaptic units comprising a synaptic unit connected in parallel,
One end of the synaptic unit is connected to a node generating write and read voltages, a neuromorphic synaptic device. According to claim 1,
In the plurality of synaptic units, the fixed resistor is a neuromorphic synaptic device, characterized in that each has a different resistance value. 3. The method of claim 2,
In the plurality of synaptic units, the fixed resistor adjusts the resistance value so that the conductance value of the ON state of the nth synaptic unit becomes 2 ^(n-1) G ₀ , thereby connecting n synaptic units in parallel. In the case of a unit, a neuromorphic synaptic device, characterized in that it implements an n-bit state. According to claim 1,
The neuromorphic synaptic device is a neuromorphic synaptic device, characterized in that selecting a synaptic unit in a state in which the resistance state of the resistance change device is ON by adjusting the applied write and read voltages. (a) a fixed resistor and a resistance change element (RRAM) are connected in series, including a synaptic unit in which a plurality of synaptic units are connected in parallel, and one end of the synaptic unit is connected to a node for generating write and read voltages, New providing a lomorphic synaptic device;
(b) a writing step of applying a write pulse to the synaptic unit of the neuromorphic synaptic element to change the resistance state of the resistance change element of the synaptic unit selected from among the parallel-connected synaptic units to ON; and
(c) applying a read voltage to the synaptic unit of the neuromorphic synaptic element, comprising a read step of indicating the sum of conductance of the selected synaptic unit as a signal, the method of operating a neuromorphic synaptic element. 6. The method of claim 5,
In the step of providing the neuromorphic synaptic device of (a), in the plurality of synaptic units, the fixed resistor has an ON state conductance value of 2 ^(n-1) G _{0 of the nth synaptic unit} By adjusting the resistance value so as to be, in the case of a synaptic unit in which n synaptic units are connected in parallel, an operation method of a neuromorphic synaptic device, characterized in that it implements an n-bit state. 6. The method of claim 5,
In the writing step of (b), the operating method of a neuromorphic synaptic device, characterized in that using an alternating pulse method (alternating pulse scheme) to apply a write pulse and an erase pulse alternately. 6. The method of claim 5,
In the reading step of (c), in order to widen a window between threshold voltages in units of synapses, a method of operating a neuromorphic synaptic device, characterized in that the voltage application time is adjusted for each synaptic unit.

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