KR20210081959A - Display Device and Driving Method of the same - Google Patents

Abstract

The present provides a display device, which includes: a display panel for displaying an image; a power supply unit supplying a high potential voltage and a low potential voltage to the display panel; and a voltage control unit controlling the power supply unit, wherein when a driving frequency of the display panel is changed from a first frequency to a second frequency, the voltage control unit generates a voltage control signal for varying the level of the low potential voltage and supplies it to the power supply unit. The second frequency may be 1/2 slower than the first frequency. Accordingly, it is possible to maintain a uniform display quality even when driving at a low speed.

Description

Display Device and Driving Method of the Same

The present invention relates to a display device and a driving method thereof.

As information technology develops, the market for display devices, which is a connection medium between users and information, is growing. Accordingly, the use of display devices such as a light emitting display (LED), a quantum dot display (QDD), and a liquid crystal display (LCD) is increasing.

The display devices described above include a display panel including sub-pixels, a driving unit outputting a driving signal for driving the display panel, and a power supply unit generating power to be supplied to the display panel or the driving unit.

In the above display devices, when a driving signal, for example, a scan signal and a data signal, is supplied to the sub-pixels formed on the display panel, the selected sub-pixel transmits light or emits light directly, thereby displaying an image. .

Meanwhile, among the display devices described above, the light emitting display device has many advantages, such as electrical and optical characteristics with a fast response speed, high luminance, and a wide viewing angle, and mechanical characteristics that can be implemented in a flexible form.

An aspect of the present invention is to improve luminance non-uniformity or flicker that may appear on a display panel during a skip period in which a data voltage and a scan signal are not output during low-speed driving. Another object of the present invention is to improve power consumption while maintaining a uniform display quality even when driving at a low speed.

As a means for solving the above problems, the present invention provides a display panel for displaying an image; a power supply supplying a high potential voltage and a low potential voltage to the display panel; and a voltage controller for controlling the power supply, wherein the voltage controller generates a voltage control signal for varying the level of the low potential voltage when the driving frequency of the display panel is changed from a first frequency to a second frequency. A display device for supplying the power supply unit is provided.

The second frequency may be the same as the first frequency or a frequency that is 1/2 slower than the first frequency.

The level of the low potential voltage may be temporarily boosted or boosted step-by-step.

The level of the low potential voltage may be temporarily boosted or boosted in stages during a skip period in which the data voltage and scan signal required for driving the display panel are not applied.

The voltage controller may output the voltage control signal after a predetermined delay time when the driving frequency of the display panel is changed from the first frequency to the second frequency.

The voltage controller may generate the voltage control signal based on a synchronization signal for driving the display panel and a gate start signal for scanning the display panel.

The voltage controller includes a signal counter for counting a synchronization signal for driving the display panel, a delay controller for delaying and outputting the synchronization signal, and a delay controller for scanning the display panel with the delayed synchronization signal output from the delay controller It may include a signal comparator that compares the gate start signal and outputs a result value, and a voltage control signal output unit that outputs the voltage control signal based on the result value output from the signal comparator.

The signal counter unit includes a first terminal receiving the synchronization signal, a second terminal receiving a first register value, and a third terminal outputting a changed synchronization signal obtained by changing the synchronization signal, the changed synchronization signal The frequency of may vary according to the value of the first register.

The delay control unit includes a first terminal receiving the synchronization signal, a second terminal receiving a second register value, and a third terminal outputting the delayed synchronization signal, the delay time of the delayed synchronization signal is It may vary according to the value of the second register.

The voltage control signal output unit includes a first terminal for receiving the result value, a second terminal for receiving a third register value, a third terminal for receiving a fourth register value, and a fourth terminal for outputting the voltage control signal. It includes a terminal, and the low potential voltage may vary according to the value of the third register, and may be restored according to the value of the fourth register.

In another aspect, the present invention provides a method of driving a display panel using a scan signal and a data voltage generated based on a first frequency; and varying the level of the low potential voltage to be applied to the display panel when the driving frequency of the display panel is changed to a second frequency slower than the first frequency.

The varying the level of the low potential voltage may be temporarily boosted or boosted in stages during a skip period in which a data voltage and a scan signal necessary for driving the display panel are not applied.

According to the present invention, the luminance unevenness or flicker on the display panel can be improved by boosting the low potential voltage from the start point of the skip section in which the data voltage and the scan signal are not output or any one selected point within the skip section during low-speed driving. there is In addition, the present invention can maintain a uniform display quality even when driving at a low speed, and lower the driving frequency when expressing a specific image, such as a still image, and change the low potential voltage, so that power consumption can be improved.

1 is a schematic block diagram of a light emitting display device according to a first embodiment of the present invention, and FIG. 2 is a schematic circuit configuration diagram of a sub-pixel.
3 is a diagram illustrating waveforms for explaining a driving method according to a first embodiment of the present invention, and FIG. 4 is a first schematic diagram showing the configuration of a circuit related to a low potential voltage change according to the first embodiment of the present invention. FIG. 5 is a second exemplary diagram schematically illustrating the configuration of a circuit related to the variable low potential voltage according to the first embodiment of the present invention, and FIG. 6 is a voltage control unit according to the first embodiment of the present invention. This is a simplified block diagram.
7 is a block diagram showing a voltage control unit in more detail according to a second embodiment of the present invention, FIG. 8 is a waveform diagram for explaining a change in a synchronization signal according to the operation of the signal counter unit, and FIGS. 9 and 10 are It is a waveform diagram for explaining a method of varying the low potential voltage during low-speed driving, and FIGS. 11 and 12 are diagrams showing examples of varying the low potential voltage.
13 to 16 are diagrams for explaining a method of driving a light emitting display device according to a third embodiment of the present invention.

The light emitting display device according to the present invention is implemented as a television, an image player, a personal computer (PC), a home theater, a smart phone, and the like. The light emitting display device is implemented based on an inorganic light emitting diode or an organic light emitting diode. However, hereinafter, for convenience of description, an example implemented based on an organic light emitting diode will be described.

1 is a schematic block diagram of a light emitting display device according to a first embodiment of the present invention, and FIG. 2 is a schematic circuit configuration diagram of a sub-pixel.

As shown in FIG. 1 , in the light emitting display device according to the first embodiment of the present invention, an image processing unit 110 , a timing control unit 120 , a data driving unit 130 , a scan driving unit 140 , and a power supply unit 180 . and a display panel 150 .

The image processing unit 110 outputs a data enable signal DE along with the data signal DATA supplied from the outside. The image processing unit 110 may output one or more of a vertical synchronization signal, a horizontal synchronization signal, and a clock signal in addition to the data enable signal DE, but these signals are omitted for convenience of description.

The timing controller 120 receives the data signal DATA from the image processing unit 110 as well as a driving signal including a data enable signal DE or a vertical synchronization signal, a horizontal synchronization signal, and a clock signal. The timing controller 120 includes a gate timing control signal GDC for controlling the operation timing of the scan driver 140 and a data timing control signal DDC for controlling the operation timing of the data driver 130 based on the driving signal. output, etc.

The data driver 130 samples and latches the digital data signal DATA supplied from the timing controller 120 in response to the data timing control signal DDC supplied from the timing controller 120 , and then sets the gamma reference voltage. It is converted into analog data voltage based on the output. The data driver 130 outputs a data voltage through the data lines DL1 to DLn. The data driver 130 may be formed in the form of an integrated circuit (IC).

The scan driver 140 outputs a scan signal in response to the gate timing control signal GDC supplied from the timing controller 120 . The scan driver 140 outputs a scan signal including a scan high voltage and a scan low voltage through the gate lines GL1 to GLm. The scan driver 140 is formed in the form of an IC or is formed in the display panel 150 in a gate-in-panel method. A description related to the gate-in-panel type scan driver will be provided below.

The power supply unit 180 is connected to the first power line VDDEL and the second power line VSSEL disposed on the display panel 150 . The power supply unit 180 outputs a high potential voltage (first potential voltage) and a low potential voltage (second potential voltage) through the first power line VDDEL and the second power line VSSEL. The high potential voltage and the low potential voltage transmitted through the first power line VDDEL and the second power line VSSEL are applied to the sub-pixels SP of the display panel 150 .

The display panel 150 displays an image in response to the voltage supplied from the power supply unit 180 , the data voltage supplied from the data driver 130 and the scan driver 140 , and the scan signal. The display panel 150 includes sub-pixels SP that operate to display an image. The sub-pixels SP may have one or more different light-emitting areas according to light-emitting characteristics (material, lifespan, luminous intensity, etc. of the device).

As shown in FIG. 2 , one sub-pixel SP is electrically connected to a data line DL1 , a gate line GL1 , a first power line VDDEL, and a second power line VSSEL. One sub-pixel SP includes an organic light emitting diode (OLED) emitting light and a pixel circuit (CC) driving the same.

The pixel circuit CC includes a switching transistor for transmitting a data voltage, a capacitor for storing the data voltage, a driving transistor for generating a driving current based on the data voltage stored in the capacitor, and the like. The pixel circuit CC may further include a compensation circuit for compensating for deterioration of a driving transistor or an organic light emitting diode (OLED).

3 is a diagram illustrating waveforms for explaining a driving method according to a first embodiment of the present invention, and FIG. 4 is a first schematic diagram showing the configuration of a circuit related to a low potential voltage change according to the first embodiment of the present invention. FIG. 5 is a second exemplary diagram schematically illustrating the configuration of a circuit related to the variable low potential voltage according to the first embodiment of the present invention, and FIG. 6 is a voltage control unit according to the first embodiment of the present invention. This is a simplified block diagram.

As shown in FIG. 3 , when the frequency change signal VRR_en for changing (lowering) the driving frequency of the display panel is activated (eg, when it occurs as logic high), the driving frequency Freq of the display panel is set for general driving. It may be changed from a frequency (eg, 60 Hz) (first frequency) to a low-speed driving frequency (eg, 30 Hz) (second frequency).

When the display panel is driven in response to a low-speed driving frequency (eg, 30Hz), the data voltage Vdata and the scan signal Scan for driving the display panel are temporarily output only during the refresh period. can

When the data voltage Vdata and the scan signal Scan are temporarily output for low-speed driving of the display panel, the luminance expressed on the display panel is not uniformly maintained and over time (increase in the holding time of the data voltage, etc.) may be changed or reduced depending on

For example, if you compare the decrease in the gate voltage (Vg) of the driving transistor when operating at a normal driving frequency (eg 60Hz) with the decrease in the gate voltage (Vg) of the driving transistor when operating at a low speed driving frequency (eg 30Hz). can As another example, it can be seen by comparing the increase in luminance of the display panel when operating at a normal driving frequency (eg 60Hz) with the increase in luminance of the display panel when operating at a low-speed driving frequency (eg 30Hz). have.

In order to minimize the phenomenon that the luminance expressed on the display panel is not uniformly maintained when the driving frequency of the display device is changed and is changed or deteriorated over time (increase in the holding time of the data voltage, etc.), When operating at a frequency (eg 30Hz), the low potential voltage applied through the second power line is varied (eg, temporarily boosted).

In the following description, a driving frequency of 30 Hz or less, which is 1/2 of a general driving frequency of 60 Hz, in a skip section to which the data voltage Vdata and the scan signal are not applied, will be defined as a low-speed driving frequency. However, the definition of the low-speed driving frequency may vary depending on the display panel or a device driving the same.

As shown in FIG. 4 , according to the first example of the present invention, the power supply unit 180 generates a low potential voltage (Vcs) based on the voltage control signal Vcs output from the voltage control unit 160 when the display panel is driven at a low speed. Vssel) can be output by varying the level. In this case, the level of the high potential voltage Vddel output from the power supply unit 180 may not be changed but may be fixed, but is not limited thereto.

As shown in FIG. 5 , according to the second exemplary embodiment of the present invention, the power supply unit 180 outputs a voltage control signal output from the voltage control unit 160 included in the data driver 130 when the display panel is driven at a low speed. Based on (Vcs), the level of the low potential voltage (Vssel) can be varied and output. In this case, the level of the high potential voltage Vddel output from the power supply unit 180 may not be changed but may be fixed, but is not limited thereto.

That is, according to the above two examples, the voltage control unit 160 for varying the voltage level of the power supply unit 180 exists separately, or is located inside another IC such as inside the data driving unit 130 or the timing control unit. may exist.

Meanwhile, when the display device is implemented as a small model, the data driver and the timing controller may be integrated into one integrated driving IC, and the voltage controller 160 may be included in the integrated driving IC. However, in the following description, it is described that the voltage control unit 160 is separately present as an example, but it is noted that it may be included in other devices as described above.

As shown in FIG. 6 , according to the first embodiment, the voltage control unit 160 includes a signal counter unit 161 , a delay control unit 163 , a signal comparison unit 165 , and a voltage control signal output unit 167 . can do.

The signal counter 161 may serve to count a synchronization signal (eg, a signal indicating the start of one frame). The signal counter 161 may perform a role of changing the frequency characteristic of the synchronization signal to change the driving frequency as well as the count of the synchronization signal. The delay control unit 163 may play a role of delaying and outputting the synchronization signal.

The signal comparison unit 165 compares the delayed synchronization signal output from the delay control unit 163 with a gate start signal for scanning the display panel (a signal indicating the start of one scan line) and outputs a result value, etc. can do. The voltage control signal output unit 167 outputs a voltage control signal Vcs for varying the level of the low potential voltage Vssel of the power supply unit 180 based on the result value output from the signal comparator 165 . role, etc.

When the low-speed driving condition is reached by the above configuration, the voltage control unit 160 outputs a voltage control signal Vcs, and the power supply unit 180 that has received it outputs a low potential voltage according to the logic state of the voltage control signal Vcs. The level of (Vssel) can be varied (eg, temporarily boosted).

7 is a block diagram showing the voltage control unit in more detail according to the second embodiment of the present invention, FIG. 8 is a waveform diagram for explaining the change of the synchronization signal according to the operation of the signal counter unit, and FIGS. 9 and 10 are It is a waveform diagram for explaining a method of varying the low potential voltage during low-speed driving, and FIGS. 11 and 12 are diagrams illustrating examples of varying the low potential voltage.

7 to 10 , according to the second embodiment, the voltage control unit 160 includes a signal counter unit 161 , a delay control unit 163 , a signal comparison unit 165 , and a voltage control signal output unit 167 . ) may be included.

The signal counter unit 161 counts the synchronization signal and outputs the frequency characteristic of the input synchronization signal by changing (change the driving frequency Freq), and the like. The signal counter unit 161 outputs the first terminal to which the first synchronization signal Bsync1 is input, the second terminal to which the first register value REG[0] is input, and the changed second synchronization signal Bsync2. It may include a third terminal.

The signal counter unit 161 changes the first synchronization signal Bsync1 input from the inside or outside to the second synchronization signal Bsync2 based on the first register value REG[0] input through the second terminal. After that, it can be output through the third terminal. The second synchronization signal Bsync2 becomes a synchronization signal (a signal indicating the start of an actual first frame) having a driving frequency Freq to be actually used in the display device.

As an example, the signal counter unit 161 receives a synchronization signal (60 Hz) corresponding to FIG. 8(a), which corresponds to a synchronization signal (30 Hz) corresponding to FIG. 8(b) or a synchronization signal corresponding to FIG. 8(c). It can be output after changing the frequency in the form of a signal (20Hz) or the like. And this may vary according to the first register value REG[0] input through the second terminal. That is, the first register value REG[0] is a factor for controlling (determining) the driving frequency to be selected by the signal counter unit 161 .

The delay control unit 163 may play a role of delaying and outputting the first synchronization signal Bsync1. The delay control unit 163 includes a first terminal receiving the first synchronization signal Bsync1, a second terminal receiving the second register value REG[1], and a third delayed synchronization signal (delayed third synchronization signal). Since is not used as a synchronization signal, it may include a third terminal for outputting an output signal 'Out'). As an example (refer to ① and ② in FIG. 10), the delay control unit 163 holds (output delay) the input first synchronization signal Bsync1 based on the second register value (REG[1]) for a predetermined time. can be printed out. That is, the delay time of the first synchronization signal Bsync1 may vary according to the value of the third register.

The signal comparator 165 compares the third synchronization signal Out and the gate start signal Gvst delayed by the delay control unit 163 and outputs a result value Comp1, and the like. The signal comparator 165 includes a first terminal receiving the delayed third synchronization signal Out, a second terminal receiving the gate start signal Gvst, and a third terminal receiving the enable signal Enable; A fourth terminal for outputting the result value Comp1 may be included.

For example, the signal comparator 165 may output 'COMP1_High' as the result value Comp1 when the condition is "OUT(High) & GVST(High)", and "OUT(High) & GVST(Low)" In case of condition, 'COMP1 Low' can be output as the result value (Comp1), but is not limited thereto. In addition, the signal comparison unit 165 may compare the two input signals according to the logic state of the enable signal Enable.

The voltage control signal output unit 167 may serve to output the voltage control signal Vcs based on the result value Comp1 output from the signal comparator 165 . The voltage control signal output unit 167 includes a first terminal receiving the result value Comp1 of the signal comparison unit 165, a second terminal receiving the third register value REG[2], and a fourth register It may include a third terminal receiving the value REG[3] and a fourth terminal outputting the voltage control signal Vcs.

As a first example (see ① in FIG. 10 ), the voltage control signal output unit 167 has a low potential voltage (Vssel) of the power supply unit 180 when the result value Comp1 of the signal comparison unit 165 is 'COMP1_High'. The voltage control signal Vcs may be provided and output in a form in which the level of is variable. In this case, the voltage control signal Vcs may be controlled according to the third register value REG[2].

By the voltage control signal Vcs, the level of the low potential voltage Vssel of the power supply unit 180 may be variable (step-up/step-down) in a step-like manner (multiple levels). That is, the third register value REG[2] may be prepared based on adjustment information of the low potential voltage Vssel for each low-speed driving frequency.

As a second example (refer to ② in FIG. 10), the voltage control signal output unit 167 has a low potential voltage (Vssel) of the power supply unit 180 when the result value Comp1 of the signal comparison unit 165 is 'COMP1_Low'. The voltage control signal Vcs may be prepared and outputted in a form in which the level of is restored to the initial value. In this case, the voltage control signal Vcs may be controlled according to the fourth register value REG[3].

The level of the low potential voltage Vssel of the power supply unit 180 may be restored to an initial state by the voltage control signal Vcs. That is, the fourth register value REG[3] may be prepared based on initial information of the low potential voltage Vssel with respect to the general driving frequency.

As described above, when the frequency change signal VRR_en for changing (lowering) the driving frequency of the display panel is activated (eg, when it occurs at logic high), the driving frequency Freq of the display panel is changed to the general driving frequency (eg, when the driving frequency of the display panel is low). : 60Hz) to low-speed driving frequency (eg 30Hz).

When the data voltage Vdata and the scan signal Scan are temporarily output to drive the display panel at a low speed, the gate voltage Vg of the driving transistor may decrease while the luminance of the display panel may increase. Accordingly, the luminance expressed on the display panel is not uniformly maintained and may be changed or deteriorated over time (eg, an increase in the holding time of the data voltage, etc.).

In order to solve the above problem, when the low-speed driving condition is reached, the voltage control unit 160 according to the second embodiment may output the voltage control signal Vcs. In addition, the power supply unit 180 may vary (boost) the level of the low potential voltage Vssel output from the buck-boost converter 185 according to the logic state of the voltage control signal Vcs.

11 or 12 , the power supply unit 180 varies (step-up/step-down) the level of the low potential voltage Vssel in a stepwise (multiple levels) according to the logic value or bit value of the voltage control signal Vcs. )can do. Of course, the level of the low potential voltage Vssel may be varied (step-up/step-down) in various forms in response to a frequency change such as whether the driving frequency is nHz or 12Hz. Here, nHz = 60Hz / (1 + number of skips).

Hereinafter, an example of resolving a problem (luminance non-uniformity or flicker) caused by Vdata leakage when a light emitting display device is driven at a low speed will be described based on the third embodiment of the present invention. However, although the sub-pixel of the light emitting display device has a 7T (Transistor) 1C (Capacitor) structure as an example, the present invention is not limited thereto.

13 to 16 are diagrams for explaining a method of driving a light emitting display device according to a third embodiment of the present invention.

As shown in FIG. 13 , in the light emitting display device according to the third exemplary embodiment, a first transistor T1 , second transistors T2a and T2b , a third transistor T3 , a fourth transistor T4 , and a fifth transistor T4 are shown. It may include a sub-pixel including transistors T5a and T5b, a sixth transistor T6, a driving transistor DT, a capacitor CST, and an organic light emitting diode (OLED).

The first transistor T1 has a gate electrode connected to the N-th scan line SCAN[n], a first electrode connected to the first data line DL1, and a second electrode connected to the first electrode of the driving transistor DT. this is connected The second transistors T2a and T2b have a gate electrode connected to the Nth scan line SCAN[n], a first electrode connected to the second electrode of the driving transistor DT, and a gate electrode connected to the driving transistor DT. The second electrode is connected. The second transistors T2a and T2b are made of two transistors to prevent current leakage as an example, but it may be formed of one transistor. The third transistor T3 has a gate electrode connected to the Nth emission control line EM[n], a first electrode connected to the first power line VDDEL, and a second electrode connected to the first electrode of the driving transistor DT. electrodes are connected.

The fourth transistor T4 has a gate electrode connected to the Nth emission control line EM[n], a first electrode connected to the second electrode of the driving transistor DT, and an anode electrode connected to the organic light emitting diode OLED. The second electrode is connected. The fifth transistors T5a and T5b have a gate electrode connected to an N-1th scan line SCAN[n-1], a first electrode connected to an initialization voltage line VINI, and a gate electrode of the driving transistor DT. The second electrode is connected to The sixth transistor T6 has a gate electrode connected to the Nth scan line SCAN[n], a first electrode connected to an initialization voltage line VINI, and a second electrode connected to the anode electrode of the organic light emitting diode OLED. Connected.

The driving transistor DT has a gate electrode connected to the other end of the capacitor CST, the first electrode of the second transistors T2a and T2b, and the second electrode of the fifth transistor T5a and T5b, and the first transistor T1 The first electrode is connected to the second electrode of the third transistor T3 and the second electrode is connected to the second electrode of the second transistors T2a and T2b, and the second electrode is connected to the first electrode of the fourth transistor T4. Connected. The capacitor CST has one end connected to the first power line EVDD and the other end connected to the gate electrode of the driving transistor DT. The organic light emitting diode OLED has an anode electrode connected to the second electrode of the fourth transistor T4 and a cathode electrode connected to the second power line EVSS.

As shown in FIG. 14 , the sub-pixel of FIG. 13 operates in the order of an initialization period t1 , a threshold voltage sensing period t2 , a sustain period t3 , and an emission period t4 .

During the initialization period t1, the N-1 th scan signal Scan[n-1] and the N-th scan line SCAN[N] are at logic low on the N-1 th scan line SCAN[N-1]. A logic high N-th scan signal Scan[n] is transmitted, and a logic-high N-th emission control signal Em[n] is transmitted to the N-th emission control line EM[n].

During the initialization period t1, the fifth transistors T5a and T5b correspond to the N-1th scan signal Scan[n-1] transmitted through the N-1th scan line SCAN[N-1]. is turned on When the fifth transistors T5a and T5b are turned on, the initialization voltage Vini transferred through the initialization voltage line VINI is applied to the first node connected to the gate electrode of the driving transistor DT. The capacitor CST is initialized (or residual charges are discharged) by the initialization voltage Vini applied to the first node.

During the threshold voltage sensing period t2, the N-1th scan signal Scan[n-1] of logic high and the Nth scan line SCAN[N-1] are connected to the N-1th scan line SCAN[N-1]. ]) of a logic low N-th scan signal Scan[n], and a logic-high N-th emission control signal Em[n] is transmitted to the N-th emission control line EM[n].

During the threshold voltage sensing period t2, the second transistors T2a and T2b are turned on in response to the N-th scan signal Scan[n] transmitted through the N-th scan line SCAN[N]. When the second transistors T2a and T2b are turned on, the drain electrode and the gate electrode of the driving transistor DT are connected to the diode connection state. Accordingly, the threshold voltage Vth of the driving transistor DT is sensed and sampled. An operation for sensing and sampling the threshold voltage Vth of the driving transistor DT is defined as a compensation operation.

During the threshold voltage sensing period t2, the first transistor T1 is turned on in response to the N-th scan signal Scan[n] transmitted through the N-th scan line SCAN[N]. When the first transistor T1 is turned on, the data voltage transferred through the first data line DL1 passes through the source electrode of the driving transistor DT and then through the drain electrode and is applied to the other end of the capacitor CST. Due to the turn-on operation of the first transistor T1 and the diode connection operation of the driving transistor DT, the capacitor CST is charged with the data voltage Vdata+Vth reflecting the threshold voltage variation of the driving transistor DT.

During the threshold voltage sensing period t2, the sixth transistor T6 is turned on in response to the N-th scan signal Scan[n] transmitted through the N-th scan line SCAN[N]. When the sixth transistor T6 is turned on, the initialization voltage Vini transmitted through the initialization voltage line VINI is applied to the anode electrode of the organic light emitting diode OLED. Accordingly, the organic light emitting diode (OLED) is initialized.

During the sustain period t3, the N-1th scan signal Scan[n-1] of logic high and the Nth scan line SCAN[N] are connected to the N-1th scan line SCAN[N-1]. A logic high N-th scan signal Scan[n] is transmitted, and a logic-high N-th emission control signal Em[n] is transmitted to the N-th emission control line EM[n].

During the holding period t3, the first transistor T1, the second transistor T2a, T2b, the third transistor T3, the fourth transistor T4, the fifth transistor T5a, T5b, the sixth transistor ( T6) and the driving transistor DT are turned off. During the sustain period t3, the capacitor CST is charged with the data voltage Vdata+Vth in which the threshold voltage variation of the driving transistor DT is reflected, and the charged voltage value is maintained.

During the light emission period t4, the N-1th scan signal Scan[n-1] of logic high and the Nth scan line SCAN[N] are connected to the N-1th scan line SCAN[N-1]. A logic-high N-th scan signal Scan[n] is transmitted, and a logic-low N-th emission control signal Em[n] is transmitted to the N-th emission control line EM[n].

During the emission period t4, the third and fourth transistors T3 and T4 are turned on in response to the N-th emission control signal Em[n] transmitted through the N-th emission control line EM[n]. . The driving transistor DT is turned on in response to the data voltage stored in the capacitor CST and generates a driving current based on the first power voltage transmitted through the first power line VDDEL. As a result, the organic light emitting diode OLED receives the driving current generated from the driving transistor DT to emit light. An operation in which the organic light emitting diode (OLED) emits light is defined as an image display operation on the display panel.

13 to 15 , in the case of the above-described sub-pixel, a voltage leakage flowing to the data voltage initialization voltage line VINI stored in the capacitor CST during the light emission period t4 may occur due to the characteristics of the P-type transistors. have. In this case, the luminance may increase while the gate voltage charged in the gate electrode of the driving transistor DT may decrease. Such a problem may become a hindrance factor in which the luminance of the display panel cannot be uniformly expressed when the light emitting display device is driven at a low speed.

Referring to the current change (DT IV curve & OLED IV curve) according to the change of the low potential voltage Vssel as shown in FIG. 16 , even if the driving region of the driving transistor DT is in the saturation region, It can be seen that the organic light emitting diode (OLED) may have a slight luminance change.

The present invention uses this feature to temporarily boost the low potential voltage from the start point (or any one selected point within the skip section) of the skip section (or the driving frequency change time) in which the data voltage and the scan signal are not output during low-speed driving by using this feature. It was found that luminance non-uniformity or flicker of the display panel can be improved by compensating the display panel. An example related to the compensation method for temporarily boosting the low potential voltage will be understood with reference to FIGS. 9, 11, and 12 described above.

As described above, the present invention can improve luminance unevenness or flicker on the display panel by boosting the low potential voltage from the start point of the skip section in which the data voltage and the scan signal are not output or any selected point within the skip section during low-speed driving. It works. In addition, the present invention can maintain a uniform display quality even when driving at a low speed, and lower the driving frequency when expressing a specific image, such as a still image, and change the low potential voltage, so that power consumption can be improved.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention can be changed to other specific forms by those skilled in the art to which the present invention pertains without changing the technical spirit or essential features of the present invention. It will be appreciated that this may be practiced. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. In addition, the scope of the present invention is indicated by the claims to be described later rather than the above detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention.

130: data driver 140: scan driver
180: power supply 150: display panel
160: voltage control unit 161: signal counter unit
163: delay control unit 165: signal comparison unit
167: voltage control signal output unit

Claims (12)

a display panel for displaying an image;
a power supply supplying a high potential voltage and a low potential voltage to the display panel; and
a voltage control unit for controlling the power supply unit;
When the driving frequency of the display panel is changed from the first frequency to the second frequency, the voltage control unit generates a voltage control signal for varying the level of the low potential voltage and supplies the generated voltage control signal to the power supply unit. According to claim 1,
The second frequency is
A display device having a frequency equal to or 1/2 slower than the first frequency. According to claim 1,
The level of the low potential voltage is
A display device that is temporarily boosted or boosted in steps. According to claim 1,
The level of the low potential voltage is
A display device in which a data voltage and a scan signal necessary for driving the display panel are temporarily boosted or boosted in stages during a skip period. According to claim 1,
The voltage controller
The display device outputs the voltage control signal after a predetermined delay time when the driving frequency of the display panel is changed from the first frequency to the second frequency. According to claim 1,
The voltage controller
A display device generating the voltage control signal based on a synchronization signal for driving the display panel and a gate start signal for scanning the display panel. According to claim 1,
The voltage controller
a signal counter for counting a synchronization signal for driving the display panel;
a delay control unit for delaying and outputting the synchronization signal;
a signal comparison unit for comparing the delayed synchronization signal output from the delay control unit with a gate start signal for scanning the display panel and outputting a result value;
and a voltage control signal output unit configured to output the voltage control signal based on a result value output from the signal comparator. 8. The method of claim 7,
the signal counter
a first terminal receiving the synchronization signal, a second terminal receiving the first register value, and a third terminal outputting a changed synchronization signal obtained by changing the synchronization signal;
The changed frequency of the synchronization signal varies according to the value of the first register. 9. The method of claim 8,
The delay control unit
a first terminal to which the synchronization signal is input;
a second terminal to which a second register value is input;
and a third terminal for outputting the delayed synchronization signal,
A delay time of the delayed synchronization signal varies according to the value of the second register. 10. The method of claim 9,
The voltage control signal output unit
a first terminal for receiving the result value;
a second terminal to which the third register value is input;
a third terminal to which the fourth register value is input;
and a fourth terminal for outputting the voltage control signal,
The low potential voltage is varied according to the value of the third register and is restored according to the value of the fourth register. driving the display panel with the scan signal and data voltage generated based on the first frequency; and
and varying a level of a low potential voltage to be applied to the display panel when the driving frequency of the display panel is changed to a second frequency slower than the first frequency. 12. The method of claim 11,
The step of varying the level of the low potential voltage includes:
A method of driving a display device in which a data voltage and a scan signal necessary for driving the display panel are temporarily boosted or boosted in stages during a skip period to which the display panel is not applied.

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