KR20210080789A - Display device and driving method for the same - Google Patents

Abstract

Embodiments of the present invention provide a display device and a driving method thereof, wherein a display panel displays a plurality of frames in response to a first driving frequency in a first mode and displays a plurality of frames in response to a second driving frequency different from the first driving frequency in a second mode, and the peak luminance of the display panel in the first mode is different from that of the display panel in the second mode. The present invention provides the display device which reduces power consumption and does not degrade image quality, and the driving method thereof.

Description

Display device and driving method thereof

The present specification relates to a display device and a driving method thereof, and more particularly, to a display device capable of reducing power consumption and preventing image quality deterioration, and a driving method thereof.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms, and a liquid crystal display device (LCD), a quantum dot light emitting display device (QLED: Quantum dot Light Emitting Display) are increasing. , and various types of display devices such as an organic light emitting display device (OLED) are being used.

The display device displays an image by sequentially displaying a plurality of frames for a preset time. In addition, the display device may display photos, games, and videos. The larger the number of frames displayed for a preset time, that is, the shorter the time of one frame, the more naturally the games and videos displayed on the display device will be displayed. can

However, as the number of frames increases, that is, as the time of one frame increases, power consumption of the display device increases. In addition, when a still image such as a photo or an image in which the difference between images is not large for each frame is displayed, the image displayed on the display device may be naturally displayed at least in the number of frames displayed for a preset time. Accordingly, there is no need to unnecessarily increase the number of frames when displaying still images.

The display device may adjust the time of one frame according to the displayed image in order to reduce power consumption. However, if one frame time is lengthened, it can be recognized that the luminance is lowered, so there is a problem in that the image quality of the display device is lowered. Accordingly, the inventors of the present specification provide a display device that reduces power consumption and does not degrade image quality, and a driving method thereof.

The problems to be solved according to the embodiments of the present specification to be described below are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

According to embodiments of the present specification, a display panel displaying an image including a plurality of frames by a plurality of data lines, a plurality of gate lines, and a plurality of pixels connected to the plurality of data lines and the plurality of gate lines displays a plurality of frames corresponding to a first driving frequency in the first mode, displays the plurality of frames in response to a second driving frequency different from the first driving frequency in a second mode, and displays the display panel in the first mode By making the peak luminance of the display panel different from the peak luminance of the display panel in the second mode, it is possible to prevent the image quality from being deteriorated.

In addition, according to the embodiments of the present specification, the display device is switched from the first mode to the second mode or from the second mode to the first mode in response to a mode conversion signal, and the mode conversion from the first mode When receiving a signal, the controller enters the second mode after lowering the voltage level of the initialization signal, and when receiving the mode conversion signal in the second mode, increases the voltage level of the initialization signal stepwise and enters the first mode Accordingly, it is possible to prevent the image quality from being deteriorated even when the mode conversion corresponding to the driving frequency is performed.

In addition, according to the embodiments of the present specification, operating in a first mode for displaying a plurality of frames in response to a first driving frequency in a display panel including a plurality of pixels initialized using an initialization signal; Displaying a plurality of frames on the display panel in response to the driving frequency, operating in a second mode in which an initialization signal input to the display panel is variable, and operating in the first mode in the display panel, mode conversion This can reduce power consumption of the display device and prevent deterioration of image quality due to mode change.

According to the embodiments of the present specification, by preventing a change in luminance from being recognized according to a driving frequency, it is possible to suppress the occurrence of image quality deterioration.

According to the embodiments of the present specification, there is an effect of reducing power consumption by allowing the display device to be switched to a mode.

The effects of the embodiments disclosed herein are not limited to the above-mentioned effects. In addition, the embodiments disclosed herein may generate other effects not mentioned above, which will be clearly understood by those skilled in the art from the following description.

1 is a structural diagram illustrating a structure of a display device according to embodiments of the present invention.
2 is a circuit diagram illustrating a pixel employed in a display device according to embodiments of the present invention.
FIG. 3 is a timing diagram illustrating an operation of the pixel illustrated in FIG. 2 .
4 is a graph showing a change in luminance for each driving frequency in the display device according to the present invention.
5 is a graph showing power consumption generated by the display device for each driving frequency.
6 is a diagram illustrating a change in luminance for each operation mode in a display device according to embodiments of the present invention.
7 is a timing diagram illustrating a first initialization signal and a second initialization signal in a display device according to embodiments of the present invention.
8 is a graph illustrating a change in luminance when changing from a first mode to a second mode in a display device according to embodiments of the present invention.
9 is a graph illustrating a change in luminance of a display panel when changing from a second mode to a first mode in a display device according to embodiments of the present invention.
10 is a timing diagram illustrating one frame period for each mode in a display device according to embodiments of the present invention.
11 is a structural diagram illustrating a controller employed in a display device according to the present invention.
12 is a flowchart illustrating a method of driving a display device according to the present invention.

Advantages and features of the present specification and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments allow the disclosure of the present specification to be complete, and common knowledge in the technical field to which this specification belongs It is provided to fully inform the possessor of the scope of the invention, and this specification is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present specification are illustrative and the present specification is not limited to the illustrated matters. The same reference numerals refer to the same elements throughout the specification. In addition, in the description of the present specification, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present specification, the detailed description thereof will be omitted. do. When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between the two parts unless 'directly' is used.

In the case of a description of a temporal relationship, for example, when a temporal relationship is described as 'after', 'following', 'after', 'before', etc., 'immediately' or 'directly' Unless ' is used, cases that are not continuous may be included.

In the case of a description of the signal flow relationship, for example, even in the case of 'a signal is transmitted from node A to node B', unless 'directly' or 'directly' is used, node A passes through another node. A case in which a signal is transmitted to node B may be included.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present specification.

Each feature of the various embodiments of the present specification may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be independently implemented with respect to each other or may be implemented together in a related relationship. may be

1 is a structural diagram illustrating a structure of a display device according to embodiments of the present invention.

Referring to FIG. 1 , the display device 100 may include a display panel 110 , a data driver 120 , a gate driver 130 , and a controller 140 .

The display panel 110 may include a plurality of data lines DL1 to DLm extending in a first direction and a plurality of gate lines GL1 to GLn extending in a second direction. Here, the first direction and the second direction may be orthogonal to each other. However, the present invention is not limited thereto.

Also, the display panel 110 may include a plurality of pixels 101 . The plurality of pixels 101 may operate by receiving the data signal transmitted through the data line in response to the gate signal transmitted through the gate line. Also, the plurality of pixels 101 may be initialized in response to the initialization signal.

The data driver 120 may be connected to the plurality of data lines DL1 to DLm and may supply data signals to the plurality of pixels 101 through the plurality of data lines DL1 to DLm. The data driver 120 may include a plurality of source drivers. Each of the plurality of source drivers may be implemented as an integrated circuit.

The gate driver 130 may be connected to the plurality of gate lines GL1 to GLn and supply a gate signal to the plurality of gate lines GL1 to GLn. The pixel receiving the gate signal through the gate line may receive the data signal.

Although the gate driver 130 is illustrated as being disposed outside the display panel 110 , the present invention is not limited thereto, and the gate driver 130 may be disposed on the display panel 110 . In addition, the gate driver 130 is disposed on the display panel 110 and may include a gate signal generator for outputting a gate signal and a level shifter for supplying a voltage and a clock to the gate signal generator. Also, the gate driver 130 may be implemented with a plurality of integrated circuits.

In addition, although the gate driver 130 is illustrated as being disposed on one side of the display panel 110 , the present invention is not limited thereto, and the gate driver 130 is disposed on both sides of the display panel 110 , and the gate driver disposed on the left side is odd-numbered. A gate driver connected to the gate line and disposed on the right side of the display panel 110 may be connected to an even-numbered gate line.

The controller 140 may control the data driver 120 and the gate driver 130 . The controller 140 may supply a data control signal to the data driver 120 and a gate control signal to the gate driver 130 . The data control signal or the gate control signal may include a clock, a vertical synchronization signal, a horizontal synchronization signal, and a start pulse. However, the signal output from the controller 140 is not limited thereto.

Also, the controller 140 may supply an image signal to the data driver 120 . The data driver 120 may generate a data signal through the image signal and the data control signal received from the controller 140 , and may supply the data signal to a plurality of data lines.

Also, the controller 140 may control the voltage supplied to the display panel 110 . The controller 140 may receive the mode conversion signal and adjust the voltage level of the voltage supplied to the display panel 110 . The voltage level of the initialization signal may be differently controlled in the first mode and the second mode by the mode change signal.

The display device 100 may be switched from the first mode to the second mode or may be switched from the second mode to the first mode. Also, when entering the second mode from the first mode, the display device 100 may enter the second mode after lowering the voltage level of the initialization signal. Also, when entering the first mode from the second mode, the display panel 110 may enter the first mode after increasing the voltage level of the initialization signal in stages.

2 is a circuit diagram illustrating a pixel employed in a display device according to embodiments of the present invention, and FIG. 3 is a timing diagram illustrating an operation of the pixel illustrated in FIG. 2 .

2 and 3 , the pixel 101 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a It may include a 6th transistor M6, a 7th transistor M7, a storage capacitor Cst, and a light emitting diode (LED).

The first transistor M1 may have a first electrode connected to the first node N1 and a second electrode connected to the second node N2 . In addition, the gate electrode of the first transistor M1 may be connected to the third node N3 .

The second transistor M2 may have a first electrode connected to the data line DL and a second electrode connected to the third node N3 . In addition, the gate electrode of the second transistor M2 may be connected to the first gate line GL1 .

The third transistor M3 may have a first electrode connected to the second node N2 and a second electrode connected to the third node N3 . In addition, the gate electrode of the third transistor M3 may be connected to the second gate line.

The fourth transistor M4 may have a first electrode connected to the first initialization signal line VL2 and a second electrode connected to the second node N2 . In addition, the gate electrode of the fourth transistor M4 may be connected to the third gate line GL3 .

The fifth transistor M5 may have a first electrode connected to a VL1 first power supply line VL1 to which the first power EVDD is transmitted, and a second electrode connected to the first node N1 . In addition, a gate electrode of the fifth transistor M5 may be connected to the emission control signal line EML.

The sixth transistor M6 may have a first electrode connected to the second node N2 and a second electrode connected to the fourth node N4 . In addition, a gate electrode of the sixth transistor M6 may be connected to the emission control signal line EML.

The seventh transistor M7 may have a first electrode connected to the second initialization signal line VL3 and a second electrode connected to the fourth node N4 . In addition, the gate electrode of the seventh transistor M7 may be connected to the third gate line GL3 .

The storage capacitor Cst may have a first electrode connected to the third node N3 and a second electrode connected to the first power line VL1 . The storage capacitor Cst may maintain the voltage of the third node N3 . Also, the storage capacitor Cst may store a voltage corresponding to the threshold voltage of the first transistor M1 .

The light emitting diode (LED) may include an anode electrode, a cathode electrode, and a light emitting layer disposed between the anode electrode and the cathode electrode. The light emitting layer may be an inorganic layer or an organic layer. The anode electrode of the light emitting diode LED may be transferred to the fourth node N4 , and the cathode electrode may be connected to the second power source EVSS having a lower voltage level than the first power source EVDD.

And the pixel 101 implemented as described above may operate as follows.

In the first period T1 , the third gate signal gs3 may be transmitted through the third gate line GL3 . The fourth transistor M4 and the seventh transistor M7 may be turned on by the third gate signal gs3 . When the fourth transistor M4 and the seventh transistor M7 are turned on, the first initialization signal Vini and the second initialization signal Var are transmitted to the second node N2 and the fourth node N4, respectively. The second node N2 and the fourth node N4 may be initialized by voltages of the first initialization signal Vini and the second initialization signal Var in a high state. The first initialization signal Vini and the second initialization signal Var may be the same signal.

The third gate signal gs3 is illustrated as a low signal, but is not limited thereto, and since the fourth transistor M4 and the seventh transistor M7 are P MOS transistors in FIG. 3 , the third gate signal gs3 is may be a low signal. However, when the fourth transistor M4 and the seventh transistor M7 are N MOS transistors, the third gate signal gs3 may be a high signal.

In the second period T2 , the third gate line GL3 may be in a high state so that the third gate signal gs may not be transmitted. When the third gate signal gs is not transmitted, the first initialization signal Vini and the second initialization signal Var may not be transmitted to the second node N2 and the fourth node N4, respectively. . Also, in the second period T2 , the first initialization signal Vini and the second initialization signal Var may be converted to a low signal. In addition, in the second period T2 , the first gate signal gs1 may be transmitted. When the first gate signal gs1 is transmitted, the third transistor M3 may be turned on. When the third transistor M1 is turned on, the third transistor M3 may be diode-connected.

In the third period T3 , the third gate signal gs may be transmitted to the third gate line GL3 . In this case, the first initialization signal Vini and the second initialization signal Var may be transmitted in a low state. When the third gate signal gs is transmitted, the fourth transistor M4 and the seventh transistor M7 are turned on, so that the second node N2 and the fourth node N4 are in the low state of the first initialization signal ( Vini) and the second initialization signal Var, the voltage level of the second node N2 and the fourth node N4 is low, so that the driving current can be prevented from flowing to the light emitting diode (LED).

In addition, since the first gate signal gs1 transmitted through the first gate line GL1 is transmitted in the third period T3 , the third transistor M3 may maintain turn-on. When the third transistor M3 is turned on, the first transistor M1 may be diode-connected to store the threshold voltage of the first transistor M1 in the storage capacitor Cst.

In the fourth period T4 , the first gate signal gs1 transmitted to the first gate line GL1 may be maintained, and the second gate signal gs may be transmitted through the second gate line GL2 . In FIG. 2 , since the second transistor M2 is a P MOS transistor, the second gate signal gs2 may be a low signal. If the second transistor M2 is an N MOS transistor, the second gate signal gs2 may be a high signal. The second transistor M2 and the third transistor M3 may be turned on by the first gate signal gs1 and the second gate signal gs.

In the fourth period T4 , the third gate signal gs3 may not be transmitted. Accordingly, the second transistor M2 and the third transistor M3 may be turned on, and the fourth transistor M4 and the seventh transistor M7 may be turned off.

When the second transistor M2 is turned on, the data voltage Vdata corresponding to the data signal may be transmitted to the first node N1 . At this time, since the third transistor M3 is turned on, the data voltage Vdata may be transferred to the storage capacitor Cst. Accordingly, a voltage corresponding to the threshold voltage of the first transistor M1 and the data voltage Vdata may be stored in the storage capacitor Cst.

After the second gate line GL2 is in a high state in the fifth period T5 and the second gate signal gs2 is not transmitted, the first gate signal gs1 may not be transmitted. When the second gate signal gs2 is not transmitted, the second transistor M2 may be turned off so that the data voltage Vdata may not be transmitted to the first node N1 . And, when the first gate signal gs1 is not transmitted, the third transistor M3 may be turned off.

In addition, in the fifth period T5 , the third gate signal gs3 may be transmitted. The fourth transistor M4 and the seventh transistor M7 may be turned on by the third gate signal gs3 , and the first initialization signal Vini and the second initialization signal Var may be transferred to a high state. The first initialization signal Vini and the second initialization signal Var transferred to the high state are transmitted to the second node N2 and the fourth node N4 by the third transistor N3 and the fourth transistor M4, respectively. may be transmitted to , so that the second node N2 and the fourth node N4 may be initialized.

In the sixth period T6 , the third gate signal gs3 is not transmitted, so that the fourth transistor M4 and the seventh transistor M7 may be turned off. In addition, the emission control signal ems may be transmitted through the emission control signal line EML. Since the fifth transistor M5 and the sixth transistor M6 are P MOS transistors, the emission control signal ems may be transmitted in a low state. However, when the fifth transistor M5 and the sixth transistor M6 are N MOS transistors, the emission control signal ems may be transferred to a high state. When the emission control signal ems is transmitted, the fifth transistor M5 and the sixth transistor M6 are turned on, and at this time, the threshold voltage and the data voltage Vddata of the first transistor M1 are applied to the storage capacitor Cst. Since a voltage corresponding to is stored, a threshold voltage of the driving current transmitted to the light emitting diode LED by the first transistor M1 may be compensated.

4 is a graph showing a change in luminance for each driving frequency in the display device according to the present invention, and FIG. 5 is a graph showing power consumption generated in the display device for each driving frequency.

Fig. 4(a) shows the change in luminance of the display device 100 in the first mode, which is normal driving, and Fig. 4(b) is displayed in the second mode, which is low power consumption driving, which consumes less power compared to the first mode. A change in luminance of the device 100 is shown. In the first mode, the driving frequency is set faster than in the second mode. In the first mode, the driving frequency may be 120 Hz, and in the second mode, the driving frequency may be 1 Hz. However, the present invention is not limited thereto.

In the pixel 101 , a driving current flows to the light emitting diode LED in response to the voltage stored in the storage capacitor Cst, and the voltage stored in the storage capacitor Cst is lowered due to leakage current, etc., so that the luminance of the display panel 110 is lowered. may fall off. When the driving frequency is 120 Hz as shown in (a) of FIG. 4 , since the time of one frame is short and the frequency of charging the voltage to the storage capacitor Cst is high, the time for the luminance to decrease in one frame (1 frame) This becomes shorter, so that the decrease in luminance X1 may appear small.

On the other hand, when the driving frequency is 1 Hz as shown in (b) of FIG. 4 , the luminance in one frame is lowered because the frequency of charging the voltage to the storage capacitor Cst is low because the time of one frame is long. There is a problem in that the luminance degradation X2 is larger than the case in which the driving frequency is 120 Hz because the time is also increased.

On the other hand, FIG. 5 compares the power consumption of the display device 100 in the first mode and the second mode, wherein (a) is the first mode and (b) is the second mode. The display device 100 includes a data driver 120 , a gate driver 130 or It may include power consumption consumed by the controller 140 .

When the display device 100 expresses the same gray level in the first mode and the second mode, since the amount of driving current supplied to the light emitting device LED is the same, as shown in the lower part of the dotted line P1, the light emitting device ( The amount of power consumed by the LED) may be the same. However, as shown in the upper part of the dotted line P1 , the logic element operates differently depending on the driving frequency, so that in the second mode, the amount of power consumed by the display device 100 is the first mode. In this case, it may be less than the amount of power consumed by the display device 100 .

6 is a diagram illustrating a change in luminance for each operation mode in a display device according to embodiments of the present invention.

Referring to FIG. 6 , the display device 100 may operate in a first mode and a second mode. The display device 100 may alternately operate in the first mode and the second mode in order to reduce power consumption.

The driving frequency of the first mode and the second mode may be different from each other, and the driving frequency of the first mode may be faster than the driving frequency of the second mode. For example, the driving frequency may be 120 Hz in the first mode and the driving frequency may be 1 Hz in the second mode.

As illustrated in FIG. 6A , the luminance of the display device 100 in the first mode may be higher than that of the display device 100 in the second mode. The peak luminance Lpeak1 of the display device 100 in the first mode may be higher than the peak luminance Lpeak2 of the display device 100 in the second mode. Also, as shown in FIG. 4 , since the decrease in luminance in the second mode is greater than that in the first mode, the average luminance in the second mode may be lower than the average luminance in the first mode. Accordingly, when the first mode and the second mode are repeatedly performed in the display device 100 , a problem in that the user recognizes a change in luminance of the display device 100 may occur.

Accordingly, as shown in (b), the peak luminance Lpeak2 of the display device 100 in the second mode may be set higher than the peak luminance Lpeak1 of the display device 100 in the first mode. Accordingly, the average luminance of the display device 100 in the first mode and the average luminance of the display device 100 in the second mode may be the same or similar. Accordingly, when the first mode and the second mode are repeatedly performed in the display device 100 , the effect that the user cannot recognize the change in luminance of the display device 100 may occur.

7 is a timing diagram illustrating a first initialization signal and a second initialization signal in a display device according to embodiments of the present invention.

Referring to FIG. 7 , the first initialization signal Vini and the second initialization signal Var may be transmitted to the second node N2 and the fourth node N4, respectively, as shown in FIG. 2 . have. In the first mode, the first initialization signal Vini and the second initialization signal Var may be constantly supplied. On the other hand, in the second mode, the voltage levels of the first initialization signal Vini and the second initialization signal Var may be varied.

As shown in FIG. 4 , in the display device 100 , the luminance may decrease during one frame period. In the second mode, the luminance decrease due to the long period of one frame should be compensated. Since the first initialization signal Vini or the second initialization signal Var is a voltage applied to the anode of the light emitting diode LED, the voltage level of the first initialization signal Vini or the second initialization signal Var is adjusted. By doing so, it is possible to compensate for the decrease in luminance in the second mode.

The voltage level of the first initialization signal Vini or the second initialization signal Var may be changed in stages. One step may correspond to the horizontal synchronization signal. Also, when switching from the first mode to the second mode, the second mode may be entered after lowering the voltage level of the first initialization signal Vini or the second initialization signal Var in the first mode. If the first initialization signal Vini or the second initialization signal Var is increased without lowering the voltage of the first initialization signal Vini or the second initialization signal Var, a problem in that the luminance is rapidly increased may occur. Accordingly, the second mode may be entered after lowering the voltage level of the first initialization signal Vini or the second initialization signal Var. And, when entering the second mode, the voltage level of the first initialization signal Vini or the second initialization signal Var may be lowered in stages. When the voltage level of the first initialization signal Vini or the second initialization signal Var is lowered, the average luminance of the display device 100 may be lowered in the second mode. Accordingly, the user may not recognize that the luminance of the display device 100 is lowered.

Then, when the second mode is switched to the first mode, the voltage level of the first initialization signal Vini or the second initialization signal Var is increased stepwise, and then the first mode may be entered.

8 is a graph illustrating a change in luminance when changing from a first mode to a second mode in a display device according to embodiments of the present invention.

8A illustrates a change in luminance of the display device 100 when the voltage level of the first initialization signal Vini or the second initialization signal Var is constant in the first mode and the second mode. And, FIG. 8(b) shows that the voltage level of the first initialization signal Vini or the second initialization signal Var is changed in stages in the first mode and the second mode. In (b) of FIG. 8 , the voltage level of the first initialization signal Vini or the second initialization signal Var is the first initialization signal Vini or the second initialization signal (Vini) in the first mode immediately before entering the second mode. After the voltage level of Var is lowered, in the second mode, it may be set higher than the voltage level of the first initialization signal Vini or the second initialization signal Var in the first mode and then lowered in stages. In this case, a period during which the voltage level of the first initialization signal Vini or the second initialization signal Var is lowered in the first mode may be shorter than one period during which the voltage is lowered in the second mode.

When changing from the first mode to the second mode, the luminance difference Y1 when the voltage level of the first initialization signal Vini or the second initialization signal Var is constant is the first initialization signal Vini or the second mode. 2 It can be seen that when the voltage level of the initialization signal Var is changed, the luminance difference Y2 is greater than that of the luminance difference Y2.

9 is a graph illustrating a change in luminance of a display panel when changing from a second mode to a first mode in a display device according to embodiments of the present invention.

FIG. 9A illustrates a change in luminance of the display device 100 when the voltage level of the first initialization signal Vini or the second initialization signal Var is constant in the second mode and in the first mode. And, FIG. 9(b) shows that the voltage level of the first initialization signal Vini or the second initialization signal Var is changed in stages in the second mode and in the first mode.

When changing from the second mode to the first mode, the luminance difference Z1 when the voltage level of the first initialization signal Vini or the second initialization signal Var is constant is the first initialization signal Vini or the second initialization signal Var. 2 It can be seen that when the voltage level of the initialization signal Var is changed, the luminance difference Z2 is larger than that of the luminance difference Z2.

10 is a timing diagram illustrating one frame period for each mode in a display device according to embodiments of the present invention.

Referring to FIG. 10 , (a) shows the first mode, and (b) shows the second mode.

In the first mode and the second mode, one frame substrate may include an active period Ta and a blank period Tb. The active period Ta is a period in which a data voltage Vdata corresponding to the data signal is written into the pixel 101 and the pixel 101 emits light, and the blank period is a period in which the pixel 101 corresponds to the written data voltage Vdata. ) may be a period during which light emission is maintained. The vertical synchronization signal may be supplied as a high signal in the active period Ta and may be supplied as a low signal in the blank period Tb. However, the present invention is not limited thereto.

As shown in FIG. 10A , in the first mode, the active period Ta may be long and the blank period Tb may be short. On the other hand, as shown in FIG. 10B , in the second mode, the active period Ta may be short and the blank period Tb may be long.

Also, in the second mode, the voltage level of the first initialization signal Vini or the second initialization signal Var may be varied. The blank period Tb may include at least a first blank period to a seventh blank period Tb1 to Tb7. The first initialization signal Vini or the second initialization signal Var may rise in the first blank period Tb1 and then gradually decrease in the second blank period to the fourth blank period Tb2 to Tb4. The step-down voltage level of the first initialization signal Vini or the second initialization signal Var is the same as the voltage level of the first initialization signal Vini or the second initialization signal Var set in the active period Ta. level can be

In addition, the first initialization signal Vini or the second initialization signal Var may increase in stages in the fifth to seventh blank periods Tb5 to Tb7. The voltage level of the seventh blank period Tb7 may rise to the voltage level of the first blank period Tb1.

The voltage level of the first initialization signal Vini or the second initialization signal Var may be lower than the voltage level set in the first mode in the active period Ta before the voltage level increases in the first blank period Tb1.

11 is a structural diagram illustrating a controller employed in a display device according to the present invention.

Referring to FIG. 11 , the controller 140 may include a timing controller 140a and a power controller 140b.

The timing controller 140a may receive a mode conversion signal MS from an external host. The timing controller 140a may be set to the second mode when receiving the mode conversion signal MS in the first mode, and set to the first mode when receiving the mode conversion signal in the second mode.

The power controller 140b may receive a mode conversion signal from an external host. However, the present invention is not limited thereto, and the mode conversion signal MS may be transmitted from the timing controller 140a. When the power controller 140b receives the mode conversion signal MS, the mode may be converted.

When the power controller 140b receives the mode conversion signal MS in the first mode, it becomes the second mode, and when it receives the mode conversion signal MS in the second mode, it may enter the first mode. In addition, when receiving the mode conversion signal MS in the first mode, the power controller 140b enters the second mode after lowering the voltage level of the initialization signal, and receives the mode conversion signal MS in the second mode. , it is possible to enter the first mode after increasing the voltage level of the initialization signal step by step. The initialization signal may be a first initialization signal Vini and/or a second initialization signal Vini.

When the voltage level of the initialization signal is increased stepwise, the power controller 140b may receive the control signal CS from the timing controller 140a to stepwise increase the voltage level of the initialization signal.

12 is a flowchart illustrating a method of driving a display device according to the present invention.

Referring to FIG. 12 , the display device driving method may operate in a first mode in which a plurality of frames are displayed in response to a first driving frequency on the display panel 110 ( S1210 ). It may include a plurality of pixels that emit light by a driving current corresponding to a data signal in response to a signal and a gate signal. Also, the display panel 110 may receive an initialization signal, and each pixel may be initialized by the initialization signal. The initialization signal may initialize the pixel in response to the first driving frequency.

In addition, a plurality of frames may be displayed on the display panel 110 in response to the second driving frequency, and the display panel 110 may operate in a second mode in which an initialization signal input to the display panel 110 is variable. (S1220) First mode is a normal mode, and the second mode may be a low power consumption mode that consumes less power than the first mode. The initialization signal may be varied in stages, and each stage may correspond to one frame period.

The image displayed by the display panel 110 includes a plurality of frames, and by sequentially displaying each frame, the image may be naturally displayed. And, one frame period represents a period in which one frame among a plurality of frames is displayed on the display device.

In addition, one frame period in the first mode may be shorter than one frame period in the second mode. In addition, one frame period may include an active period and a blank period. In the first mode, the length of the active period is set longer than the length of the blank period, and in the second mode, the length of the blank period is longer than the length of the active period. It can be set long. When entering the second mode, the voltage level of the initialization signal is input higher than the voltage level of the initialization signal in the first mode, and then the voltage level of the initialization signal is gradually lowered to become the voltage level of the initialization signal in the first mode. . Also, when switching from the first mode to the second mode, the second mode may be entered after the voltage level of the initialization signal is lowered.

Also, the voltage level of the initialization signal may be varied in the blank period of the second mode. In the blank period of the second mode, the voltage level of the initialization signal may be varied step by step. In addition, the blank period of the second mode includes at least a first blank period to a seventh blank period, and the initialization signal is set to be higher than the voltage level of the initialization signal set in the active period in the first blank period. can

Further, in the second blank period to the seventh blank period, the voltage level of the initialization signal may be lowered stepwise to a voltage level equal to the voltage level of the initialization signal set in the active period, and then may be raised again stepwise.

Then, the display panel may operate in the first mode. (S1230) When the second mode is switched to the first mode, the voltage level of the initialization signal may be increased stepwise, and then the first mode may be entered. The voltage level of the initialization signal in the second mode before entering the first mode may be the voltage level of the initialization signal when entering the second mode.

Although the embodiments of the present specification have been described in more detail with reference to the accompanying drawings, the present specification is not necessarily limited to these embodiments, and various modifications may be made within the scope without departing from the technical spirit of the present specification. . Accordingly, the embodiments disclosed in the present specification are for explanation rather than limiting the technical spirit of the present specification, and the scope of the technical spirit of the present specification is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present specification should be construed by the claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present specification.

100: display device
110: display panel
120: data driver
130: gate driver
140: controller
150: touch sensor

Claims (18)

a display panel for displaying an image including a plurality of frames by a plurality of data lines, a plurality of gate lines, and a plurality of pixels connected to the plurality of data lines and the plurality of gate lines;
a data driver supplying a data signal corresponding to the image to the display panel through the plurality of data lines; and
a gate driver supplying a gate signal to the display panel through the plurality of gate lines;
The display panel displays the plurality of frames in response to a first driving frequency in a first mode, and displays the plurality of frames in response to a second driving frequency different from the first driving frequency in a second mode,
A display device in which a peak luminance of the display panel in the first mode is different from a peak luminance of the display panel in the second mode.
According to claim 1,
In the display panel, the average luminance of the display panel in the first mode and the average luminance of the display panel in the second mode are the same.
According to claim 1,
The pixel is initialized by receiving an initialization signal, and voltage levels of the initialization signal are different in the first mode and the second mode.
4. The method of claim 3,
In the second mode, the voltage level of the initialization signal is variable.
5. The method of claim 4,
When the first driving frequency is higher than the second driving frequency, the voltage level of the initialization signal in a first period of the second mode is lower than the voltage level of the initialization signal in the first mode, In a second period of the mode, the voltage level of the initialization signal is higher than the voltage level of the initialization signal in the first mode, and in a third period of the second mode, the voltage level of the initialization signal is the second of the second modes. a display device lower than the voltage level of the initialization signal in a period.
5. The method of claim 4,
When the first driving frequency is a frequency higher than the second driving frequency, the first mode is entered after the pressure level of the initialization signal is increased stepwise in the second mode when the second mode is progressed to the first mode and a voltage level of the initialization signal decreases when entering the first mode.
4. The method of claim 3,
Further comprising a controller for switching from the first mode to the second mode or switching from the second mode to the first mode in response to a mode conversion signal,
When receiving the mode conversion signal in the first mode, the controller lowers the voltage level of the initialization signal, enters the second mode, and receives the mode conversion signal in the second mode. The display device enters the first mode after increasing the voltage level step by step.
4. The method of claim 3,
In the second mode, one frame period includes an active period and a blank period,
A display device in which a voltage level of the initialization signal is varied during the blank period.
9. The method of claim 8,
The blank period includes at least a first blank period to a seventh blank period, wherein the voltage level of the initialization signal in the first blank period is set higher than the voltage level of the initialization signal set in the active period;
In the second blank period to the seventh blank period, the voltage level of the initialization signal is lowered in steps to a voltage level equal to the voltage level of the initialization signal set in the active period, and then rises again in steps.
a display panel for displaying an image including a plurality of frames by a plurality of data lines and a plurality of gate lines, and a plurality of pixels connected to the plurality of data lines and the plurality of gate lines and initialized in response to an initialization signal;
a data driver supplying a data signal corresponding to the image to the display panel through the plurality of data lines;
a gate driver supplying a gate signal to the display panel through the plurality of gate lines; and
When the first mode is switched from the first mode to the second mode or the second mode is switched to the first mode, and the voltage level of the initialization signal is lowered when the first mode is switched from the first mode to the second mode, the second mode is switched on. The display device enters the first mode after stepwise increasing the voltage level of the initialization signal when the second mode is switched from the second mode to the first mode.
11. The method of claim 10,
A display device in which a peak luminance of the display panel in the first mode is different from a peak luminance of the display panel in the second mode.
12. The method of claim 11,
The average luminance of the display panel in the first mode and the average luminance of the display panel in the second mode are the same.
11. The method of claim 10,
In the second mode, one frame period includes an active period and a blank period,
A display device in which a voltage level of the initialization signal is varied during the blank period.
14. The method of claim 13,
The blank period includes at least a first blank period to a seventh blank period, wherein the voltage level of the initialization signal in the first blank period is set lower than the voltage level of the initialization signal set in the active period,
The voltage level of the initialization signal in the second blank period is set higher than the voltage of the initialization signal set in the active period,
In the third blank period to the seventh blank period, the voltage level of the initialization signal is gradually lowered to a voltage level equal to the voltage level of the initialization signal set in the active period, and then increased again in stages.
operating in a first mode for displaying a plurality of frames in response to a first driving frequency in a display panel including a plurality of pixels that are initialized using an initialization signal;
displaying a plurality of frames on the display panel in response to a second driving frequency and operating in a second mode in which a voltage level of the initialization signal input to the display panel is varied; and
and operating the display panel in the first mode.
16. The method of claim 15,
When switching from the first mode to the second mode, after lowering the voltage level of the initialization signal, it enters the second mode,
When the second mode is changed to the first mode, the display device drives into the first mode after increasing the voltage level of the initialization signal step by step.
16. The method of claim 15,
In the second mode, one frame period corresponding to each of the plurality of frames includes an active period and a blank period,
A display device in which a voltage level of the initialization signal is varied during the blank period.
18. The method of claim 17,
The blank period includes at least a first blank period to a seventh blank period, wherein the initialization signal has a voltage level of the initialization signal set higher than a voltage level of the initialization signal set in the active period in the first blank period; ,
In the second blank period to the seventh blank period, the voltage level of the initialization signal is gradually lowered to a voltage level equal to the voltage level of the initialization signal set in the active period, and then increased again in stages.

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