KR20210067836A - Semiconductor device - Google Patents

Abstract

A semiconductor element according to embodiments of the present invention includes: a semiconductor layer on a substrate; active fins defined on top of the semiconductor layer; a spacer covering sidewalls of each of the active fins; a gate pattern crossing the active fins; a source region and a drain region respectively provided on both sides of the gate pattern; and a source electrode and a drain electrode respectively contacting the source region and the drain region. The spacer is interposed between the sidewalls of each of the active fins and the gate pattern, and each of the active fins includes a metal-semiconductor compound layer thereon. The metal-semiconductor compound layer may contact the gate pattern.

Description

semiconductor device

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device in which an insulating layer is not provided on upper surfaces of active fins.

Gallium nitride (GaN)-based transistors have excellent properties in terms of breakdown voltage, saturation rate, and thermal characteristics, and thus are being actively studied. However, there is a problem in that transconductance increases and then rapidly decreases as the drain current increases. In order to solve this problem, a transistor having a fin structure is emerging as an alternative. A transistor having a fin structure has advantages in that the gate driving ability is improved and a charge trap phenomenon can be suppressed due to a decrease in the buffer layer compared to the conventional transistor.

In a transistor having a fin structure, an insulating film is formed on sidewalls and top surfaces of the fin structure to reduce a gate leakage current. Accordingly, there is a problem in that the distance from the gate to the channel is increased and the gate driving ability is reduced.

An object of the present invention is to provide a semiconductor device in which an insulating layer is formed only on sidewalls of active fins.

The problem to be solved by the present invention is not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those of ordinary skill in the art from the following description.

A semiconductor device according to embodiments of the present invention includes a semiconductor layer on a substrate; active fins defined on top of the semiconductor layer; a spacer covering sidewalls of each of the active fins; a gate pattern crossing the active fins; a source region and a drain region respectively provided on both sides of the gate pattern; and a source electrode and a drain electrode contacting the source region and the drain region, respectively, wherein the spacer is interposed between the sidewalls of each of the active fins and the gate pattern, and each of the active fins is formed on an upper portion of the spacer. and a metal-semiconductor compound layer, wherein the metal-semiconductor compound layer may contact the gate pattern.

The semiconductor device according to the embodiments of the present invention has an advantage that an insulating layer is provided only on sidewalls of the active fins, thereby reducing a gate leakage current and improving a gate driving capability.

The effects of the present invention are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those of ordinary skill in the art from the following description.

1 is a plan view of a semiconductor device according to embodiments of the present invention as viewed from above.
2A, 2B, and 2C are cross-sectional views of semiconductor devices according to embodiments of the present invention, respectively, taken along lines AA′, BB′, and C-C′ of FIG.
3A to 9A are cross-sectional views illustrating a method of manufacturing a semiconductor device according to embodiments of the present invention, and are cross-sectional views taken along line AA′ of FIG. 1 .
3B to 9B are cross-sectional views for explaining a method of manufacturing a semiconductor device according to embodiments of the present invention, and are cross-sectional views taken along line BB′ of FIG. 1 .

In order to fully understand the configuration and effect of the present invention, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention is not limited to the embodiments disclosed below, but may be implemented in various forms and various modifications and changes may be made. However, it is provided in order to complete the disclosure of the present invention through the description of the present embodiment, and to fully inform those of ordinary skill in the art to which the present invention pertains to the scope of the invention. In the accompanying drawings, for convenience of description, the size is enlarged than the actual size, and the ratio of each component may be exaggerated or reduced.

The terminology used herein is for the purpose of describing the embodiment and is not intended to limit the present invention. Also, unless otherwise defined, terms used herein may be interpreted as meanings commonly known to those of ordinary skill in the art.

As used herein, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, 'comprises' and/or 'comprising' refers to the presence of one or more other components, steps, operations and/or elements mentioned. or addition is not excluded.

When a layer is referred to herein as being 'on' another layer, it may be formed directly on top of the other layer, or a third layer may be interposed therebetween.

Although terms such as first and second are used herein to describe various regions, layers, and the like, these regions and layers should not be limited by these terms. These terms are only used to distinguish one region or layer from another. Accordingly, a part referred to as the first part in one embodiment may be referred to as the second part in another embodiment. The embodiments described and illustrated herein also include complementary embodiments thereof. Parts indicated with like reference numerals throughout the specification indicate like elements.

1 is a plan view of a semiconductor device according to embodiments of the present invention as viewed from above. 2A, 2B, and 2C are cross-sectional views of semiconductor devices according to embodiments of the present invention, and are cross-sectional views taken along lines A-A', B-B', and C-C' of FIG. 1, respectively.

1 , 2A, 2B, and 2C , a semiconductor layer 110 may be provided on a substrate 100 . For example, the substrate 100 may include at least one of silicon (Si), silicon carbide (SiC), sapphire, gallium nitride (GaN), or diamond, or a combination thereof. However, the materials constituting the substrate 100 are exemplary and are not limited thereto.

The semiconductor layer 110 may include a first semiconductor layer 111 and a second semiconductor layer 112 . A first semiconductor layer 111 may be provided on the substrate 100 , and a second semiconductor layer 112 may be provided on the first semiconductor layer 112 . The first semiconductor layer 111 may include a group III-V compound semiconductor. For example, the first semiconductor layer 111 may include at least one of aluminum nitride (AlN), indium gallium nitride (InGaN), aluminum indium nitride (AlInN), and aluminum gallium indium nitride (AlGaInN) or a combination thereof. may include Also, as an example, the first semiconductor layer 111 may be an intrinsic compound semiconductor layer. As another example, the first semiconductor layer 111 may be a compound semiconductor layer doped with a small amount of impurities.

The second semiconductor layer 112 may include a group III-V compound semiconductor. For example, the second semiconductor layer 112 may include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum indium nitride (AlInN), or aluminum gallium indium nitride (AlGaInN). may include at least one or a combination thereof. The second semiconductor layer 112 may have a single-layer structure or a multi-layer structure.

A band gap and a lattice constant of the second semiconductor layer 112 may be greater than a band gap and a lattice constant of the first semiconductor layer 111 , respectively. The second semiconductor layer 112 may include a group III-V compound semiconductor, but may include a material different from that of the first semiconductor layer 111 . The first semiconductor layer 111 and the second semiconductor layer 112 may be hetero-junctioned to form a 2-dimensional electron gas (2-DEG) region on the junction surface. The two-dimensional electron gas (2-DEG) region may be used as a channel region through which current flows.

For example, the second semiconductor layer 112 may be an intrinsic compound semiconductor layer. As another example, the second semiconductor layer 112 may be a compound semiconductor layer doped with a trace amount of impurities. The thickness of the second semiconductor layer 112 may be several to several tens of nanometers (nm). For example, the thickness of the second semiconductor layer 112 may be 30 nm or less.

Although not shown, a transition layer (not shown) may be provided on the substrate 100 . A transition layer (not shown) may be provided between the substrate 100 and the first semiconductor layer 111 . The transition layer (not shown) may alleviate a difference in thermal expansion coefficient and lattice constant between the substrate 100 and the first semiconductor layer 111 . For example, the transition layer (not shown) may include at least one of gallium nitride (GaN), aluminum nitride (AlN), and aluminum gallium nitride (AlGaN), or a combination thereof. The transition layer (not shown) may not be provided as an optional component.

Although not shown, an interface layer (not shown) may be provided between the first semiconductor layer 111 and the second semiconductor layer 112 . For example, the interfacial layer (not shown) may include aluminum nitride (AlN). The interface layer (not shown) may improve the mobility of the two-dimensional electron gas region 2-DEG by improving the interface characteristics between the first semiconductor layer 111 and the second semiconductor layer 112 . The interfacial layer (not shown) may not be provided as an optional component.

A portion of the semiconductor layer 110 may form active fins AF. The active fins AF may be formed by etching a portion of the semiconductor layer 110 . The active fins AF may include a portion of the first semiconductor layer 111 and the second semiconductor layer 112 . The active fins AF may extend in a first direction D1 and may be arranged to be spaced apart from each other by a predetermined interval in a second direction D2 crossing the first direction D1 . The active fins AF may be portions protruding from the first semiconductor layer 111 in a vertical direction. That is, the active fins AF may be portions protruding from the first semiconductor layer 111 in the third direction D3 perpendicular to the plane formed by the first direction D1 and the second direction D2 . For example, a width of the active fins AF in the second direction D2 may be 100 to 500 nm, and a width between adjacent active fins AF in the second direction D2 may be 50 to 300 nm. .

Trenches TR may be formed between adjacent active fins AF. The trenches TR may be formed by etching the first semiconductor layer 111 and the second semiconductor layer 112 . A portion of the first semiconductor layer 111 may be exposed by the trenches TR. That is, lower surfaces of the trenches TR may be located at a lower level than the lower surfaces of the second semiconductor layer 112 . The trenches TR may include sidewalls extending in the first direction D1 and sidewalls extending in the second direction D2 . Sidewalls extending in the first direction D1 of the trenches TR may be sidewalls of the active fins AF. The trenches TR may have a rectangular shape when viewed from above.

A spacer 201 may cover sidewalls of each of the active fins AF. The spacer 201 may extend in the first direction D1 along sidewalls of each of the active fins AF. The spacer 201 may include an insulating material. The spacer 201 may be a high-k film. For example, the spacer 201 may be a single-layer or multi-layer film including at least one of silicon nitride, silicon oxide, aluminum oxide, and hafnium oxide.

The spacer 201 may cover sidewalls of the trenches TR. In other words, the spacer 201 may be provided on the four sidewalls of the trenches TR to cover all the four sidewalls.

The gate pattern GP may cross the active fins AF. The gate pattern GP may cross the active fins AF while extending in the second direction D2 . The gate pattern GP may cross the active fins AF and the trenches TR while extending in the second direction D2 . The gate pattern GP may cover a portion of top surfaces and a portion of sidewalls of the active fins AF. The gate pattern GP may cover a portion of lower surfaces of the trenches TR. The lowermost surface of the gate pattern GP may be positioned at a lower level than the lower surface of the second semiconductor layer 112 . The gate pattern GP may include a metal material. For example, the gate pattern GP may include Ni/Au or Pt/Au.

Each of the active fins AF may include a metal-semiconductor compound layer MS. The metal-semiconductor compound layer MS may be positioned on the active fins AF. The gate pattern GP may contact the metal-semiconductor compound layer MS on the active fins AF. The metal-semiconductor compound layer MS may be locally positioned under the gate pattern GP.

The spacer 201 may be interposed between sidewalls of each of the active fins AF and the gate pattern GP. The spacer 201 may extend in the first direction D1 between sidewalls of each of the active fins AF and the gate pattern GP. The spacer 201 may not be provided on top surfaces of the active fins AF but may be provided only on sidewalls of the active fins AF.

A source region SR and a drain region DR may be formed on both sides of the gate pattern GP, respectively. In addition, the source/drain electrodes 300 contacting the source region SR and the drain region DR may be provided on both sides of the gate pattern GP. For example, the source/drain electrode 300 may include at least one of titanium (Ti), aluminum (Al), nickel (Ni), and gold (Au).

A channel region (not shown) may be interposed between the source region SR and the drain region DR. The channel region (not shown) may be the semiconductor layer 110 positioned under the gate pattern GP. The source/drain electrode 300 may include a source electrode 300a and a drain electrode 300b. The source electrode 300a and the drain electrode 300b may be spaced apart from each other in the first direction D1 . The source electrode 300a may be formed on one side of the gate pattern GP and contact the source region SR. The drain electrode 300b may be formed on the other side of the gate pattern GP to contact the drain region DR. The source region SR and the drain region DR may be provided at positions corresponding to the source electrode 300a and the drain electrode 300b, respectively. The source region SR and the drain region DR may be positioned under the source electrode 300a and the drain electrode 300b, respectively. The gate pattern GP may be spaced apart from the source/drain electrode 300 in the first direction D1 .

The width W1 in the first direction D1 between the gate pattern GP and the source electrode 300a is the width W2 in the first direction D1 between the gate pattern GP and the drain electrode 300b. ) can be less than (W1<W2). That is, the gate pattern GP may be asymmetrically formed to be closer to the source electrode 300a than the drain electrode 300b. Since the gate pattern GP is formed closer to the source electrode 300a than the drain electrode 300b, the breakdown voltage of the semiconductor device may be improved.

3A to 9A are cross-sectional views for explaining a method of manufacturing a semiconductor device according to embodiments of the present invention, and are cross-sectional views taken along line A-A' of FIG. 1 . 3B to 9B are cross-sectional views for explaining a method of manufacturing a semiconductor device according to embodiments of the present invention, and are cross-sectional views taken along line B-B' of FIG. 1 .

3A and 3B , a source region SR, a drain region DR, and a source/drain electrode 300 may be formed on the semiconductor layer 110 disposed on the substrate 100 . A source region SR and a source electrode 300a may be formed on one side of the semiconductor layer 110 , and a drain region DR and a drain electrode 300b may be formed on the other side of the semiconductor layer 110 . The source region SR and the drain region DR may include an n-type conductivity type impurity. For example, by depositing Ti/Al/Ni/Au on the semiconductor layer 110 to form the source/drain electrodes 300 and rapid heat treatment at a high temperature, the source region SR doped with n-type conductivity type impurities. ) and the drain region DR may be formed under the source electrode 300a and the drain electrode 300b, respectively. As another example, after forming the source region SR and the drain region DR doped with an n-type conductivity type impurity through an ion implantation process, the source electrode 300a and the drain electrode 300b may be deposited. As another example, after forming the source region SR and the drain region DR through an epitaxial process (eg, gallium nitride (GaN) regrowth process), the source electrode 300a and the drain electrode 300b may be formed. can

A channel region (not shown) may be interposed between the source region SR and the drain region DR. The channel region (not shown) may be positioned under the gate pattern GP. For example, the channel region (not shown) may be located 5 to 10 nm below the interface between the first semiconductor layer 111 and the second semiconductor layer 112 .

4A and 4B , a photoresist pattern PR may be patterned on the semiconductor layer 110 disposed on the substrate 100 . For example, after the photoresist pattern PR is applied on the second semiconductor layer 112 , it may be patterned through an e-beam lithography process. For example, the photoresist pattern PR may include polymethyl methacrylate (PMMA), and may have a thickness of about 1000 to 2800 angstroms.

5A and 5B , the first semiconductor layer 111 and the second semiconductor layer 112 may be etched by using the photoresist pattern PR as an etch mask. Active fins AF and trenches TR may be formed by etching the first semiconductor layer 111 and the second semiconductor layer 112 . For example, the height of the active fins AF may be etched to be 30 to 120 nm. The first semiconductor layer 111 may be exposed by the trenches TR. That is, in the region exposed by the photoresist pattern PR, all of the second semiconductor layer 112 may be etched, and only a portion of the first semiconductor layer 111 may be etched.

In the etching process of the semiconductor layer 110 , a dry etching process may be used for the vertical structure of the active fins AF. For example, an inductively coupled plasma (ICP) etching process may be used to mitigate etching damage, and the etching gas may include Cl ₂ or BCl ₃ .

6A and 6B , after the etching process, the photoresist pattern PR used as the etching mask may be removed through an ashing process. After the ashing process, a wet etching process may be additionally performed for the vertical structure of the active fins AF. For example, a tetra methyl ammonium hydroxide (TMAH) solution may be used in an additional wet etching process.

7A and 7B , an insulating layer 200 may be formed on upper surfaces of the active fins AF. The insulating layer 200 may be formed to cover upper surfaces and sidewalls of the active fins AF, lower surfaces and sidewalls of the trenches TR, and a portion of the upper surface of the second semiconductor layer 112 . The insulating layer 200 may include an insulating material. The insulating film 200 may be a high-k film. For example, the insulating layer 200 may have a single-layer or multi-layer structure including at least one of silicon nitride, silicon oxide, aluminum oxide, and hafnium oxide. For example, the insulating layer 200 may be formed to have a thickness of 100 to 500 angstroms.

8A and 8B , a spacer 201 may be formed by selectively removing a portion of the insulating layer 200 through an etching process. The insulating layer 200 formed on top surfaces of the active fins AF, bottom surfaces of the trenches TR, and a portion of the top surface of the second semiconductor layer 112 may be selectively etched. Accordingly, the spacer 201 may be provided only on the sidewalls of the active fins AF and the sidewalls of the trenches TR. That is, the spacer 201 may cover sidewalls of the active fins AF and sidewalls of the trenches TR.

In order to selectively etch the insulating layer 200 , a dry etching process having excellent anisotropic etching characteristics may be used. For example, an inductively coupled plasma (ICP) etching process may be used to mitigate etching damage, and the etching gas may include fluorine (F).

9A and 9B , the gate pattern GP may be formed to cross the active fins AF. The gate pattern GP may be formed to cross the active fins AF and the trenches TR in the second direction D2 . The gate pattern GP may be formed to cover a portion of top surfaces and a portion of sidewalls of the active fins AF. A portion of upper surfaces of the active fins AF may be exposed by the gate pattern GP. The gate pattern GP may be positioned between the source electrode 300a and the drain electrode 300b to be spaced apart from each other in the first direction D1 . As described above, the gate pattern GP may be asymmetrically formed to improve the breakdown voltage of the semiconductor device. The gate pattern GP may include a metal material. For example, the gate pattern GP may be formed by patterning a photoresist pattern and depositing Ni/Au or Pt/Au.

Each of the active fins AF may include a metal-semiconductor compound layer MS thereon. That is, the metal-semiconductor compound layer MS may be formed on the active fins AF to contact the gate pattern GP. The metal-semiconductor compound layer MS may be locally formed under the gate pattern GP.

The width W1 in the first direction D1 between the gate pattern GP and the source electrode 300a is the width W2 in the first direction D1 between the gate pattern GP and the drain electrode 300b. ) may be smaller than That is, the gate pattern GP may be formed to be closer to the source electrode 300a than the drain electrode 300b.

In the above, embodiments of the present invention have been described with reference to the accompanying drawings, but those of ordinary skill in the art to which the present invention pertains can practice the present invention in other specific forms without changing its technical spirit or essential features. You will understand that there is Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

Claims (1)

a semiconductor layer on the substrate;
active fins defined on top of the semiconductor layer;
a spacer covering sidewalls of each of the active fins;
a gate pattern crossing the active fins;
a source region and a drain region respectively provided on both sides of the gate pattern; and
a source electrode and a drain electrode respectively contacting the source region and the drain region;
the spacer is interposed between the sidewalls of each of the active fins and the gate pattern;
Each of the active fins includes a metal-semiconductor compound layer thereon,
The metal-semiconductor compound layer is in contact with the gate pattern.

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