KR20210065870A - Access line management for an array of memory cells - Google Patents

Abstract

Disclosed are a method, system and device for managing an access line for an array of memory cells. Some memory devices may include a plate which is joined to a memory cell related to a plurality of digit lines and/or a plurality of word lines. Because the plate is joined to a plurality of the digit lines and/or the word lines, unintended cross connection among various components of the memory device may be important. In order to mitigate an effect of the unintended cross connection among various components, the memory device may float a word line deselected during one or more of access operations. Accordingly, a voltage of each word line deselected may be related to a voltage of the plate because a change in the voltage of the plate can occur. The method for managing an access line for an array of memory cells comprises the following steps of: driving a plate joined to a first memory cell of an array of memory cells with a first voltage; identifying an access operation related to a second memory cell of the array of memory cells; floating the first access line joined to the first memory cell for the duration, based on at least some part of the access operation related to the second memory cell; and driving the plate for the duration with the first voltage to a second voltage, based on at least some part of the access operation related to the second memory cell.

Description

ACCESS LINE MANAGEMENT FOR AN ARRAY OF MEMORY CELLS

cross reference

This patent application claims priority to U.S. Patent Application No. 16/695,848 by Vimercati, entitled “ACCESS LINE MANAGEMENT FOR AN ARRAY OF MEMORY CELLS,” filed on November 26, 2019, which is filed on May 4, 2018 is a continuation-in-part of U.S. Patent Application No. 15/971,639 to Vimercati, entitled "ACCESS LINE MANAGEMENT FOR AN ARRAY OF MEMORY CELLS," filed at This application is expressly incorporated by reference in its entirety.

The following relates generally to access management for memory cells, and more specifically to access line management for an array of memory cells.

BACKGROUND Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming the various states of the memory device. For example, a binary device has two states, often denoted as a logic "1" or a logic "0." In other systems, more than two states may be stored. To access the stored information, the electronic device's A component may read or sense the state stored in the memory device To store information, a component of the electronic device may write or program the state in the memory device.

Magnetic Hard Disk, Random Access Memory (RAM), Read Only Memory (ROM), Dynamic RAM (DRAM), Synchronous Dynamic RAM (SDRAM), Ferroelectric RAM (FeRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), Flash Various types of memory devices exist, including memory, phase change memory (PCM), and the like. A memory device may be volatile or non-volatile. Non-volatile memories such as FeRAM can retain stored logic states for long periods of time even in the absence of an external power source. For example, volatile memory devices such as DRAMs may lose their stored state over time unless periodically refreshed by an external power source. FeRAM may use a device architecture similar to volatile memory, but may have non-volatile properties because it uses a ferroelectric capacitor as the storage device. Thus, FeRAM devices can have improved performance compared to other non-volatile and volatile memory devices.

Improving memory devices may generally include increasing memory cell density, increasing read/write speeds, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among others.

1 illustrates an example of a memory array that supports access line management for an array of memory cells in accordance with an example of the present disclosure.
2 illustrates an example of circuitry supporting techniques for access line management in accordance with examples of this disclosure.
3 illustrates an example of a memory device supporting techniques for access line management in accordance with examples of this disclosure.
4A and 4B illustrate examples of memory devices and timing diagrams supporting techniques for access line management in accordance with examples of this disclosure.
5A and 5B illustrate examples of memory devices and timing diagrams supporting techniques for access line management in accordance with examples of this disclosure.
6 and 7 show block diagrams of devices supporting techniques for access line management according to examples of the present disclosure.
8-10 illustrate a method for access line management for an array of memory cells in accordance with examples of the present disclosure.
11 illustrates an example of circuitry supporting techniques for managing access lines for an array of memory cells in accordance with examples of this disclosure.
12A-12D illustrate example timing diagrams supporting techniques for access line management for an array of memory cells in accordance with examples of this disclosure.
13 illustrates a block diagram of an access line manager that supports access line management for an array of memory cells in accordance with an example of the present disclosure.
14 illustrates a diagram of a system including a device that supports access line management for an array of memory cells in accordance with examples of this disclosure.
15 illustrates a method for access line management for an array of memory cells in accordance with an example of the present disclosure.

Some memory arrays may include a plate common to a plurality of memory cells, the memory cells also associated with a plurality of digit lines and/or a plurality of word lines. As the voltage of the plate (and thus also the voltage of the associated plate line) fluctuates in connection with an access operation (eg, between a high voltage and a low voltage) to a selected memory cell, some memory devices cause the plate (deselection) to occur at a fixed voltage. Each word line may be maintained for a common deselected memory cell (which may be referred to as an unselected word line). This is the leakage current due to capacitive (eg, parasitic) cross-coupling associated with each deselected word line (eg, between each deselected word line and a common plate or plate line). and associated power loss. If the plate is common to many memory cells, the amount of capacitance (eg, parasitic capacitance) and unintentional cross-coupling between the plate and the deselected word line, and thus the associated power loss, can be significant. Along with additional power consumption by the memory array, parasitic signals due to this unintended cross-coupling can disrupt the logic state stored in the deselected memory cells. For example, parasitic signaling can introduce errors into data by changing states stored in memory cells or introducing errors into access operations, among other effects.

Access lines (e.g., deselected access lines, deselected A technique for managing word lines) is described in this application. For example, to reduce or mitigate the effects of unintentional cross-coupling, the memory device may float a number of deselected access lines (eg, word lines) when changing the voltage of the plate. . Accordingly, the memory device may float the deselected word line during one or more portions of an access operation to the selected memory cell, and in some cases for a duration before or after the access operation. Floating deselected access lines reduces the overall power consumption of the memory array by enabling the voltage of each deselected access line to track (eg, maintain a constant or near constant difference) the voltage of the plate and plate line can be lowered as well as errors associated with deselected memory cells. As used herein, node floating may refer to electrically isolating a node from any defined voltage source.

Features of the disclosure introduced above are further described below in the context of FIGS. 1-3 . Specific examples are then described with reference to FIGS. 4A-4B and 5A-5B, 11 and 12A-12D. These and other features of the present disclosure are further illustrated and described by apparatus diagrams, system diagrams, and flow diagrams related to techniques for managing an access line for an array of memory cells.

1 illustrates an exemplary memory array 100 in accordance with various embodiments of the present disclosure. Memory array 100 may also be referred to as an electronic memory device. Memory array 100 includes memory cells 105 programmable to store different states. Each memory cell 105 may be programmable to store two states, denoted logic 0 and logic 1. In some cases, memory cell 105 is configured to store two or more logic states. Memory cell 105 may store charge in a capacitor representing a programmable state; For example, a charged capacitor and an uncharged capacitor may individually exhibit two logic states. DRAM architectures may typically use such designs, and the capacitors used may include dielectric materials with linear or super-electrically polarizing properties as insulators. Conversely, a ferroelectric memory cell may include a capacitor having a ferroelectric as an insulating material. Different charge levels of ferroelectric capacitors can represent different logic states. Ferroelectric materials have nonlinear polarization properties; Some details and advantages of ferroelectric memory cell 105 are discussed below.

The memory array 100 may be a three-dimensional (3D) memory array in which two-dimensional (2D) memory arrays are formed on top of each other. This can increase the number of memory cells that can be formed on a single die or substrate compared to a 2D array, which in turn can reduce production costs or increase the performance of the memory array, or both . According to the example shown in FIG. 1 , the memory array 100 includes two levels of memory cells 105 and thus may be considered a three-dimensional memory array; However, the number of levels is not limited to two. Each level may be aligned or positioned such that the memory cells 105 are approximately aligned with each other across each level to form a memory cell stack 145 . In some cases, the memory array 100 may be referred to as a memory device 100 .

Each row of memory cells 105 is coupled to an access line 110 , and each column of memory cells 105 is coupled to a bit line 115 . Access line 110 and bit line 115 may be substantially perpendicular to each other to create an array. Additionally, each row of memory cells 105 may be coupled to at least one plate line (not shown). As used herein, the terms plate node, plate line, or simply plate may be used interchangeably. 1 , each memory cell 105 of the memory cell stack 145 may be coupled to a separate conductive line, such as a bit line 115 . In other examples (not shown), two memory cells 105 of memory cell stack 145 may share a common conductive line, eg, bit line 115 . That is, the bit line 115 may be in electronic communication with the bottom electrode of the upper memory cell 105 and the upper electrode of the lower memory cell 105 . Other configurations may be possible and for example the third deck may share the access line 110 with the lower deck. In general, one memory cell 105 may be located at the intersection of two conductive lines, such as an access line 110 and a bit line 115 . This intersection may be referred to as an address of a memory cell. The target memory cell 105 may be a memory cell 105 located at the intersection of the energized access line 110 and the bit line 115 ; That is, the access line 110 and the bit line 115 may be energized to read or write the memory cell 105 at their intersection. Another memory cell 105 in electronic communication with (eg, connected to) the same access line 110 or bit line 115 may be referred to as a non-target memory cell 105 .

As discussed above, the electrode may be coupled to the memory cell 105 and the access line 110 or bit line 115 . The term electrode may refer to an electrical conductor and in some cases may be used as an electrical contact to the memory cell 105 . Electrodes may include traces, wires, conductive lines, conductive layers, etc. that provide conductive paths between elements or components of memory array 100 .

Operations such as read and write may be performed on memory cell 105 by activating or selecting access line 110 and digit line 115 . Access line 110 may also be known as word line 110 , and bit line 115 may also be known digit line 115 . In general, the term access line may refer to a word line, bit line, digit line, or plate line. References to word lines and bit lines or the like are interchangeable without loss of understanding or operation. Activating or selecting the word line 110 or digit line 115 may include applying a voltage to the respective line. The word line 110 and the digit line 115 may be formed of a conductive material such as a metal (eg, copper (Cu), aluminum (Al), gold (Au), tungsten (W), etc.), a metal alloy, carbon, doping. semiconductors, or other conductive materials, alloys, compounds, etc.

In some architectures, the cell's logic storage device, eg, a capacitor, may be electrically isolated from the digit line by a select component. The word line 110 may be controlled by being connected to a selection component. For example, the select component may be a transistor and the word line 110 may be coupled to the gate of the transistor. Activating the word line 110 creates an electrical connection or closed circuit between the capacitor of the memory cell 105 and the corresponding digit line 115 . The digit line can then be accessed to read or write the memory cell 105 . Upon selection of memory cell 105, the resulting signal can be used to determine a stored logic state.

Access of the memory cell 105 may be controlled through the row decoder 120 and the column decoder 130 . For example, the row decoder 120 may receive a row address from the memory controller 140 and activate an appropriate word line 110 based on the received row address. Similarly, the column decoder 130 receives the column address from the memory controller 140 and activates the appropriate digit line 115 . For example, memory array 100 may include multiple word lines 110 and multiple digit lines 115 . Thus, by activating the word line 110 and the digit line 115, the memory cell 105 at their intersection can be accessed. As described in more detail below, the effects of unintentional cross coupling can be mitigated by floating deselected access lines (eg, deselected word lines). For example, a plate may be coupled to a plurality of memory cells, which in turn may be coupled (directly or indirectly) to a plurality of word lines and a plurality of digit lines. During a period associated with an access operation of one memory cell, the word line associated with the remaining deselected memory cell associated with the plate may float. By floating the deselected word lines, the effects associated with cross coupling between the deselected word lines and the plate can be mitigated.

When accessed, the memory cell 105 may be read or sensed by the sensing component 125 to determine the stored state of the memory cell 105 . For example, after accessing the memory cell 105 , the ferroelectric capacitor of the memory cell 105 may be discharged onto the corresponding digit line 115 . Discharging the capacitor can be caused by biasing or applying a voltage to the capacitor. The discharge can cause a change in the voltage on the digit line 115 that the sensing component 125 can compare to a reference voltage (not shown) to determine the stored state of the memory cell 105 . Exemplary access operations are described below with reference to FIGS. 4A-4B and 5A-5B.

The sensing component 125 may include various transistors or amplifiers to detect and amplify differences in signals, which may be referred to as latching. The detected logic state of memory cell 105 may then be output via column decoder 130 as output 135 . In some cases, sensing component 125 may be part of column decoder 130 or row decoder 120 . Alternatively, the sensing component 125 may be connected or in electronic communication with the column decoder 130 or the row decoder 120 . As described in more detail below, deselected word lines may be floated for a period associated with an access operation to mitigate the effects associated with cross-coupling of word lines.

In some memory architectures, accessing the memory cell 105 may degrade or destroy a stored logic state, and a rewrite or refresh operation may be performed to return the original logic state to the memory cell 105 . For example, in DRAMs, capacitors can be partially or fully discharged during a sensing operation to corrupt stored logic states. Thus, the logic state can be rewritten after the sensing operation. Additionally, activating a single word line 110 may result in the discharge of all memory cells in a row; Accordingly, some or all of the memory cells 105 in a row may need to be rewritten. However, in a non-volatile memory, such as an array using a ferroelectric, accessing the memory cell 105 may not destroy the logic state, and thus the memory cell 105 may not require rewriting after access. In some examples, multiple levels of memory cells may be coupled to the same plate. Such a plate configuration may result in a smaller amount of area used to connect higher level memory cells to the substrate.

Some memory architectures, including DRAM, can lose their stored state over time unless they are periodically refreshed by an external power source. For example, a charged capacitor may discharge over time through leakage current, resulting in loss of stored information. The refresh rate of these so-called volatile memory devices can be relatively high, and for example, in the case of DRAM arrays, significant power consumption can occur due to tens of refresh operations per second. Increased power consumption due to increasingly larger memory arrays may impede the placement or operation of memory arrays (e.g., power supplies, heat generation, material limitations, etc.) can

Memory controller 140 operates (eg, reads, writes, rewrites, reads, writes, rewrites, refresh, discharge, etc.) can be controlled. In some cases, one or more of the row decoder 120 , the column decoder 130 , and the sensing component 125 may be co-located with the memory controller 140 . Memory controller 140 may generate row and column address signals to activate desired word lines 110 and digit lines 115 . Memory controller 140 may also generate and control various voltages or currents used during operation of memory array 100 . For example, a discharge voltage may be applied to the word line 110 or digit line 115 after accessing one or more memory cells 105 . In general, the amplitude, shape, or duration of the applied voltage or current discussed herein may be adjusted or varied and may be different for the various operations discussed in operating the memory array 100 . Moreover, one, multiple, or all memory cells 105 in memory array 100 may be accessed simultaneously; For example, many or all cells of memory array 100 may be accessed concurrently during a reset operation in which all memory cells 105 or groups of memory cells 105 are set to a single logic state.

In some examples, memory controller 140 can be configured to float one or more access lines (eg, word line 110 ) of memory array 100 for one or more periods associated with an access operation. For example, the memory controller 140 can identify an access operation associated with the selected memory cell 104 . Upon identifying the access operation, the memory controller 140 may initiate driving the plate (not shown) from the first voltage to the second voltage based at least in part on the access operation associated with the selected memory cell 105 . In some examples, the memory controller 140 provides an access line (eg, word line 110 ) to the deselected memory cell 105 based at least in part on an access operation associated with the selected memory cell 105 . Floating can be initiated. Memory controller 140 may be configured to initiate floating of the deselected access line before or at the same time as starting to drive the plate to the second voltage. Thus, during an access operation, the memory controller 140 controls other access lines of the memory array 100 (eg, other accesses associated with the deselected memory cells 105 sharing a plate with the selected memory cell 105 ). lines) while floating, one access line can be selected. By floating deselected access lines, an aspect of the memory array 100 differs from the deselected access lines (eg, a plate common to the selected memory cell 105 and one or more deselected memory cells 105 ). Undesirable effects associated with cross-linking between the two can be avoided or mitigated.

2 illustrates an example circuit 200 in accordance with various embodiments of the present disclosure. Circuit 200 includes a memory cell 105 - a, a word line 110 - a, a digit line 115 - a, and a sensing component 125 - a, which is the memory cell described with reference to FIG. 1 . 105 , word line 110 , digit line 115 , and sense component 125 , respectively. The memory cell 105 - a may include a logic storage component having a first plate, a cell plate 230 and a second plate, a cell bottom 215 , such as a capacitor 205 . Cell plate 230 and cell bottom 215 may be capacitively coupled via a ferroelectric material positioned therebetween. The orientation of the cell plate 230 and the cell bottom 215 can be flipped without changing the operation of the memory cell 105 - a. The circuit 200 also includes a selection component 220 and a reference line 225 .

Cell plate 230 can be accessed via plate line 210 and cell bottom 215 can be accessed via digit line 115 - a. In some cases, some memory cells 105 - a may share access lines (eg, digit lines, word lines, plate lines) with other memory cells. For example, digit line 115 - a can be shared with memory cells 105 - a in the same column, and word line 110 - a can be shared with memory cells 105 - a and plate line 210 in the same row. ) (and corresponding plate 230 ), and may be shared with memory cell 105 - a in the same section, tile, deck or even multiple decks. As described above, various states may be stored by the charging or discharging capacitor 205 . In many examples, a connector or socket may be used to couple the digit lines 115 - a or plate lines 210 of higher level levels of memory cells to a substrate located below the array of memory cells. The size of the connector or socket may be modified based on the plate line configuration of the memory array.

In some cases, a memory array 100 comprising a plate (not shown) associated with a plurality of memory cells 105 associated with a plurality of different word lines 110 and/or digit lines 115 is described herein. It can have its own unique access behavior. For example, if an deselected word line is held at a fixed voltage while the plate voltage changes, unwanted leakage or leakage due to capacitance between the deselected word line and the plate or between the deselected word line and one or more digit lines Power consumption may occur. Consequently, techniques are provided for mitigating or reducing the effects of such capacitances or cross-coupling during access operations of a memory array comprising a plate common to more than one memory cell 105 , which may be referred to as a common plate.

The stored state of capacitor 205 may be read or sensed by operating various elements represented in circuit 200 . Capacitor 205 may be in electronic communication with digit line 115 - a. For example, capacitor 205 may be insulated from digit line 115 - a when selection component 220 is inactive, and capacitor 205 may be insulated from digit line 115 - a when selection component 220 is activated. a) can be connected. Activating the selection component 220 may refer to selecting the memory cell 105 - a. In some cases, select component 220 is a transistor, and its operation is controlled by applying a voltage to the transistor gate whose voltage magnitude is greater than a threshold magnitude of the transistor. word line 110 - a can activate selection component 220 ; For example, a voltage applied to word line 110-a is applied to the transistor gate to connect capacitor 205 to digit line 115-a. As described in more detail below, an access operation (eg, a read operation or a write operation) may be performed based on the plate configuration of the memory array. For example, one or more deselected access lines (eg, deselected word lines, not shown) may be floated. By floating deselected access lines, negative cross-linking effects can be prevented or mitigated.

In other examples, the positions of selection component 220 and capacitor 205 may be switched such that selection component 220 is connected between plate line 210 and cell plate 230 and capacitor 205 is a digit line connected to be between 115 - a and the other terminal of the selection component 220 . In this embodiment, the selection component 220 may maintain electronic communication with the digit line 115 - a via the capacitor 205 . This configuration may involve alternative timing and biasing for read and write operations.

In some cases, due to the ferroelectric material between the plates of capacitor 205 , capacitor 205 may not discharge when connected to digit line 115 - a. In one approach, to sense the logic state stored in the ferroelectric capacitor 205 , the word line 110 - a may be biased to select the memory cell 105 , and a voltage will be applied to the plate line 210 . can In some cases, prior to biasing plate line 210 and word line 110 - a, digit line 115 - a is virtually grounded and then isolated from a virtual ground. Biasing the plate line 210 may result in a voltage difference across the capacitor 205 (eg, the plate line 210 voltage minus the digit line 115 - a voltage). The voltage difference may result in a change in the stored charge on the capacitor 205 , where the magnitude of the change in the stored charge depends on the initial state of the capacitor 205 , such as whether the initial state stores a logic one or a logic zero. can depend on the state. This may change the voltage on digit line 115 - a based on the charge stored in capacitor 205 . The operation of the memory cell 105 - a by varying the voltage across the cell plate 230 may be referred to as "moving the cell plate." As described in more detail below, some aspects of an access operation (eg, a read operation or a write operation) may be performed based on the plate configuration of the memory array.

The change in voltage on digit line 115 - a may depend on its intrinsic capacitance. That is, since charge flows through digit line 115 - a , some limited charge can be stored in digit line 115 - a and the resulting voltage depends on the intrinsic capacitance. The intrinsic capacitance may depend on physical properties including the dimensions of the digit line 115 - a. Since digit line 115 - a may connect many memory cells 105 , digit line 115 - a may have a length that results in a non-negligible capacitance (eg, a size in picofarads (pF)). ). The resulting voltage on digit line 115 - a is then applied to a reference (eg, the voltage on reference line 225 ) by sense component 125 - a to determine a logic state stored in memory cell 105 - a . ) can be compared with Other sensing processes may be used.

Sensing component 125 - a may include various transistors or amplifiers for detecting and amplifying differences in signals, which may be referred to as latching. Sense component 125 - a may include a sense amplifier that receives and compares voltages on digit line 115 - a and reference line 225 , which may be a reference voltage. The sense amplifier output may be driven to a higher (eg, positive) or lower (eg, negative or ground) supply voltage based on the comparison. For example, if digit line 115 - a has a higher voltage than reference line 225 , the sense amplifier output can be driven with a positive supply voltage.

In some cases, the sense amplifier may additionally drive the digit line 115 - a to a supply voltage. The sense component 125 - a may latch the output of the sense amplifier and/or the voltage of the digit line 115 - a, which determines the stored state of the memory cell 105 - a, eg, a logic one. can be used to Alternatively, if digit line 115 - a has a lower voltage than reference line 225 , the sense amplifier output may be driven to a negative or ground voltage. The sense component 125 - a may similarly latch the sense amplifier output to determine the stored state of the memory cell 105 - a, eg, a logic zero. The latched logic state of memory cell 105 - a may then be output via column decoder 130 , for example, as output 135 with reference to FIG. 1 .

To write memory cell 105 - a, a voltage may be applied across capacitor 205 . Various methods can be used. In one example, select component 220 can be activated via word line 110 - a to electrically connect capacitor 205 to digit line 115 - a. A voltage may be applied to capacitor 205 by controlling the voltages of cell plate 230 (via plate line 210 ) and cell bottom 215 (via digit line 115 - a ). To write a logic zero, the cell plate 230 can be taken high, ie a positive voltage can be applied to the plate line 210 and the cell bottom 215 is, for example, effectively grounded. Alternatively, it can be taken low by applying a negative voltage to digit line 115 - a. The reverse process is performed to write a logic one, where cell plate 230 takes low and cell bottom 215 takes high.

3 illustrates an example of a memory device 300 supporting techniques for managing access lines for an array of memory cells in accordance with examples of this disclosure. Memory device 300 may include a plurality of memory cells 305 coupled with one or more word lines 310 and one or more digit lines 315 to form an array 320 . Memory device 300 may include a plate 325 coupled with one or more memory cells 305 associated with a plurality of word lines 310 or a plurality of digit lines 315 of an array 320 . In some examples, memory array 320 may include a plurality of ferroelectric memory cells or other capacitor based memory cells.

For example, plate 325 may include memory cells 305 and/or first digit lines 315 - a, a second associated with first word line 310 - a and second word line 310 - b , A digit line 315 - b and a memory cell 305 associated with a third digit line 315 - c may be coupled. In some cases, a single plate 325 may be associated with any number of word lines 310 or memory cells 305 associated with (eg, coupled to) digit lines. The memory device 300 may be an example of or may be included in the memory array 100 described with reference to FIG. 1 .

In some examples, the quantity of plate nodes in the array of memory cells can be reduced compared to alternative architectures by having one or more plates each common to multiple memory cells. This may result in more efficient use of die area in the memory array and/or more efficient use of power during access operations. In some cases, plate drivers associated with plate 325 may be located external to memory array 320 , thereby providing more space for other components of array 320 . Also, by reducing the number of plates, the memory device 300 can be configured to reduce the number of plate drivers in the array of memory cells compared to an alternative architecture.

In some cases, a single plate 325 may be combined with memory cells 305 in different decks. In such a case, a single plate 325 may be combined with the memory cells of the first deck and the memory cells of the second deck. This arrangement can further reduce the plate and plate drivers in the array 320 .

Having a plate 325 common to multiple memory cells can create an associated risk of undesirable coupling between different components of the array 320 . During an access operation of a selected memory cell, deselected access lines (eg, deselected word lines) may be susceptible to cross coupling with one or more digit lines 315 and plate 325 during an access operation. have. In some cases, cross-coupling may result in a parasitic signal (e.g., between each deselected word line 310 and an individual digit line 315 and between each deselected word line 310 and a plate 325). , leakage current). Because these parasitic effects can occur on every deselected word line 310 , in a memory array comprising multiple word lines and multiple digit lines, the impact of such effects can be significant. In some examples, such cross-coupling and related effects can “disturb” the logic state stored in the deselected memory cell. For example, the parasitic signal may cause charge to be stored in the middle electrode of the deselected memory cell 305 . In some cases, this accumulation or other parasitic effect may result in additional power consumption by the memory device 300 .

During an access operation, typically only a small number of memory cells (eg, one or more) in a given segment of array 320 are accessed. In the illustrative example of FIG. 3 , memory cell 305 - b may be a memory cell selected for an access operation (eg, read, write, and/or precharge) and may include memory cells 305 - a, 305 - c, 305-d, 305-e, and 305-f) may be deselected memory cells. Each of these memory cells 305 is coupled to a common plate 325 . In this example, a parasitic signal (eg, due to unintentional capacitive cross-coupling) is transmitted between the deselected word line 310-b and the deselected digit line (eg 315-b, 315-c). and between each deselected word line and plate 325 .

In some cases, when the plate 325 is biased from a first state to a second state (eg, driven from a first voltage to a second voltage), a parasitic signal may occur between multiple components. For example, biasing plate 325 to a first voltage while maintaining deselected word lines 315-b and 315-c at a fixed voltage can be performed between each deselected word line and an individual digit line and Capacitance between each deselected word line and plate 325 can cause parasitic signals. To avoid or mitigate this undesirable effect, deselected word lines 315 - b and 315 - c may be floated relative to plate 325 . For example, if plate 325 is biased from a first voltage to a second voltage as part of an access operation to selected memory cell 305 - b, then deselected digit lines 315 - b and 315 - c are It can float as the voltage on the plate 325 changes, eventually tracking the voltage on the plate 325 (eg, maintaining a common difference).

These operations can be performed on any combination of deselected word lines. For example, the memory array may include a plurality of word lines (eg, 1024 word lines) and a plurality of digit lines (eg, 1024 digit lines). During a single access operation, a large number of word lines may be deselected (eg, 1023 deselected word lines). Plotting any combination of deselected word lines (e.g., any of 1023 deselected word lines) for a period associated with an access operation associated with the selected word line results in performance for the entire memory device 300 . can be improved (eg, reduced power consumption, increased reliability).

Memory cell 305 may be an example of memory cell 105 described with reference to FIG. 1 . In some cases, the memory cell 305 may be a ferroelectric memory cell, a DRAM memory cell, a NAND memory cell, a phase change memory cell, or any other type of memory cell. The word line 310 may be an example of the word line 110 described with reference to FIG. 1 . Digit line 315 may be an example of digit line 115 described with reference to FIG. 1 . Plate 325 may be an example of and related to plate 230 and/or plate line 210 described with reference to FIG. 2 .

As an example, FIG. 3 can illustrate a memory array 320 including a first memory cell 305 - a and a second memory cell 305 - f. As described above, the memory array 320 includes a plate 325 coupled with a first memory cell 305 - a and a second memory cell 305 - f, and a plate line coupled with the plate 325 . A driver (not shown) may be included. In some examples, a first access line 310 - a can be coupled to a first memory cell 305 - a, and an access line driver (not shown) can be coupled to a first access line 310 - a have. In some examples, the access line driver can be configured to float the first access 310 - a line for a duration based at least in part on an access operation associated with the second memory cell 305 - f. In some examples, each of memory cells 305 - a , 305 - b , 305 - c , 305 - d and 305 - e is floating for a duration based at least in part on an access operation associated with memory cell 305 - f . can be In some examples, the plate line driver can be configured to drive the plate 325 to the first voltage prior to a duration of time based at least in part on an access operation associated with the second memory cell 305 - f for a duration of time. The plate 325 may be configured to drive at the second voltage.

4A illustrates an example of a memory device 400 - a supporting techniques for access line management for an array of memory cells in accordance with examples of this disclosure. In some examples, the memory device 400 - a may include a driver 405 , which may be referred to as a memory driver 405 . Memory driver 405 may be coupled with any number of access lines and may enable access operations of one or more memory cells (eg, memory cells 305a - 305f described with reference to FIG. 3 ). have. The memory driver 405 may be coupled with an access line 420 , an access line 425 , an access line 430 , and an access line 435 , for example. Each of the access lines 420 , 425 , 430 , and 435 may be an example of a word line of a memory array (eg, the word line 310 - a , 310 - b described with reference to FIG. 3 ). The memory driver 405 may include various sub-components such as a driver component 410 and a driver component 415 . In other examples (not shown), the memory driver 405 can include any number of sub-components (eg, any number of driver components).

As noted above, each access line 420 , 425 , 430 , 435 may be an example of a word line of a memory array (eg, memory array 320 described with reference to FIG. 3 ). For example, the access line 420 may be referred to as a first access line 420 and the access line 425 may be referred to as a second access line 425 . Additionally or alternatively, access line 430 and access line 435 may be examples of access lines representing the total number of access lines associated with memory device 400 - a .

For example, access line 435 _{may be referred to as access line “AL n} ”, where “n” is the total number of access lines associated with the memory array, and access line 430 is referred to as access line “AL _{n ” -1} ". In some examples, the memory array associated with driver 405 may include 1024 access lines (eg, word lines), such that access line 430 may represent the 1023th access line of the memory array, Access line 435 may represent the 1024th access line of the memory array. Each of the access lines 420 , 425 , 430 , 435 may be associated with a respective individual memory cell - for example, no memory cell 105 can be associated with any one of the access lines 420 , 425 , 430 and 435 . It cannot be common across access lines 420 , 425 , 430 and 435 , whether associated with a single memory cell 105 or multiple memory cells 105 .

In some examples, the memory driver 405 may enable an access operation of a memory cell coupled with one of the access lines 420 , 425 , 430 or 435 . For example, an access operation may be performed on a memory cell coupled with access line 425 , which may be referred to as a second memory cell. A memory controller (eg, memory controller 140 described with reference to FIG. 1 ) may identify an access operation associated with the second memory cell. The driver 405 can then float the first access line 420 (eg, for a duration). In some examples, the driver 405 can float each of the access lines 420 - 435 other than the access line 425 . In other words, the driver 405 may float all deselected access lines associated with the selected memory cell and the memory cell 105 having a common plate. Floating the deselected access lines allows the voltage of each deselected access line to track the voltage of the associated plate (eg, plate 325 described with reference to FIG. 3 ).

In the examples described above, the memory driver 405 may include any number of sub-components, and each sub-component may be coupled with any number of access lines. For example, the memory driver 405 may include a separate driver component for each access line, and may include a separate driver component for each unique subset of access lines.

4B illustrates an example timing diagram 400 - b supporting techniques for access line management for an array of memory cells in accordance with examples of this disclosure. In some examples, timing diagram 400 - b can illustrate an access operation associated with memory device 400 - a as described above with reference to FIG. 4A . In some examples, timing diagram 400 - b shows voltages of plate line 440 , deselected access lines 445 , 445 - a , and selected access line 450 as described above with reference to FIG. 4A . can be exemplified. Timing diagram 400 - b illustrates the voltages on plate line 440 , deselected access lines 445 , 445 - a , and selected access line 450 during intervals 455 , 458 , 460 , 462 and 465 . can do.

As noted above, the memory array may include a plurality of individual access lines to a plurality of memory cells (eg, access lines 420 , 425 , 430 and 435 as described above with reference to FIG. 4A ). and each memory cell has a common plate. Each access line may be referred to as a word line and may be selected or deselected (eg, by a driver) based on a particular access operation. Any one access line may be selected during a particular access operation, and the remaining number of access lines associated with the plate may remain deselected during the operation. For example, a memory cell with a common plate may be associated with 1024 access lines (eg, word lines). Thus, during an access operation, one access line associated with the memory cell to be accessed may be selected (eg, selected access line 450 ) and the remaining number of access lines may remain deselected ( For example, deselected access lines (445, 445-a)). As described above with reference to FIG. 3 , a plate (eg, plate line 440 ) may be coupled with the memory array.

An access operation associated with the memory cell may be identified (eg, by the memory controller 140 described with reference to FIG. 1 ). At gap 455 , plate line 440 is shown initially driven to a first voltage (eg, a high voltage such as 1.5V). The selected access line 450 is shown driven with a high voltage (eg, 3V), and the deselected access line 445 is shown driven with a different voltage (eg, 0V). The deselected access line 445 may have a different voltage (e.g., 0V).

At spacing 458 , plate line 440 may transition from a first voltage (eg, a high voltage) to a second voltage (eg, a low voltage such as 0V). The selected access line 450 can be held at a high value (eg, 3V), and the deselected access line 445 can be floated. In some examples, the deselected access line 445 can float at the same time as the plate line 440 transitions to the second voltage, or when the voltage on the plate line 440 begins to transition. To ensure that 445 is floating, the deselected access line 445 may begin to float in some guard period before the plate line 440 transitions to the second voltage.

Due to the capacitive coupling between the deselected access line 445 and the plate line 440 , floating the deselected access line 445 causes the voltage on the deselected access line 445 to be the voltage can be tracked. In other words, as the voltage on the plate line 440 decreases during the interval 458 , it may lower the voltage on the floating deselected access line 445 by the same or substantially similar amount. For example, if the voltage on the plate line 440 decreases from 1.5V to 0V, the voltage on the deselected access line 445 may decrease from 0V to approximately -1.5V. Between the plate line 440 and the deselected access line 445 by allowing the voltage on the deselected access line 445 to track the voltage on the plate line 440 as the voltage on the plate line 440 changes. The voltage difference between s may be constant or may be kept substantially constant. Thus, as the voltage of plate line 440 changes, leakage current (eg, due to capacitive coupling between plate line 440 and deselected access line 445 ) can be reduced or eliminated and , the power consumption associated with the access operation can be reduced.

At interval 460 , plate line 440 can be maintained at a second voltage (eg, a low voltage such as 0V) and the selected access line 450 is maintained at a high voltage (eg, 3V). can be In some examples, the deselected access line 445 may continue to float throughout the interval 460 such that the voltage of the deselected access line 445 stays at the level obtained at the end of the interval 458 . (stay) In these examples, the difference between the voltage on the deselected access line 445 and the voltage on the plate line 440 during the gap 460 may not exactly match that during the gap 455 . For example, if the voltage on plate line 440 decreases from 1.5V to 0V, the voltage on deselected access line 445 approaches a level that is close to but not exactly equal from 0V to -1.5V during interval 458 ( For example, it may decrease to -1.4 V), and the voltage on the deselected access line 445 may remain at an approximate level (eg, -1.4 V) throughout the gap 460 .

In some examples, after floating, as shown in FIG. 4B by deselected access line 445 - a , deselected access line 445 changes the voltage of plate line 440 during interval 458 . may be driven with a desired low voltage based on The deselected access line 445 - a may be driven to a desired voltage based on a plate voltage swing such that, for example, subsequent connections between the plate line 440 and the deselected access line 445 - a The voltage difference is guaranteed to be the same as during interval 455 (eg, the voltage on the plate changes from 1.5V to 0V during interval 458 and the voltage on access line 445 deselected during interval 455 ) When this is 0V, the voltage on the deselected access line 445 can be driven to -1.5V to ensure a voltage difference of 1.5V).

In some examples, the deselected access lines 445 - a are either at the beginning of the interval 460 (eg, when the plate line 440 reaches the second voltage) or during the interval 460 (eg, For example, at time t') it can be driven to the desired voltage. In other examples, deselected access lines 445 - a can be driven to a desired voltage at the beginning of interval 460 . Driving the deselected access line 445 to the desired voltage to ensure a desired voltage difference (eg, the same voltage difference as that during interval 455) relative to the voltage on plate line 440 is ) may introduce some additional complexity as opposed to continuing to float the deselected access line 445 during , but may further reduce leakage current and associated power consumption as a result of voltage changes on the plate line 440 and , can provide greater control over the voltage of the deselected access line 445 during the interval 460 . Thus, the voltage on the deselected access line 445 can track the voltage on the plate line 440 .

At interval 462 , plate line 440 can be driven from a second voltage (eg, at a low voltage) to a first voltage (eg, at a high voltage). The selected access line 450 can be held at a high voltage (eg, 3V) and the deselected access line 445 can be floated (remain floating if floated for the interval 460, or selected For the unlocked access line 445 - a, the plate line 440 voltage starts to float before it starts to transition or at some guard period). Due to the capacitive coupling between the deselected access line 445 and the plate line 440 , floating the deselected access line 445 causes the voltage on the deselected access line 445 to flow across the plate line 440 . The voltage may be tracked (eg, substantially tracked). Accordingly, the voltage on the deselected access line 445 may increase as the voltage on the plate line 440 increases. By tracking the voltage on the plate line 440 , the voltage difference between the voltage on the plate line 440 and the voltage on the deselected access line 445 can be kept constant or substantially constant. Accordingly, the leakage current associated with the plate line 440 and the deselected access line 445 can be mitigated, and the power consumption of the associated memory device can be reduced.

At interval 465 , the selected access line 450 can be held at a high voltage (eg, 3V). Plate line 440 may return to a first voltage (eg, high voltage) as described in interval 455 , and deselected access line 445 may return to high voltage (eg, 0V). can be driven As noted above, the deselected access line 445 may be referred to as being at a high voltage (eg, 0V) due to the transition between the high voltage (eg, 0V) and the negative voltage.

Although the example of FIG. 4B is illustrated as transitioning from a high voltage to a low voltage back to a high voltage, in some examples, the techniques described herein allow plate line 440 to transition from a low voltage to a high voltage and back to a low voltage. can be applied when When the plate line 440 transitions from a low voltage to a high voltage or from a high voltage to a low voltage, it may be referred to as toggling or toggling the voltage of the plate line 440 . Regardless of the direction of toggling, deselected access lines 445 , 445 - a may float when the voltage on plate line 440 is toggled.

In various examples, plate toggling may occur, such that deselected access lines 445 , 445 - a may float at any time in connection with an access operation. For example, deselected access lines 445 , 445 - a can be floated (eg, read or written) before, during, or after the selected memory cell is accessed.

In some examples described herein, operations supporting techniques for access line management are described in the context of an array of memory cells having one common plate (ie, common to all memory cells in the array). It should be understood that the same techniques described herein may be supported by an array of memory cells comprising more than one common plate, wherein each plate may be common to a subset of memory cells in the array. Accordingly, the techniques described herein may be applied in the context of a memory array having any number of plates.

In the examples described herein, the absolute voltage levels described (eg, 3V, 0V, -1.5V, etc.) are for illustrative purposes only. Accordingly, any absolute voltage level(s) other than the absolute voltage levels described herein may be used.

5A illustrates an example of a memory device 500 - a that supports techniques for managing access lines for an array of memory cells in accordance with examples of this disclosure. In some examples, the memory device 500 - a may include a driver 505 , which may be referred to as a memory driver 505 . Memory driver 505 may be coupled with any number of access lines and may enable access operations of one or more memory cells (eg, memory cells 305a - 305f described with reference to FIG. 3 ). have. The memory driver 505 may be coupled with an access line 520 , an access line 525 , an access line 530 , an access line 535 , and an access line 537 , for example. Each access line 520 , 525 , 530 , 535 , 537 may be an example of a word line of a memory array (eg, word line 310 - a , 310 - b described with reference to FIG. 3 ). The memory driver 505 may include various sub-components such as a driver component 510 and a driver component 515 . In other examples (not shown), the memory driver 505 may include any number of sub-components (eg, any number of driver components).

As noted above, each access line 520 , 525 , 530 , 535 , 537 may be an example of a word line of a memory array (eg, memory array 320 described with reference to FIG. 3 ). For example, access line 520 may be or may be referred to as a first access line 520 , access line 525 may be or may be referred to as a second access line 525 , and access line 530 may be referred to as a second access line 525 . ) may be or may be referred to as the third access line 530 .

Additionally or alternatively, access line 430 and access line 435 can be examples of access lines representing the total number of access lines associated with memory device 500 - a . For example, access line 537 _{may be referred to as access line “AL n} ”, where “n” is the total number of access lines associated with the memory array, and access line 535 is access line “AL _{n ” -1} ". In some examples, the memory array associated with driver 505 may include 1024 access lines (eg, word lines), such that access line 535 may represent the 1023th access line of the memory array, Access line 537 may represent the 1024th access line of the memory array. Each of the access lines 520 , 525 , 530 , 535 , and 537 may be associated with a respective individual memory cell - for example, any memory cell 105 may be associated with an access line 520 , 525 , 530 , 535 , and No one of 537 may be common across access lines 520 , 525 , 530 , 535 , and 537 , regardless of whether it relates to a single memory cell 105 or multiple memory cells 105 .

In some examples, memory driver 505 may enable an access operation of a memory cell coupled with one of access lines 520 , 525 , 530 , 535 , and 537 . For example, an access operation may be performed on a memory cell coupled with access line 525 , which may be referred to as a second memory cell. In some examples, a memory controller (eg, memory controller 140 described with reference to FIG. 1 ) can identify an access operation associated with the second memory cell. The driver 505 can then float the first access line 520 (eg, for a duration). In another example, the driver 505 can float each of the access lines 520 - 537 other than the access line 455 . In other words, the driver 505 may float all deselected access lines associated with the selected memory cell and the memory cell 105 having a common plate. By plotting the deselected access lines, the voltage of each deselected access line can track the voltage of the associated plate (eg, plate 325 described with reference to FIG. 3 ).

In some examples, the driver 505 can float the deselected access line using multiple floating operations and/or multiple subcomponents. For example, a first subset of deselected access lines may be floated using a first floating operation and/or a first combination of subcomponents of driver 505 , and a second sub set of deselected access lines The set may be floated using a second floating operation and/or a second combination of subcomponents of the driver 505 . Since the driver 505 may be associated with all but one deselected access line depending on the size of the memory array (eg, associated with 1023 of 1024 deselected access lines), the first A first subset of deselected access lines floated using a floating operation and/or a first combination and a second set of deselected access lines floated using a second floating operation and/or a second combination of subcomponents The two subsets may have a total of 1023 access lines.

In some cases, a subcomponent of driver 505 (eg, driver component 510 ) includes a selected access line (eg, access line 520 ) and one or more deselected access lines (eg, Although common to access lines 525 and 530 ), one or more other subcomponents of driver 505 (eg, driver component 515 ) may be connected to a plurality of other deselected access lines (eg, access lines 535 and 537). In this example, driver component 510 may operate deselected access lines 525 , 530 unlike the way driver component 515 may operate deselected access lines 535 , 537 . For example, driver component 515 may operate deselected access lines 535 , 537 substantially as described with reference to FIG. 4 , while driver component 510 does not allow driver component 510 to be selected. Deselected access lines 525 , 530 can be driven with a voltage configured to minimize voltage stress on a component (eg, a transistor) in driver component 510 because it is common with access line 520 . have.

In the examples described above, the memory driver 505 may include any number of sub-components, and each sub-component may be coupled with any number of access lines. For example, the memory driver 505 may include a separate driver component for each access line or may include a separate driver component for each unique subset of access lines.

5B illustrates an example timing diagram 500 - b supporting techniques for access line management for an array of memory cells in accordance with examples of this disclosure. In some examples, timing diagram 500 - b can illustrate an access operation associated with memory device 500 - a as described above with reference to FIG. 5A . In some examples, timing diagram 500 - b shows a subset of plate line 540 , deselected access line 545 , 545 - a , selected access line 550 , and deselected access line 552 . voltage can be exemplified. Timing diagram 500 - b shows plate lines 540 , deselected access lines 545 and 545 - a , selected access lines 550 and deselected access lines 550 during intervals 555 , 558 , 560 , 562 and 565 . The voltage of a subset of the access lines 552 can be illustrated. In some examples, the subset of deselected access lines 552 includes selected access lines 550 and one or more drivers or driver components (eg, driver components 510 as described above with reference to FIG. 5A ). It may be or refer to a shared deselected access line.

As noted above, the memory array includes a plurality of individual access lines to a plurality of memory cells (eg, access lines 520 , 525 , 530 , 535 and 537 as described above with reference to FIG. 5A ). and each memory cell has a common plate. Each access line may be referred to as a word line and may be selected or deselected (eg, by a driver) based on a particular access operation. Any one access line may be selected during a particular access operation, and the remaining number of access lines associated with the plate may remain deselected during the operation. For example, a memory cell with a common plate may be associated with 1024 access lines (eg, word lines). Thus, during an access operation, one access line associated with the memory cell to be accessed may be selected (eg, selected access line 550 ), and the remaining number of access lines may remain deselected ( For example, deselected access lines (545, 545-a)). As described above with reference to FIG. 3 , a plate (eg, plate line 540 ) may be coupled with the memory array.

An access operation associated with the memory cell may be identified (eg, by the memory controller 140 described with reference to FIG. 1 ). At gap 555 , plate line 540 is shown initially driven to a first voltage (eg, a high voltage). The selected access line 550 is shown driven with a high voltage (eg, 3V), and the deselected access line 552 is shown driven with a different voltage (eg, 0V). A deselected access line 445 may be referred to as being at a different voltage (eg, 0V) because the deselected line may transition between a voltage (eg, 0V) and a negative voltage.

At interval 558 , plate line 540 can transition from a first voltage (eg, a high voltage) to a second voltage (eg, a low voltage). The selected access line 550 can be held at a high value (eg, 3V) and the deselected access line 545 can be floated. In some examples, deselected access line 545 may begin to float at the same time plate line 540 transitions to the second voltage, or deselected access line 545 may cause plate line 540 to transition to the second voltage. may start to float before transitioning to . Due to the capacitive coupling between the deselected access line and plate line 540 , floating the deselected access line 545 causes the voltage on the deselected access line 545 to track the voltage on the plate line 540 . can do. In other words, as the voltage on the plate line 540 decreases during the interval 558 , it can lower the voltage on the floating deselected access line 545 by an equal or substantially similar amount.

For example, if the voltage on plate line 540 decreases from 1.5V to 0V, the voltage on deselected access line 545 may decrease from 0V to approximately -1.5V. Between the plate line 540 and the deselected access line 545 by allowing the voltage on the deselected access line 545 to track the voltage on the plate line 540 as the voltage on the plate line 540 changes. The voltage difference between s may be constant or may be kept substantially constant. Thus, as the voltage of plate line 540 changes, leakage current (eg, due to capacitive coupling between plate line 540 and deselected access line 545 ) can be reduced or eliminated and , the power consumption associated with the access operation may be reduced.

At spacing 560 , plate line 540 may be maintained at a second voltage (eg, low voltage) and selected access line 550 may be maintained at a high voltage (eg, 3V). . In some examples, the deselected access line 545 may continue to float throughout the interval 560 such that the voltage of the deselected access line 545 stays at the level obtained at the end of the interval 558 . can be In these examples, the difference between the voltage on the deselected access line 545 and the voltage on the plate line 540 during the gap 560 may not exactly match that during the gap 555 . For example, if the voltage on plate line 540 decreases from 1.5V to 0V, the voltage on deselected access line 545 approaches a level that is close to, but not exactly equal to, 0V to -1.5V during interval 558 ( For example, it may decrease to -1.4 V), and the voltage on the deselected access line 545 may remain at an approximate level (eg, -1.4 V) throughout the interval 560 .

In some examples, after floating, as shown in FIG. 5B by deselected access line 545 - a , deselected access line 545 changes the voltage of plate line 540 during interval 458 . may be driven with a desired low voltage based on Deselected access line 545 - a can be driven to a desired voltage based on the plate voltage swing so that, for example, a subsequent voltage difference between plate line 540 and deselected access line 545 - a is guaranteed to be the same as during interval 555 (e.g., the voltage on the plate changes from 1.5V to 0V during interval 558, and the voltage on deselected access line 545 during interval 555 is 0V In this case, the voltage on the deselected access line 545 can be driven to -1.5V to ensure a voltage difference of 1.5V).

In some examples, deselected access lines 545 - a are either at the beginning of interval 560 (eg, when plate line 540 reaches a second voltage) or during interval 560 (eg, For example, at time t') it can be driven to the desired voltage. In other examples, deselected access lines 545 - a can be driven to a desired voltage at the beginning of interval 560 . Driving the deselected access line 545 to the desired voltage to ensure the desired voltage difference (eg, the same voltage difference as during the interval 555) relative to the voltage on the plate line 540 is ) may introduce some additional complexity as opposed to continuing to float the deselected access line 545 during , but may further reduce leakage current and associated power consumption as a result of changing the voltage on the plate line 540 and , can provide greater control over the voltage of the deselected access line 545 during the interval 560 . Thus, the voltage on the deselected access line 545 can track the voltage on the plate line 540 .

At interval 562 , plate line 540 can be driven from a second voltage (eg, at a low voltage) to a first voltage (eg, a high voltage). The selected access line 550 can be held at a high voltage (eg, 3V) and the deselected access line 545 can be floated (remain floating if floated for the interval 460, or selected For the unlocked access line 545 - a, the plate line 540 voltage starts to float before it starts to transition or at some guard period). Due to the capacitive coupling between the deselected access line 545 and the plate line 540 , floating the deselected access line 545 causes the voltage on the deselected access line 545 to rise from The voltage may be tracked (eg, substantially tracked). Accordingly, the voltage on the deselected access line 545 may increase as the voltage on the plate line 540 increases. By tracking the voltage on the plate line 540 , the voltage difference between the voltage on the plate line 540 and the voltage on the deselected access line 545 can be limited. Accordingly, the leakage current associated with the plate line 540 and the deselected access line 545 can be mitigated, and the power consumption of the associated memory device can be reduced.

At interval 565 , the selected access line 550 can be held at a high voltage (eg, 3V). Plate line 540 may return to a first voltage (eg, high voltage) as described in interval 555 , and deselected access line 545 may return to high voltage (eg, 0V). can be driven As noted above, the deselected access line 545 may be referred to as being at a high voltage (eg, 0V) due to the transition between the high voltage (eg, 0V) and the negative voltage.

As noted above, the subset of deselected access lines 552 may be maintained at a constant voltage (eg, 0V) across intervals 555 , 558 , 560 , 562 and 565 . Deselected access in which a subset of deselected access lines 552 share one or more driver components (eg, driver components 510 described above with reference to FIG. 5A ) with selected access lines 550 . As may be or refer to a line, this configuration may add additional complexity to the memory device (eg, memory device 500 - a described with reference to FIG. 5A ; the memory described with reference to FIG. 4A ) device (compare 400-a)). However, in some examples, such a configuration may reduce voltage stress and thus one or more transistors in common between the deselected access lines 545 , 545 - a and the selected access line 550 (eg, one or more transistors located within the driver component) may reduce the required voltage tolerance.

Additionally or alternatively, the voltage difference between the selected access line 550 and the subset of deselected access lines 552 may be determined by determining the selected access line 450 and the deselected access line as described above with reference to FIG. 4B . may be less than the voltage difference between (445, 445-a). For example, as described above with reference to FIG. 4B , the voltage difference between the selected access line 450 and the deselected access lines 445 , 445-a may be 4.5V (eg, -1.5V). deselected access lines at V (445, 445-a)); Access line selected at 3V). As described with reference to FIG. 5B , the voltage difference between the selected access line 450 and a subset of the deselected access lines 552 may be 3V (eg, 0V to the deselected access line ( 552); selected access lines at 3V). When the driver 505 includes multiple driver components 510, each driver component performs the operation of any one corresponding access line described with reference to the selected access line 550 while the deselected access line ( It can support any other corresponding access line operation described with reference to the subset of 552 , as well as deselected access line 545 depending on whether any access line corresponding to driver component 510 is selected. ) can support all corresponding access lines described with reference to

Although the example of FIG. 5B is illustrated as transitioning from a high voltage to a low voltage and back to a high voltage, in some examples, the techniques described herein allow the plate line 540 to move from a low voltage to a high voltage or to a high voltage. may be applied when transitioning from to a low voltage, which may be referred to as toggling or toggling the voltage on the plate line 540 . Regardless of the direction of toggling, deselected access lines 545 , 545 - a and/or a subset of deselected access lines 552 can float when the voltage on plate line 540 is toggled. have.

In various examples, plate toggling may occur, such that a subset of deselected access lines 545 , 545 - a and/or deselected access lines 552 may float at any time associated with an access operation. can For example, deselected access lines 545 , 545 - a and/or a subset of deselected access lines 552 may be used before, during, or after a selected memory cell is accessed (eg, read or written to). ) can be floated.

In some examples described herein, operations supporting techniques for access line management are described in the context of an array of memory cells having one common plate (ie, common to all memory cells in the array). It should be understood that the same techniques described herein may be supported by an array of memory cells comprising more than one common plate, wherein each plate may be common to a subset of memory cells in the array. Accordingly, the techniques described herein may be applied in the context of a memory array having any number of plates.

In the examples described herein, the absolute voltage levels described (eg, 3V, 0V, -1.5V, etc.) are for illustrative purposes only. Accordingly, any absolute voltage level(s) other than the absolute voltage levels described herein may be used.

6 shows a block diagram 600 of an access line manager 615 that supports access line management for an array of memory cells in accordance with an example of the present disclosure. Access line manager 615 may be an example of aspects of access line manager 715 described with reference to FIG. 7 . The access line manager 615 can include a biasing component 620 , a timing component 625 , a driving component 630 , an identification component 635 , a floating component 640 , and an initiation component 645 . Each of these modules may communicate with each other directly or indirectly (eg, via one or more buses).

Driving component 630 can drive a plate coupled with at least a first memory cell of the array of memory cells to a first voltage. In some examples, the driving component 630 can drive the plate from the first voltage to the second voltage based on an access operation associated with the second memory cell for a duration. In other examples, the driving component 630 can drive the first access line to a desired voltage after a duration based at least in part on a difference between the first voltage and the second voltage. Additionally or alternatively, the driving component 630 can drive the plate from the second voltage to the first voltage. In some examples, the driving component 630 can drive the second access line coupled with the second memory cell to the third voltage for a duration. In other examples, the driving component 630 can drive the third access line coupled with the third memory cell to the fourth voltage for a duration and simultaneously drive the plate from the first voltage to the second voltage.

Identification component 635 can identify an access operation associated with a second memory cell of the array of memory cells.

The floating component 640 can float a first access line coupled with a first memory cell of the array of memory cells for a duration based on an access operation associated with the second memory cell. In other examples, the floating component 640 can float the first access line after driving the first access line to a desired voltage and simultaneously drive the plate from the second voltage to the first voltage. In other examples, floating component 640 can float the first access line for a second duration immediately following the duration. Additionally or alternatively, floating component 640 can float the first access line and simultaneously drive the plate to a second voltage.

The initiating component 645 can initiate driving the third access line to the fifth voltage. The fifth voltage may be associated with a second logic value of the third memory cell. In some examples, the initiating component 645 can initiate driving the plate from the first voltage to the second voltage based on an access operation associated with the second memory cell. In some examples, initiating component 645 can initiate floating of the first access line based on an access operation associated with the second memory cell. Additionally or alternatively, initiating component 645 can initiate driving a third access line associated with a third memory cell of the set of memory cells to a third voltage based on an access operation associated with the second memory cell.

It should be understood that, in some examples, one or more components of access line manager 615 may be coupled (eg, biasing component 620 , driving component 630 , and floating component 640 ).

7 shows a diagram of a system 700 that includes a device 705 that supports access line management for an array of memory cells in accordance with examples of this disclosure. Apparatus 705 may be or include, for example, components of memory array 100 described above with reference to FIG. 1 . The device 705 includes an access line manager 715 , a memory cell 720 , a Basic Input/Output System (BIOS) component 725 , a processor 730 , an I/O controller 735 , and a peripheral component 740 . It may include a component for two-way voice and data communication including a component for transmitting and receiving communication. These components may communicate electronically via one or more buses (eg, bus 710 ).

Memory cell 720 may store information (ie, in the form of logic states) as described herein.

The BIOS component 725 is a software component including a firmware-operated BIOS capable of initializing and executing various hardware components. BIOS component 725 may also manage data flow between the processor and various other components, eg, peripheral components, input/output control components, and the like. BIOS component 725 may include programs or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

Processor 730 may be an intelligent hardware device (eg, a general purpose processor, DSP, central processing unit (CPU), microcontroller, ASIC, FPGA, programmable logic device, discrete gate or transistor logic component, discrete hardware component, or a combinations) may be included. In some cases, the processor 730 may be configured to operate a memory array using a memory controller. In other cases, the memory controller may be integrated into the processor 730 . Processor 730 may be configured to execute computer readable instructions stored in memory to perform various functions (eg, functions or tasks that support access line management for an array of memory cells).

I/O controller 735 may manage input and output signals to device 705 . The I/O controller 735 may also manage peripherals not integrated into the device 705 . In some cases, I/O controller 735 may represent a physical connection or port to an external peripheral. In some cases, the I/O controller 735 may use an operating system such as iOS®, Android®, MS-DOS®, MS-WINDOWS®, OS/2®, UNIX®, LINUX®, or other known operating systems. have. In other cases, I/O controller 735 may represent or interact with a modem, keyboard, mouse, touch screen, or similar device. In some cases, I/O controller 735 may be implemented as part of a processor. In some cases, a user may interact with device 705 via I/O controller 735 or a hardware component controlled by I/O controller 735 .

Peripheral component 740 may include any input or output device, or an interface for such a device. Examples include peripheral card slots such as disk controllers, sound controllers, graphics controllers, Ethernet controllers, modems, USB (Universal Serial Bus) controllers, serial or parallel ports, Peripheral Component Interconnect (PCI) or accelerated graphics port (AGP). can do.

Input 745 may represent a device or signal external to device 705 that provides an input to device 705 or a component thereof. This may include a user interface or an interface with or between other devices. In some cases, input 745 may be managed by I/O controller 735 and may interact with device 705 via peripheral component 740 .

The output 750 can also represent a device or signal external to the device 705 configured to receive an output from the device 705 or any of its components. Examples of output 750 may include displays, audio speakers, printing devices, other processors or printed circuit boards, and the like. In some cases, output 750 may be a peripheral element that interfaces with device 705 via peripheral component(s) 740 . In some cases, output 750 is can be managed

Components of device 705 may include circuitry designed to perform its functions. It may include various circuit elements configured to perform the functions described herein, for example, conductive lines, transistors, capacitors, inductors, resistors, amplifiers or other active or non-active elements. Device 705 may be a computer, server, laptop computer, notebook computer, tablet computer, mobile phone, wearable electronic device, personal electronic device, or the like. Alternatively, device 705 may be a part or aspect of such a device.

8 shows a flow diagram illustrating a method 800 for access line management for an array of memory cells in accordance with examples of this disclosure. The operations of method 800 may be implemented by a memory controller whose components described herein. For example, the operations of method 800 may be performed by the access line manager described with reference to FIG. 6 .

At 805 the memory array 100 plate coupled with at least a first memory cell of the array of memory cells may be driven to a first voltage. The operation of 805 may be performed according to the method described herein. In certain examples, aspects of the operations of 805 may be performed by the driving component described with reference to FIG. 6 .

At 810 , an access operation associated with a second memory cell of the array of memory cells may be identified. The operation of 810 may be performed according to a method described herein. In certain examples, aspects of the operations of 810 may be performed by the identification component described with reference to FIG. 6 .

At 815 , a first access line coupled with a first memory cell of the array of memory cells may be floated for a duration based at least in part on an access operation associated with the second memory cell. The operation of 815 may be performed according to the method described herein. In certain examples, aspects of the operations of 815 may be performed by the floating component described with reference to FIG. 6 .

At 820 , the plate may be driven from the first voltage to the second voltage for a duration based at least in part on an access operation associated with the second memory cell. The operation of 820 may be performed according to the method described herein. In certain examples, aspects of the operations of 820 may be performed by the driving component described with reference to FIG. 6 .

9 shows a flow diagram illustrating a method 900 for access line management for an array of memory cells in accordance with examples of this disclosure. The operations of method 900 may be implemented by a memory controller or a component thereof described herein. For example, the operations of method 900 may be performed by the access line manager described with reference to FIG. 6 .

At 905 , a plate coupled with at least a first memory cell of the array of memory cells may be driven to a first voltage. The operation of 905 may be performed according to a method described herein. In certain examples, aspects of the operations of 905 may be performed by the driving component described with reference to FIG. 6 .

At 910 an access operation associated with a second memory cell of the array of memory cells can be identified. The operation of 910 may be performed according to the method described in this application. In certain examples, aspects of the operations of 910 may be performed by the identification component described with reference to FIG. 6 .

At 915 , a first access line coupled with a first memory cell of the array of memory cells may be floated for a duration based at least in part on an access operation associated with the second memory cell. The operation of 915 may be performed according to the method described in the present application. In certain examples, aspects of the operations of 915 may be performed by the floating component described with reference to FIG. 6 .

At 920 , the plate may be driven from the first voltage to the second voltage based at least in part on an access operation associated with the second memory cell for a duration of time. The operation of 920 may be performed according to a method described herein. In certain examples, aspects of the operations of 920 may be performed by the driving component described with reference to FIG. 6 .

At 925 , the first access line may be driven to a desired voltage after a duration based at least in part on a difference between the first voltage and the second voltage. The operation of 925 may be performed according to the method described herein. In certain examples, aspects of the operations of 925 may be performed by the driving component described with reference to FIG. 6 .

10 shows a flow diagram illustrating a method 1000 for access line management for an array of memory cells in accordance with examples of this disclosure. The operations of method 1000 may be implemented by a memory controller or a component thereof described herein. For example, the operations of method 1000 may be performed by the access line manager described with reference to FIG. 6 .

At 1005 , a plate coupled with at least a first memory cell of the array of memory cells may be driven to a first voltage. The operation of 1005 may be performed according to a method described in the present application. In certain examples, aspects of the operations of 1005 may be performed by the driving component described with reference to FIG. 6 .

At 1010 , an access operation associated with a second memory cell of the array of memory cells can be identified. The operation of 1010 may be performed according to the method described in this application. In certain examples, aspects of the operations of 1010 may be performed by the identification component described with reference to FIG. 6 .

At 1015 , a first access line coupled with a first memory cell of the array of memory cells may be floated for a duration based at least in part on an access operation associated with the second memory cell. The operation of 1015 may be performed according to the method described in the present application. In certain examples, aspects of the operations of 1015 may be performed by the floating component described with reference to FIG. 6 .

At 1020 , the plate may be driven from the first voltage to the second voltage based at least in part on an access operation associated with the second memory cell for a duration of time. The operation of 1020 may be performed according to the method described in this application. In certain examples, aspects of the operations of 1020 may be performed by the driving component described with reference to FIG. 6 .

At 1025 , the first access line may be floated for a second duration immediately following the duration. The operation of 1025 may be performed according to the method described in this application. In certain examples, aspects of the operations of 1025 may be performed by the floating component described with reference to FIG. 6 .

In some cases, the method may include driving a plate coupled with at least a first memory cell of the array of memory cells to a first voltage. In some examples, floating the first access line and driving the plate to the second voltage can occur simultaneously. In other examples, the method can include floating a first access line coupled with a first memory cell of the array of memory cells for a duration based at least in part on an access operation associated with the second memory cell.

In some cases, the method can include driving the plate from the first voltage to the second voltage based at least in part on an access operation associated with the second memory cell for a duration of time. In some examples, the method can include driving the first access line to a desired voltage after a duration based at least in part on a difference between the first voltage and the second voltage. Additionally or alternatively, the method may include driving the plate from the second voltage to the first voltage. In other cases, the method may include identifying an access operation associated with a second memory cell of the array of memory cells.

In some cases, the method may include driving a second access line coupled with the second memory cell to a third voltage for a duration. In some examples, the method can include driving a third access line coupled with the third memory cell to a fourth voltage for a duration and simultaneously driving the plate from the first voltage to the second voltage. In some cases, the method may include floating the first access line for a second duration immediately following the duration. Additionally or alternatively, the plate may be coupled with a plurality of memory cells of the array of memory cells. The plurality of memory cells may include a first memory cell and a second memory cell.

In some cases, the plate may be associated with multiple rows or multiple columns of memory cells of a first deck of an array of memory cells, and with multiple rows or multiple columns of memory cells of a second deck of memory cells. can be In other cases, the method may include floating the first access line after driving the plate to the second voltage and simultaneously driving the plate from the second voltage to the first voltage.

11 illustrates an example of a circuit 1100 supporting techniques for managing access lines for an array of memory cells in accordance with examples of this disclosure. In some examples, circuit 1100 may include driver 1105 , which may in some cases be an example of a word line driver. Driver 1105 may be coupled with access line 1110 , which in some cases may be an example of a word line discussed in this application. Driver 1105 may enable an access operation of one or more memory cells coupled with access line 1110 . In some examples, circuit 1100 may be combined with or included in an access line decoder described herein, such as a word line decoder (or row decoder) or a digit line decoder (or column decoder).

Driver 1105 may be coupled with various control circuits, such as control circuitry 1115 , control circuitry 1120 , and control circuitry 1125 . Operation of driver 1105 and/or control circuitry 1115 , 1120 , and/or 1125 may enable an access operation of one or more memory cells described herein. It is noted that one or more structural or functional aspects of the control circuit 1115 , the control circuit 1120 , and the control circuit 1125 may in some cases be alternatively integrated into or otherwise considered part of the driver 1105 . It is understood.

In some examples, driver 1105 may represent one of a plurality of word line drivers of a memory device. For example, driver 1105 may represent one of 1,024 word line drivers of a memory device. It is to be understood that specific numbers herein and elsewhere are used only for clarity of description and not limitation of the scope of the claims. Each driver 1105 may include one or more transistors. For example, the driver 1105 may include a transistor 1130 (eg, a first transistor 1130 ) and a transistor 1135 (eg, a second transistor 1135 ). The first transistor 1130 and the second transistor 1135 may be arranged in a cascode configuration. The driver 1105 may also include a transistor 1140 (eg, a third transistor 1140 ) and a transistor 1145 (eg, a fourth transistor 1145 ). In some examples, the first transistor 1130 and the second transistor 1135 may be PMOS transistors, and the third transistor 1140 and the fourth transistor 1145 may be NMOS transistors.

In some examples, driver 1105 may include a node 1180 that may be referred to as an output node of driver 1105 and may be coupled with access line 1110 . Node 180 may also be coupled with the drain terminal of the second transistor 1135 , the source terminal of the fourth transistor 1145 , and the source terminal of the third transistor 1140 .

Driver 1105 may also include one or more nodes configured to receive control signals from control circuitry 1115 , 1120 and/or 1125 . For example, the driver 1105 can include a node 1170 (eg, a first node 1170 ) configured to receive a control signal 1160 from the control circuit 1125 . The node 1170 may refer to a terminal (eg, a source terminal) of the first transistor 1130 . In some examples, the control signal 1160 may be referred to as ARFX. The driver 1105 may also include a node 1185 (eg, a third node) configured to receive a control signal 1167 from the control circuit 1125 . The node 1185 may refer to the gate of the third transistor 1140 . Control signal 1185 may be referred to as ARFX' and may be inverted relative to control signal 1160 .

The word line driver may also include a node 1175 (eg, a second node) configured to receive a control signal 1165 from the control circuit 1120 . Node 1175 may refer to a terminal (eg, source terminal) of third transistor 1140 and a terminal (eg, source terminal) of fourth transistor 1145 , which may be coupled together. In some examples, the state of the control signal 1165 may be based on a setting of the control circuit 1120 .

In some examples, the driver 1105 may be configured to receive two control signals from the control circuit 1115 . The first control signal 1150 generated by the control circuit 115 may be referred to as MWLF_H and may be received at the gate of the transistor 1130 . Also, the gate of the fourth transistor 1145 may be configured to receive the second control signal 1155 from the control circuit 1115 . The control signal 1155 may be referred to as MWLF_L. In some examples, control signal 1150 can have a different (eg, higher) voltage swing than control signal 1155 .

The control circuit 1115 shown in FIG. 11 may be one of a plurality of control circuits 1115 of the memory device. For example, the control circuit 1115 may represent one of 64 control circuits 1115 of a memory device. That is, continuing the above example where 1,024 drivers 1105 are each coupled with each access line 1110 , a single control circuit 1115 can be coupled with 16 drivers 1105 . Thus, for each control circuit 1115 , the control signal 1150 and the control signal 1155 generated and output by the control circuit 1115 are common (received by each) to the 16 drivers 1105 . can

In some examples, as described above, the control signal 1150 may be applied to the gate of the transistor 1130 of the driver 1105 . For example, applying a control signal 1150 to the gate of transistor 1130 may cause the control signal to be in a low state (low voltage) or inactive (eg, turn off) because transistor 1130 may be a PMOS device. ), the transistor 1130 may be activated (eg, turned on) or deactivated (eg, turned off) when the control signal is in a high state (high voltage). Similarly, applying a control signal 1155 to the gate of transistor 1145 causes transistor 1145 to activate ( For example, it may be turned on) or it may be deactivated (eg, turned off) when the control signal is in a low state (low voltage).

The control signals 1150 and 1155 may have different voltage swings. For example, the voltage swing of the control signal 1155 may be less than the voltage swing of the control signal 1150 or vice versa. In some examples, each of the control signals 1150 and 1155 may be associated with the same lower bound (eg, 0V), but may have a different upper bound. For example, the upper limit of the control signal 1150 may be 3V and the upper limit of the control signal 1155 may be 1.5V. In some examples, a plurality of different control circuits 1115 within the same device may apply different control signals to different individual drivers 1105 during various phases of an access operation.

configure control circuit 1115 to generate two different control signals 1150 and 1155 and output them to driver 1105, further using two control signals 1150 and 1155 with different voltage swings, some placing excessive stresses (eg, undesirably high voltages) on one or more components (eg, transistors) of the driver 1105 in this case may be another advantage that will be appreciated by those skilled in the art. Among them, it can support the use of lower voltage tolerance devices and thus provide space, switching speed and efficiency advantages. Additionally or alternatively, including transistor 1130 and transistor 1135 in a cascode configuration may result in excessive stress (eg, undesirable) across one or more components (eg, transistors) of driver 1105 . undesirably high voltages) can be avoided, which can support the use of lower voltage tolerance devices and thus provide space, switching speed and efficiency advantages, among other advantages that will be recognized by those skilled in the art. .

The control circuit 1120 shown in FIG. 11 may be one of a plurality of control circuits 1120 of the memory device. For example, the control circuit 1120 may represent one of 16 control circuits 1120 of a memory device. That is, continuing the above example in which 1,024 drivers 1105 are each coupled to each access line 1110 , a single control circuit 1120 may be coupled to 64 drivers 1105 . Thus, for each control circuit 1120 , the control signal 1165 generated and output by the control circuit 1120 can be common (received by each) to the 64 drivers 1105 . The control circuit 1120 may be configured to apply a control signal 1165 to a respective node 1175 of each driver 1105 to which the control circuit 1120 is coupled.

In some examples, at different times during an access operation to one or more memory cells in the memory device, the control signal 1165 may drive the node 1175 to a relatively high voltage, which may be referred to as VNWL (eg, 0V). may drive node 1175 to a relatively low voltage, which may be referred to as VNNWL (eg, -1.5V, VNNWL), or electrically float (eg, FLOAT) node 1175 . can The state of the control signal 1165 may be based on one or more control signals received by the control circuit 1120 (eg, from a controller). The voltage swing between the possible voltages of the control signal 1165 may be equal to the voltage change of the plate of the memory device during an access operation. That is, the voltage swing between a relatively high voltage and a relatively low voltage may be 1.5V, which may be equal to the voltage change of the plate during an access operation (eg, when the plate changes from 1.5V to 0V). ). In some examples, a plurality of different control circuits 1120 within the same device may apply different control signals to different respective drivers 1105 during various phases of an access operation.

The control circuit 1125 shown in FIG. 11 may be one of a plurality of control circuits 1125 of the memory device. For example, control circuit 1125 may represent one of 16 control circuits 1125 of a memory device. That is, continuing the above example where 1,024 drivers 1105 are coupled with each access line 1110 , a single control circuit 1125 can be coupled with 64 drivers 1105 . Thus, for each control circuit 1125 , the control signals 1160 and 1167 generated and output by the control circuit 1125 can be common (received by each) to the 64 drivers 1105 . Each control circuit 1125 provides a control signal 1160 to each node 1185 and/or a control signal 1167 to each node 1170 of each driver 1105 to which the control circuit 1125 is coupled. ) can be configured to apply. In some cases, a control circuit 1125 may be associated with a corresponding control circuit 1120 such that both the control circuit 1125 and the corresponding control circuit 1120 may be coupled with the same set of drivers 1105 - That is, if two or more drivers 1105 are coupled with the same control circuit 1125 , they may also be coupled with the same control circuit 1120 .

In some examples, control circuit 1125 may include transistors 1190 , 1192 , 1194 . Transistors 1190 and 1192 may be NMOS transistors, and transistor 1194 may be PMOS transistors. In some examples, transistor 1190 may be arranged with transistor 1192 in a cas code configuration. In some examples, a terminal (eg, source terminal) of transistor 1194 may be coupled with a first voltage source (eg, VCCP) and a terminal (eg, source terminal) of transistor 1190 . may be coupled with another voltage source (eg, VSS). Transistors 1190, 1192, 1194 may include (implement) an inverter, but have an asymmetric number of transistors in the two legs of the inverter. Moreover, the control circuit 1125 may also include a second inverter 1196 that may be coupled with the gate of the transistor 1194 and/or the transistor 1190 .

The control circuit 1125 may be configured to output (eg, generate) a control signal 1160 and a control signal 1167 . Control signals 1160 , 1167 may be logic inverses of each other (eg, since the inverter formed by transistors 1190 , 1192 , 1194 is between the respective output nodes of control signals 1160 and 1167 ). That is, when one is high, the other is low.

In some examples, the control circuit 1125 may also be configured to float the node 1170 based on the FLOAT2 control signal. The FLOAT2 control signal may be received by (eg, from a controller) control circuitry 1125 , and when activated, the control signal 1160 may be electrically floated. In some examples, FLOAT2 can be the active row, and when FLOAT2 is high, transistors 1190 , 1192 , 1194 can act as an inverter in series with inverter 1196 . However, if FLOAT2 is low while the output of inverter 1196 is high, then control signal 1160 and thus node 1170 can be floated. For example, node 1170 indicates that transistor 1192 is simultaneously deactivated (e.g., off) because FLOAT2 is low because transistor 1194 is disabled (eg, off) because the output of inverter 1196 is high. For example, it may float because it is off). In some examples, a plurality of different control circuits 1125 within the same device may apply different control signals to different individual drivers 1105 during various phases of an access operation.

12A shows an example timing diagram 1200 - a supporting techniques for access line management for an array of memory cells in accordance with examples of this disclosure. In some examples, timing diagram 1200 - a may illustrate an access operation associated with (eg, executed using) circuit 1100 described above with reference to FIG. 1 . In some examples, timing diagram 1200 - a may illustrate voltages at plate line 1205 , word line 1110 - a , node 1170 - a , and node 1175 - a. The voltages of the word line 1110 - a , the node 1170 - a , and the node 1175 - a are the voltages applied to the access line 1110 , the node 1170 , and the node 1175 described with reference to FIG. 11 . can indicate Timing diagram 1200 - a will illustrate the voltages at plate line 1205 , word line 1110 - a , and nodes 1170 - a and 1175 - a during intervals 1210 , 1215 , 1220 , 1225 and 1230 . can

As described herein, a memory array may include a plurality of individual access lines (eg, a plurality of word lines) to a plurality of memory cells, each memory cell having a common plate. Each access line may be selected or deselected based on whether the cell associated with the access line is targeted (accessed) by a particular access operation (eg, driver 1105 described with reference to FIG. 11 ). by). In some cases, any one access line of a given type may be selected during a particular access operation, and the remaining number of access lines of the same type associated with the plate may remain deselected during the operation.

The timing diagram 1200 - a may illustrate an access operation associated with the circuit 1100 as described above with reference to FIG. 11 for a selected access line (eg, a selected word line). The memory cells associated with the selected access line may be accessed during one or more intervals illustrated in FIG. 12A .

During interval 1210 , the voltage on plate line 1205 is shown initially driven to a first voltage (eg, a high voltage such as 1.5V). While the plate is being driven at the first voltage, before the interval 1210 , the word line 1110 - a may be selected. 12A-12D , although the examples are described in terms of word lines, it should be understood that the teachings can be applied to any type of access line. In some examples, the selected word line may be represented by the voltage of the word line 1110 - a at a high voltage, such as 3V, at the beginning of the 1210 interval. To select word line 1110 - a, control circuit 1125 may apply high control signal 1160 to node 1170 (eg, by activating transistor 1194 ), which is an inverter may be based on a logic high signal received at the input of 1196), resulting in the voltage at node 1170 - a being driven to a high voltage, such as 3V. While node 1170 - a is at a high voltage, control circuit 1115 may apply low control signal 1150 to transistor 1130 . The row control signal 1150 may be, for example, 0V. When the control signals 1160 and 1150 are applied to the driver 1105 , the transistors 1130 and 1135 may be activated (eg, turned on). Accordingly, the voltage of the word line 1110 - a may be driven to 3V.

In some examples, the control circuit 1120 can apply a high control signal 1165 (eg, VNWL) to the node 1175 . Accordingly, the voltage at node 1175-a may be 0V. While node 1175 is 0V, control circuit 1115 may apply low control signal 1155 to transistor 1145 , and control circuit 1125 may apply low control signal 1167 to transistor 1140 . can be authorized The row control signals 1155 and 1167 may be, for example, 0V. Accordingly, when the control signals 1155 and 1167 are applied to the driver 1105 , the transistors 1140 and 1145 may be deactivated (eg, turned off). Thus, word line 1110 - a may be isolated from node 1175 .

During the interval 1215 , the voltage on the plate line 1205 may transition from a first voltage (eg, a high voltage) to a second voltage (eg, a low voltage such as 0V). The voltage of the selected word line 1110 - a and the voltage at node 1170 - a may be held high (eg, at 3V), and the voltage at node 1175 - a may be held low (eg, at 3V). , at 0V) can be maintained.

During interval 1220 , the voltage on plate line 1205 may be maintained at a second voltage (eg, a low voltage such as 0V). The voltage at word line 1110 - a and the voltage at node 1170 - a can be held high (eg, at 3V), and the voltage at node 1175 - a is held low (eg, at 3V) at 0V) can be maintained.

During interval 1225 , the voltage of plate line 1205 may be driven from a second voltage (eg, at a low voltage) to a first voltage (eg, a high voltage). The voltage of the selected word line 1110 - a and the voltage at node 1170 - a may be held high (eg, at 3V), and the voltage at node 1175 - a may be held low (eg, at 3V). , at 0V) can be maintained.

During the interval 1230 , the voltage on the plate line 1205 may be maintained at a first voltage (eg, a high voltage). The voltage at word line 1110 - a and the voltage at node 1170 - a can be held high (eg, at 3V), and the voltage at node 1175 - a is held low (eg, at 3V) at 0V) can be maintained. In the examples described herein, the absolute voltage levels described (eg, 3V, 0V, -1.5V, etc.) are for illustrative purposes only. Accordingly, any absolute voltage level(s) other than the absolute voltage levels described herein may be used.

In some examples, each of transistors 1130 , 1135 , 1140 , and 1145 in driver 1105 for selected word line 1110 - a has a relatively low gate-to-source voltage (eg, V _gs ) and /or a drain-source voltage (eg, V _ds ). For example, during an access operation, none of transistors 1130 , 1135 , 1140 , 1145 generates V _gs and/or V _ds (eg, MWLF_H, which may be 3V) greater than the voltage swing of control signal 1150 . don't have

12B shows an example timing diagram 1200 - b supporting techniques for access line management for an array of memory cells in accordance with examples of this disclosure. In some examples, timing diagram 1200 - b may illustrate an access operation associated with (eg, executed using) circuit 1100 described above with reference to FIG. 11 . In some examples, timing diagram 1200 - b may illustrate voltages at plate line 1205 , word line 1110 - b , node 1170 - b , and node 1175 - b . The voltages at the word line 1110-b, the node 1170-b, and the node 1175-b are the voltages applied to the access line 1110, the node 1170, and the node 1175 described with reference to FIG. can indicate Timing diagram 1200 - b illustrates the voltages at plate line 1205 , word line 1110 - b and nodes 1170 - b and 1175 - b during intervals 1210 , 1215 , 1220 , 1225 and 1230 . can

As described herein, a memory array may include a plurality of individual access lines (eg, a plurality of word lines) to a plurality of memory cells, each memory cell having a common plate. Each access line may be selected or deselected based on whether a cell associated with the access line is targeted (accessed) by a particular access operation (eg, to the driver 1105 described with reference to FIG. 11 ). due to). In some cases, any one access line may be selected during a particular access operation, and the remaining number of access lines of the same type associated with the plate may remain deselected during operation.

Timing diagram 1200 - a may illustrate an access operation associated with circuit 1100 as described above with reference to FIG. 11 for a first subset of deselected access lines. For example, timing diagram 1200 - b may illustrate the voltage of word lines 1110 - b sharing the same control circuit 1120 and control circuit 1125 as driver 1105 of the selected word line. (eg, selected word line 1110 - a discussed with reference to FIG. 12A ). Thus, continuing the above example where 1,024 drivers 1105 are coupled with each word line 1110, the voltage of the deselected word line 1110 - b is controlled equal to the driver 1105 of the selected word line. It can represent the voltage of 63 deselected word lines 1110 sharing circuit 1120 and control circuit 1125 .

During interval 1210 , the voltage on plate line 1205 is shown initially driven to a first voltage (eg, a high voltage such as 1.5V). While the plate is being driven at the first voltage, one word line 1110 - a may be selected prior to the interval 1210 , and a subset of the word lines 1110 may remain deselected. In some examples, the subset of word lines that remain deselected can be represented by the voltage of the remaining word lines 1110 - b with a low voltage, such as 0V. When a subset of word lines 1110-b is deselected but shares a common control circuit 1125 with the selected word line 1110-a, control circuit 1125 sends a high control signal 1160 to node 1170. ), which may result in the voltage of node 1170 - b being driven to a high voltage, such as 3V. While node 1170 - b is at a high voltage, control circuit 1115 - which may not be in common with the first subset of selected word lines 1110 - a and deselected word lines 1110 - b - A high control signal 1150 may be applied to the transistor 1130 . The high control signal 1150 may be, for example, 3V. Accordingly, when the control signals 1160 and 1150 are applied to the driver 1105 , the transistors 1130 and 1135 may be deactivated (eg, turned off). Accordingly, the deselected word line 1110 - b may be isolated from the node 1170 .

In some examples (eg, when the subset of word lines 1110 - b is not selected but shares a common control circuit 1120 with the selected word line 1110 - a), the control circuit 1120 is A high control signal 1165 (eg, VNWL) may be applied. For example, the voltage at node 1175-a may be 0V. While control signal 1165 is applied to node 1175 , control circuit 1115 may apply high control signal 1155 to transistor 1145 , and control circuit 1125 may apply low to transistor 1140 . A control signal 1167 may be applied. The high control signal 1155 may be, for example, 1.5V, and the low control signal 1167 may be 0V. Accordingly, when the control signals 1155 and 1167 are applied to the driver 1105 , the transistor 1145 may be activated (eg, turned on) and the transistor 1140 may be deactivated (eg, turned off). Thus, the deselected word line may be coupled to node 1175 via transistor 1145 , which may cause node 1175 and the deselected word line to have the same voltage (eg, 0V).

During the interval 1215 , the voltage on the plate line 1205 may transition from a first voltage (eg, a high voltage) to a second voltage (eg, a low voltage such as 0V). The voltage of the deselected word line 1110 - b may be held low (eg, at 0V) and the voltage at node 1170 - a may be held high (eg, at 3V). and the voltage at node 1175-a may be held low (eg, at 0V).

During interval 1220 , the voltage on plate line 1205 may be maintained at a second voltage (eg, a low voltage such as 0V). The voltage of the deselected word line 1110 - b may be held low (eg, at 0V) and the voltage at node 1170 - a may be held high (eg, at 3V). and the voltage at node 1175-a may be held low (eg, at 0V).

During interval 1225 , the voltage of plate line 1205 may be driven from a second voltage (eg, at a low voltage) to a first voltage (eg, a high voltage). The voltage of the deselected word line 1110 - b may be held low (eg, at 0V) and the voltage at node 1170 - a may be held high (eg, at 3V). and the voltage at node 1175-a may be held low (eg, at 0V).

During the interval 1230 , the voltage on the plate line 1205 may be maintained at a first voltage (eg, a high voltage). The voltage of the deselected word line 1110 - b may be held low (eg, at 0V) and the voltage at node 1170 - a may be held high (eg, at 3V). and the voltage at node 1175-a may be held low (eg, at 0V). In the examples described herein, the absolute voltage levels described (eg, 3V, 0V, -1.5V, etc.) are for illustrative purposes only. Accordingly, any absolute voltage level(s) other than the absolute voltage levels described herein may be used.

In some instances, choose ?サ? Each of transistors 1130 , 1135 , 1140 , and 1145 in driver 1105 for word line 1110 - b has a relatively low gate-to-source voltage (eg, V _gs ) and/or drain-to-source throughout the access operation. voltage (eg, V _ds ). For example, during an access operation, none of transistors 1130 , 1135 , 1140 , 1145 generates V _gs and/or V _ds (eg, MWLF_H, which may be 3V) greater than the voltage swing of control signal 1150 . don't have

12C shows an example timing diagram 1200 - c supporting techniques for managing access lines for an array of memory cells in accordance with examples of this disclosure. In some examples, timing diagram 1200 - c may illustrate an access operation associated with (eg, executed using) circuit 1100 described above with reference to FIG. 11 . In some examples, timing diagram 1200 - c may illustrate voltages at plate line 1205 , word line 1110 - c , node 1170 - c , and node 1175 - c . Timing diagram 1200 - c may also illustrate the replacement voltage of word line 1110 - c shown by the voltage trace labeled 1110 - c′. The voltages of the word line 1110 - c , the node 1170 - c , and the node 1175 - c are the voltages applied to the word line 1110 , the node 1170 , and the node 1175 described with reference to FIG. 11 . can indicate Timing diagram 1200 - c illustrates the voltages of plate line 1205 , word line 1110 - c , and nodes 1170 - c and 1175 - c during intervals 1210 , 1215 , 1220 , 1225 and 1230 . can

As described herein, a memory array may include a plurality of individual access lines (eg, a plurality of word lines) to a plurality of memory cells, each memory cell having a common plate. Each access line may be selected or deselected based on whether a cell associated with the access line is targeted (accessed) by a particular access operation (eg, to the driver 1105 described with reference to FIG. 11 ). due to). In some cases, any one access line may be selected during a particular access operation, and the remaining number of access lines of the same type associated with the plate may remain deselected during operation.

Timing diagram 1200 - c may illustrate an access operation associated with circuit 1100 as described above with reference to FIG. 11 for a subset of deselected access lines. For example, timing diagram 1200 - c shows a word line 1110 - c sharing another control circuit 1115 , another control circuit 1120 and another control circuit 1125 with the driver 1105 of the selected access line. ) (eg, selected word line 1110 - a discussed with reference to FIG. 12A ). Thus, continuing the above example with 1,024 drivers 1105 coupled with each word line 1110 , the voltage on the deselected word line 1110 - c is equal to that of the 945 deselected word line 1110 . voltage can be exemplified.

During interval 1210 , the voltage on plate line 1205 is shown initially driven to a first voltage (eg, a high voltage such as 1.5V). While the plate is being driven at the first voltage, before the interval 1210 , the subset of word lines 1110 - c may remain deselected. In some examples, the word lines 1110 - c that remain deselected can be represented by the voltage of the remaining word lines 1110 - c with a low voltage, such as 0V. If the subset of word lines is not selected and does not share the common control circuit 1125 with the selected word line 1110 - a , the control circuit 1125 applies the row control signal 1160 to the node 1170 . This may result in the voltage of node 1170 - c being driven to a low voltage such as 0V. While node 1170 - c is at a low voltage, the control circuit 1115 may apply a high control signal 1150 to the transistor 1130 . The high control signal 1150 may be, for example, 3V. Accordingly, when the control signals 1160 and 1150 are applied to the driver 1105 , the transistors 1130 and 1135 may be deactivated (eg, turned off). Accordingly, the deselected word line may be isolated from node 1170 .

In some examples, the control circuit 1115 can apply the high control signal 1155 to the transistor 1145 , and the control circuit 1125 can apply the high control signal 1167 to the node 1185 . In some examples, high control signal 1155 can be 1.5V and high control signal 1167 can be 1.5V. Accordingly, transistor 1145 may be activated (eg, on) and transistor 1140 may be activated (eg, on). Thus, deselected word line 1110 - c may be coupled with node 1175 via transistor 1140 and transistor 1145 , at a voltage equal to the output of control circuit 1120 (eg, control voltage equal to the voltage of signal 1165). During interval 1210 , control circuit 1120 may output control signal 1165 corresponding to VNWL, which may be, for example, 0V. Accordingly, the voltage at node 1175-c and the voltage at deselected word line 1110-c during interval 1210 may be 0V.

During the interval 1215 , the voltage on the plate line 1205 may transition from a first voltage (eg, a high voltage) to a second voltage (eg, a low voltage such as 0V). In some cases, during interval 1215 , node 1170 may also float, in which the voltage at node 1170 - c may float. For example, control circuit 1125 may receive the FLOAT2 control signal at the gate of transistor 1192, which may be low while the input to inverter 1196 is low, which may include control signal 1160 and This may cause node 1170 to float. Node 1170 indicates that transistor 1192 is disabled (e.g., off) because FLOAT2 is low because transistor 1194 is disabled (e.g., turned off) because the output of inverter 1196 is high. ), so it can be floated.

The control circuit 1120 may float the control signal 1165 and thus the node 1175 during the interval 1215 . As node 1175 is isolated from node 1170 and node 1175 is floating, the deselected word line 1110 - c may float. And due to the capacitive coupling between the deselected word line 1110 and the plate line 1205 , floating the deselected word line 1110 causes the voltage on the deselected word line 1110 to increase to the plate line 1205 . voltage can be tracked. In other words, as the voltage on the plate line 1205 decreases during the interval 1215 , it can lower the voltage on the floating deselected word line 1110 by an equal or substantially similar amount. For example, if the voltage on the plate line 1205 decreases from 1.5V to 0V, the voltage on the deselected access line 1105 may decrease from 0V to approximately -1.5V.

Thus, during the interval 1215 , the deselected access line 1105 may float by adjusting the control signal 1165 applied to the node 1175 . For example, the control circuit 1120 can output a FLOAT control signal 1165 that can float the deselected word line 1110 . Accordingly, the voltage of the deselected word line 1110 - c may be reduced to, for example, -1.4V.

During the interval 1220 , the voltage on the plate line 1205 may be maintained at a second voltage (eg, a low voltage such as 0V). In some examples, the deselected word lines 1110 - c can remain floating based on the control signal 1165 applied to the node 1175 .

In another example, deselected word line 1110 - c can be driven to a desired voltage during interval 1220 (eg, with deselected word lines 1110 - c during interval 1220 ). may be driven with a voltage such that the voltage difference between the deselected word lines 1110 - c during 1210 is equal to the voltage difference between the plate during interval 1220 and the plate during interval 1210). For example, during interval 1220 (eg, at time t′, which may be before, concurrently with, or after the beginning of interval 1220 ), another control signal 1165 may be applied to node 1175 . . Control signal 1165 may be VNNWL, which may be -1.5V. Accordingly, the deselected word line 1110 - c is coupled with the node 1175 so that the voltage of the deselected word line 1110 - c can be driven to -1.5V, which in some cases is shown in FIG. 12C ( As shown by the alternative voltage trace associated with 1110-c', it may be slightly different from the voltage of the deselected word line 1110-c when floated through gap 1220.

In some cases, during interval 1220 , node 1170 may continue to float as if it were at interval 1215 . In other examples, node 1170 can be driven at a low voltage for an interval 1220 such as 0V. Due to the potential capacitive coupling between the deselected word line 1110 and the plate 1205, the voltage at node 1170-c changes slightly (drifts) during the interval 1215 (e.g., reduced to a voltage slightly below 0V), and node 1170 can be driven to 0V during interval 1220 or another voltage based on expected drift during interval 1215 .

During interval 1225 , the voltage of plate line 1205 may be driven from a second voltage (eg, at a low voltage) to a first voltage (eg, a high voltage). The control circuit 1120 can output a FLOAT control signal 1165 that can float the deselected word line 1110 as described above with reference to the spacing 1215 . Accordingly, the voltage of the deselected word line 1110 - c may increase to -0.1V, for example. Additionally, the control circuit 1125 can float (eg, keep floating) the node 1170 as described with reference to the spacing 1215 .

During the interval 1230 , the voltage on the plate line 1205 may be maintained at a first voltage (eg, a high voltage). Control circuit 1120 can output high control signal 1165 (eg, VNWL), which can be, for example, 0V. Accordingly, the voltage at node 1175-c and the voltage at deselected word line 1110-c during interval 1230 may be 0V. Additionally or alternatively, during interval 1230 , node 1170 - c may be driven to 0V. In the examples described herein, the absolute voltage levels described (eg, -1.4 V, -1.5V, 3V, 0V, etc.) are for illustrative purposes only. Accordingly, any absolute voltage level(s) other than the absolute voltage levels described herein may be used.

In some examples, each of transistors 1130 , 1135 , 1140 , and 1145 in drivers 1105 for deselected word lines 1110 - c has a relatively low gate-to-source voltage (e.g., for example, V _gs ) and/or a drain-to-source voltage (eg, V _ds ). For example, during an access operation, none of transistors 1130 , 1135 , 1140 , 1145 generates V _gs and/or V _ds greater than the voltage swing of control signal 1150 (eg, MWLF_H, which may be 3V). don't have

Additionally or alternatively, the cascode configuration of transistors 1130 and 1135 allows plate line 1205 to be at a low voltage (eg, 0V) and deselected access line 1105 to a low voltage (eg, 0V). -1.4V), transistor 1130 may have a relatively low gate-to-source voltage (eg, V _gs ). Also, since control signals 1167 and 1155 may have relatively low voltage swings, transistor 1145 indicates that plate line 1205 is at a low voltage (eg, 0V) and deselected access line 1105 ) is at low voltage (eg -1.4V) to avoid _{excessive V gs .}

12D illustrates an example timing diagram 1200 - d supporting techniques for access line management for an array of memory cells in accordance with examples of this disclosure. In some examples, timing diagram 1200 - d can illustrate an access operation associated with (eg, executed using) circuit 1100 as described above with reference to FIG. 11 . In some examples, timing diagram 1200 - d can illustrate voltages at plate line 1205 , word line 1110 - d , node 1170 - d , and node 1175 - d . Timing diagram 1200 - d may also illustrate the replacement voltage of word line 1110 - d as shown by the voltage trace labeled 1110 - d′. The voltages at word lines 1110 - d and 1110 - d′, node 1170 - d and node 1175 - d are the voltages at word line 1110 , node 1170 and node 1175 described with reference to FIG. 11 . ) can be exemplified by the voltage applied to it. Timing diagram 1200-d shows plate line 1205, word line 1110-d (and word line 1110-d') and node 1170-d and node 1170-d during intervals 1210, 1215, 1220, 1225 and 1230. 1175-d) can be exemplified.

As described herein, a memory array may include a plurality of individual access lines (eg, a plurality of word lines) to a plurality of memory cells, each memory cell having a common plate. Each access line may be selected or deselected based on whether the cell associated with the access line is targeted (accessed) by a particular access operation (eg, the driver 1105 described with reference to FIG. 11 ). by). Any one access line may be selected during a particular access operation, and the remaining number of access lines of the same type associated with the plate may remain deselected during the operation.

Timing diagram 1200 - d may illustrate an access operation associated with circuit 1100 described above with reference to FIG. 11 for a subset of deselected access lines. For example, timing diagram 1200 - d shares the same control circuitry 1115 as driver 1105 of a selected access line (eg, selected word line 1110 - a discussed with reference to FIG. 12A ). may illustrate the voltage of word line 1110-d (and/or 1110-d′). Thus, continuing the above example where 1,024 drivers 1105 are coupled with each word line 1110 , the voltage on the deselected word line 1110 - d is equal to that of the 15 deselected word line 1110 . voltage can be exemplified.

During interval 1210, the voltage on plate line 1205 is shown initially driven to a first voltage (eg, a high voltage such as 1.5V). While the plate is driven to the first voltage, prior to the interval 1210 , a subset of the word lines 1110 may remain deselected. In some examples, the deselected word lines 1110 - d that remain deselected can be represented by the voltage of the remaining word lines 1110 - d at a low voltage, such as 0V. If the subset of word lines 1110 - d is not selected and does not share the control circuit 1125 with the selected word line 1110 - a , the control circuit 1125 sends a low control signal 1160 to node 1170 . ), which may result in the voltage at node 1170-d being driven to a low voltage, such as 0V. While node 1170 - d is at a low voltage, when a subset of word lines 1110 - d is unselected and shares the control circuit 1115 with the selected word line 1110 - a, the control circuit 1115 ) may apply the low voltage control signal 1150 to the transistor 1130 . The row control signal 1150 may be, for example, 0V. Accordingly, when the control signals 1160 and 1150 are applied to the driver 1105 , the transistors 1130 and 1135 may be deactivated (eg, turned off). Accordingly, the deselected word line may be isolated from node 1170 .

In some examples, when the subset of word lines 1110 - d is unselected and shares the control circuit 1115 with the selected word line 1110 - a , the control circuit 1115 is low on the transistor 1145 . A control signal 1155 may be applied and the control circuit 1125 may apply a high control signal 1167 to the node 1185 . In some examples, the low control signal 1155 can be 0V and the high control signal 1167 can be 1.5V. Accordingly, transistor 1145 can be deactivated (eg, off) and transistor 1140 can be activated (eg, on). Thus, deselected word line 1110 - d can be coupled with node 1175 via transistor 1140 , with a voltage equal to the output of control circuit 1120 (eg, the voltage of control signal 1165 ). the same voltage as ). During interval 1210 , control circuit 1120 may output control signal 1165 corresponding to VNWL, which may be, for example, 0V. Thus, the voltage at node 1175-d and the voltage at deselected word line 1110 - d during interval 1210 may be 0V.

During the interval 1215 , the voltage on the plate line 1205 may transition from a first voltage (eg, a high voltage) to a second voltage (eg, a low voltage such as 0V). Due to the capacitive coupling between the deselected word line 1110 and the plate line 1205 , floating the deselected word line 1110 causes the voltage on the deselected word line 1110 to be applied to the plate line 1205 . voltage can be tracked. In other words, as the voltage on the plate line 1205 decreases during the interval 1215 , it can lower the voltage on the floating deselected word line 1110 by an equal or substantially similar amount. For example, if the voltage on the plate line 1205 decreases from 1.5V to 0V, the voltage on the deselected access line 1105 may decrease from 0V to approximately -1.5V.

Thus, during the interval 1215 , the deselected access line 1105 may float by applying a different control signal 1165 to the node 1175 . For example, the control circuit 1120 can output a FLOAT control signal 1165 that can float the deselected word line 1110 . Accordingly, the voltage of the deselected word line 1110 - d may be reduced to, for example, -1.4V.

In some cases, during interval 1215 , node 1170 may also float. For example, the control circuit 1125 may receive the FLOAT2 control signal at the gate of the transistor 1192 , which may be low while the input to the inverter 1196 is low, which sends the control signal 1160 . may cause node 1170 to float accordingly. Node 1170 indicates that FLOAT2 is low because transistor 1192 is disabled (eg, off) because transistor 1194 is disabled (eg, off) because the output of inverter 1196 is high. Because of this, it can float.

During the interval 1220 , the voltage on the plate line 1205 may be maintained at a second voltage (eg, a low voltage such as 0V). In some examples, the deselected word lines 1110 - d can remain floating based on the control signal 1165 applied to the node 1175 . In other examples, deselected word lines 1110 may be driven to a desired voltage during interval 1220 . For example, during interval 1220 (eg, at time t′), another control signal 1165 may be applied to node 1175 . Control signal 1165 may be VNNWL, which may be -1.5V.

In some cases, during interval 1220 , node 1170 may continue to float as if it were at interval 1215 . In other examples, node 1170 can be driven at a low voltage for an interval 1220 such as 0V. Due to potential capacitive coupling between deselected word line 1110 and plate 1205, the voltage at node 1170-d changes slightly (drifts) during interval 1215 (e.g., reduced to a voltage slightly below 0V), and node 1170 can be driven to 0V during interval 1220 or another voltage based on expected drift during interval 1215 .

During interval 1225 , the voltage of plate line 1205 may be driven from a second voltage (eg, at a low voltage) to a first voltage (eg, a high voltage). The control circuit 1120 can output a FLOAT control signal 1165 that can float the deselected word line 1110 . Additionally, the control circuit 1125 can float (eg, keep floating) the node 1170 as described with reference to the spacing 1215 . During interval 1225, the voltage on deselected word line 1110-d (or 1110-d') may increase to -0.1V, for example.

During the interval 1230 , the voltage on the plate line 1205 may be maintained at a first voltage (eg, a high voltage). Control circuit 1120 can output high control signal 1165 (eg, VNWL), which can be, for example, 0V. Thus, during interval 1230 , the voltage at node 1175-d and the voltage at deselected word line 1110 - d (and 1110 - d′) may be 0V. Additionally or alternatively, during interval 1230 , node 1170 - d may be driven to 0V. In the examples described herein, the absolute voltage levels described (eg, -1.4 V, -1.5V, 3V, 0V, etc.) are for illustrative purposes only. Accordingly, any absolute voltage level(s) other than the absolute voltage levels described herein may be used.

In some examples, each of transistors 1130 , 1135 , 1140 , and 1145 in drivers 1105 for deselected word lines 1110 - d has a relatively low gate-to-source voltage (e.g., for example, V _gs ) and/or a drain-to-source voltage (eg, V _ds ). For example, during an access operation, none of transistors 1130 , 1135 , 1140 , 1145 generates V _gs and/or V _ds greater than the voltage swing of control signal 1150 (eg, MWLF_H, which may be 3V). don't have

Additionally or alternatively, the cascode configuration of transistors 1130 and 1135 allows plate line 1205 to be at a low voltage (eg, 0V) and deselected access line 1105 to a low voltage (eg, 0V). -1.4V), transistor 1130 may have a relatively low gate-to-source voltage (eg, V _gs ). Also, since control signals 1167 and 1155 may have relatively low voltage swings, transistor 1145 indicates that plate line 1205 is at a low voltage (eg, 0V) and deselected access line 1105 ) is at low voltage (eg -1.4V) to avoid _{excessive V gs .}

13 shows a block diagram 1300 of an access line manager 1315 that supports access line management for an array of memory cells in accordance with an example of the present disclosure. Access line manager 1315 may be an example of aspects of access line manager 1415 described with reference to FIG. 14 . The access line manager 1315 can include a biasing component 1320 , a timing component 1325 , a driving component 1330 , an identification component 1335 , a floating component 1340 , and an application component 1345 . Each of these modules can communicate with each other either directly or indirectly (for example, via one or more buses).

Driving component 1330 can drive a plate coupled with at least a first memory cell of the array of memory cells to a first voltage. In some examples, driving component 1330 can drive the plate from the first voltage to the second voltage for a duration based on an access operation associated with the second memory cell.

The identification component 1335 can identify an access operation associated with a second memory cell of the array of memory cells.

The floating component 1340 can float a first access line coupled with a first memory cell of the array of memory cells for a duration based on an access operation associated with the second memory cell. In other examples, the floating component 1340 is based on applying a first control signal having a first voltage swing and a second control signal having a second voltage swing different from the first voltage swing to the driver for the first access line. to float the first access line.

In some examples, the floating component 1340 can float the second node of the driver for at least a portion of the duration. The second node may include a source or a drain of the fourth transistor included in the driver. Floating the first access line may be based on floating the second node.

The application component 1345 may apply a fourth control signal to a third transistor included in the driver. The fourth control signal may be inverted relative to the third control signal and has a different voltage swing.

It should be understood that, in some examples, one or more components of access line manager 1315 may be coupled (eg, biasing component 1320 , driving component 1330 , and floating component 1340 ).

14 shows a diagram of a system 1400 including a device 1405 that supports access line management for an array of memory cells in accordance with an example of this disclosure. Device 1405 may be an example or include, for example, a component of memory array 100 as described above with reference to FIG. 1 . The device 1405 includes an access line manager 1415 , a memory cell 1420 , a basic input/output system (BIOS) component 1425 , a processor 1430 , an I/O controller 1435 , and a peripheral component 1440 . It may include a component for two-way voice and data communication, including a component for transmitting and receiving communication comprising a. The access line manager 1415 may be an example of the access line manager 1315 described with reference to FIG. 13 . These components may communicate electronically via one or more buses (eg, bus 1410 ).

Memory cell 1420 may store the information described herein (ie, in the form of logic states).

The BIOS component 1425 is a software component including a BIOS operating as firmware capable of initializing and executing various hardware components. BIOS component 1425 may also manage data flow between the processor and various other components, eg, peripheral components, input/output control components, and the like. BIOS component 1425 may include programs or software stored in read only memory (ROM), flash memory, or other non-volatile memory.

The processor 1430 may be an intelligent hardware device (eg, a general purpose processor, DSP, central processing device (CPU), microcontroller, ASIC, FPGA, programmable logic device, discrete gate or transistor logic component, discrete hardware component, or their combinations) may be included. In some cases, the processor 1430 may be configured to operate a memory array using a memory controller. In other cases, the memory controller may be integrated into the processor 1430 . The processor 1430 may be configured to execute computer readable instructions stored in memory to perform various functions (eg, functions or tasks that support access line management for an array of memory cells).

I/O controller 1435 may manage input and output signals to device 1405 . The I/O controller 1435 may also manage peripheral devices that are not integrated into the device 1405 . In some cases, I/O controller 1435 may represent a physical connection or port to an external peripheral device. In some cases, I/O controller 1435 may use an operating system such as iOS®, Android®, MS-DOS®, MS-WINDOWS®, OS/2®, UNIX®, LINUX®, or other known operating systems. have. In other cases, I/O controller 1435 may represent or interact with a modem, keyboard, mouse, touch screen, or similar device. In some cases, I/O controller 1435 may be implemented as part of a processor. In some cases, a user may interact with device 1405 through I/O controller 1435 or through hardware components controlled by I/O controller 1435 .

Peripheral component 1440 may include any input or output device, or an interface for such a device. Examples include disk controllers, sound controllers, graphics controllers, Ethernet controllers, modems, Universal Serial Bus (USB) controllers, serial or parallel ports, or peripheral card slots such as peripheral component interconnect (PCI) or accelerated graphics port (AGP) slots. can do.

Input 1445 may represent a device or signal external to device 1405 that provides an input to device 1405 or a component thereof. This may include a user interface or an interface with or between other devices. In some cases, input 1445 may be managed by I/O controller 1435 and may interact with device 1405 via peripheral component 1440 .

Output 1450 may also represent a device or signal external to device 1405 configured to receive output from device 1405 or any of its components. Examples of output 1450 may include displays, audio speakers, printed devices, other processors or printed circuit boards, and the like. In some cases, output 1450 can be a peripheral element that interfaces with device 1405 via peripheral component(s) 1440 . In some cases, output 1450 may be managed by I/O controller 1435 .

Components of device 1405 may include circuitry designed to perform its functions. It may include various circuit elements configured to perform the functions described herein, such as conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or non-active elements. Device 1405 may be a computer, server, laptop computer, notebook computer, tablet computer, mobile phone, wearable electronic device, personal electronic device, or the like. Alternatively, device 1405 may be part or an aspect of such a device.

15 shows a flow diagram illustrating a method 1500 for access line management for an array of memory cells in accordance with examples of this disclosure. The operations of method 1500 may be implemented by a memory controller or a component thereof described herein. For example, the operations of method 1500 may be performed by the access line manager described with reference to FIG. 6 .

At 1505 , a plate coupled with at least a first memory cell of the array of memory cells may be driven to a first voltage. The operation of 1505 may be performed according to the method described herein. In certain examples, aspects of the operations of 1505 may be performed by the driving component described with reference to FIG. 6 .

At 1510 an access operation associated with a second memory cell of the array of memory cells can be identified. The operation of 1510 may be performed according to the method described in this application. In certain examples, aspects of the operations of 1510 may be performed by the identification component described with reference to FIG. 6 .

At 1515 , a first access line coupled with a first memory cell of the array of memory cells may be floated for a duration based at least in part on an access operation associated with the second memory cell. In some examples, the floating can be based on applying a first control signal having a first voltage swing and a second control signal having a second voltage swing different from the first voltage swing to the driver for the first access line. The operation of 1515 may be performed according to the method described in this application. In certain examples, aspects of the operations of 1515 can be performed by the floating component described with reference to FIG. 2 .

At 1520 , the plate can be driven from the first voltage to the second voltage based, at least in part, on an access operation associated with the second memory cell, for a duration. The operation of 1520 may be performed according to the method described in this application. In certain examples, aspects of the operations of 1520 may be performed by the driving component described with reference to FIG. 6 .

In some examples, the method can include floating the first node of the word line driver for at least a portion of the duration. A first node of the word line driver may be configured to receive a third control signal, and floating the first access line may be based on floating the first node. In some examples, the first control signal may be applied to a gate of a transistor included in the driver, and the first node may include a source or drain of the transistor. In some examples, the transistor may be in a cas code configuration with a second transistor included in the driver.

In some examples, the fourth control signal may be applied to a third transistor included in the driver. The fourth control signal may be inverted relative to the third control signal and has a different voltage swing.

In some examples, the method can include floating the second node of the driver for at least a portion of the duration. The second node may include a source or a drain of the fourth transistor included in the driver. In some examples, floating the first access line can be based on floating the second node. In some examples, the second control signal may be applied to the gate of the fourth transistor.

The device is described. In some examples, an apparatus includes a memory cell coupled with the access line, a driver coupled with the access line, and a control circuit coupled with the driver and operable to generate a first control signal for the driver and a second control signal for the driver can do. In some examples, the second control signal may have a different voltage swing than the first control signal.

The apparatus may include a second control circuit coupled with the driver and operable to float the first node of the driver. In some examples, the driver may be operative to float the access line based on the first node being floated. The apparatus may include a third control circuit coupled to the driver and operable to float a second node of the driver. In some examples, the driver may be operative to float the access line based on the second node being floated.

In some examples, the driver is one of a subset of a set of drivers, and each driver in the set may be associated with a respective access line to a memory array comprising a memory cell. In some examples, a control circuit may be coupled with each driver of the subset, and the first control signal and the second control signal may be common to the drivers of the subset. In some examples, the apparatus can include a third control circuit coupled with the second subset of the driver set. The third control circuit is operable to generate a third control signal common to the second subset of drivers.

In some examples, the third control circuit may be further operable to generate a fourth control signal common to the drivers of the second subset. The fourth control signal may be inverted relative to the third control signal and have a different voltage swing.

The apparatus may include a controller coupled with a control circuit, a second control circuit, and a third control circuit. The controller identifies an access operation associated with a second memory cell of the memory array, the first node of the driver during a portion of the access operation associated with the second memory cell based on the second subset that the second control circuit does not include the driver It can operate to make it float. In some examples, the second memory cell can be coupled with a second access line coupled with a second driver of the set. The second subset may not include the second driver. In some examples, the driver may be operable to float the access line based at least in part on the first node being floated.

The controller identifies a second access operation associated with a third memory cell of the memory array and causes the second control circuit to drive the driver to the first voltage during an access operation associated with the third memory cell based on the second driver coupled with the second control circuit. It can operate to drive a node of A third memory cell may be coupled with a third access line coupled with a third driver of the set. In some examples, the third driver may be coupled with the second control circuit.

The apparatus may include a controller coupled with a control circuit, a second control circuit, and a third control circuit. The controller is configured to identify an access operation associated with a second memory cell of the memory array, wherein the third control circuitry is configured to cause the third control circuitry to operate at the second node of the driver during at least a portion of the access operation associated with the second memory cell based on the second driver coupled with the control circuitry. It can operate to make it float. In some examples, the second driver may be coupled with the control circuit. The driver is operable to float the access line based on the second node being floated.

In some examples, the controller identifies a second access operation associated with a third memory cell of the memory array, wherein during an access operation associated with the third memory cell based on the subset not including the third driver, the third control circuit and further operable to drive the second node to the first voltage or the second voltage. In some examples, the subset may not include the third driver.

The device is described. In some examples, a device includes a first transistor in a cascode configuration having a memory cell coupled with the access line, a driver coupled with the access line, the driver having a second transistor, and coupled with the driver and providing a first control signal. and a control circuit operable to output to the first transistor and output a second control signal to a third transistor of the driver.

In some examples, the device can include a second memory cell. The source of the first transistor and the source of the third transistor are operable to float concurrently with an access operation to the second memory cell. In some examples, the driver is operable to float the access line based on one or more of the source of the first transistor being floated or the source of the third transistor being floated.

The device is described. In some examples, the apparatus includes means for driving a plate coupled with a first memory cell of an array of memory cells to a first voltage, means for identifying an access operation associated with a second memory cell of the array of memory cells, a second Means for floating for a duration a first access line coupled with a first memory cell based at least in part on an access operation associated with the memory cell, wherein the floating includes a first control signal having a first voltage swing and a first voltage based at least in part on applying a second control signal having a second voltage swing different from the swing to the driver for the first access line and based at least in part on an access operation associated with the second memory cell for a duration of time. means for driving the plate from the first voltage to the second voltage.

In some examples, the apparatus may include means for floating a first node of the word line driver for at least a portion of a duration, the first node of the word line driver being configured to receive a third control signal, wherein Floating the first access line is based, at least in part, on floating the first node. In this example, the apparatus may include means for applying a fourth control signal to a third transistor included in the driver, wherein the fourth control signal is inverted with respect to the third control signal and has a different voltage swing. In some examples, the apparatus can include means for floating a second node of the driver for at least a portion of a duration, wherein the second node includes a source or drain of a fourth transistor included in the driver, wherein , floating the first access line is based, at least in part, on floating the second node.

It should be noted that the method described above describes possible implementations, and that the actions and steps may be rearranged or otherwise modified and that other implementations are possible. Moreover, examples from two or more methods may be combined.

The information and signals described herein may be represented using any of a variety of different technologies and technologies. For example, data, instructions, instructions, information, signals, bits, symbols, and chips that may be referenced throughout the above description include voltages, currents, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof. can be expressed as Some figures may illustrate a signal as a single signal; However, it will be understood by those skilled in the art that a signal may represent a bus of signals, wherein the bus may have various bit widths.

The terms “electronic communication” and “coupled” refer to a relationship between components that support electronic flow between the components. This may involve direct connections between components, or intermediate components may be involved. Electronic communications or components coupled to each other may or may not be actively exchanging electrons or signals (eg, in a powered circuit) or not actively exchanging electrons or signals (eg, in a de-energized circuit). ), however, can be configured and operated to exchange electrons or signals when the circuit is energized. For example, two components physically connected via a switch (eg, a transistor) may be in electronic communication or coupled regardless of the state of the switch (ie, open or closed).

As used herein, the term "substantially" means that the transformed property (e.g., a verb or adjective that is substantially modified by the term) need not be absolute, but must be close enough to achieve the advantage of the trait. means

The term “isolated” refers to a relationship between a component through which a signal cannot currently flow between the components; Components are isolated from each other if there is an open circuit between them. For example, two components physically connected by a switch can be isolated from each other when the switch is open.

The devices discussed herein, including the memory array 100 , may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, or the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be an epitaxial layer of semiconductor material on a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or other substrate. The conductivity of the substrate, or sub-regions of the substrate, can be controlled through doping using various chemical species including but not limited to phosphorus, boron or arsenic. Doping may be performed during initial formation or growth of the substrate, by ion implantation, or by any other doping means.

The transistor or transistors discussed in this application may be representative of a field effect transistor (FET) and may include a three terminal device including a source, a drain, and a gate. The terminals may be connected to other electronic elements through conductive materials such as metals. The source and drain may be conductive and may include heavily doped, eg, degenerate semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. When the channel is n-type (ie, the majority of carriers are electrons), the FET may be referred to as an n-type FET. When the channel is p-type (ie, the majority of carriers are holes), the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, a channel can become conductive by applying a positive or negative voltage to an n-type FET or a p-type FET, respectively. A transistor may be "on" or "activated" when a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate. A transistor may be “off” or “deactivated” when a voltage lower than the threshold voltage of the transistor is applied to the transistor gate.

The description set forth in this application in connection with the appended drawings describes exemplary configurations and does not represent all examples that may be implemented or are within the scope of the claims. As used herein, the terms “exemplary” and “exemplary” mean “serving as an example, instance, or illustration,” and are not “preferred” or “advantageous over other examples.” The detailed description includes specific details that provide an understanding of the described technology. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

Similar components or features in the accompanying drawings may have the same reference label. In addition, various components of the same type may be distinguished by a dash and a second label after a reference label that distinguishes similar components. If only the first reference label is used in the specification, the description is applicable to one of the similar components having the same first reference label irrespective of the second reference label.

The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, instructions, information, signals, bits, symbols, and chips that may be referenced throughout the above description include voltages, currents, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof. can be expressed as

The various illustrative blocks and modules described in connection with the disclosure of this application may be a general purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or perform the functions described herein. It may be implemented or performed in a combination of these designed to A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (eg, a combination of a digital signal processor (DSP) and a microprocessor, multiple microprocessors, one or more microprocessors in combination with a DSP core, or other such configuration).

The functions described in this application may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing functions may also be physically located at various locations, including distributed such that portions of functions are implemented at different physical locations. Also, as used in this application, including in the claims, "or" as used in a list of items (eg, a list of items initiated by a phrase such as "at least one of" or "one or more of") means "or" For example, a generic list is represented such that the list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (ie, A and B and C). Also, as used herein, the phrase “based on” should not be construed as a reference to a closed set of conditions. For example, exemplary steps described as “based on condition A” may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used in this application, the phrase “based on” should be interpreted in the same way as the phrase “based at least in part.”

Computer-readable media includes non-transitory computer storage media and communication media including any medium that enables transmission of a computer program from one place to another. Non-transitory storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer readable media may include RAM, ROM, EEPROM (Electrically Erasable Programmable Read Only Memory), CD (Compact Disk) ROM or other optical disk storage, magnetic disk storage or other magnetic storage device. , a general or special purpose computer or other non-transitory medium accessible by a general or special purpose processor and usable for carrying or storing the desired program code means in the form of instructions or data structures. Also, any connection is properly termed a computer-readable medium. For example, if the Software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology such as infrared, radio and microwave, coaxial cable; Fiber optic cables, duplex, DSL (Digital Subscriber Line) or wireless technologies such as infrared, radio and microwave are included in the media definition. Disc and disc used in the present application include CD, laser disc, optical disc, DVD (Digital Versatile Disc), floppy disc, and Blu-ray disc, and the disc is generally data Discs use lasers to reproduce data optically, while discs reproduce data magnetically. Combinations of the above are also included within the scope of computer-readable media.

The description herein is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined in this application may be applied to other modifications without departing from the scope of the disclosure. Accordingly, the present disclosure is not to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (20)

In the method,
driving a plate coupled with a first memory cell of the array of memory cells to a first voltage;
identifying an access operation associated with a second memory cell of the array of memory cells;
floating a first access line coupled with the first memory cell for a duration based at least in part on the access operation associated with the second memory cell, wherein the floating is a first voltage swing wherein the floating is based, at least in part, on applying a first control signal to a driver for the first access line to a driver for the first access line and a second control signal having a second voltage swing different from the first voltage swing; and
and driving the plate from the first voltage to a second voltage for the duration based at least in part on an access operation associated with the second memory cell. The method of claim 1,
for at least a portion of the duration, further comprising floating a first node of the driver, the first node of the driver configured to receive a third control signal, and floating the first access line is based, at least in part, on floating the first node. 3. The method of claim 2,
the first control signal is applied to a gate of a transistor included in the driver; and
and the first node comprises a source or drain of the transistor. 4. The method of claim 3, wherein the transistor is in a cascode configuration with a second transistor included in the driver. 3. The method of claim 2,
and applying a fourth control signal to a third transistor included in the driver, wherein the fourth control signal is inverted with respect to the third control signal and has a different voltage swing. The method of claim 1,
for at least a portion of the duration, floating a second node of the driver, the second node comprising the source or drain of a fourth transistor included in the driver, and connecting the first access line wherein the floating is based at least in part on floating the second node. 7. The method of claim 6, wherein the second control signal is applied to the gate of the fourth transistor. In the device,
a memory cell coupled with an access line;
a driver coupled to the access line; and
a control circuit coupled to the driver and operable to generate a first control signal for the driver and a second control signal for the driver, the second control signal having a different voltage swing than the first control signal A device comprising a control circuit. 9. The method of claim 8,
and a second control circuit coupled with the driver and operable to float a first node of the driver, wherein the driver is operable to float the access line based at least in part on the first node being floated. . 10. The method of claim 9,
and a third control circuit coupled with the driver and operable to float a second node of the driver, wherein the driver is operable to float the access line based at least in part on the second node being floated. . 9. The method of claim 8,
the driver is one of a subset of a set of drivers, each driver of the set coupled to a respective access line to a memory array comprising the memory cell;
the control circuit is coupled to each driver of the subset; and
and the first control signal and the second control signal are common to the subset of drivers. 12. The method of claim 11,
and a second control circuit coupled with a second subset of the set of drivers, wherein the drivers are one of the second subsets, the second subset comprising more drivers than the subset. . 13. The method of claim 12,
and a third control circuit coupled with a second subset of the set of drivers, wherein the third control circuit is operable to generate a third control signal common to the drivers of the second subset. 14. The method of claim 13, wherein the third control circuit is further operable to generate a fourth control signal common to the drivers of the second subset, the fourth control signal being inverted with respect to the third control signal and having a different voltage swing, the device. 14. The method of claim 13,
a controller coupled with the control circuitry, the second control circuitry, and the third control circuitry, the controller comprising:
identify an access operation associated with a second memory cell of the memory array, the second memory cell being coupled with a second access line coupled with a second driver of the set, the second subset using the second driver not including; and
operable to cause the second control circuit to float a first node of the driver during at least a portion of an access operation associated with the second memory cell based at least in part on the second subset not including the second driver and the driver is operable to float the access line based at least in part on the first node being floated. 16. The method of claim 15, wherein the controller,
identify a second access operation associated with a third memory cell of the memory array, the third memory cell coupled with a third access line coupled with a third driver of the set, the third driver causing the second control coupled with the circuit; and
further cause a second control circuit to drive the first node of the driver to a first voltage during an access operation associated with the third memory cell based at least in part on the second driver coupled with the second control circuit operable device. 14. The method of claim 13,
a controller coupled with the control circuitry, the second control circuitry, and the third control circuitry, the controller comprising:
identify an access operation associated with a second memory cell of the memory array, the second memory cell coupled with a second access line coupled with a second driver of the set, the second driver coupled with the control circuitry; ; and
operable to cause the third control circuit to float a second node of the driver based at least in part on the second driver coupled with the control circuit during at least a portion of an access operation associated with the second memory cell; and a driver operable to float the access line based at least in part on the second node being floated. The method of claim 17, wherein the controller comprises:
identify a second access operation associated with a third memory cell of the memory array, wherein the third memory cell is coupled with a third access line coupled with a third driver of the set, wherein the subset uses the third driver not including; and
cause the third control circuit to drive a second node of the driver to a first voltage or a second voltage during an access operation associated with the third memory cell based at least in part on the subset not including the third driver. a device further operable to do so. In the device,
a memory cell coupled with an access line;
a driver coupled to the access line, the driver comprising a second transistor and a first transistor in a cascode configuration; and
a control circuit coupled to the driver and operable to output a first control signal to a first transistor and output a second control signal to a third transistor of the driver. 20. The method of claim 19,
A second memory cell, further comprising a second memory cell, wherein the source of the first transistor and the source of the third transistor are operable to float concurrently with an access operation to the second memory cell, and wherein the driver is the source of the floating first transistor. or float the access line based at least in part on one or more of the sources of the third transistor.

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