CN112951292A

CN112951292A - Access line management for memory cell arrays

Info

Publication number: CN112951292A
Application number: CN202011238485.XA
Authority: CN
Inventors: D·维梅尔卡蒂
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2019-11-26
Filing date: 2020-11-09
Publication date: 2021-06-11
Also published as: KR20210065870A; KR102400518B1

Abstract

The present application relates to access line management of memory cell arrays. Some memory devices may include a plate coupled with memory cells associated with multiple digit lines and/or multiple word lines. Because the plate is coupled with multiple digit lines and/or word lines, unintended cross-coupling between various components of the memory device can be significant. To mitigate the effects of unintended cross-coupling between various components, the memory device may float unselected word lines during one or more portions of an access operation. Thus, the voltage of each unselected word line may be related to the voltage of the plate, as plate voltage changes may occur.

Description

Access line management for memory cell arrays

Cross-referencing

The present patent application claims priority from U.S. patent application No. 16/695,848 entitled "access line management FOR MEMORY cell ARRAYs" filed by Vimercati on 2019, 26, which is a partially-continued application OF U.S. patent application No. 15/971,639 entitled "access line management FOR MEMORY cell ARRAYs (ACCESS LINE MANAGEMENT FOR AN ARRAY OF MEMORY CELLS)" filed by Vimercati on 2018, 5, 4, each OF which is assigned to the present assignee and is expressly incorporated herein by reference in its entirety.

Technical Field

The technical field relates to access line management of memory cell arrays.

Background

The following relates generally to managing access to memory cells, and more particularly to access line management for an array of memory cells.

Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, binary devices have two states, often represented by a logical "1" or a logical "0". In other systems, more than two states may be stored. To access the stored information, components of the electronic device may read or sense the stored state in the memory device. To store information, components of an electronic device may write or program states in a memory device.

There are various types of memory devices, including magnetic hard disks, Random Access Memory (RAM), Read Only Memory (ROM), dynamic RAM (dram), synchronous dynamic RAM (sdram), ferroelectric RAM (feram), magnetic RAM (mram), resistive RAM (rram), flash memory, Phase Change Memory (PCM), and others. The memory devices may be volatile or non-volatile. Even in the absence of an external power source, a non-volatile memory, such as FeRAM, may maintain its stored logic state for an extended period of time. Volatile memory devices, such as DRAMs, may lose their stored state over time unless the volatile memory device is periodically refreshed by an external power source. FeRAM may use a similar device architecture as volatile memory, but may have non-volatile properties due to the use of ferroelectric capacitors as storage devices. Thus, FeRAM devices may have improved performance compared to other non-volatile and volatile memory devices.

In general, improving a memory device may include increasing memory cell density, increasing read/write speed, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics.

Disclosure of Invention

A method is described. In some examples, the method may include: driving a plate coupled with a first memory cell of the memory cell array to a first voltage; identifying an access operation associated with a second memory cell of the array of memory cells; floating a first access line coupled with the first memory cell for a duration based at least in part on the access operation associated with the second memory cell, wherein the floating is based at least in part on applying a first control signal having a first voltage swing and a second control signal having a second voltage swing different from the first voltage swing to a driver of the first access line and driving the plate from the first voltage to a second voltage during the duration based at least in part on the access operation associated with the second memory cell.

An apparatus is described. In some examples, the apparatus may include: the memory device includes a memory cell coupled with an access line, a driver coupled with the access line, and a control circuit coupled with the driver and operable to generate a first control signal for the driver and a second control signal for the driver, the second control signal having a different voltage swing than the first control signal.

An apparatus is described. In some examples, the apparatus may include: a memory cell coupled with an access line; a driver coupled with the access line, wherein the driver comprises a first transistor in a cascode configuration with a second transistor; and a control circuit coupled with the driver and operable to output a first control signal to the first transistor and a second control signal to a third transistor of the driver.

Drawings

FIG. 1 shows an example of a memory array supporting access line management for an array of memory cells, according to an example of the invention.

FIG. 2 shows an example of circuitry supporting techniques for access line management, according to an example of this disclosure.

FIG. 3 shows an example of a memory device supporting techniques for access line management, according to an example of the disclosure.

Fig. 4A and 4B show examples of memory devices and timing diagrams supporting techniques for access line management, according to examples of the invention.

Figures 5A and 5B show examples of memory devices and timing diagrams that support techniques for access line management, according to examples of this disclosure.

FIGS. 6 and 7 show block diagrams of devices that support techniques for access line management, according to examples of this disclosure.

Figures 8-10 show a method for access line management of a memory cell array, according to an example of the invention.

FIG. 11 shows an example of a circuit supporting techniques for access line management for an array of memory cells, according to an example of the invention.

12A-12D show example timing diagrams of techniques to support access line management for an array of memory cells, according to examples of this disclosure.

FIG. 13 shows a block diagram of an access line manager that supports access line management of an array of memory cells, according to an example of the invention.

FIG. 14 shows a diagram of a system including a device that supports access line management of an array of memory cells, according to an example of the invention.

FIG. 15 shows a method of access line management for an array of memory cells according to an example of the invention.

Detailed Description

Some memory arrays may include plates that are common to multiple memory cells, which are also associated with multiple digit lines and/or multiple word lines. Because the voltage of a plate (and thus also the voltage of the associated plate line) fluctuates in relation to the access operation for the selected memory cell, such as between a high voltage and a low voltage, some memory devices can maintain each word line (which can be referred to as an unselected word line) for unselected memory cells that are common to the plate at a fixed voltage. This may result in leakage currents and associated power losses due to capacitive (e.g., parasitic) cross-coupling associated with each unselected word line, such as between each unselected word line and a common plate or plate line. Where the plate is common to many memory cells, the amount of capacitance (e.g., parasitic capacitance) and unintended cross-coupling between the plate and unselected word lines can be significant, and thus, the amount of associated power loss can be significant. Parasitic signals due to such unintended cross-coupling, along with the additional power consumption of the memory array, can interfere with the logic states stored on unselected memory cells. For example, parasitic signaling may result in errors being introduced into the data by changing the state stored on the memory cell or by introducing errors into the access operation, among other effects.

Techniques are described herein for managing access lines (e.g., unselected access lines, unselected word lines) during access operations in a memory device that may include a plate common to memory cells associated (directly or indirectly) with multiple digit lines and/or multiple word lines. For example, to reduce or mitigate the effects of unintended cross-coupling, a memory device can float a plurality of unselected access lines (e.g., word lines) while changing the voltage of the plate. Thus, the memory device may float unselected word lines during one or more portions of an access operation for a selected memory cell, and in some cases, for a duration before or after the access operation. Floating the unselected access lines may facilitate the voltages of each unselected access line tracking the voltages of the plate and plate lines (e.g., maintaining a constant or near constant differential with the voltages of the plate and plate lines), resulting in overall lower power consumption of the memory array, and less resulting errors associated with the unselected memory cells. As used herein, floating a node may refer to electrically isolating the node from any defined voltage source.

The features of the invention introduced above are further described below in the context of fig. 1-3. Specific examples are then described with reference to fig. 4A-4B, 5A-5B, and 11 and 12A-12D. These and other features of the present invention are further illustrated by and described with reference to apparatus diagrams, system diagrams, and flow charts related to techniques for access line management of an array of memory cells.

FIG. 1 shows an example memory array 100 according to various embodiments of the invention. The memory array 100 may also be referred to as an electronic memory device. The memory array 100 includes memory cells 105 that are programmable to store different states. Each memory cell 105 may be programmable to store two states, represented as a logic 0 and a logic 1. In some cases, memory cell 105 is configured to store more than two logic states. Memory cell 105 may store a charge representing a programmable state in a capacitor; for example, charged and uncharged capacitors may represent two logic states, respectively. DRAM architectures may typically use such designs, and the capacitors used may include dielectric materials having linear or paraelectric polarization properties as insulators. In contrast, a ferroelectric memory cell may include a capacitor having a ferroelectric as an insulating material. Different charge levels of the ferroelectric capacitor may represent different logic states. The ferroelectric material has nonlinear polarization properties; some details and advantages of ferroelectric memory cell 105 are discussed below.

The memory array 100 may be a three-dimensional (3D) memory array, where two-dimensional (2D) memory arrays are formed on top of each other. This may increase the number of memory cells that can be formed on a single die or substrate, which in turn may reduce production costs or increase performance of the memory array, or both, as compared to a 2D array. According to the example depicted in FIG. 1, memory array 100 includes two levels of memory cells 105, and thus can be considered a three-dimensional memory array; however, the number of levels is not limited to two. Each level may be aligned or positioned such that memory cells 105 may be substantially aligned with each other across each level, forming a memory cell stack 145. In some cases, the memory array 100 may be referred to as a memory device 100.

Each row of memory cells 105 is connected to an access line 110, and each column of memory cells 105 is connected to a bit line 115. The access lines 110 and bit lines 115 may be substantially perpendicular to each other to create an array. Additionally, each row of memory cells 105 may be coupled to at least one plate line (not shown). As used herein, the terms board node, board line, or simply board may be used interchangeably. As shown in fig. 1, each memory cell 105 in memory cell stack 145 may be coupled to a separate conductive line, such as a bitline 115. In other examples (not shown), two memory cells 105 in memory cell stack 145 may share a common conductive line, such as bitline 115. That is, bit line 115 may be in electronic communication with a bottom electrode of upper memory cell 105 and a top electrode of lower memory cell 105. Other configurations may be possible, for example, the third bank may share access lines 110 with the lower bank. In general, one memory cell 105 may be located at the intersection of two conductive lines, such as access line 110 and bit line 115. This intersection may be referred to as the address of the memory cell. Target memory cell 105 may be memory cell 105 located at the intersection of powered access line 110 and bitline 115; that is, access line 110 and bit line 115 may be energized in order to read or write memory cell 105 at their intersection. Other memory cells 105 in electronic communication with (e.g., connected to) the same access line 110 or bitline 115 may be referred to as non-target memory cells 105.

As discussed above, electrodes may be coupled to memory cells 105 and access lines 110 or bit lines 115. The term electrode can refer to an electrical conductor, and in some cases can be used as an electrical contact to contact the memory cell 105. The electrodes may include traces, wires, conductive lines, conductive layers, or the like that provide a conductive path between elements or components of the memory array 100.

Operations such as reads and writes may be performed on memory cells 105 by activating or selecting access lines 110 and digit lines 115. The access lines 110 may also be referred to as word lines 110 and the bit lines 115 may also be referred to as digit lines 115. In general, the term access line may refer to a word line, a bit line, a digit line, or a plate line. References to word lines and bit lines or the like are interchangeable without losing understanding or operation. Activating or selecting a word line 110 or digit line 115 may include applying a voltage to the respective line. The word lines 110 and digit lines 115 may be made of conductive materials such as metals (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W), etc.), metal alloys, carbon, conductively doped semiconductors, or other conductive materials, alloys, compounds, or the like.

In some architectures, the logic storage of a cell (e.g., a capacitor) may be electrically isolated from the digit line by a select component. The word line 110 may be connected to and may control the select component. For example, the select component may be a transistor, and the word line 110 may be connected to the gate of the transistor. Activating a word line 110 causes an electrical connection or closed circuit between the capacitor of a memory cell 105 and its corresponding digit line 115. The digit lines can then be accessed to read or write to memory cells 105. Upon selection of memory cell 105, the resultant signal may be used to determine the stored logic state.

Access to the memory cells 105 may be controlled via a row decoder 120 and a column decoder 130. For example, the row decoder 120 may receive a row address from the memory controller 140 and activate the appropriate word line 110 based on the received row address. Similarly, column decoder 130 receives a column address from memory controller 140 and activates the appropriate digit lines 115. For example, the memory array 100 may include a plurality of word lines 110 and a plurality of digit lines 115. Thus, by activating word line 110 and digit line 115, memory cell 105 at its intersection can be accessed. As described in more detail below, by floating unselected access lines (e.g., unselected word lines), the effects of unintended cross-coupling can be mitigated. For example, a plate may be coupled with a plurality of memory cells, which in turn may be coupled (directly or indirectly) with a plurality of word lines and a plurality of digit lines. During a period associated with an access operation of one memory cell, word lines associated with remaining unselected memory cells coupled to the plate may be floated. By floating the unselected word lines, the effects associated with cross-coupling between the unselected word lines and the plate can be mitigated.

Upon access, the memory cell 105 may be read or sensed by the sensing component 125 to determine the stored state of the memory cell 105. For example, after accessing memory cell 105, the capacitor of memory cell 105 may discharge onto its corresponding digit line 115. Discharging the capacitor may be due to biasing to the capacitor or applying a voltage to the capacitor. The discharge may cause a voltage change of digit line 115 that sensing component 125 may compare to a reference voltage (not shown) in order to determine the stored state of memory cell 105. Exemplary access operations are described below with reference to fig. 4A-4B and 5A-5B.

The sensing component 125 may include various transistors or amplifiers in order to detect and amplify the difference of the signals, which may be referred to as latching. The detected logic state of memory cell 105 may then be output as output 135 via column decoder 130. In some cases, sensing component 125 may be part of column decoder 130 or row decoder 120. Alternatively, sensing component 125 can be connected to column decoder 130 or row decoder 120 or in electronic communication with column decoder 130 or row decoder 120. As described in more detail below, unselected word lines may be floated during periods associated with access operations to mitigate effects associated with cross-coupling of word lines.

In some memory architectures, accessing memory cell 105 may degrade or destroy the stored logic state, and a rewrite or refresh operation may be performed to return the original logic state to memory cell 105. In a DRAM, for example, the capacitor may partially or fully discharge during a sensing operation, destroying the stored logic state. Thus, the logic state may be rewritten after the sensing operation. Additionally, activating a single word line 110 may cause all of the memory cells in a row to discharge; thus, it may be desirable to rewrite some or all of the memory cells 105 in a row. But in non-volatile memories, such as those using arrays of ferroelectrics, accessing memory cell 105 may not destroy the logic state, and thus, memory cell 105 may not need to be rewritten after access. In some examples, multiple levels of memory cells may be coupled to the same plate. Such a plate configuration may result in a smaller amount of area to connect higher level memory cells to the substrate.

Some memory architectures that include DRAM may lose their stored state over time unless they are periodically refreshed by an external power source. For example, a charged capacitor may discharge over time via leakage current, resulting in loss of stored information. The refresh rate of these so-called volatile memory devices may be relatively high, for example, tens of refresh operations per second for DRAM arrays, which may result in significant power consumption. As memory arrays become larger, the increase in power consumption may inhibit the deployment or operation of the memory array (e.g., power supply, heat generation, material limitations, etc.), especially for mobile devices that rely on a limited power source, such as a battery.

The memory controller 140 may control the operation (e.g., read, write, rewrite, refresh, discharge, etc.) of the memory cells 105 via various components (e.g., the row decoder 120, the column decoder 130, and the sensing component 125). In some cases, one or more of the row decoder 120, column decoder 130, and sensing component 125 may be co-located with the memory controller 140. The memory controller 140 may generate row and column address signals in order to activate the desired word line 110 and digit line 115. The memory controller 140 may also generate and control various voltages or currents used during operation of the memory array 100. For example, it may apply a discharge voltage to the word line 110 or digit line 115 after accessing one or more memory cells 105. In general, the amplitude, shape, or duration of the applied voltages or currents discussed herein may be adjusted or varied, and may be different for the various operations discussed in operating the memory array 100. Furthermore, one, more, or all of the memory cells 105 within the memory array 100 may be accessed simultaneously; for example, multiple or all cells of the memory array 100 may be accessed simultaneously during a reset operation in which all memory cells 105 or a group of memory cells 105 are set to a single logic state.

In some examples, the memory controller 140 may be configured to float one or more access lines (e.g., word lines 110) of the memory array 100 during one or more periods associated with an access operation. For example, the memory controller 140 may identify an access operation associated with the selected memory cell 104. Upon identifying an access operation, memory controller 140 may initiate driving a plate (not shown) from a first voltage to a second voltage based at least in part on the access operation associated with the selected memory cell 105. In some examples, memory controller 140 can initiate floating an access line (e.g., word line 110) for unselected memory cells 105 based at least in part on an access operation associated with a selected memory cell 105. Memory controller 140 can be configured to initiate floating unselected access lines at the same time or prior to initiating driving the plate to the second voltage. Thus, during an access operation, memory controller 140 may select one access line while floating other access lines of memory array 100 (e.g., other access lines associated with unselected memory cells 105, unselected memory cells 105 sharing a plate with selected memory cells 105). By floating the unselected access lines, the undesirable effects associated with cross-coupling between the unselected access lines and other aspects of the memory array 100, such as plates common to the selected memory cell 105 and one or more unselected memory cells 105, can be avoided or mitigated.

FIG. 2 shows an example circuit 200 according to various embodiments of the invention. The circuit 200 includes a memory cell 105-a, a word line 110-a, a digit line 115-a, and a sensing component 125-a, which may be examples of a memory cell 105, a word line 110, a digit line 115, and a sensing component 125, respectively, as described with reference to FIG. 1. Memory cell 105-a may include a logic storage component, such as capacitor 205, having a first plate, cell plate 230, and a second plate, cell bottom 215. Cell plate 230 and cell bottom 215 may be capacitively coupled via a material, such as a ferroelectric material, positioned between cell plate 230 and cell bottom 215. The orientation of the cell plate 230 and the cell bottom 215 may be flipped without changing the operation of the memory cell 105-a. The circuit 200 also includes a select component 220 and a reference line 225.

Cell plate 230 may be accessed via plate line 210 and cell bottom 215 may be accessed via digit line 115-a. In some cases, some memory cells 105-a may share an access line (e.g., a digit line, a word line, a plate line) with other memory cells. For example, digit line 115-a may be shared with memory cells 105-a in the same column, word line 110-a may be shared with memory cells 105-a in the same row, and plate line 210 (and corresponding plate 230) may be shared with memory cells 105-a in the same sector, block, group, or even multiple groups. As described above, various states may be stored by charging or discharging the capacitor 205. In many examples, a connector or socket may be used to couple the digit line 115-a or plate line 210 of an upper level of memory cells to a substrate positioned below the memory cell array. The size of the connector or receptacle may be modified based on the configuration of the plateline in the memory array.

In some cases, a memory array 100 including a plate (not shown) coupled to a plurality of memory cells 105 associated with a plurality of different word lines 110 and/or digit lines 115 may have unique access operations as described herein. For example, if the unselected word lines are maintained at a fixed voltage when the plate voltage changes, the unselected word lines may cause undesirable leakage or power consumption due to capacitance between the unselected word lines and the plate or between the unselected word lines and one or more digit lines. Accordingly, techniques are provided herein for mitigating or reducing the effects of such capacitance or cross-coupling during access operations of a memory array that includes a plate that is common to more than one memory cell 105, which may be referred to as a common plate.

The stored state of the capacitor 205 may be read or sensed by operating the various elements represented in the circuit 200. Capacitor 205 may be in electronic communication with digit line 115-a. For example, capacitor 205 may be isolated from digit line 115-a when select component 220 is deactivated, and capacitor 205 may be connected to digit line 115-a when select component 220 is activated. Activating the select component 220 may be referred to as selecting the memory cell 105-a. In some cases, the select component 220 is a transistor, and its operation is controlled by applying a voltage to the transistor gate, where the voltage magnitude is greater than the threshold magnitude of the transistor. The word line 110-a may activate the select element 220; for example, a voltage applied to word line 110-a is applied to the transistor gate, connecting capacitor 205 with digit line 115-a. As described in more detail below, access operations (e.g., read operations or write operations) may be performed based on the plate configuration of the memory array. For example, one or more unselected access lines (e.g., unselected word lines; not shown) may be floated. By floating the unselected access lines, negative cross-coupling effects can be prevented or mitigated.

In other examples, the locations of the select element 220 and the capacitor 205 may be switched such that the select element 220 is connected between the plate line 210 and the cell plate 230 and such that the capacitor 205 is between the digit line 115-a and the other terminal of the select element 220. In this embodiment, selection component 220 may remain in electronic communication with digit line 115-a via capacitor 205. This configuration may be associated with alternative timing and bias voltages for read and write operations.

In some cases, capacitor 205 may not discharge upon connection to digit line 115-a due to the ferroelectric material between the plates of capacitor 205. In one scheme, to sense the logic state stored by ferroelectric capacitor 205, word line 110-a may be biased to select memory cell 105-a, and a voltage may be applied to plate line 210. In some cases, prior to biasing the plate line 210 and word line 110-a, the digit line 115-a is virtually grounded and then isolated from the virtual ground. Biasing plate line 210 may create a voltage differential across capacitor 205 (e.g., plate line 210 voltage minus digit line 115-a voltage). The voltage difference may cause a stored charge on the capacitor 205 to change, where the magnitude of the stored charge change may depend on the initial state of the capacitor 205 — e.g., whether the initial state stores a logic 1 or a logic 0. This may cause the voltage of digit line 115-a to change based on the charge stored on capacitor 205. Operating memory cell 105-a by varying the voltage of cell plate 230 may be referred to as "moving the cell plate". As described in more detail below, some aspects of an access operation (e.g., a read operation or a write operation) may be modified based on the plate configuration of the memory array.

The voltage change of digit line 115-a may depend on its intrinsic capacitance. That is, as charge flows through digit line 115-a, some finite charge may be stored in digit line 115-a, and the resulting voltage depends on the intrinsic capacitance. The intrinsic capacitance may depend on the physical characteristics of the digit line 115-a, including size. Digit line 115-a may connect many memory cells 105 and thus digit line 115-a may have a length that produces a non-negligible capacitance (e.g., on the order of micro-farads (pF)). The resulting voltage of digit line 115-a may then be compared by sensing component 125-a to a reference, such as the voltage of reference line 225, in order to determine a stored logic state in memory cell 105-a. Other sensing processes may be used.

The sensing component 125-a may include various transistors or amplifiers to detect and amplify the difference of the signals, which may be referred to as latching. Sense component 125-a may include a sense amplifier that receives and compares the voltages of digit line 115-a and reference line 225, which may be a reference voltage. The sense amplifier output may be driven to a higher (e.g., positive) or lower (e.g., negative or ground) supply voltage based on the comparison. For example, if digit line 115-a has a higher voltage than reference line 225, the sense amplifier output may be driven to a positive supply voltage.

In some cases, the sense amplifier may additionally drive the digit line 115-a to a supply voltage. Sense component 125-a may then latch the output of the sense amplifier and/or the voltage of digit line 115-a, which may be used to determine a stored state, such as a logic 1, in memory cell 105-a. Alternatively, if digit line 115-a has a lower voltage than reference line 225, the sense amplifier output may be driven to a negative or ground voltage. Sense component 125-a may similarly latch the sense amplifier output to determine a stored state, such as a logic 0, in memory cell 105-a. Referring to FIG. 1, the latched logic state of memory cell 105-a may then be output as output 135, e.g., via column decoder 130.

To write to memory cell 105-a, a voltage may be applied across capacitor 205. Various methods may be used. In one example, the select component 220 may be activated via the word line 110-a in order to electrically connect the capacitor 205 to the digit line 115-a. A voltage may be applied across capacitor 205 by controlling the voltage of cell plate 230 (via plate line 210) and cell bottom 215 (via digit line 115-a). To write a logic 0, cell plate 230 may be taken high, i.e., a positive voltage may be applied to plate line 210, and cell bottom 215 may be taken low, e.g., to virtually ground digit line 115-a or to apply a negative voltage to digit line 115-a. The reverse process is performed to write a logic 1, with cell plate 230 taken low and cell bottom 215 taken high.

FIG. 3 shows an example of a memory device 300 that supports techniques for access line management for an array of memory cells, according to an example of the invention. The memory device 300 may include a plurality of memory cells 305, the plurality of memory cells 305 coupled with one or more word lines 310 and one or more digit lines 315 to form an array 320. The memory device 300 may include a plate 325 coupled with one or more memory cells 305, the one or more memory cells 305 being associated with a plurality of word lines 310 or a plurality of digit lines 315 in an array 320. In some examples, memory array 320 may include a plurality of ferroelectric memory cells or other capacitor-based memory cells.

For example, the plate 325 may be coupled to memory cells 305 associated with a first word line 310-a and a second word line 310-b, and/or memory cells 305 associated with a first digit line 315-a, a second digit line 315-b, and a third digit line 315-c. In some cases, a single plate 325 may be coupled to memory cells 305 associated with (e.g., coupled to) any number of word lines 310 or digit lines. The memory device 300 may be an example of the memory array 100 described with reference to FIG. 1 or included in the memory array 100.

In some examples, by having one or more plates that are each common to multiple memory cells, the number of plate nodes in a memory cell array can be reduced relative to alternative architectures. This may result in more efficient use of die area in the memory array and/or more efficient use of power during access operations. In some cases, the plate drivers associated with plate 325 may be located outside of memory array 320, thereby providing more space for other components of array 320. In addition, by reducing the number of plates, the memory device 300 can be configured to reduce the number of plate drivers in the memory cell array relative to alternative architectures.

In some cases, a single plate 325 may be coupled with different sets of memory cells 305. In some such cases, a single plate 325 may be coupled with the memory cells of the first set and the memory cells of the second set. Such an arrangement may cause the boards and board drivers in array 320 to shrink even more.

Having a plate 325 that is common to multiple memory cells may create an associated risk of poor coupling between different components of the array 320. During an access operation of a selected memory cell, unselected access lines (e.g., unselected word lines) may be susceptible to cross-coupling with one or more digit lines 315 and plate 325 during the access operation. In some cases, cross-coupling may generate parasitic signals (e.g., leakage currents) between each unselected word line 310 and the respective digit line 315, and between each unselected word line 310 and the plate 325. Because such parasitic effects may occur at each unselected word line 310, the impact of such effects may be significant in memory arrays containing multiple word lines and multiple digit lines. In some examples, such cross-coupling and related effects may "disturb" the logic states stored on unselected memory cells. For example, parasitic signals may cause charge to be stored on the middle electrode of unselected memory cell 305. In some cases, such accumulation or other parasitic effects may result in additional power consumption by the memory device 300.

During an access operation, only a small number of memory cells (e.g., one or more) are typically accessed in a given segment of the array 320. In the illustrative example of FIG. 3, memory cells 305-b may be selected memory cells for access operations (e.g., read, write, and/or precharge), and memory cells 305-a, 305-c, 305-d, 305-e, and 305-f may be unselected memory cells. Each of these memory cells 305 is coupled with a common plate 325. In such examples, parasitic signals (e.g., due to unintended capacitive cross-coupling) may develop between the unselected word lines 310-b and the unselected digit lines (e.g., 315-b, 315-c) and between each of the unselected word lines and the plate 325.

In some cases, when plate 325 is biased from a first state to a second state (e.g., driven from a first voltage to a second voltage), parasitic signals may occur between several components. For example, biasing the plate 325 to a first voltage while maintaining the unselected word lines 315-b, 315-c at a fixed voltage may cause parasitic signals due to capacitance between each unselected word line and the respective digit line and between each unselected word line and the plate 325. To avoid or mitigate such undesirable effects, the unselected word lines 315-b, 315-c may be floated relative to the plate 325. For example, if plate 325 is biased from a first voltage to a second voltage as part of an access operation for the selected memory cell 305-b, the unselected digit lines 315-b, 315-c may be floated as the voltage of plate 325 changes, and the unselected digit lines 315-b, 315-c may in turn track the voltage of plate 325 (e.g., maintain a common differential with the voltage of plate 325).

Such operations may be carried out on any combination of unselected word lines. For example, a memory array may include a plurality of word lines (e.g., 1024 word lines) and a plurality of digit lines (e.g., 1024 digit lines). During a single access operation, a large number of word lines may be unselected (e.g., 1023 unselected word lines). Floating any combination of unselected word lines, such as any of the 1023 unselected word lines, during a period associated with an access operation associated with the selected word line, may result in improved performance (e.g., reduced power consumption, increased reliability) of the overall memory device 300.

Memory cell 305 may be an example of memory cell 105 described with reference to fig. 1. In some cases, memory cells 305 may be ferroelectric memory cells, DRAM memory cells, NAND memory cells, phase change memory cells, or any other type of memory cells. The word line 310 may be an example of the word line 110 described with reference to fig. 1. Digit line 315 may be an example of digit line 115 described with reference to figure 1. Plate 325 may be an example of plate 230 and/or plate line 210 described with reference to fig. 2, and may be associated with plate 230 and/or plate line 210.

As an example, FIG. 3 may depict a memory array 320 including a first memory cell 305-a and a second memory cell 305-f. As described above, memory array 320 may include a plate 325 coupled with first memory cell 305-a and second memory cell 305-f, and may include a plate-line driver (not shown) coupled with plate 325. In some examples, a first access line 310-a may be coupled with a first memory cell 305-a, and an access line driver (not shown) may be coupled with the first access line 310-a. In some examples, the access line driver may be configured to float the first access line 310-a for a duration based at least in part on an access operation associated with the second memory cell 305-f. In some examples, each of memory cells 305-a, 305-b, 305-c, 305-d, and 305-e may be floated for a duration based at least in part on an access operation associated with memory cell 305-f. In some examples, the plate-line driver may be configured to drive plate 325 to a first voltage before a duration and may be configured to drive plate 325 to a second voltage during the duration based at least in part on an access operation associated with the second memory cell 305-f.

FIG. 4A shows an example of a memory device 400-a that supports techniques for access line management for an array of memory cells, according to an example of the invention. In some examples, memory device 400-a may include driver 405, driver 405 may be referred to as memory driver 405. Memory driver 405 may be coupled with any number of access lines and may facilitate access operations of one or more memory cells (e.g., memory cells 305-a-305-f as described with reference to FIG. 3). Memory driver 405 may be coupled with, for example, access line 420, access line 425, access line 430, and access line 435. Each of the

access lines

420, 425, 430, and 435 may be an example of a word line (e.g., word lines 310-a, 310-b as described with reference to FIG. 3) of a memory array. Memory driver 405 may include various subcomponents, such as driver component 410 and driver component 415. In other examples (not shown), memory driver 405 may contain any number of subcomponents (e.g., any number of driver components).

As described above, each of

access lines

420, 425, 430, and 435 can be an example of a word line of a memory array (e.g., memory array 320 as described with reference to fig. 3). For example, access line 420 may be referred to as a first access line 420, and access line 425 may be referred to as a second access line 425. Additionally or alternatively,

access lines

430 and 435 can be examples of access lines representing a total number of access lines associated with memory device 400-a.

For example, access line 435 may be referred to as access line "AL_n", where" n "is the total number of access lines associated with the memory array, and access line 430 may be referred to as access line" AL_n-1". In some examples, the memory array associated with driver 405 may include 1024 access lines (e.g., word lines), so access line 430 may represent the 1023 rd access line of the memory array, and access line 435 may represent the 1024 th access line of the memory array. Each of

access lines

420, 425, 430, and 435 can be associated with a respective individual memory cell- -for example, no memory cell 105 can be common across

access lines

420, 425, 430, and 435, regardless of whether any of

access lines

420, 425, 430, and 435 are associated with a single memory cell 105 or multiple memory cells 105.

In some examples, memory driver 405 may facilitate access operations of memory cells coupled with one of

access lines

420, 425, 430, or 435. For example, an access operation may be performed on a memory cell coupled with access line 425, which may be referred to as a second memory cell. A memory controller (e.g., memory controller 140 as described with reference to fig. 1) may identify an access operation associated with the second memory cell. The driver 405 may then float (e.g., for a duration) the first access line 420. In some examples, driver 405 may float each of access lines 420-435 other than access line 425. In other words, driver 405 may float each unselected access line associated with memory cell 105, memory cell 105 having a common plate with the selected memory cell. Floating the unselected access lines may cause the voltage of each unselected access line to track the voltage of the associated plate (e.g., plate 325 as described with reference to fig. 3).

In the examples described above, memory driver 405 may include any number of subcomponents, and each subcomponent may be coupled with any number of access lines. For example, memory driver 405 may include a separate driver component for each access line, may include a separate driver component for each unique subset of access lines.

FIG. 4B depicts an example timing diagram 400-B of a technique to support access line management for an array of memory cells, according to an example of the invention. In some examples, timing diagram 400-b may depict access operations associated with memory device 400-a as described above with reference to FIG. 4A. In some examples, timing diagrams 400-b may depict the voltages of plate lines 440, unselected access lines 445, 445-a, and selected access line 450 as described above with reference to FIG. 4A. Timing diagram 400-b may depict the voltages of plateline 440, unselected access lines 445, 445-a, and selected access line 450 during

intervals

455, 458, 460, 462, and 465.

As described above, the memory array may include a plurality of respective access lines (e.g.,

access lines

420, 425, 430, and 435 as described above with reference to FIG. 4A) for a plurality of memory cells, each having a common plate. Each access line may be referred to as a word line and may be selected or unselected (e.g., by a driver) based on a particular access operation. Any one access line may be selected during a particular access operation, and the remaining number of access lines associated with a plate may remain unselected during that operation. For example, memory cells for which a plate is common may be associated with 1024 access lines (e.g., word lines). Thus, during an access operation, one access line associated with the memory cell to be accessed may be selected (e.g., selected access line 450), and the remaining number of access lines may remain unselected (e.g., unselected access lines 445, 445-a). As described above with reference to fig. 3, a plate (e.g., plate line 440) may be coupled with the memory array.

An access operation associated with the memory cell may be identified (e.g., by the memory controller 140 as described with reference to fig. 1). At interval 455, plate line 440 is shown initially driven to a first voltage (e.g., a high voltage, such as 1.5V). The selected access line 450 is shown driven to a high voltage (e.g., 3V) and the unselected access lines 445 are shown driven to a different voltage (e.g., 0V). The unselected access lines 445 may be referred to as being at different voltages (e.g., 0V) because the unselected lines may transition between the voltages (e.g., 0V) and negative voltages during the intervals depicted in fig. 4B.

At interval 458, plate line 440 may transition from a first voltage (e.g., a high voltage) to a second voltage (e.g., a low voltage, such as 0V). The selected access lines 450 may remain at a high value (e.g., 3V), and the unselected access lines 445 may be left floating. In some examples, unselected access lines 445 may be floated concurrently with the plate line 440 transitioning to the second voltage, or unselected access lines 445 may begin to float at some guard period before the plate line 440 transitions to the second voltage to ensure that the unselected access lines 445 are floating as the voltage of the plate line 440 begins to transition.

Floating the unselected access lines 445 may cause the voltage of the unselected access lines 445 to track the voltage of the plate lines 440 due to capacitive coupling between the unselected access lines 445 and the plate lines 440. In other words, as the voltage of plate line 440 decreases during interval 458, it may pull down the voltage of the floating unselected access lines 445 by an equal or substantially similar amount. For example, if the voltage of plate line 440 is reduced from 1.5V to 0V, the voltage of unselected access lines 445 may be reduced from 0V to or about-1.5V. By allowing the voltage of unselected access lines 445 to track the voltage of plate lines 440 as the voltage of plate lines 440 changes, the voltage differential between plate lines 440 and unselected access lines 445 may remain constant or substantially constant. Thus, as the voltage of plate lines 440 changes, leakage current (e.g., due to capacitive coupling between plate lines 440 and unselected access lines 445) may be reduced or eliminated, and power consumption associated with access operations may be reduced.

In interval 460, plate line 440 may be held at a second voltage (e.g., a low voltage, such as 0V), and selected access line 450 may be held at a high voltage (e.g., 3V). In some examples, unselected access lines 445 may continue to float during the entire interval 460, and the voltage of unselected access lines 445 may thus remain at the level obtained at the end of interval 458. In such examples, the difference between the voltage of the unselected access line 445 and the voltage of the plate line 440 during interval 460 may not be exactly the difference during interval 455. For example, if the voltage of plate line 440 is reduced from 1.5V to 0V, the voltage of unselected access lines 445 may be reduced from 0V to some level (e.g., -1.4V) that is close to, but not exactly equal to-1.5V during interval 458, and the voltage of unselected access lines 445 may remain at that approximate level (e.g., -1.4V) throughout interval 460.

In some examples, after floating, unselected access lines 445 may be driven to a desired low voltage that is based on and compatible with the voltage change of plate line 440 during interval 458, as shown in FIG. 4B by unselected access lines 445-a. The unselected access lines 445-a may be driven to a desired voltage based on the plate voltage swing, e.g., such that the subsequent voltage differential between the plate line 440 and the unselected access lines 445-a is ensured to be the same as during interval 455 (e.g., if the voltage of the plate changes from 1.5V to 0V during interval 458, and the voltage of the unselected access lines 445 is 0V during interval 455, the voltage of the unselected access lines 445 may be driven to-1.5V to ensure a voltage differential of 1.5V).

In some examples, the unselected access lines 445-a may be driven to the desired voltage at the beginning of interval 460 (e.g., once plate line 440 reaches the second voltage) or at some later time during interval 460 (e.g., at time t'). In other examples, the unselected access lines 445-a may be driven to a desired voltage at the beginning of interval 460. Driving the unselected access lines 445 to desired voltages in order to ensure a desired voltage differential relative to the voltage of the plate lines 440 (e.g., a voltage differential equal to the voltage differential during interval 455) may introduce a certain amount of additional complexity as opposed to continuing to float the unselected access lines 445 throughout interval 460, but may further reduce leakage current and associated power consumption due to the voltage change of the plate lines 440, and may provide greater control of the voltage of the unselected access lines 445 during interval 460. Thus, the voltage of unselected access line 445 may track the voltage of plate line 440.

At interval 462, plate line 440 may be driven from a second voltage (e.g., from a low voltage) to a first voltage (e.g., to a high voltage). The selected access line 450 may remain at a high voltage (e.g., at 3V), and the unselected access lines 445 may be left floating (either in the case where they float during the entire interval 460, or in the case of unselected access lines 445-a, at the time the plateline 440 voltage begins to transition, or some protected period before the plateline 440 voltage begins to transition). Floating the unselected access lines 445 may cause the voltage of the unselected access lines 445 to track (e.g., substantially track) the voltage of the plate lines 440 due to capacitive coupling between the unselected access lines 445 and the plate lines 440. Thus, as the voltage of plate line 440 increases, the voltage of unselected access lines 445 may increase. By tracking the voltage of plate line 440, the voltage differential between the voltage of plate line 440 and the voltage of unselected access lines 445 may remain constant or substantially constant. Thus, leakage currents associated with plate lines 440 and unselected access lines 445 may be mitigated, and power consumption of the associated memory device may be reduced.

In interval 465, the selected access line 450 may be held at a high voltage (e.g., 3V). The plate lines 440 may return to a first voltage (e.g., a high voltage), as described at interval 455, and the unselected access lines 445 may be driven to a high voltage (e.g., 0V). As described above, unselected access lines 445 may be referred to as being at a high voltage (e.g., 0V) due to transitioning between a high voltage (e.g., 0V) and a negative voltage.

Although shown in the example of fig. 4B as transitioning from a high voltage to a low voltage and returning to a high voltage, in some examples, the techniques described herein may be applied when plate line 440 transitions from a low voltage to a high voltage and returns to a low voltage. When plate line 440 transitions from a low voltage to a high voltage or from a high voltage to a low voltage, this may be referred to as switching or switching the voltage of plate line 440. Unselected access lines 445, 445-a may be floated when the voltage of plate line 440 is switched, regardless of the direction of switching.

In various examples, a plate switch may occur, and thus the unselected access lines 445, 445-a may be floated at any time associated with an access operation. For example, unselected access lines 445, 445-a may be floated before, during, or after accessing (e.g., reading from or writing to) a selected memory cell.

In some of the examples described herein, operations supporting techniques for access line management are described in the context of an array of memory cells, the array having one common plate (i.e., common to all memory cells of the array). It should be understood that the same techniques described herein may be supported by an array of memory cells that includes more than one common plate, where each plate may be common to a subset of the memory cells of the array. Thus, the techniques described herein may be applied in the context of a memory array having any number of plates.

In the examples described herein, the absolute voltage levels (e.g., 3V, 0V, -1.5V, etc.) described are for illustrative purposes only. Thus, any absolute voltage level different from that described herein may be used.

FIG. 5A shows an example of a memory device 500-a supporting techniques for access line management for an array of memory cells, according to an example of the invention. In some examples, memory device 500-a may include driver 505, and driver 505 may be referred to as memory driver 505. Memory driver 505 may be coupled with any number of access lines and may facilitate access operations of one or more memory cells (e.g., memory cells 305-a-305-f as described with reference to FIG. 3). Memory driver 505 may be coupled with, for example, access line 520, access line 525, access line 530, access line 535, and access line 537. Each of

access lines

520, 525, 530, 535, and 537 may be an example of a word line (e.g., word lines 310-a, 310-b as described with reference to FIG. 3) of a memory array. Memory driver 505 may include various subcomponents, such as driver component 510 and driver component 515. In other examples (not shown), memory driver 505 may contain any number of subcomponents (e.g., any number of driver components).

As described above, each of

access lines

520, 525, 530, 535, and 537 may be an example of a word line of a memory array (e.g., memory array 320 as described with reference to FIG. 3). For example, access line 520 may be or may be referred to as a first access line 520, access line 525 may be or may be referred to as a second access line 525, and access line 530 may be or may be referred to as a third access line 530.

Additionally or alternatively,

access lines

430 and 435 can be examples of access lines representing a total number of access lines associated with memory device 500-a. For example, access line 537 may be referred to as access line "AL_n", where" n "is the total number of access lines associated with the memory array, and access line 535 may be referred to as access line" AL_n-1". In some examples, the memory array associated with driver 505 may include 1024 access lines (e.g., word lines), so access line 535 may represent the 1023 rd access line of the memory array, and access line 537 may represent the 1024 th access line of the memory array. Each of

access lines

520, 525, 530, 535, and 537 may be associated with an individual memory cell- -for example, no memory cell 105 may be common across

access lines

520, 525, 530, 535, and 537, regardless of whether any of

access lines

520, 525, 530, 535, and 537 is associated with a single memory cell 105 or multiple memory cells 105.

In some examples, memory driver 505 may facilitate access operations to memory cells coupled with one of

access lines

520, 525, 530, 535, and 537. For example, an access operation may be performed on a memory cell coupled with access line 525, which may be referred to as a second memory cell. In some examples, a memory controller (e.g., memory controller 140 as described with reference to fig. 1) may identify an access operation associated with the second memory cell. The driver 505 may then float (e.g., for a duration) the first access line 520. In other examples, driver 505 may float each of access lines 520-537 other than access line 525. In other words, driver 505 may float each unselected access line associated with memory cell 105, memory cell 105 having a common plate with the selected memory cell. By floating the unselected access lines, the voltage of each unselected access line can track the voltage of the associated plate (e.g., plate 325 as described with reference to FIG. 3).

In some examples, driver 505 may float unselected access lines using multiple floating operations and/or using multiple subcomponents. For example, a first subset of unselected access lines may be floated using a first floating operation and/or a first combination of subcomponents of driver 505, and a second subset of unselected access lines may be floated using a second floating operation and/or a second combination of subcomponents of driver 505. Because driver 505 may be coupled with all but one unselected access line (e.g., with 1023 of the 1024 unselected access lines) depending on the size of the memory array, a first subset of unselected access lines that float using a first combination of first floating operations and/or subcomponents and a second subset of unselected access lines that float using a second combination of second floating operations and/or subcomponents may total 1023 access lines.

In some cases, a subcomponent of driver 505, such as driver component 510, may be common to a selected access line, such as access line 520, and one or more unselected access lines, such as

access lines

525, 530, while one or more other subcomponents of driver 505, such as driver component 515, may be common to a plurality of other unselected access lines, such as

access lines

535, 537. In such examples, driver component 510 may operate

unselected access lines

525, 530 differently than the way driver component 515 may operate

unselected access lines

535, 537. For example, driver component 515 may operate

unselected access lines

535, 537 substantially as described with reference to fig. 4, while driver component 510 may drive (rather than float) unselected

access lines

525, 530 to voltages configured to minimize voltage stress on components (e.g., transistors) within driver component 510, because driver component 510 is common with selected access line 520.

In the examples described above, memory driver 505 may include any number of subcomponents, and each subcomponent may be coupled with any number of access lines. For example, the memory driver 505 may include a separate driver component for each access line, or may include a separate driver component for each unique subset of access lines.

FIG. 5B depicts an example timing diagram 500-B of a technique to support access line management for an array of memory cells, according to an example of the invention. In some examples, timing diagram 500-b may depict access operations associated with memory device 500-a as described above with reference to FIG. 5A. In some examples, timing diagram 500-b may depict voltages for a subset of plate lines 540, unselected access lines 545, 545-a, selected access line 550, and unselected access line 552. Timing diagram 500-b may depict voltages of a subset of plate lines 540, unselected access lines 545, 545-a, selected access lines 550, and unselected access lines 552 during

intervals

555, 558, 560, 562, and 565. In some examples, a subset of unselected access lines 552 may be or may refer to unselected access lines that share one or more drivers or driver components (e.g., driver components 510 as described above with reference to fig. 5A) with selected access lines 550.

access lines

520, 525, 530, 535, and 537 as described above with reference to FIG. 5A) for a plurality of memory cells, each having a common plate. Each access line may be referred to as a word line and may be selected or unselected (e.g., by a driver) based on a particular access operation. Any one access line may be selected during a particular access operation, and the remaining number of access lines associated with a plate may remain unselected during that operation. For example, memory cells for which a plate is common may be associated with 1024 access lines (e.g., word lines). Thus, during an access operation, one access line associated with the memory cell to be accessed may be selected (e.g., selected access line 550), and the remaining number of access lines may remain unselected (e.g., unselected access lines 545, 545-a). As described above with reference to fig. 3, a plate (e.g., plate line 540) may be coupled with the memory array.

An access operation associated with the memory cell may be identified (e.g., by memory controller 140 described with reference to fig. 1). At interval 555, plate line 540 is shown initially driven to a first voltage (e.g., a high voltage). The selected access line 550 is shown driven to a high voltage (e.g., 3V) and the

unselected lines

445, 552 are shown driven to a different voltage (e.g., 0V). The unselected access lines 445 may be referred to as being at different voltages (e.g., 0V) because the unselected lines may transition between the voltages (e.g., 0V) and negative voltages.

At interval 558, plate line 540 may transition from a first voltage (e.g., a high voltage) to a second voltage (e.g., a low voltage). The selected access lines 550 may remain at a high value (e.g., 3V) and the unselected access lines 545 may be floated. In some examples, floating unselected access lines 545 may begin simultaneously with the plate line 540 transitioning to the second voltage, or unselected access lines 545 may begin to float before the plate line 540 transitions to the second voltage. Floating unselected access lines 545 may cause the voltages of unselected access lines 545 to track the voltage of plate lines 540 due to capacitive coupling between the unselected access lines and plate lines 540. In other words, as the voltage of plate line 540 decreases during interval 558, it may pull down the voltage of the floated unselected access line 545 by an equal or substantially similar amount.

For example, if the voltage of plate line 540 is reduced from 1.5V to 0V, the voltage of unselected access lines 545 may be reduced from 0V to or about-1.5V. By allowing the voltage of unselected access lines 545 to track the voltage of plate lines 540 as the voltage of plate lines 540 changes, the voltage differential between plate lines 540 and unselected access lines 545 may remain constant or substantially constant. Thus, as the voltage of plate line 540 changes, leakage current (e.g., due to capacitive coupling between plate line 540 and unselected access lines 545) may be reduced or eliminated, and power consumption associated with access operations may be reduced.

At interval 560, plate line 540 may be held at a second voltage (e.g., a low voltage), and selected access line 550 may be held at a high voltage (e.g., 3V). In some examples, unselected access lines 545 may continue to float throughout interval 560, and the voltage of unselected access lines 545 may thus remain at the level obtained at the end of interval 558. In such examples, the difference between the voltage of unselected access lines 545 and the voltage of plate line 540 during interval 560 may not be exactly the difference during interval 555. For example, if the voltage of plate line 540 is reduced from 1.5V to 0V, the voltage of unselected access lines 545 may be reduced from 0V to some level (e.g., -1.4V) that is close to, but not exactly equal to-1.5V during interval 558, and the voltage of unselected access lines 545 may remain at that approximate level (e.g., -1.4V) throughout interval 560.

In some examples, after floating, unselected access lines 545 may be driven to a desired low voltage that is based on and compatible with the voltage change of plate line 540 during interval 458, as shown in FIG. 5B by unselected access lines 545-a. The unselected access lines 545-a may be driven to a desired voltage based on the plate voltage swing, e.g., such that the subsequent voltage differential between plate line 540 and unselected access lines 545-a is ensured to be the same as during interval 555 (e.g., if the voltage of the plate changes from 1.5V to 0V during interval 558 and the voltage of unselected access lines 545 is 0V during interval 555, the voltage of unselected access lines 545 may be driven to-1.5V to ensure a voltage differential of 1.5V).

In some examples, the unselected access lines 545-a may be driven to the desired voltage at the beginning of interval 560 (e.g., once plate line 540 reaches the second voltage) or at some later time during interval 560 (e.g., at time t'). In other examples, unselected access lines 545-a may be driven to a desired voltage at the beginning of interval 560. Driving unselected access lines 545 to desired voltages in order to ensure a desired voltage differential relative to the voltage of plate lines 540 (e.g., a voltage differential equal to the voltage differential during interval 555) may introduce a certain amount of additional complexity as opposed to continuing to float unselected access lines 545 throughout interval 460, but may further reduce leakage current and associated power consumption due to voltage changes of plate lines 540, and may provide greater control of the voltage of unselected access lines 545 during interval 560. Thus, the voltage of the unselected access line 545 may track the voltage of the plate line 540.

At interval 562, plate line 540 may be driven from a second voltage (e.g., from a low voltage) to a first voltage (e.g., to a high voltage). Selected access line 550 may remain at a high voltage (e.g., at 3V), and unselected access line 545 may be left floating (either in the case where it floats during the entire interval 460, or in the case of unselected access line 545-a, at the time the plateline 540 voltage begins to transition, or some protected period before the plateline 540 voltage begins to transition). Floating the unselected access lines 545 may cause the voltage of the unselected access lines 545 to track (e.g., substantially track) the voltage of the plate lines 540 due to capacitive coupling between the unselected access lines 545 and the plate lines 540. Thus, as the voltage of plate line 540 increases, the voltage of unselected access lines 545 may increase. By tracking the voltage of plate line 540, the voltage differential between the voltage of plate line 540 and the voltage of unselected access line 545 may be limited. Thus, leakage currents associated with plate lines 540 and unselected access lines 545 may be mitigated, and power consumption of the associated memory device may be reduced.

At interval 565, the selected access line 550 may remain at a high voltage (e.g., 3V). Plate lines 540 may return to a first voltage (e.g., a high voltage), as described at interval 555, and unselected access lines 545 may be driven to a high voltage (e.g., 0V). As described above, unselected access lines 545 may be referred to as being at a high voltage (e.g., 0V) due to transitioning between a high voltage (e.g., 0V) and a negative voltage.

As described above, a subset of unselected access lines 552 may be held at a constant voltage (e.g., 0V) throughout

intervals

555, 558, 560, 562, and 565. Because a subset of unselected access lines 552 may be or may refer to unselected access lines that share one or more driver components (e.g., driver component 510 as described above with reference to FIG. 5A) with selected access lines 550, such a configuration may add additional complexity to the memory device (e.g., memory device 500-a as described with reference to FIG. 5A; compared to 400-a in a memory as described with reference to FIG. 4A). However, in some examples, such configurations can reduce voltage stress and thus reduce the necessary voltage tolerance of one or more transistors (e.g., one or more transistors located within a driver component) that are common between the unselected access lines 545, 545-a and the selected access line 550.

Additionally or alternatively, the voltage differential between a subset of selected access lines 550 and unselected access lines 552 may be less than the voltage differential between selected access lines 450 and unselected access lines 445, 445-a as described above with reference to fig. 4B. For example, as described above with reference to FIG. 4B, the voltage differential between the selected access line 450 and the unselected access lines 445, 445-a may be 4.5V (e.g., the unselected access lines 445, 445-a are at-1.5V; the selected access line is at 3V). As described with reference to FIG. 5B, the voltage differential between selected access lines 450 and a subset of unselected access lines 552 can be 3V (e.g., a subset of unselected access lines 552 is at 0V; the selected access lines are at 3V). It should be understood that where driver 505 includes multiple driver components 510, each driver component may support operating any one corresponding access line as described with reference to selected access line 550, while operating any other corresponding access line as described with reference to a subset of unselected access lines 552, and operating all corresponding access lines as described with reference to unselected access lines 545, depending on whether any access line corresponding to driver component 510 is selected.

Although shown in the example of fig. 5B as transitioning from a high voltage to a low voltage and back to a high voltage, in some examples, the techniques described herein may be applied when plate line 540 transitions from a low voltage to a high voltage or from a high voltage to a low voltage, which may be referred to as switching or switching the voltage of plate line 540. Regardless of the direction of switching, a subset of unselected access lines 545, 545-a and/or unselected access lines 552 may be floated when the voltage of plate line 540 is switched.

In various examples, a plate switch may occur, and thus a subset of unselected access lines 545, 545-a and/or unselected access lines 552 may be floated at any time associated with an access operation. For example, a subset of unselected access lines 545, 545-a and/or unselected access line 552 may be floated before, during, or after accessing (e.g., reading from or writing to) a selected memory cell.

In some of the examples described herein, operations supporting techniques for access line management are described in the context of an array of memory cells, the array having one common plate (i.e., common to all memory cells of the array). It should be understood that the same techniques described herein may be supported by an array of memory cells that includes more than one plate in common, where each plate may be common to a subset of the memory cells of the array. Thus, the techniques described herein may be applied in the context of a memory array having any number of plates.

FIG. 6 shows a block diagram 600 of an access line manager 615 that supports access line management for an array of memory cells, according to an embodiment of the invention. The access line manager 615 may be an example of an aspect of the access line manager 715 described with reference to fig. 7. Access line manager 615 may include a bias component 620, a timing component 625, a drive component 630, an identify component 635, a float component 640, and an initiate component 645. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

The driving component 630 may drive a plate coupled with at least a first memory cell of the memory cell array to a first voltage. In some examples, drive component 630 may drive the plate from the first voltage to the second voltage based on an access operation associated with the second memory cell during the time duration. In other examples, drive component 630 may drive the first access line to a desired voltage after a duration based at least in part on a difference between the first voltage and the second voltage. Additionally or alternatively, the drive component 630 may drive the plate from the second voltage to the first voltage. In some examples, drive component 630 may drive a second access line coupled with a second memory cell to a third voltage during the duration. In other examples, drive component 630 may drive a third access line coupled with a third memory cell to a fourth voltage during the duration when the plate is driven from the first voltage to the second voltage.

The identifying component 635 may identify an access operation associated with a second memory cell of the memory cell array.

The floating component 640 can float a first access line coupled with a first memory cell of the array of memory cells for a duration based on an access operation associated with a second memory cell. In other examples, floating component 640 may float the first access line after driving the first access line to a desired voltage when driving the plate from the second voltage to the first voltage. In other examples, the floating component 640 may float the first access line for a second duration immediately following the duration. Additionally or alternatively, the floating component 640 may simultaneously float the first access line and drive the plate to the second voltage.

The initiating component 645 may initiate driving the third access line to a fifth voltage. The fifth voltage may be associated with a second logic value of the third memory cell. In some examples, the initiating component 645 may initiate driving the plate from the first voltage to the second voltage based on an access operation associated with the second memory cell. In some examples, the initiation component 645 may initiate floating the first access line based on an access operation associated with the second memory cell. Additionally or alternatively, the initiation component 645 may initiate driving a third access line associated with a third memory cell of the set of memory cells to a third voltage based on an access operation associated with the second memory cell.

It should be understood that in some cases, one or more components of access line manager 615 (e.g., bias component 620, drive component 630, and floating component 640) may be combined.

FIG. 7 shows an illustration of a system 700 that includes a device 705 that supports access line management for an array of memory cells, according to an embodiment of the disclosure. The device 705 may be an example of or include components of the memory array 100 as described above, for example, with reference to FIG. 1. Device 705 may include components for two-way voice and data communications, including components for transmitting and receiving communications, including access line manager 715, memory unit 720, basic input/output system (BIOS) component 725, processor 730, I/O controller 735, and peripheral components 740. These components may be in electronic communication via one or more buses, such as bus 710.

Memory cell 720 may store information (i.e., in the form of logic states) as described herein.

The BIOS component 725 is a software component that includes a BIOS operating as firmware, which may initialize and run various hardware components. The BIOS component 725 may also manage the flow of data between the processor and various other components (e.g., peripheral components, input/output control components, etc.). The BIOS component 725 may include programs or software stored in Read Only Memory (ROM), flash memory, or any other non-volatile memory.

Processor 730 may include intelligent hardware devices such as general purpose processors, DSPs, Central Processing Units (CPUs), microcontrollers, ASICs, FPGAs, programmable logic devices, discrete gate or transistor logic components, discrete hardware components, or any combinations thereof. In some cases, processor 730 may be configured to operate a memory array using a memory controller. In other cases, a memory controller may be integrated into processor 730. The processor 730 may be configured to execute computer-readable instructions stored in memory to perform various functions (e.g., functions or tasks to support access line management for an array of memory cells).

I/O controller 735 may manage input and output signals for device 705. The I/O controller 735 may also manage peripheral devices that are not integrated into the device 705. In some cases, I/O controller 735 may represent a physical connection or port to an external peripheral device. In some cases, I/O controller 735 may utilize, for example

Or another known operating system. In other cases, I/O controller 735 may represent or interact with a modem, keyboard, mouse, touch screen, or similar device. In some cases, I/O controller 735 may be implemented as part of a processor. In some cases, a user may interact with the device 705 via the I/O controller 735 or via hardware components controlled by the I/O controller 735.

Peripheral components 740 may include any input or output device, or interface for such devices. Examples may include a disk controller, a sound controller, a graphics controller, an ethernet controller, a modem, a Universal Serial Bus (USB) controller, a serial or parallel port, or a peripheral card slot, such as a Peripheral Component Interconnect (PCI) or Accelerated Graphics Port (AGP) slot.

Input 745 may represent a device or signal external to device 705 that provides an input to device 705 or a component thereof. This may include a user interface, or interface with or between other devices. In some cases, input 745 may be managed by I/O controller 735 and may interact with device 705 via peripheral components 740.

Output 750 may also represent a device or signal external to device 705 that is configured to receive output from device 705 or any component thereof. Examples of output 750 may include a display, an audio speaker, a printing device, another processor or printed circuit board, and so forth. In some cases, the output 750 may be a peripheral element that interfaces with the device 705 via a peripheral component 740. In some cases, output 750 may be managed by I/O controller 735.

The components of device 705 may include circuitry designed to perform its functions. This may include various circuit elements configured to perform the functions described herein, such as conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements. The device 705 may be a computer, server, laptop, notebook, tablet, mobile phone, wearable electronic device, personal electronic device, or the like. Alternatively, the device 705 may be a part or aspect of such a device.

FIG. 8 shows a flow chart depicting a method 800 for access line management for an array of memory cells, in accordance with an example of the present invention. The operations of method 800 may be implemented by a memory controller or components thereof as described herein. For example, the operations of method 800 may be performed by an access line manager as described with reference to FIG. 6.

At 805, a plate coupled with at least a first memory cell of the memory cell array can be driven to a first voltage. The operations of 805 may be performed according to methods described herein. In certain examples, aspects of the operation of 805 may be performed by a drive component as described with reference to fig. 6.

At 810, an access operation associated with a second memory cell of the memory cell array can be identified. The operations of 810 may be performed according to methods described herein. In some examples, aspects of the operations of 810 may be performed by an identification component as described with reference to fig. 6.

At 815, a first access line coupled with a first memory cell of the array of memory cells may be floated for a duration based at least in part on an access operation associated with a second memory cell. The operations of 815 may be performed according to methods described herein. In some examples, aspects of the operation of 815 may be performed by a floating component as described with reference to fig. 6.

At 820, the plate may be driven from a first voltage to a second voltage during a duration based at least in part on an access operation associated with the second memory cell. The operations of 820 may be performed according to methods described herein. In certain examples, aspects of the operation of 820 may be performed by a drive assembly as described with reference to fig. 6.

FIG. 9 shows a flow chart depicting a method 900 for access line management of an array of memory cells, in accordance with an example of the present invention. The operations of method 900 may be implemented by a memory controller or components thereof as described herein. For example, the operations of method 900 may be performed by an access line manager as described with reference to FIG. 6.

At 905, a plate coupled with at least a first memory cell of the memory cell array can be driven to a first voltage. The operations of 905 may be performed according to methods described herein. In certain examples, aspects of the operation of 905 may be performed by a drive assembly as described with reference to fig. 6.

At 910, an access operation associated with a second memory cell of the array of memory cells can be identified. The operations of 910 may be performed according to methods described herein. In some examples, aspects of the operations of 910 may be performed by an identification component as described with reference to fig. 6.

At 915, a first access line coupled with a first memory cell of the array of memory cells may be floated for a duration based at least in part on an access operation associated with a second memory cell. The operations of 915 may be performed according to methods described herein. In some examples, aspects of the operations of 915 may be performed by a floating component as described with reference to fig. 6.

At 920, the plate may be driven from the first voltage to the second voltage during a duration based at least in part on an access operation associated with the second memory cell. The operations of 920 may be performed according to methods described herein. In certain examples, aspects of the operation of 920 may be performed by a drive assembly as described with reference to fig. 6.

At 925, the first access line can be driven to a desired voltage after a duration based at least in part on a difference between the first voltage and the second voltage. The operations of 925 may be performed according to methods described herein. In certain examples, aspects of the operation of 925 may be performed by a drive component as described with reference to fig. 6.

FIG. 10 shows a flow chart depicting a method 1000 for access line management of an array of memory cells, in accordance with an example of the present invention. The operations of method 1000 may be implemented by a memory controller or components thereof as described herein. For example, the operations of method 1000 may be performed by an access line manager as described with reference to FIG. 6.

At 1005, a plate coupled with at least a first memory cell of the memory cell array can be driven to a first voltage. The operations of 1005 may be performed in accordance with the methods described herein. In certain examples, aspects of the operation of 1005 may be performed by a drive component as described with reference to fig. 6.

At 1010, an access operation associated with a second memory cell of the memory cell array can be identified. The operations of 1010 may be performed according to methods described herein. In certain examples, aspects of the operations of 1010 may be performed by an identification component as described with reference to fig. 6.

At 1015, a first access line coupled with a first memory cell of the array of memory cells can be floated for a duration based at least in part on an access operation associated with a second memory cell. The operations of 1015 may be performed according to the methods described herein. In certain examples, aspects of the operation of 1015 may be performed by a floating component as described with reference to fig. 6.

At 1020, the plate may be driven from a first voltage to a second voltage during a time duration based at least in part on an access operation associated with the second memory cell. The operations of 1020 may be performed in accordance with the methods described herein. In certain examples, aspects of the operation of 1020 may be performed by a drive assembly as described with reference to fig. 6.

At 1025, the first access line may be floated for a second duration immediately following the duration. The operations of 1025 may be performed according to methods described herein. In some examples, aspects of the operation of 1025 may be performed by a floating component as described with reference to fig. 6.

In some cases, the method can include driving a plate coupled with at least a first memory cell of the memory cell array to a first voltage. In some examples, floating the first access line and driving the plate to the second voltage may occur simultaneously. In other examples, the method can include floating a first access line coupled with a first memory cell of the array of memory cells for a duration based at least in part on an access operation associated with a second memory cell.

In some cases, the method may include driving the plate from the first voltage to the second voltage during the duration based at least in part on an access operation associated with the second memory cell. In some examples, the method may include driving the first access line to a desired voltage after a duration based at least in part on a difference between the first voltage and the second voltage. Additionally or alternatively, the method may include driving the plate from the second voltage to the first voltage. In other cases, the method may include identifying an access operation associated with a second memory cell of the memory cell array.

In some cases, the method may include driving a second access line coupled with a second memory cell to a third voltage during the duration. In some examples, the method may include driving a third access line coupled with a third memory cell to a fourth voltage during a duration when the plate is driven from the first voltage to the second voltage. In some cases, the method may include floating the first access line for a second duration immediately following the duration. Additionally or alternatively, the plate may be coupled with a plurality of memory cells of the memory cell array. The plurality of memory cells may include a first memory cell and a second memory cell.

In some cases, the plate may be coupled with a first set of rows or columns of memory cells of the memory cell array and with a second set of rows or columns of memory cells of the memory cell array. In other cases, the method may include floating the first access line after driving the plate to the second voltage when driving the plate from the second voltage to the first voltage.

FIG. 11 shows an example of a circuit 1100 that supports techniques for access line management for an array of memory cells, according to an example of the invention. In some examples, the circuit 1100 may include a driver 1105, which in some cases may be an example of a wordline driver. The driver 1105 may be coupled with an access line 1110, which in some cases may be an example of a word line as discussed herein. The driver 1105 may facilitate access operations of one or more memory cells coupled with the access line 1110. In some examples, the circuit 1100 may be coupled with or included in an access line decoder, such as a word line decoder (or row decoder) or a digit line decoder (or column decoder), as described herein.

Driver 1105 may be coupled to various control circuits such as control circuit 1115, control circuit 1120, and control circuit 1125. Operation of the drivers 1105 and/or

control circuitry

1115, 1120, and/or 1125 may facilitate access operations of one or more memory cells as described herein. It should be understood that in some cases, one or more structural or functional aspects of control circuitry 1115, control circuitry 1120, and control circuitry 1125 may instead be integrated into driver 1105 or otherwise considered part of driver 1105.

In some examples, driver 1105 may represent one of a plurality of word line drivers of a memory device. For example, driver 1105 may represent one of the 1,024 word line drivers of a memory device. It should be understood that here and elsewhere, specific numerals are merely for clarity of description and the claims are not limited thereto. Each driver 1105 may include one or more transistors. For example, the driver 1105 may include a transistor 1130 (e.g., a first transistor 1130) and a transistor 1135 (e.g., a second transistor 1135). The first transistor 1130 and the second transistor 1135 may be arranged in a cascode configuration. The driver 1105 may also include a transistor 1140 (e.g., a third transistor 1140) and a transistor 1145 (e.g., a fourth transistor 1145). In some examples, the first transistor 1130 and the second transistor 1135 may be PMOS transistors, and the third transistor 1140 and the fourth transistor 1145 may be NMOS transistors.

In some examples, driver 1105 may include node 1180, which may be referred to as an output node of driver 1105, and which may be coupled with access lines 1110. The node 180 may also be coupled with a drain terminal of the second transistor 1135, a source terminal of the fourth transistor 1145, and a source terminal of the third transistor 1140.

Driver 1105 may also include one or more nodes configured to receive control signals from

control circuitry

1115, 1120, and/or 1125. For example, driver 1105 may include a node 1170 (e.g., first node 1170) configured to receive control signals 1160 from control circuitry 1125. The node 1170 may refer to a terminal (e.g., a source terminal) of the first transistor 1130. In some examples, control signal 1160 may be referred to as ARFX. Driver 1105 may also include a node 1185 (e.g., a third node) configured to receive control signal 1167 from control circuitry 1125. The node 1185 may refer to a gate of the third transistor 1140. In some examples, control signal 1185 may be referred to as ARFX' and may be inverted relative to control signal 1160.

The word line driver may also include a node 1175 (e.g., a second node) configured to receive a control signal 1165 from the control circuitry 1120. The node 1175 may refer to a terminal (e.g., a source terminal) of the third transistor 1140 and a terminal (e.g., a source terminal) of the fourth transistor 1145, which may be coupled to each other. In some examples, the state of control signal 1165 may be based on settings of control circuit 1120.

In some examples, the driver 1105 may be configured to receive two control signals from the control circuitry 1115. The first control signal 1150 generated by the control circuit 115 may be referred to as MWLF _ H and may be received at the gate of the transistor 1130. Further, the gate of the fourth transistor 1145 may be configured to receive the second control signal 1155 from the control circuitry 1115. Control signal 1155 may be referred to as MWLF _ L. In some examples, control signal 1150 may have a different (e.g., higher) voltage swing than control signal 1155.

The control circuitry 1115 shown in fig. 11 may be one of a plurality of control circuitry 1115 for a memory device. For example, the control circuitry 1115 may represent one of sixty-four (64) control circuitry 1115 for a memory device. That is, following the example described above, where 1,024 drivers 1105 are each coupled with a respective access line 1110, a single control circuit 1115 may be coupled with sixteen (16) drivers 1105. Thus, for each control circuit 1115, the

control signals

1150 and 1155 generated and output by the control circuit 1115 may be common to (received by each of) sixteen (16) drivers 1105.

In some examples, as explained above, the control signal 1150 may be applied to the gate of the transistor 1130 of the driver 1105. For example, applying the control signal 1150 to the gate of the transistor 1130 may cause the transistor 1130 to be activated (e.g., turned on) when the control signal is in a low state (low voltage) or deactivated (e.g., turned off) when the control signal is in a high state (high voltage) because the transistor 1130 may be a PMOS device. Similarly, applying the control signal 1155 to the gate of the transistor 1145 may cause the transistor 1145 to be activated (e.g., turned on) when the control signal is in a high state (high voltage) or deactivated when the control signal is in a low state (low voltage), as the transistor 1145 may be an NMOS device.

Control signals 1150 and 1155 may have different voltage swings from one another. For example, the voltage swing of control signal 1155 may be less than the voltage swing of control signal 1150, or vice versa. In some examples, each of

control signals

1150 and 1155 may be associated with the same lower limit (e.g., 0V), but may have a different upper limit. For example, the upper limit of control signal 1150 may be 3V, and the upper limit of control signal 1155 may be 1.5V. In some examples, different control circuits 1115 of multiple control circuits within the same device may apply different control signals to different respective drivers 1105 during phases of an access operation.

In some cases, configuring the control circuitry 1115 to generate and output two

different control signals

1150 and 1155 to the driver 1105, and further the two

control signals

1150 and 1155 have different voltage swings may avoid placing undue stress (e.g., excessive voltages) on one or more components (e.g., transistors) of the driver 1105, which may support the use of low voltage tolerant devices, which may provide space, switching speed, and efficiency benefits, among other benefits that may be appreciated by one skilled in the art. Additionally or alternatively, including transistor 1135 in a cascode configuration with transistor 1130 may avoid placing undue stress (e.g., too high a voltage) on one or more components (e.g., transistors) of driver 1105, which may support the use of low voltage tolerant devices, which may provide space, switching speed, and efficiency benefits, among other benefits that may be appreciated by one skilled in the art.

The control circuit 1120 shown in fig. 11 may be one of a plurality of control circuits 1120 of a memory device. For example, the control circuit 1120 may represent one of sixteen (16) control circuits 1120 of a memory device. That is, following the example described above, where 1,024 drivers 1105 are each coupled with a respective access line 1110, a single control circuit 1120 may be coupled with sixty-four (64) drivers 1105. Thus, for each control circuit 1120, the control signal 1165 generated and output by the control circuit 1120 may be common to (received by each of) sixty-four (64) drivers 1105. The control circuitry 1120 can be configured to apply a control signal 1165 to a respective node 1175 of each driver 1105 coupled with the control circuitry 1120.

In some examples, at different times during an access operation of one or more memory cells within a memory device, control signal 1165 may drive node 1175 to a relatively higher voltage, which may be referred to as VNWL (e.g., 0V), may drive node 1175 to a relatively lower voltage, which may be referred to as VNNWL (e.g., -1.5V, VNNWL), or may electrically FLOAT node 1175 (e.g., FLOAT). The state of control signal 1165 may be based on one or more control signals received by control circuitry 1120 (e.g., from a controller). The voltage swing between possible voltages of the control signal 1165 may be the same as the voltage variation of the plates of the memory device during the access operation. That is, the voltage swing between the relatively high voltage and the relatively low voltage may be 1.5V, which may be the same as the voltage change of the plate during the access operation (e.g., if the plate changes from 1.5V to 0V). In some examples, different control circuits 1120 of multiple control circuits within the same device may apply different control signals to different respective drivers 1105 during various stages of an access operation.

The control circuit 1125 shown in fig. 11 may be one of a plurality of control circuits 1125 of a memory device. For example, control circuit 1125 may represent one of sixteen (16) control circuits 1125 of a memory device. That is, following the example described above, where 1,024 drivers 1105 are each coupled with a respective access line 1110, a single control circuit 1125 may be coupled with sixty-four (64) drivers 1105. Thus, for each control circuit 1125, the

control signals

1160 and 1167 generated and output by control circuit 1125 may be common to (received by each of) sixty-four (64) drivers 1105. Each control circuit 1125 may be configured to apply a control signal 1160 to a respective node 1170 and/or a control signal 1167 to a respective node 1185 of each driver 1105 coupled with the control circuit 1125. In some cases, control circuit 1125 may be associated with a corresponding control circuit 1120, such that both control circuit 1125 and corresponding control circuit 1120 may be coupled with the same set of drivers 1105, that is, if two or more drivers 1105 are coupled with the same control circuit 1125, they may also be coupled with the same control circuit 1120.

In some examples, control circuit 1125 may include

transistors

1190, 1192, and 1194. Transistors 1190 and 1192 may be NMOS transistors and transistor 1194 may be a PMOS transistor. In some examples, transistor 1190 may be arranged in a cascode configuration with transistor 1192. In some examples, a terminal (e.g., a source terminal) of the transistor 1194 may be coupled with a first voltage source (e.g., VCCP), and a terminal (e.g., a source terminal) of the transistor 1190 may be coupled with a different voltage source (e.g., VSS).

Transistors

1190, 1192, and 1194 may comprise (implement) inverters, but the number of transistors on the two legs of the inverters is not symmetrical. In addition, the control circuit 1125 may also include a second inverter 1196, which may be coupled to the gate of transistor 1194 and/or transistor 1190.

Control circuit 1125 may be configured to output (e.g., generate) control signal 1160 and control signal 1167. Control signals 1160 and 1167 may have opposite logic from each other (e.g., due to inverters formed between respective output nodes of

control signals

1160 and 1167 by transistors 1190, 1192, and 1194). That is, when one is high, the other is low.

In some examples, the control circuit 1125 may also be configured to FLOAT the node 1170 based on the FLOAT2 control signal. The FLOAT2 control signal may be received by the control circuit 1125 (e.g., from a controller) and may cause the control signal 1160 to electrically FLOAT when active. In some examples, FLOAT2 may be active low, and when FLOAT2 is high,

transistors

1190, 1192, and 1194 may act as inverters in series with inverter 1196. But if FLOAT2 is low when the output of inverter 1196 is high, then control signal 1160 may FLOAT and therefore node 1170 may FLOAT. For example, node 1170 may FLOAT because transistor 1194 is deactivated (e.g., turned off) because the output of inverter 1196 is high and simultaneously transistor 1192 is deactivated (e.g., turned off) because FLOAT2 is low. In some examples, different control circuits 1125 in multiple control circuits within the same device may apply different control signals to different respective drivers 1105 during various stages of an access operation.

FIG. 12A depicts an example timing diagram 1200-a of a technique to support access line management for an array of memory cells, according to an example of the invention. In some examples, timing diagram 1200-a may depict access operations associated with (e.g., performed using) circuit 1100 described above with reference to FIG. 11. In some examples, timing diagram 1200-a may depict the voltages of plate line 1205, word line 1110-a, node 1170-a, and node 1175-a. The voltages of word line 1110-a, node 1170-a, and node 1175-a may illustrate the voltages applied to access line 1110, node 1170, and node 1175 described with reference to FIG. 11. Timing diagram 1200-a may depict the voltages of plate line 1205, wordline 1110-a, and nodes 1170-a and 1175-a during

intervals

1210, 1215, 1220, 1225, and 1230.

As described herein, a memory array can include a plurality of respective access lines (e.g., a plurality of word lines) for a plurality of memory cells, each memory cell having a common plate. Each access line may be selected or unselected (e.g., by driver 1105 as described with reference to fig. 11) based on whether the cell coupled with that access line is the target of (accessed by) a particular access operation. In some cases, any access line of a given type may be selected during a particular access operation, while the remaining number of access lines of the same type associated with a plate may remain unselected during that operation.

The timing diagram 1200-a may depict access operations of a selected access line (e.g., a selected word line) associated with the circuit 1100 described above with reference to FIG. 11. The memory cells associated with the selected access line may be accessed during one or more of the intervals shown in fig. 12A.

During interval 1210, the voltage of plate line 1205 is shown initially being driven to a first voltage (e.g., a high voltage, such as 1.5V). When the plate is driven to a first voltage, prior to interval 1210, word line 1110-a may be selected. In fig. 12A-12D, examples are described in terms of word lines, but it should be understood that the teachings may be used with any type of access line. In some examples, the word line that has been selected may be represented as word line 1110-a at a high voltage, e.g., 3V, at the beginning of interval 1210. To select the word line 1110-a, the control circuit 1125 may apply a high control signal 1160 to the node 1170 (e.g., by activating the transistor 1194), which may be based on a logic high signal received at the input of the inverter 1196, and may cause the voltage of the node 1170-a to be driven to a high voltage, e.g., 3V. When the node 1170-a is at a high voltage, the control circuit 1115 may apply a low control signal 1150 to the transistor 1130. The low control signal 1150 may be, for example, 0V. Applying

control signals

1160 and 1150 to driver 1105 may cause

transistors

1130 and 1135 to be activated (e.g., turned on). Thus, the voltage of word line 1110-a may be driven to 3V.

In some examples, control circuitry 1120 may apply a high control signal 1165 (e.g., VNWL) to node 1175. Thus, the voltage of node 1175-a may be at 0V. When the node 1175 is at 0V, the control circuit 1115 may apply a low control signal 1155 to the transistor 1145, and the control circuit 1125 may apply a low control signal 1167 to the transistor 1140.

Low control signals

1155 and 1167 may be, for example, 0V. Thus, application of

control signals

1155 and 1167 to driver 1105 may cause

transistors

1140 and 1145 to be deactivated (e.g., turned off). Thus, word line 1110-a may be isolated from node 1175.

During interval 1215, the voltage of plate line 1205 may transition from a first voltage (e.g., a high voltage) to a second voltage (e.g., a low voltage, such as 0V). The voltage of the selected word line 1110-a and the voltage of the node 1170-a may remain high (e.g., 3V), and the voltage of the node 1175-a may remain low (e.g., 0V).

During interval 1220, the voltage of plate line 1205 may be held at a second voltage (e.g., a low voltage, such as 0V). The voltage of the wordline 1110-a and the voltage of the node 1170-a may remain high (e.g., 3V), and the voltage of the node 1175-a may remain low (e.g., 0V).

During interval 1225, the voltage of plate line 1205 can be driven from a second voltage (e.g., from a low voltage) to a first voltage (e.g., a high voltage). The voltage of the selected word line 1110-a and the voltage of the node 1170-a may remain high (e.g., 3V), and the voltage of the node 1175-a may remain low (e.g., 0V).

During interval 1230, the voltage of plate line 1205 may remain at a first voltage (e.g., a high voltage). The voltage of the wordline 1110-a and the voltage of the node 1170-a may remain high (e.g., 3V), and the voltage of the node 1175-a may remain low (e.g., 0V). In the examples described herein, the absolute voltage levels (e.g., 3V, 0V, -1.5V, etc.) are described for illustrative purposes only. Thus, any absolute voltage level different from that described herein may be used.

In some examples, each of the

transistors

1130, 1135, 1140, and 1145 within the driver 1105 of the selected word line 1110-a may have a relatively low gate-to-source voltage (e.g., V) throughout an access operation_gs) And/or drain-source voltage (e.g., V)_ds). For example, none of

transistors

1130, 1135, 1140, and 1145 have a Vgs and/or Vds that is greater than the voltage swing (e.g., MWLF _ H, which may be 3V) of control signal 1150 throughout the access operation.

FIG. 12B depicts an example timing diagram 1200-B of a technique to support access line management for an array of memory cells, according to an example of the invention. In some examples, timing diagrams 1200-b may depict access operations associated with (e.g., performed using) the circuit 1100 described above with reference to FIG. 11. In some examples, timing diagram 1200-b may depict the voltages of plate line 1205, word line 1110-b, node 1170-b, and node 1175-b. The voltages of word line 1110-b, node 1170-b, and node 1175-b may illustrate the voltages applied to access line 1110, node 1170, and node 1175 described with reference to FIG. 11. Timing diagram 1200-b may depict the voltages of plate line 1205, wordline 1110-b, and nodes 1170-b and 1175-b during

intervals

1210, 1215, 1220, 1225, and 1230.

As described herein, a memory array can include a plurality of respective access lines (e.g., a plurality of word lines) for a plurality of memory cells, each memory cell having a common plate. Each access line may be selected or unselected (e.g., by driver 1105 as described with reference to fig. 11) based on whether the cell coupled with that access line is the target of (accessed by) a particular access operation. In some cases, any access line may be selected during a particular access operation, while the remaining number of access lines of the same type associated with a plate may remain unselected during that operation.

Timing diagram 1200-b may depict access operations associated with circuit 1100 described above with reference to FIG. 11 for a first subset of unselected access lines. For example, the timing diagram 1200-b may depict the voltages of the word lines 1110-b of the control circuit 1120 and the control circuit 1125 that share the same driver 1105 as the selected word line (e.g., the selected word line 1110-a as discussed with reference to FIG. 12A). Thus, following the example above, where 1,024 drivers 1105 are each coupled with a respective wordline 1110, the voltage of the unselected wordline 1110-b may illustrate the voltage of 63 unselected wordlines 1110 sharing the same control circuitry 1120 and control circuitry 1125 as the driver 1105 of the selected wordline.

During interval 1210, the voltage of plate line 1205 is shown initially being driven to a first voltage (e.g., a high voltage, such as 1.5V). When the plate is driven to a first voltage, one wordline 1110-a may be selected and a subset of wordlines 1110 may remain unselected prior to interval 1210. In some examples, the subset of word lines that remain unselected may represent the voltage of word line 1110-b remaining low, e.g., 0V. When a subset of the word lines 1110-b are unselected but share a common control circuit 1125 with the selected word line 1110-a, the control circuit 1125 may apply a high control signal 1160 to the node 1170, which may cause the voltage of the node 1170-b to be driven to a high voltage, e.g., 3V. When the node 1170-b is at a high voltage, the control circuitry 1115, which may not be common to the first subset of the selected word lines 1110-a and unselected word lines 1110-b, may apply a high control signal 1150 to the transistors 1130. The high control signal 1150 may be, for example, 3V. Thus, applying

control signals

1160 and 1150 to driver 1105 may cause

transistors

1130 and 1135 to be deactivated (e.g., turned off). Thus, the unselected wordline 1110-b may be isolated from the node 1170.

In some examples (e.g., when a subset of word lines 1110-b are unselected but share common control circuitry 1120 with the selected word line 1110-a), the control circuitry 1120 may apply a high control signal 1165 (e.g., VNWL) to the node 1175. For example, the voltage of node 1175-a may be 0V. When the control signal 1165 is applied to the node 1175, the control circuitry 1115 may apply a high control signal 1155 to the transistor 1145, and the control circuitry 1125 may apply a low control signal 1167 to the transistor 1140. High control signal 1155 may be, for example, 1.5V and low control signal 1167 may be 0V. Thus, application of the

control signals

1155 and 1167 to the driver 1105 may cause the transistor 1145 to be activated (e.g., turned on) and the transistor 1140 to be deactivated (e.g., turned off). Thus, the unselected word lines may be coupled with the node 1175 via the transistor 1145, which may cause the node 1175 and the unselected word lines to have the same voltage (e.g., 0V).

During interval 1215, the voltage of plate line 1205 can transition from a first voltage (e.g., a high voltage) to a second voltage (e.g., a low voltage, such as 0V). The voltage of the unselected word line 1110-b may remain low (e.g., 0V), the voltage of the node 1170-a may remain high (e.g., 3V), and the voltage of the node 1175-a may remain low (e.g., 0V).

During interval 1220, the voltage of plate line 1205 may be held at a second voltage (e.g., a low voltage, such as 0V). The voltage of the unselected word line 1110-b may remain low (e.g., 0V), the voltage of the node 1170-a may remain high (e.g., 3V), and the voltage of the node 1175-a may remain low (e.g., 0V).

During interval 1225, the voltage of plate line 1205 can be driven from a second voltage (e.g., a low voltage) to a first voltage (e.g., a high voltage). The voltage of the unselected word line 1110-b may remain low (e.g., 0V), the voltage of the node 1170-a may remain high (e.g., 3V), and the voltage of the node 1175-a may remain low (e.g., 0V).

During interval 1230, the voltage of plate line 1205 may remain at a first voltage (e.g., a high voltage). The voltage of the unselected word line 1110-b may remain low (e.g., 0V), the voltage of the node 1170-a may remain high (e.g., 3V), and the voltage of the node 1175-a may remain low (e.g., 0V). In the examples described herein, the absolute voltage levels (e.g., 3V, 0V, -1.5V, etc.) are described for illustrative purposes only. Thus, any absolute voltage level different from that described herein may be used.

In some examples, each of the

transistors

1130, 1135, 1140, and 1145 within the driver 1105 of the unselected word line 1110-b may have a relatively low gate-to-source voltage (e.g., V) throughout the access operation_gs) And/or drain-source voltage (e.g., V)_ds). For example, none of

transistors

FIG. 12C depicts an example timing diagram 1200-C of a technique to support access line management for an array of memory cells, according to an example of the invention. In some examples, timing diagrams 1200-c may depict access operations associated with (e.g., performed using) the circuit 1100 described above with reference to fig. 11. In some examples, timing diagram 1200-c may depict the voltages of plate line 1205, word line 1110-c, node 1170-c, and node 1175-c. The timing diagram 1200-c may also depict alternative voltages for the word line 1110-c, as shown by the voltage trace denoted 1110-c'. The voltages of the wordline 1110-c, node 1170-c, and node 1175-c may illustrate the voltages applied to the wordline 1110, node 1170, and node 1175 described with reference to FIG. 11. Timing diagram 1200-c may depict the voltages of plate line 1205, wordline 1110-c, and nodes 1170-c and 1175-c during

intervals

1210, 1215, 1220, 1225, and 1230.

Timing diagram 1200-c may depict access operations associated with circuit 1100 described above with reference to FIG. 11 for an unselected subset of access lines. For example, the timing diagrams 1200-c may depict the voltages of the word lines 1110-c sharing different control circuits 1115, different control circuits 1120, and different control circuits 1125 than the drivers 1105 of a selected access line (e.g., the selected word line 1110-a as discussed with reference to FIG. 12A). Thus, following the example above, where 1,024 drivers 1105 are each coupled with a respective word line 1110, the voltage of the unselected word lines 1110-c may account for the voltage of 945 unselected word lines 1110.

During interval 1210, the voltage of plate line 1205 is shown initially being driven to a first voltage (e.g., a high voltage, such as 1.5V). When the plate is driven to a first voltage, a subset of word lines 1110-c may remain unselected until interval 1210. In some examples, holding the unselected word lines 1110-c may represent the voltage of the word lines 1110-c being held at a low voltage, such as 0V. When the subset of word lines is unselected and does not share the common control circuit 1125 with the selected word line 1110-a, the control circuit 1125 may apply a low control signal 1160 to the node 1170, which may cause the voltage of the node 1170-c to be driven to a low voltage, such as 0V. When the node 1170-c is at a low voltage, the control circuit 1115 may apply a high control signal 1150 to the transistor 1130. The high control signal 1150 may be, for example, 3V. Thus, applying

control signals

1160 and 1150 to driver 1105 may cause

transistors

1130 and 1135 to be deactivated (e.g., turned off). Thus, the unselected word lines may be isolated from node 1170.

In some examples, control circuitry 1115 may apply a high control signal 1155 to transistor 1145, and control circuitry 1125 may apply a high control signal 1167 to node 1185. In some examples, high control signal 1155 may be 1.5V and high control signal 1167 may be 1.5V. Thus, the transistor 1145 may be activated (e.g., turned on) and the transistor 1140 may be activated (e.g., turned on). Thus, the unselected word line 1110-c may be coupled with the node 1175 via the transistor 1140 and the transistor 1145, and may be the same voltage as the output of the control circuit 1120 (e.g., the same voltage as the voltage of the control signal 1165). During interval 1210, control circuitry 1120 may output a control signal 1165 corresponding to VNWL, which may be, for example, 0V. Thus, during interval 1210, the voltage of node 1175-c and the voltage of unselected word lines 1110-c may be 0V.

During interval 1215, the voltage of plate line 1205 can transition from a first voltage (e.g., a high voltage) to a second voltage (e.g., a low voltage, such as 0V). In some cases, during interval 1215, node 1170 may also float, which may cause the voltage of node 1170-c to float. For example, control circuit 1125 may receive the FLOAT2 control signal at the gate of transistor 1192, which may be low when the input of inverter 1196 is low, which may FLOAT control signal 1160, and thus node 1170. Node 1170 may FLOAT due to transistor 1194 being deactivated (e.g., turned off) because the output of inverter 1196 is high and transistor 1192 being deactivated (e.g., turned off) because floor 2 is low.

Control circuitry 1120 may float control signal 1165, and thus node 1175, during interval 1215. The unselected word line 1110-c may float due to isolation from node 1170 and floating of node 1175. And floating of the unselected word lines 1110 may cause the voltage of the unselected word lines 1110 to track the voltage of the plate line 1205 due to capacitive coupling between the unselected word lines 1110 and the plate line 1205. In other words, as the voltage of plate line 1205 decreases during interval 1215, it may pull down the voltage of the floating unselected word line 1110 by an equal or substantially similar amount. For example, if the voltage of plate line 1205 is reduced from 1.5V to 0V, the voltage of unselected access lines 1105 may be reduced from 0V to-1.5V or substantially to-1.5V.

Thus, during interval 1215, unselected access lines 1105 may be floated by adjusting the control signal 1165 applied to node 1175. For example, the control circuit 1120 may output a FLOAT control signal 1165, which may FLOAT the unselected word lines 1110. Thus, the voltage of the unselected word line 1110-c may be reduced to, for example, -1.4V.

During interval 1220, the voltage of plate line 1205 may be held at a second voltage (e.g., a low voltage, such as 0V). In some examples, the unselected word lines 1110-c may remain floating based on the control signal 1165 being applied to the node 1175.

In other examples, the unselected wordlines 1110-c may be driven to a desired voltage during interval 1220 (e.g., may be driven to a voltage such that the voltage difference between the unselected wordlines 1110-c during interval 1220 and the unselected wordlines 1110-c during interval 1210 is equal to the voltage difference between the plates during interval 1220 and the plates during interval 1210). For example, during interval 1220 (e.g., at time t', which may be before, at, or after the beginning of interval 1220), a different control signal 1165 may be applied to node 1175. Control signal 1165 may be VNNWL, which may be-1.5V. Thus, since the unselected word line 1110-C is coupled with the node 1175, the voltage of the unselected word line 1110-C may be driven to-1.5V, which in some cases may be slightly different from the voltage of the unselected word line 1110-C that floats throughout the interval 1220, as shown in FIG. 12C by the alternative voltage trace associated with 1110-C'.

In some cases, during interval 1220, node 1170 may continue to float as it did during interval 1215. In other examples, node 1170 may be driven to a low voltage, such as 0V, during interval 1220. Due to potential capacitive coupling between the unselected wordline 1110 and the plate 1205, the voltage of the node 1170-c may vary (drift) slightly during interval 1215 (e.g., decrease to a voltage slightly below 0V), and based on the expected drift during interval 1215, the node 1170 may be driven to 0V or a different voltage during interval 1220.

During interval 1225, the voltage of plate line 1205 can be driven from a second voltage (e.g., a low voltage) to a first voltage (e.g., a high voltage). The control circuit 1120 may output a FLOAT control signal 1165, which may FLOAT the unselected word lines 1110, as described above with reference to interval 1215. Thus, the voltage of the unselected word line 1110-c may be increased to, for example, -0.1V. In addition, control circuitry 1125 may float (e.g., continue to float) node 1170, as described with reference to interval 1215.

During interval 1230, the voltage of plate line 1205 may remain at a first voltage (e.g., a high voltage). Control circuitry 1120 may output a high control signal 1165 (e.g., VNWL) which may be, for example, 0V. Thus, during interval 1230, the voltage of node 1175-c and the voltage of unselected word line 1110-c may be 0V. Additionally or alternatively, during interval 1230, node 1170-c may be driven to 0V. In the examples described herein, the absolute voltage levels (e.g., -1.4V, -1.5V, 3V, 0V, etc.) are described for illustrative purposes only. Thus, any absolute voltage level different from that described herein may be used.

In some examples, each of the

transistors

1130, 1135, 1140, and 1145 within the driver 1105 of the unselected word line 1110-c may have a relatively low gate-to-source voltage (e.g., V) throughout the access operation_gs) And/or drain-source voltage (e.g., V)_ds). For example, none of

transistors

Additionally or alternatively, the cascode configuration of

transistors

1130 and 1135 may be such that when plate line 1205 is at a low voltage (e.g., 0V) and unselected access line 1105 is at a low voltage (e.g., -1.4V), transistor 1130 has a relatively low gate-to-source voltage (e.g., V)_gs). Furthermore, because control signals 1167 and 1155 may have relatively low voltage swings, transistor 1145 may avoid excessive V when plate line 1205 is at a low voltage (e.g., 0V) and unselected access lines 1105 are at a low voltage (e.g., -1.4V)_gs。

FIG. 12D depicts an example timing diagram 1200-D of a technique to support access line management for an array of memory cells, according to an example of the invention. In some examples, timing diagrams 1200-d may depict access operations associated with (e.g., performed using) the circuit 1100 described above with reference to FIG. 11. In some examples, timing diagram 1200-d may depict the voltages of plate line 1205, word line 1110-d, node 1170-d, and node 1175-d. The timing diagram 1200-d may also depict alternative voltages for the word line 1110-d, as shown by the voltage trace designated 1110-d'. The voltages of the word lines 1110-d and 1110-d', the node 1170-d, and the node 1175-d may illustrate the voltages applied to the word line 1110, the node 1170, and the node 1175 described with reference to FIG. 11. Timing diagram 1200-d may depict the voltages of plate line 1205, wordline 1110-d (and wordlines 1110-d'), and nodes 1170-d and 1175-d during

intervals

1210, 1215, 1220, 1225, and 1230.

As described herein, a memory array can include a plurality of respective access lines (e.g., a plurality of word lines) for a plurality of memory cells, each memory cell having a common plate. Each access line may be selected or unselected (e.g., by driver 1105 as described with reference to fig. 11) based on whether the cell coupled with that access line is the target of (accessed by) a particular access operation. Any access line may be selected during a particular access operation, while the remaining number of access lines of the same type associated with a plate may remain unselected during that operation.

Timing diagrams 1200-d may depict access operations associated with the circuit 1100 described above with reference to FIG. 11 for a subset of unselected access lines. For example, the timing diagrams 1200-d may depict the voltages of the word lines 1110-d (and/or 1110-d') sharing the same control circuitry 1115 as the driver 1105 of a selected access line (e.g., the selected word line 1110-a as discussed with reference to FIG. 12A). Thus, following the example above, where 1,024 drivers 1105 are each coupled with a respective word line 1110, the voltage of the unselected word lines 1110-d may illustrate the voltage of fifteen (15) unselected word lines 1110.

During interval 1210, the voltage of plate line 1205 is shown initially being driven to a first voltage (e.g., a high voltage, such as 1.5V). When the plate is driven to a first voltage, a subset of word lines 1110 may remain unselected prior to interval 1210. In some examples, the unselected word lines 1110-d that remain unselected may be represented as the voltage of the word lines 1110-d remaining low, e.g., 0V. When a subset of the word lines 1110-d are unselected and control circuit 1125 is not shared with the selected word line 1110-a, the control circuit 1125 may apply a low control signal 1160 to the node 1170, which may cause the voltage of the node 1170-d to be driven to a low voltage, such as 0V. When the node 1170-d is at a low voltage, the control circuitry 1115 may apply a low control signal 1150 to the transistor 1130 when a subset of the wordlines 1110-d are unselected and share the control circuitry 1115 with the selected wordline 1110-a. The low control signal 1150 may be, for example, 0V. Thus, applying

control signals

1160 and 1150 to driver 1105 may cause

transistors

In some examples, when a subset of word lines 1110-d are unselected and control circuitry 1115 is shared with the selected word line 1110-a, control circuitry 1115 may apply a low control signal 1155 to transistor 1145, and control circuitry 1125 may apply a high control signal 1167 to node 1185. In some examples, low control signal 1155 may be 0V and high control signal 1167 may be 1.5V. Thus, the transistor 1145 may be deactivated (e.g., turned off) and the transistor 1140 may be activated (e.g., turned on). Thus, the unselected word line 1110-d may be coupled with the node 1175 via the transistor 1140, and may be the same voltage as the output of the control circuit 1120 (e.g., the same voltage as the voltage of the control signal 1165). During interval 1210, control circuitry 1120 may output a control signal 1165 corresponding to VNWL, which may be, for example, 0V. Thus, during interval 1210, the voltage of node 1175-d and the voltage of unselected word lines 1110-d may be 0V.

During interval 1215, the voltage of plate line 1205 can transition from a first voltage (e.g., a high voltage) to a second voltage (e.g., a low voltage, such as 0V). Floating the unselected word lines 1110 may cause the voltage of the unselected word lines 1110 to track the voltage of the plate lines 1205 due to capacitive coupling between the unselected word lines 1110 and the plate lines 1205. In other words, as the voltage of plate line 1205 decreases during interval 1215, it may pull down the voltage of the floating unselected word line 1110 by an equal or substantially similar amount. For example, if the voltage of plate line 1205 is reduced from 1.5V to 0V, the voltage of unselected access lines 1105 may be reduced from 0V to-1.5V or substantially to-1.5V.

Thus, during interval 1215, unselected access lines 1105 may be floated by applying a different control signal 1165 to node 1175. For example, the control circuit 1120 may output a FLOAT control signal 1165, which may FLOAT the unselected word lines 1110. Thus, the voltage of the unselected word line 1110-d may be reduced to, for example, -1.4V.

In some cases, node 1170 may also float during interval 1215. For example, control circuit 1125 may receive the FLOAT2 control signal at the gate of transistor 1192, which may be low when the input of inverter 1196 is low, which may FLOAT control signal 1160, and thus node 1170. Node 1170 may FLOAT due to transistor 1194 being deactivated (e.g., turned off) because the output of inverter 1196 is high and transistor 1192 being deactivated (e.g., turned off) because floor 2 is low.

During interval 1220, the voltage of plate line 1205 may be held at a second voltage (e.g., a low voltage, such as 0V). In some examples, the unselected word lines 1110-d may remain floating based on the control signal 1165 being applied to the node 1175. In other examples, the unselected word line 1110 may be driven to a desired voltage during interval 1220. For example, during interval 1220 (e.g., at time t'), a different control signal 1165 may be applied to node 1175. Control signal 1165 may be VNNWL, which may be-1.5V.

In some cases, during interval 1220, node 1170 may continue to float as it did during interval 1215. In other examples, node 1170 may be driven to a low voltage, such as 0V, during interval 1220. Due to potential capacitive coupling between the unselected wordline 1110 and the plate 1205, the voltage of the node 1170-d may vary (drift) slightly during interval 1215 (e.g., decrease to a voltage slightly below 0V), and based on the expected drift during interval 1215, the node 1170 may be driven to 0V or a different voltage during interval 1220.

During interval 1225, the voltage of plate line 1205 can be driven from a second voltage (e.g., a low voltage) to a first voltage (e.g., a high voltage). The control circuit 1120 may output a FLOAT control signal 1165, which may FLOAT the unselected word lines 1110. In addition, control circuitry 1125 may float (e.g., continue to float) node 1170, as described with reference to interval 1215. During interval 1225, the voltage of the unselected word lines 1110-d (or 1110-d') may increase to, for example, -0.1V.

During interval 1230, the voltage of plate line 1205 may remain at a first voltage (e.g., a high voltage). Control circuitry 1120 may output a high control signal 1165 (e.g., VNWL) which may be, for example, 0V. Thus, during interval 1230, the voltage of node 1175-d and the voltage of unselected word lines 1110-d (and 1110-d') may be 0V. Additionally or alternatively, during interval 1230, node 1170-d may be driven to 0V. In the examples described herein, the absolute voltage levels (e.g., -1.4V, -1.5V, 3V, 0V, etc.) are described for illustrative purposes only. Thus, any absolute voltage level different from that described herein may be used.

In some examples, each of the

transistors

1130, 1135, 1140, and 1145 within the driver 1105 of the unselected word lines 1110-d may have a relatively low gate-to-source voltage (e.g., V) throughout the access operation_gs) And/or drain-source voltage (e.g., V)_ds). For example, none of

transistors

Additionally or alternatively, the cascode configuration of

transistors

FIG. 13 shows a block diagram 1300 of an access line manager 1315 that supports access line management of an array of memory cells, according to an example of the invention. The access line manager 1315 may be an example of aspects of the access line manager 1415 described with reference to FIG. 14. Access line manager 1315 may include a biasing component 1320, a timing component 1325, a driving component 1330, an identification component 1335, a floating component 1340, and an applying component 1345. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

Drive component 1330 can drive a plate coupled with at least a first memory cell of the array of memory cells to a first voltage. In some examples, the drive component 1330 may drive the plate from the first voltage to the second voltage during the duration based on an access operation associated with the second memory cell.

The identifying component 1335 can identify an access operation associated with a second memory cell of the array of memory cells.

The floating component 1340 may float a first access line coupled with a first memory cell of the array of memory cells for a duration of time based on an access operation associated with a second memory cell. In other examples, floating component 1340 can float the first access line based on applying a first control signal having a first voltage swing and a second control signal having a second voltage swing different from the first voltage swing to a driver of the first access line.

In some examples, the floating component 1340 can float the second node of the driver for at least a portion of the duration. The second node may include a source or a drain of a fourth transistor included in the driver. Floating the first access line may be based on floating the second node.

The applying component 1345 may apply a fourth control signal to a third transistor included in the driver. The fourth control signal may be inverted relative to the third control signal and have a different voltage swing than the third control signal.

It is to be appreciated that in some examples, one or more components of the access line manager 1315 may be combined (e.g., the biasing component 1320, the driving component 1330, and the floating component 1340).

FIG. 14 shows a diagram of a system 1400 including a device 1405 supporting access line management of an array of memory cells, according to an example of the invention. The device 1405 may be an example of or include components of the memory array 100 as described above, for example, with reference to fig. 1. Device 1405 may include components for two-way voice and data communications, including components for transmitting and receiving communications, including access line manager 1415, memory unit 1420, basic input/output system (BIOS) component 1425, processor 1430, I/O controller 1435, and peripheral components 1440. The access line manager 1415 may be an example of the access line manager 1315 described with reference to fig. 13. These components may be in electronic communication via one or more buses, such as bus 1410.

Memory cell 1420 may store information (i.e., in the form of logic states), as described herein.

The BIOS component 1425 may be a software component that contains a BIOS operating as firmware, which may initialize and run various hardware components. The BIOS component 1425 may also manage data flow between the processor and various other components (e.g., peripheral components, input/output control components, etc.). The BIOS component 1425 may include programs or software stored in Read Only Memory (ROM), flash memory, or any other non-volatile memory.

Processor 1430 may include intelligent hardware devices (e.g., general purpose processors, DSPs, Central Processing Units (CPUs), microcontrollers, ASICs, FPGAs, programmable logic devices, discrete gate or transistor logic components, discrete hardware components, or any combinations thereof). In some cases, processor 1430 may be configured to operate the memory array using a memory controller. In other cases, memory controller may be integrated into processor 1430. The processor 1430 may be configured to execute computer-readable instructions stored in memory to perform various functions (e.g., functions or tasks to support access line management of an array of memory cells).

I/O controller 1435 may manage input and output signals of device 1405. The I/O controller 1435 may also manage peripheral devices that are not integrated into the device 1405. In some cases, I/O controller 1435 may represent a physical connection or port for an external peripheral device. In some cases, I/O controller 1435 may utilize an operating system, for example

Or another known operating system. In other cases, I/O controller 1435 may represent or interact with a modem, keyboard, mouse, touch screen, or similar device. In some cases, I/O controller 1435 may be implemented as part of a processor. In some cases, the user may be via the I/O controller1435 or hardware components controlled via the I/O controller 1435 interact with the device 1405.

Peripheral components 1440 may include any input or output device or interface for such devices. Examples may include disk controllers, sound controllers, graphics controllers, ethernet controllers, modems, Universal Serial Bus (USB) controllers, serial or parallel ports, or peripheral device card slots, such as Peripheral Component Interconnect (PCI) or Accelerated Graphics Port (AGP) slots.

Input 1445 may represent a device or signal external to device 1405 that provides an input to device 1405 or a component thereof. This may include a user interface or an interface with other devices or interfaces between other devices. In some cases, inputs 1445 can be managed by the I/O controller 1435 and can interact with the device 1405 via the peripheral components 1440.

Output 1450 may also represent a device or signal external to device 1405 configured to receive output from device 1405 or any of its components. Examples of output 1450 may include a display, an audio speaker, a printing device, another processor or printed circuit board, and so forth. In some cases, output 1450 may be a peripheral element that interfaces with device 1405 through peripheral components 1440. In some cases, output 1450 may be managed by I/O controller 1435.

The components of device 1405 may include circuitry designed to perform their functions. This may include various circuit elements, such as conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or inactive elements, configured to perform the functions described herein. The device 1405 may be a computer, server, laptop, notebook, tablet, mobile phone, wearable electronic device, personal electronic device, or the like. Alternatively, the device 1405 may be a part or an aspect of such a device.

FIG. 15 shows a flow chart depicting a method 1500 of access line management of an array of memory cells, according to an example of the invention. The operations of method 1500 may be implemented by a memory controller or components thereof, as described herein. For example, the operations of method 1500 may be performed by the access line manager described with reference to FIG. 6.

At 1505, a plate coupled with at least a first memory cell of the memory cell array can be driven to a first voltage. 1505 may be performed in accordance with the methods described herein. In some examples, aspects of the operation of 1505 may be performed by the drive assembly described with reference to fig. 6.

At 1510, an access operation associated with a second memory cell of the memory cell array can be identified. 1510 may be performed according to the methods described herein. In some examples, aspects of the operation of 1510 may be performed by the identification component described with reference to fig. 6.

At 1515, a first access line coupled with a first memory cell of the array of memory cells can be floated for a duration based at least in part on an access operation associated with a second memory cell. In some examples, floating may be based on applying a first control signal having a first voltage swing and a second control signal having a second voltage swing different from the first voltage swing to a driver of a first access line. 1515 the operations may be performed according to the methods described herein. In some examples, aspects of the operation of 1515 may be performed by the floating component described with reference to fig. 6.

At 1520, the plate can be driven from the first voltage to a second voltage during a duration based at least in part on an access operation associated with the second memory cell. 1520 may be performed according to the methods described herein. In some examples, aspects of the operation of 1520 may be performed by the drive components described with reference to fig. 6.

In some examples, the method may include floating a first node of a word line driver for at least a portion of a duration. The first node of the word line driver may be configured to receive a third control signal, and floating the first access line may be based on floating the first node. In some examples, the first control signal may be applied to a gate of a transistor included in the driver, and the first node may include a source or a drain of the transistor. In some examples, the transistor may be in a cascode configuration with a second transistor included in the driver.

In some examples, the fourth control signal may be applied to a third transistor included in the driver. The fourth control signal may be inverted relative to the third control signal and have a different voltage swing than the third control signal.

In some examples, the method may include floating a second node of the driver for at least a portion of the duration. The second node may include a source or a drain of a fourth transistor included in the driver. In some examples, floating the first access line may be based on floating the second node. In some examples, the second control signal may be applied to a gate of the fourth transistor.

An apparatus is described. In some examples, the apparatus may include: the memory device includes a memory cell coupled with an access line, a driver coupled with the access line, and a control circuit coupled with the driver and operable to generate a first control signal for the driver and a second control signal for the driver. In some examples, the second control signal may have a different voltage swing than the first control signal.

The apparatus may include a second control circuit coupled with the driver and operable to float a first node of the driver. In some examples, the driver may be used to float the access line based on the first node floating. The apparatus may include a third control circuit coupled with the driver and operable to float a second node of the driver. In some examples, the driver may be used to float the access line based on the second node floating.

In some examples, the driver is one of a subset of a set of drivers, and each driver in the set may be coupled with a respective access line of a memory array that includes the memory cell. In some examples, the control circuit may be coupled with each driver in the subset, and the first control signal and the second control signal may be common to the drivers in the subset. In some examples, the apparatus may include a control circuit coupled with a second subset of the set of drivers. The third control circuit may be for generating a third control signal common to the drivers in the second subset.

In some examples, the third control circuit can be further used to generate a fourth control signal common to the drivers in the second subset. The fourth control signal may be inverted relative to the third control signal and have a different voltage swing than the third control signal.

The apparatus may include a controller coupled with the control circuit, the second control circuit, and the third control circuit. The controller is operable to identify an access operation associated with a second memory cell of the memory array and cause the second control circuitry to float a first node of the driver during a portion of the access operation associated with the second memory cell based on the second subset not including the driver. In some examples, the second memory cell may be coupled with a second access line coupled with a second driver in the set. The second subset may not include the second driver. In some examples, the driver may be used to float the access line based at least in part on the first node floating.

The controller is operable to identify a second access operation associated with a third memory cell of the memory array and to cause the second control circuitry to drive the node of the driver to a first voltage during the access operation associated with the third memory cell based on the second driver being coupled with the second control circuitry. The third memory cell may be coupled with a third access line coupled with a third driver in the set. In some examples, the third driver may be coupled with the second control circuit.

The apparatus may include a controller coupled with the control circuit, the second control circuit, and the third control circuit. The controller is operable to identify an access operation associated with a second memory cell of the memory array and to cause the third control circuitry to float a second node of the driver during at least a portion of the access operation associated with the second memory cell based on the second driver being coupled with the control circuitry. In some examples, the second driver may be coupled with the control circuit. The driver may be used to float the access line based on the second node floating.

In some examples, the controller may be further for identifying a second access operation associated with a third memory cell of the memory array, and causing the third control circuitry to drive the second node of the driver to a first voltage or a second voltage during the access operation associated with the third memory cell based on the subset not including the third driver. In some examples, the subset may not include the third driver.

An apparatus is described. In some examples, the apparatus may include: a memory cell coupled with an access line; a driver coupled with the access line, wherein the driver may include a first transistor in a cascode configuration with a second transistor; and a control circuit coupled with the driver and operable to output a first control signal to the first transistor and a second control signal to a third transistor of the driver.

In some examples, the apparatus may include a second memory cell. A source of the first transistor and a source of the third transistor may be used to float while an access operation of the second memory cell. In some examples, the driver may be used to float the access line based on one or more of the source of the first transistor or the source of the third transistor being floating.

An apparatus is described. In some examples, the apparatus may include: means for driving a plate coupled with a first memory cell of the memory cell array to a first voltage; means for identifying an access operation associated with a second memory cell of the array of memory cells; means for floating a first access line coupled with the first memory cell for a duration based at least in part on the access operation associated with the second memory cell, wherein the floating is based at least in part on applying a first control signal having a first voltage swing and a second control signal having a second voltage swing different from the first voltage swing to a driver of the first access line; and means for driving the plate from the first voltage to a second voltage during the duration based at least in part on the access operation associated with the second memory cell.

In some examples, the apparatus may include means for floating a first node of the word line driver for at least a portion of the duration, wherein the first node of the word line driver is configured to receive a third control signal, and wherein floating the first access line is based at least in part on floating the first node. In such an example, the apparatus may include means for applying a fourth control signal to a third transistor included in the driver, wherein the fourth control signal is inverted relative to the third control signal and has a different voltage swing than the third control signal. In some examples, the apparatus may include means for floating a second node of the driver for at least a portion of the duration, wherein the second node comprises a source or a drain of a fourth transistor included in the driver, and wherein floating the first access line is based at least in part on floating the second node.

It should be noted that the methods described above describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and that other implementations are possible. Furthermore, examples from two or more of the methods may be combined.

Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some of the figures may depict the signals as a single signal; however, one of ordinary skill in the art will appreciate that a signal may represent a bus of signals, where the bus may have various bit widths.

The terms "electronic communication" and "coupling" refer to the relationship between components that supports electronic flow between the components. This may include direct connections between the components or may include intermediate components. Components that are in electronic communication or coupled with each other may or may not actively exchange electrons or signals (e.g., in an energized circuit), but may be configured and operable to exchange electrons or signals upon the circuits being energized. As an example, two components that are physically connected via a switch (e.g., a transistor) are in electronic communication, or can be coupled regardless of the state (i.e., open or closed) of the switch.

As used herein, the term "substantially" means that the modified characteristic (e.g., verb or adjective substantially modified by the term) need not be absolute, but rather close enough to achieve the stated characteristic's advantages.

The term "isolated" refers to the relationship between components between which electrons are not currently able to flow; if there is an open circuit between the components, the components are isolated from each other. For example, when a switch is open, two components physically connected by the switch may be isolated from each other.

The devices discussed herein, including the memory array 100, may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-Sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate may be controlled via doping using various chemical species including, but not limited to, phosphorous, boron, or arsenic. The doping may be performed during the initial formation or growth of the substrate by ion implantation or by any other doping means.

The one or more transistors discussed herein may represent Field Effect Transistors (FETs) and include three-terminal devices, including sources, drains, and gates. The terminals may be connected to other electronic components via conductive materials (e.g., metals). The source and drain may be conductive and may comprise heavily doped (e.g., retrograde) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be covered by an insulated gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. A transistor may be "on" or "activated" when a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate. A transistor may be "off" or "deactivated" when a voltage less than the threshold voltage of the transistor is applied to the transistor gate.

The description set forth herein, in connection with the appended drawings, describes example configurations and is not intended to represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration," and not "preferred" or "superior to other instances. The detailed description includes specific details for the purpose of providing an understanding of the described technology. However, the techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

In the drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used in this specification, the description applies to any one of the similar components having the same first reference label, regardless of the second reference label.

Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

Thus, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed with each of the following designed to perform the functions described herein: a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a Digital Signal Processor (DSP) and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the invention and the following claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard-wired, or a combination of any of these. Features that implement a function may also be physically located at various locations, including portions that are distributed such that the function is implemented at different physical locations. Further, as used herein (including in the claims), "or" as used in a list of items (e.g., a list of items followed by a phrase such as "at least one of" or "one or more of) indicates an inclusive list such that a list of at least one of A, B or C means a or B or C or AB or AC or BC or ABC (i.e., a and B and C). Further, as used herein, the phrase "based on" should not be considered a reference to a closed set of conditions. For example, an exemplary step described as "based on condition a" may be based on both condition a and condition B without departing from the scope of the disclosure. In other words, the phrase "based on," as used herein, should be considered in a manner identical to the phrase "based, at least in part, on.

Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium may be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, a non-transitory computer-readable medium may comprise RAM, ROM, electrically erasable programmable read-only memory (EEPROM), Compact Disc (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that may be used to carry or store desired program code means in the form of instructions or data structures and that may be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Further, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes CD, laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

The description herein is provided to enable any person skilled in the art to make or use the invention. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method, comprising:

driving a plate coupled with a first memory cell of the memory cell array to a first voltage;

identifying an access operation associated with a second memory cell of the array of memory cells;

floating a first access line coupled with the first memory cell for a duration based at least in part on the access operation associated with the second memory cell, wherein the floating is based at least in part on applying a first control signal having a first voltage swing and a second control signal having a second voltage swing different from the first voltage swing to a driver of the first access line; and

driving the plate from the first voltage to a second voltage during the duration based at least in part on the access operation associated with the second memory cell.

2. The method of claim 1, further comprising:

floating a first node of the driver for at least a portion of the duration, wherein the first node of the driver is configured to receive a third control signal, and wherein floating the first access line is based at least in part on floating the first node.

3. The method of claim 2, wherein:

the first control signal is applied to a gate of a transistor included in the driver; and is

The first node comprises a source or a drain of the transistor.

4. The method of claim 3, wherein the transistor is in a cascode configuration with a second transistor included in the driver.

5. The method of claim 2, further comprising:

applying a fourth control signal to a third transistor included in the driver, wherein the fourth control signal is inverted with respect to the third control signal and has a different voltage swing than the third control signal.

6. The method of claim 1, further comprising:

floating a second node of the driver for at least a portion of the duration, wherein the second node comprises a source or a drain of a fourth transistor included in the driver, and wherein floating the first access line is based at least in part on floating the second node.

7. The method of claim 6, wherein the second control signal is applied to a gate of the fourth transistor.

8. An apparatus, comprising:

a memory cell coupled with an access line;

a driver coupled with the access line; and

a control circuit coupled with the driver and capable of being used to generate a first control signal for the driver and a second control signal for the driver, the second control signal having a different voltage swing than the first control signal.

9. The apparatus of claim 8, further comprising:

a second control circuit coupled with the driver and configured to float a first node of the driver, wherein the driver is configured to float the access line based at least in part on the first node floating.

10. The apparatus of claim 9, further comprising:

a third control circuit coupled with the driver and configured to float a second node of the driver, wherein the driver is configured to float the access line based at least in part on the second node floating.

11. The apparatus of claim 8, wherein:

the driver is one of a subset of a set of drivers, each driver in the set coupled with a respective access line of a memory array including the memory cell;

the control circuit is coupled with each driver in the subset; and is

The first control signal and the second control signal are common to the drivers in the subset.

12. The apparatus of claim 11, further comprising:

a second control circuit coupled with a second subset of the set of drivers, wherein the driver is one of the second subset, and wherein the second subset includes more drivers than the subset.

13. The apparatus of claim 12, further comprising:

a third control circuit coupled with the second subset of the set of drivers, wherein the third control circuit is operable to generate a third control signal common to the drivers in the second subset.

14. The apparatus of claim 13, wherein the third control circuit is further operable to generate a fourth control signal common to the drivers in the second subset, and wherein the fourth control signal is inverted with respect to the third control signal and has a different voltage swing than the third control signal.

15. The apparatus of claim 13, further comprising:

a controller coupled with the control circuitry, the second control circuitry, and the third control circuitry, wherein the controller is operable to:

identifying an access operation associated with a second memory cell of the memory array, wherein the second memory cell is coupled with a second access line coupled with a second driver in the set, and wherein the second subset does not include the second driver; and

causing the second control circuitry to float a first node of the driver during at least a portion of the access operation associated with the second memory cell based at least in part on the second subset not including the second driver, wherein the driver is operable to float the access line based at least in part on the first node floating.

16. The apparatus of claim 15, wherein the controller is further operable to:

identifying a second access operation associated with a third memory cell of the memory array, wherein the third memory cell is coupled with a third access line coupled with a third driver in the set, and wherein the third driver is coupled with the second control circuit; and

causing the second control circuitry to drive the first node of the driver to a first voltage during the access operation associated with the third memory cell based at least in part on the second driver being coupled with the second control circuitry.

17. The apparatus of claim 13, further comprising:

identifying an access operation associated with a second memory cell of the memory array, wherein the second memory cell is coupled with a second access line coupled with a second driver in the set, and wherein the second driver is coupled with the control circuit; and

causing the third control circuitry to float a second node of the driver during at least a portion of the access operation associated with the second memory cell based, at least in part, on the second driver being coupled with the control circuitry, wherein the driver is operable to float the access line based, at least in part, on the second node floating.

18. The apparatus of claim 17, wherein the controller is further operable to:

identifying a second access operation associated with a third memory cell of the memory array, wherein the third memory cell is coupled with a third access line coupled with a third driver in the set, and wherein the subset does not include the third driver; and

causing the third control circuitry to drive the second node of the driver to a first voltage or a second voltage during the access operation associated with the third memory cell based at least in part on the subset not including the third driver.

19. An apparatus, comprising:

a memory cell coupled with an access line;

a driver coupled with the access line, wherein the driver comprises a first transistor in a cascode configuration with a second transistor; and

a control circuit coupled with the driver and capable of being used to output a first control signal to the first transistor and a second control signal to a third transistor of the driver.

20. The apparatus of claim 19, further comprising:

a second memory cell, wherein a source of the first transistor and a source of the third transistor are operable to float concurrently with an access operation of the second memory cell, and wherein the driver is operable to float the access line based at least in part on one or more of the source of the first transistor or the source of the third transistor floating.